Back contact for stacked field effect transistors

Abstract

Embodiments of a semiconductor device and a method for manufacturing are disclosed. The apparatus includes a first gate having a top FET disposed over a bottom FET and in electrical contact with a top source / drain epitaxy (S / D epi) and a back end line (BEOL) interconnect. In addition, the device includes a bottom FET. The bottom FET is in electrical contact with the bottom S / D epitaxy. Further, the shallow backside contact is in electrical contact with the bottom S / D epitaxy. In addition, the apparatus includes a deep via in electrical contact with the BEOL interconnect and the shallow backside contact. A deep via and a shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S / D epitaxy.

Description

Technical Field

[0001] The present disclosure relates to back contacts, and more particularly, to back contacts for stacked field effect transistor (FET) semiconductor devices. Background Art

[0002] Semiconductor devices (devices) can be used in computer processors, computer memories, and the like. These devices include transistors, such as field effect transistors (FETs), which implement the processing and data storage of computer processors and memories by controlling the current flowing from a source to a drain. FETs control the current by using an electric field. Some semiconductor devices include stacked FETs, i.e., two layers, where each layer has metal wiring and contacts to the front and back of the device.

[0003] The term "front side" refers to the back end of line (BEOL) interconnect, which includes signal wiring for semiconductor devices. The signal wiring can include logic circuits for the device. Regarding the back side, the term specifically refers to the back side interconnect, which can include wiring for power (i.e., Vss / Vdd) to the device.

[0004] Semiconductor devices are fabricated on wafers. Thus, when discussing the fabrication of wafers with semiconductor devices, it may be useful to describe the positions of the elements of the wafer using reference points. More specifically, the back side and the front side provide reference points to describe the relative positions of specific elements of the wafer. For example, the back side is "below" the front side. Additionally, the wafer includes a middle-of-line (MOL) having wiring and contacts. In these descriptions, the BEOL interconnect (front side) is above the top layer of the FET, the top layer of the FET is above the MOL, the MOL is above the bottom layer of the FET, and the bottom layer of the FET is above the back side interconnect. However, the references to relative positions herein (e.g., above, below, beneath, left, etc.) are merely examples and are non-limiting with respect to any particular arrangement being described.

[0005] As previously mentioned, FETs can be stacked in a top layer and a bottom layer. Thus, the top layer of the stacked FETs is disposed between the BEOL and the bottom source / drain (S / D), which is the S / D of the FET in the bottom layer. Thus, the top layer FET blocks the potential path of the wiring between the bottom S / D and the BEOL. Additionally, using a back contact for wiring may potentially short circuit to the Vss / Vdd on the back side. Thus, it can be challenging to route wiring between the bottom S / D and the signal wiring of the BEOL. Summary of the Invention

[0006] Embodiments for a semiconductor device are disclosed. The device includes a first gate stack having a top FET disposed above a bottom FET and in electrical contact with a top source / drain epitaxy (S / D epi) and a back-end-of-line (BEOL) interconnect. Additionally, the device includes a bottom FET. The bottom FET is in electrical contact with a bottom S / D epi. Further, a shallow back contact is in electrical contact with the bottom S / D epi. Additionally, the device includes a deep via in electrical contact with the BEOL interconnect and the shallow back contact. The deep via and the shallow back contact provide a conductive path between the BEOL interconnect and the bottom S / D epi.

[0007] Embodiments for a method of manufacturing a semiconductor device are disclosed. The method includes forming a first back contact placeholder by forming a first groove below an area of a first bottom source / drain epitaxy (S / D epi) of a first gate stack, the first gate stack having a first top S / D epi disposed above the first bottom S / D epi. The method further includes depositing a sacrificial dielectric material in the first groove. Additionally, the method includes forming a first gate cut between the first gate stack and a second gate stack. Further, the method includes filling the first gate cut with a dual dielectric filler. The method additionally includes forming a first deep via through an inner dielectric of the dual dielectric filler, wherein the first deep via contacts the back contact placeholder. The method further includes removing the first back contact placeholder. Additionally, the method includes forming a shallow back contact by filling an area previously occupied by the removed back contact placeholder with a conductive metal in electrical contact with the first deep via and the first bottom S / D epi, recessing the first deep back contact, and forming a back-end-of-line (BEOL) interconnect in electrical contact with the first deep via. The shallow back contact does not short to a back-side power rail (BSPR).

[0008] Other aspects of the present disclosure relate to computer program products having functions similar to the functions discussed above with respect to the computer-implemented methods. This summary is not intended to describe every embodiment and / or every aspect of every embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings included in this application are incorporated into the specification and form a part of the specification. They illustrate embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure. The drawings are only illustrative of certain embodiments and do not limit the present disclosure.

[0010] Figure 1 is a block diagram of an example computing environment in accordance with some embodiments of the present disclosure.

[0011] Figure 2A is a top view of an example semiconductor device in accordance with some embodiments of the present invention.

[0012] Figure 2B is a vertical cross-sectional view of an exemplary semiconductor device in accordance with some embodiments of the present invention.

[0013] Figure 3A and 3B is a partial process flow diagram of a method for manufacturing an exemplary semiconductor device in accordance with some embodiments of the present invention.

[0014] Figure 4 is a block diagram of a top view of an exemplary semiconductor device during manufacturing in accordance with some embodiments of the present invention.

[0015] Figure 5A , 5B , 5C, 5D are exemplary manufacturing states of a manufactured exemplary semiconductor device in accordance with some embodiments of the present invention.

[0016] Figure 5E is a block diagram of a top view of an exemplary semiconductor device during manufacturing in accordance with some embodiments of the present invention.

[0017] Figure 5F is an exemplary manufacturing state of a manufactured exemplary semiconductor device in accordance with some embodiments of the present invention.

[0018] Figure 5G is a block diagram of a top view of an exemplary semiconductor device during manufacturing in accordance with some embodiments of the present invention.

[0019] Figure 5H is an exemplary manufacturing state of a manufactured exemplary semiconductor device in accordance with some embodiments of the present invention.

[0020] Figure 5I is a block diagram of a top view of an exemplary semiconductor device during manufacturing in accordance with some embodiments of the present invention.

[0021] Figure 5J is an exemplary manufacturing state of a manufactured exemplary semiconductor device in accordance with some embodiments of the present invention.

[0022] Figure 5K is a block diagram of a top view of an exemplary semiconductor device during manufacturing in accordance with some embodiments of the present invention.

[0023] Figure 5L is an exemplary manufacturing state of a manufactured exemplary semiconductor device in accordance with some embodiments of the present invention.

[0024] Figure 5M is a block diagram of a top view of an exemplary semiconductor device during manufacturing in accordance with some embodiments of the present invention.

[0025] Figure 5N , Figure 5O ,Figure 5P , Figure 5Q , Figure 5R , Figure 5S is an example manufacturing state of an example semiconductor device fabricated in accordance with some embodiments of the present disclosure.

[0026] Figure 5T is a block diagram of a top view of an example semiconductor device during manufacturing in accordance with some embodiments of the present invention.

[0027] Figure 5U , Figure 5V , Figure 5W is an example manufacturing state of an example semiconductor device fabricated in accordance with some embodiments of the present disclosure.

[0028] While the present disclosure is amenable to various modifications and alternative forms, specific details have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the present disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. Detailed Description

[0029] As previously mentioned, congestion in the wiring of stacked FET devices can be reduced by using buried power rails (BPRs) and backside power distribution networks (BSPDNs) in the backside interconnect. However, routing connections between the bottom S / D of the stacked FET and the signal routing in the BEOL can be challenging.

[0030] Accordingly, some embodiments of the present disclosure can fabricate a stacked FET semiconductor device having routing between the bottom S / D epitaxy (epis) and the signal routing of the BEOL. Such embodiments can include a gate cut region filled with a bilayer dielectric and located between the top stacked FET cell and the bottom stacked FET cell. Additionally, such embodiments can include at least one deep through hole formed through the internal dielectric fill. The deep through hole is connected to a shallow backside contact, which is connected to the bottom S / D. Additionally, the reduced depth of the shallow backside contact can prevent a short circuit with the backside power rail. Furthermore, such embodiments include a backside contact having a greater height compared to the shallow backside contact routing the bottom S / D epitaxy to the BPR. Additionally, such embodiments can include a deep through hole routing the top S / D epitaxy to the BPR. In this manner, such embodiments can provide a stacked FET semiconductor device having routing between the bottom S / D epitaxy and the BEOL and between the top S / D epitaxy and the backside.

[0031] Figure 1It is a block diagram of an exemplary computing environment 100 according to some embodiments of the present disclosure. Aspects of the present disclosure are described by narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flowchart, depending on the technology involved, operations may be performed in an order different from the order shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in the reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0032] A computer program product embodiment (“CPP embodiment” or “CPP”) is a term used in the present disclosure to describe any collection of one or more storage media (also referred to as “media”) jointly included in a set of one or more storage devices, the set of one or more storage devices jointly including machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A “storage device” is any tangible device that can retain and store instructions used by a computer processor. By way of non-limitation, computer-readable storage media may be electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded devices such as punched cards or pits / lands formed in the major surface of a disc, or any suitable combination of the foregoing. As used in the present disclosure, the term computer-readable storage media should not be construed to store in the form of transitory signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, optical pulses through an optical fiber cable, electrical signals transmitted through wires and / or other transmission media. As will be understood by those skilled in the art, during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, data typically moves at some occasional points in time, but this does not make the storage device transitory because the data is not transitory when it is stored.

[0033] Computing environment 100 includes examples of environments for executing at least some of the computer code involved in performing the methods of the present invention, such as a semiconductor device manufacturing manager 150. Additionally, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, computer 101 includes a set of processors 110 (including processing circuitry 120 and cache 121), a communication fabric 111, volatile memory 112, a permanent storage device 113 (including an operating system 122 and semiconductor device manufacturing manager 150, as described above), a set of peripheral devices 114 (including a set of user interface (UI) devices 123, a storage device 124, and a set of Internet of Things (IoT) sensors 125), and a network module 115. Remote server 104 includes a remote database 130. Public cloud 105 includes a gateway 140, a cloud orchestration module 141, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0034] Computer 101 can take the form of a desktop computer, a laptop computer, a tablet computer, a smart phone, a smart watch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or developed in the future that is capable of running programs, accessing a network, or querying a database (such as remote database 130). As is well understood in the computer technology field and depending on the technology, the execution of computer-implemented methods can be distributed among multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 100, the discussion focuses on a single computer, specifically computer 101, to keep the presentation as simple as possible. Computer 101 can be located in the cloud, even if it is not shown in the Figure 1 cloud. On the other hand, there is no requirement that computer 101 be in the cloud, except to the extent that it may be affirmatively indicated.

[0035] The set of processors 110 includes one or more computer processors of any type now known or developed in the future. Processing circuitry 120 can be distributed across multiple packages, for example, multiple coordinated integrated circuit chips. Processing circuitry 120 can implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the (one or more) processor chip packages and is typically used for data or code that should be made available for rapid access by threads or cores running on the set of processors 110. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache for the processor group can be located "off-chip". In some computing environments, the set of processors 110 can be designed to work with qubits and perform quantum computing.

[0036] Computer-readable program instructions are typically loaded onto computer 101 to cause a set of processors 110 of computer 101 to execute a series of operational steps to implement a computer-implemented method such that the instructions so executed will instantiate the method specified in the flowchart and / or the narrative description of the computer-implemented method included in this document (collectively referred to as "the method of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the set of processors 110 to control and direct the execution of the method of the present invention. In computing environment 100, at least some of the instructions for executing the method of the present invention may be stored in semiconductor device fabrication manager 150 in persistent storage device 113.

[0037] Communication structure 111 is a signal transmission path that allows the various components of computer 101 to communicate with each other. Generally, this structure is made up of switches and conductive paths, such as switches and conductive paths that make up a bus, a bridge, a physical input / output port, etc. Other types of signal communication paths may be used, such as fiber optic communication paths and / or wireless communication paths.

[0038] Volatile memory 112 is any type of volatile memory now known or developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Generally, volatile memory 112 is characterized by random access, but this is not required unless affirmatively indicated. In computer 101, volatile memory 112 is located in a single package and inside computer 101, but alternatively or additionally, volatile memory may be distributed across multiple packages and / or be located external to computer 101.

[0039] Persistent storage device 113 is any form of non-volatile storage device for a computer now known or developed in the future. The non-volatility of this storage device means that the stored data is retained regardless of whether power is supplied to computer 101 and / or directly to persistent storage device 113. Persistent storage device 113 may be read-only memory (ROM), but generally at least a portion of the persistent storage device allows data to be written, deleted, and rewritten. Some familiar forms of persistent storage devices include magnetic disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or open-source portable operating system interface type operating systems that employ a kernel. The code included in block 150 generally includes at least some of the computer code involved in executing the method of the present invention.

[0040] The peripheral device set 114 includes the peripheral device set of the computer 101. The data communication connection between the peripheral devices and other components of the computer 101 can be implemented in various ways, such as a Bluetooth connection, a near-field communication (NFC) connection, a connection by a cable (such as a universal serial bus (USB) type cable), a plug-in connection (e.g., a Secure Digital (SD) card), a connection through a local communication network, and even a connection through a wide area network (such as the Internet). In various embodiments, the UI device set 123 can include components such as a display screen, a speaker, a microphone, wearable devices (such as goggles and smartwatches), a keyboard, a mouse, a printer, a touchpad, a game controller, and a haptic device. The storage device 124 is an external storage device, such as an external hard disk drive, or a pluggable storage device, such as an SD card. The storage device 124 can be persistent and / or volatile. In some embodiments, the storage device 124 can take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where the computer 101 needs to have a large amount of storage (e.g., in the case where the computer 101 locally stores and manages a large database), the storage can be provided by a peripheral storage device designed to store a very large amount of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor can be a thermometer, and another sensor can be a motion detector.

[0041] The network module 115 is a collection of computer software, hardware, and firmware that allows the computer 101 to communicate with other computers through the WAN 102. The network module 115 can include hardware (such as a modem or a Wi-Fi signal transceiver), software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control function and the network forwarding function of the network module 115 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control function and the forwarding function of the network module 115 are executed on physically separate devices, such that the control function manages several different network hardware devices. The computer-readable program instructions for performing the methods of the present invention can generally be downloaded to the computer 101 from an external computer or an external storage device through a network adapter card or a network interface included in the network module 115.

[0042] WAN 102 is any wide area network (e.g., the Internet) that can transmit computer data over non-local distances via any technology, now known or hereafter developed, for transmitting computer data. In some embodiments, WAN 102 may be replaced and / or supplemented by local area networks (LANs) (such as Wi-Fi networks) designed to transmit data between devices located in a local area. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0043] The end user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and may take any form discussed above in connection with computer 101. The EUD 103 typically receives helpful and useful data from the operation of computer 101. For example, in the hypothetical case where computer 101 is designed to provide recommendations to an end user, the recommendation will typically be transmitted from the network module 115 of computer 101 to the EUD 103 via WAN 102. In this way, the EUD 103 can display or otherwise present the recommendation to the end user. In some embodiments, the EUD 103 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0044] The remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. The remote server 104 may be controlled and used by the same entity that operates computer 101. The remote server 104 represents a machine that collects and stores useful and helpful data for use by other computers such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, the historical data may be provided to computer 101 from the remote database 130 of remote server 104.

[0045] A public cloud 105 is any computer system that can be used by multiple entities, which provides on-demand availability of computer system resources and / or other computing capabilities, especially data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing typically utilizes resource sharing to achieve consistency and economies of scale. The direct and active management of the computing resources of the public cloud 105 is performed by the computer hardware and / or software of the cloud orchestration module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers of a collection of host physical machines 142, where the collection of host physical machines 142 is the totality of physical computers in and / or available for the public cloud 105. The virtual computing environments typically take the form of virtual machines from a collection of virtual machines 143 and / or containers from a collection of containers 144. It should be understood that these VCEs can be stored as images and can be transferred among and between various physical machine hosts either as images or after instantiation of the VCEs. The cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs and manages the active instantiations of VCE deployments. The gateway 140 is a collection of computer software, hardware and firmware that allows the public cloud 105 to communicate over the WAN 102.

[0046] Some further explanations of virtualized computing environments (VCEs) will now be provided. A VCE can be stored as an “image”. New active instances of a VCE can be instantiated from the image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows for the existence of multiple isolated user space instances (called containers). From the perspective of the programs running within them, these isolated user space instances typically appear as real computers. A computer program running on a normal operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU capabilities, and quantifiable hardware capabilities. However, a program running within a container can only use the contents of the container and the devices allocated to the container, which is a characteristic known as containerization.

[0047] The private cloud 106 is similar to the public cloud 105, except that the computing resources are only available for a single enterprise. Although the private cloud 106 is depicted as communicating with the WAN 102, in other embodiments, the private cloud can be completely disconnected from the Internet and only accessible through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private cloud, community cloud, or public cloud types) that are typically implemented by different providers. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technology that enables orchestration, management, and / or data / application portability between the multiple constituent clouds. In this embodiment, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0048] Figure 2A FIG. 250 is a top view of an exemplary semiconductor device 200 in accordance with some embodiments of the present invention. The top view 250A includes four device regions 252-1, 252-2, 252-3, 252-4 (collectively referred to as device regions 252) and three gate regions 254-1, 254-2, 254-3 (collectively referred to as gate regions 254). The device regions 252 represent the locations of the channels and S / D epitaxies of the exemplary semiconductor device 200. The gate regions 254 include regions over the intersecting device regions 252 having stacked FETs. Additionally, the top view 250A includes X, Y1, and Y2 cut lines corresponding to cross-sectional views of the exemplary semiconductor device 200 (described below).

[0049] Figure 2B FIG. 251 is a vertical cross-sectional view of an exemplary semiconductor device 200 in accordance with some embodiments of the present invention. As shown, the X cut line corresponds to the X view, which represents a cross-section of the device region 252-1 across the gate regions 254-1, 254-2, 254-3. Additionally, the Y1 view represents a cross-section of the gate region 254-1 across the device regions 252-1, 252-2; and the Y2 view represents a cross-section of the intermediate space between the gate regions 254-2, 254-3 (i.e., along the device regions 252-1, 252-2, 252-3, 252-4).

[0050] In addition, the views share similar features across views. For example, the X, Y1, and Y2 views include a carrier wafer 202, BEOL 204, and ILD 206 on the front side; and a backside ILD layer 216, BSPR 222, and BSPDN 224 on the back side. The carrier wafer 202 may represent a silicon (Si) wafer layer. In addition, BEOL 204 may be composed of multiple layers of metal lines (including signal wiring and power rails) and vias (e.g., Cu-based interconnects). Regarding the back side, the backside ILD layer 216 may be a material such as SiO2, SiOC, SiN, low-k oxide, etc. The backside ILD layer 216 isolates the backside contacts from each other and isolates the device layer from BSPR 222. BSPR 222 includes source and drain power rails in the back side. The backside ILD layer 216 is a backside interlayer dielectric (ILD) deposited from the back side of the wafer. Thus, BSPR 222 and BSPDN 224 can power the example semiconductor device 200 when connected to a power source. BSPDN 224 includes an insulator (e.g., backside ILD) and backside interconnects (e.g., backside metal lines and backside metal vias).

[0051] Since the X view represents the device region 252-1 across three gate regions 254, the X view includes three stacks of stacked FETs 212 (e.g., gate stacks), two stacks of S / D epitaxy 214 between these three gate stacks, contacts, and vias. The gate stack includes a top FET 212-T and a bottom FET 212-B (collectively referred to as stacked FET 212) from top to bottom. ILD 206 may be a dielectric material such as SiO2, SiN, SiBCN, SiOCN, SiOC, SiC, etc. Regarding the gate stack, the top FETs and the bottom FETs are separated from each other by an intermediate dielectric isolation (MDI) layer 212-0M. Similarly, the bottom FET 212-B is separated from the backside ILD layer 216 by a bottom dielectric isolation (BDI) layer 212-0B.

[0052] Additionally, the stacked FETs 212 can represent a transistor having spacers 212-1, nanosheet channels 212-2, internal spacers 212-3, high-k metal gates (HK / MG) 212-4, MDI layer 212-0M, and BDI layer 212-0B. The spacers 212-1 can include a dielectric material layer that is deposited and etch-back to provide a spacing between the HK / MG 212-4 and the contact 208-A. Additionally, the nanosheet channels 212-2 can include nanosheets of semiconductor material that can be conductive in the transistor "on" state or highly resistive in the transistor "off" state. The conductivity of the nanosheet channels 212-2 can be controlled by the HK / MGs 212-4. Further, the internal spacers 212-3 can represent a dielectric material that provides a spacing between the HK / MGs 212-4 and the S / D epitaxy 214. Additionally, the HK / MGs 212-4 can include a transistor gate electrode and a gate dielectric of a high-k material (e.g., k = 7 or greater). The material of the HK / MGs 212-4 can vary based on the type of device in the construction (e.g., N-type or P-type FET).

[0053] In addition, the X-view includes two stacks of the S / D epitaxy 214 (top S / D epitaxy 214-T and bottom S / D epitaxy 214-B). The S / D epitaxy 214 can be a heavily doped epitaxial layer, such as boron-doped SiGe for p-type field effect transistors (PFETs) or phosphorus-doped Si for n-type FETs (NFETs). Further, the S / D epitaxy stack includes, from top to bottom, the contact 208-A, the top S / D epitaxy 214-T, the ILD 206 (isolating the top and bottom S / D epitaxies from each other), and the bottom S / D epitaxy 214-B. Additionally, the S / D epitaxy stack varies below the bottom S / D epitaxy 214-B. More specifically, the left S / D epitaxy stack (between the gate regions 254-1 and 254-2) further includes a shallow back contact 208-S, which is part of an interconnect (not shown) between the bottom S / D epitaxy 214-B and the BEOL 204. According to some embodiments of the present disclosure, the shallow back contact 208-S enables the example semiconductor device 200 to connect to the interconnect without the risk of shorting with the BSPR 222. In contrast, the right S / D epitaxy stack (between the gate regions 254-2 and 254-3), the bottom S / D epitaxy 214-B is connected to the BSPR 222 through a deep back contact 208-D.

[0054] As described above, the Y1 view represents a cross-section of the gate region 254-1 across the device regions 252-1, 252-2. Thus, the Y1 view represents four FETs (i.e., two gate stacks), contacts, and vias at and between these device regions. The Y1 view structure includes (from top to bottom) contact 208-B, HK / MG 212-4, nanosheet channel 212-2, and MDI 212-0M at the bottom of the top FET 212-T, and BDI layer 212-0B at the bottom of the bottom FET 212-B. In addition, the Y1 view structure includes STI layer 218. Each gate stack is located above and isolated from BSPR 222-VSS.

[0055] Between the gate stacks, the Y1 view includes backside ILD layer 216 on each side of deep via 210. Deep via 210 provides a conductive path between the top S / D epitaxy 214-T and BSPR 222-VDD (shown in view Y2). Additionally, backside ILD layer 216 isolates deep via 210 from the gate stacks.

[0056] As described above, the Y2 view represents a cross-section of exemplary semiconductor device 200 of device regions 252-1, 252-2, 252-3, 252-4 in the intervening space between gate regions 254-2, 254-3. More specifically, the Y2 view includes S / D epitaxies, contacts, and vias between the gates (i.e., stacked FETs) at these gate regions. Thus, the Y2 view represents a cross S / D epitaxy view of four S / D epitaxy stacks (i.e., top and bottom S / D epitaxies), contacts, and vias located between 16 stacked FETs 212 (eight stacks, four stacks along each of gate regions 254-2, 254-3). The S / D epitaxy stacks of the Y2 view are similar to those of the X and Y1 views. From left to right, the S / D epitaxy stacks represent the S / D epitaxies at device regions 252-1, 252-2, 252-3, 252-4, and include deep back contact 208-D, shallow back contact 208-S, deep back contact 208-D, and deep front contact 208-DF. Deep front contact 208-DF shorts the bottom S / D epitaxy 214-B and the top S / D epitaxy 214-T together.

[0057] In addition, between the S / D epitaxial stacks at device regions 252-1 and 252-2, the Y2 view includes columns of a first dielectric material 217-1 and a second dielectric material 217-2, a STI layer 218, and a backside ILD layer 216. Additionally, between the S / D epitaxial stacks at device regions 252-2 and 252-3, the Y2 view includes a deep via 210 that contacts the BEOL 204 and a shallow back contact 208-S. Additionally, on either side of the deep via 210, the backside ILD layer 216 isolates the deep via 210 from an adjacent S / D epitaxy 214. The backside ILD layer 216 also contacts the STI layer 218. In this manner, the exemplary semiconductor device 200 provides a conductive path between signal routing in the BEOL 204 and the bottom S / D epitaxy of the bottom FET in the stacked FET device.

[0058] In addition, between the S / D epitaxial stacks at device regions 252-3 and 252-4, the Y2 view includes a deep via 210 that contacts a contact 208-A at the top of the S / D epitaxial stack and a BSPR 222-VDD. Additionally, on either side of the deep via 210, the backside ILD layer 216 isolates the deep via 210 from an adjacent S / D epitaxial stack. In this manner, the deep via 210 provides a conductive path from the top S / D epitaxy 214T to the BSPR 222-VDD.

[0059] Figure 3 (covering Figure 3A and 3B ) is a process flow diagram of a method 300 for manufacturing a semiconductor device according to some embodiments of the present invention. In some embodiments, an exemplary semiconductor device fabrication manager (such as the semiconductor device fabrication manager 150 described with respect to Figure 1 ) may execute the method 300. In this method, the semiconductor device fabrication manager 150 may fabricate a semiconductor device, such as the semiconductor device 200 described with respect to Figure 2. For clarity, the method 300 is described with respect to Figure 4 and 5A to 5W, and Figure 4 and 5A to 5W provide views of exemplary semiconductor devices fabricated after each operation of the method 300. Additionally, Figure 4 and Figures 5A to 5W The views represented in are merely examples of views that the method 300 may produce. However, some practices of the method 300 may produce other views.

[0060] At operation 302, the semiconductor device fabrication manager 150 may direct a fabrication tool to form a dummy gate. Forming the dummy gate may involve depositing a sacrificial layer that serves as a placeholder for the gate. More specifically, the semiconductor device fabrication manager 150 may direct the fabrication tool to form a patterned nanosheet stack over the isolation layer. Nanosheet patterning may involve forming a patterned nanosheet stack over the underlying layer. More specifically, the fabrication tool may deposit alternating nanosheet layers of a sacrificial nanosheet layer and a nanosheet channel layer. The sacrificial nanosheet layer may be composed of silicon germanium (e.g., SiGe). Additionally, the channel layer may be composed of Si. Further, forming the dummy gate may involve depositing materials to form the dummy gate and a gate hard mask over the patterned nanosheet stack. For clarity, with respect to Figure 4 and 5A operation 302 is described.

[0061] Figure 4 FIG. 450 is a block diagram of a top view of an example semiconductor device 400 during fabrication in accordance with some embodiments of the present invention. In top view 450, the example semiconductor device 400 includes device regions 452-1, 452-2, 452-3, 452-4 (collectively device regions 452) and gate regions 454-1, 454-2, 454-3 (collectively gate regions 454). The device regions 452 represent the locations of the channels and S / D epitaxies to be fabricated. Similarly, the gate regions 454 indicate the locations of the gates to be fabricated, specifically, at the intersecting device regions 452 and gate regions 454. Top view 450 is similar to top view 250A described with respect to Figure 2A Thus, top view 450 includes X, Y1, and Y2 cut lines that correspond to the cross-sectional views described below with respect to Figures 5A to 5D FIG.

[0062] As described below, Figures 5A - 5W includes the fabrication states of example semiconductor devices during fabrication. It is noted that these figures include multiple elements, each labeled for discussion. However, due to the number of elements, including reference numerals for each element may clutter and confuse the figures. Therefore, the following steps are taken to limit the reuse of reference numerals in the figures. For example, these figures include multiple views of the same device. Thus, some of the views share the same elements. Therefore, to limit reference numerals, reference numerals are placed only on the leftmost view of an element. Similarly, similar elements (without reference numerals) are represented by the same vertical position (as shown) and the same hash pattern (or none). Additionally, when an element is added to a figure, the element has a reference numeral. However, even if the element remains, subsequent figures may not include the reference numeral. For example, an element introduced and thus labeled in Figure 5A may not be in Figure 5BMiddle markings. Although these steps are useful for reducing clutter in the figure, there are some exceptions to the markings as described above for clarity of description.

[0063] Figure 5A is an exemplary manufacturing state 500A of an exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The exemplary manufacturing state 500A may represent the state of the semiconductor device after operation 302. The exemplary manufacturing state 500A includes X, Y1, and Y2 views, which correspond to the X, Y1, and Y2 cut lines described with respect to Figure 4 Similar to the exemplary semiconductor device 200 described with respect to Figure 2B The views of the exemplary manufacturing state 500A share features that are similar across views. For example, the X, Y1, and Y2 views all include a substrate 402-S (e.g., silicon (Si)), an etch stop layer 404, a silicon layer 402-1, and a patterned nanosheet stack 406. Additionally, the nanosheet stack 406 includes sacrificial layers 406-1, 406-2, which may be composed of SiGe60 and SiGe30, respectively. Additionally, the nanosheet stack 406 includes nanosheet channels 406-3, which may be composed of a semiconductor material such as Si.

[0064] Furthermore, both the X and Y1 views include a dummy gate 407-DG and a gate hard mask 407-HM. The dummy gate may serve as a placeholder for the actual gate fabricated in different manufacturing states. The gate hard mask 407-HM may be a cap that facilitates patterning of the nanosheet stack. The dummy gate 407-DG in the X view may represent the position (from left to right as shown) with respect to the gate regions 454-1, 454-2, 454-3 described with respect to Figure 4

[0065] Additionally, the Y1 view includes two nanosheet stacks 406, representing device regions 452-1 and 452-2 along the cut line Y1. Furthermore, the Y1 view includes a STI layer 408 in the trenches between the two nanosheet stacks 406 and on either side of the two nanosheet stacks 406. The STI layer 408 may be similar to the STI layer 218 described with respect to Figure 2.

[0066] Furthermore, the Y2 view includes four nanosheet stacks 406, representing device regions 452-1, 452-2, 452-3, 452-4 along the cut line Y2. Similar to the Y1 view, the Y2 view includes a STI layer 408 between the nanosheet stacks 406 and on either side of the nanosheet stacks 406. In this way, the exemplary manufacturing state 500A may represent the state of the semiconductor device being fabricated after performing operation 302.

[0067] Return to reference Figure 3A ​, at operation 304, the semiconductor device manufacturing manager 150 may direct the manufacturing tool to perform sacrificial layer removal; form spacers, BDI, MDI, and internal spacers. The manufacturing tool removes the sacrificial layer 406-1, which may be composed of a SiGe material such as SiGe60. Removing the SiGe60 layer may involve etching the sacrificial layer 406-1 selectively with respect to the Si nanosheet channels 406-3 and other surrounding materials.

[0068] In addition, forming the spacers may involve conformal dielectric deposition and anisotropic reactive ion etching (RIE) to remove spacer material from horizontal surfaces. The spacers may be dielectric materials (e.g., SiN, SiBCN, SiOCN, SiOC, etc.). In addition, forming the BDI involves depositing a dielectric material in the region previously occupied by the sacrificial layer removed from the bottom of the nanosheet stack 406. Similarly, forming the MDI involves depositing a dielectric material in the region previously occupied by the sacrificial layer removed from the middle of the nanosheet stack 406.

[0069] Additionally, forming the internal spacers may involve performing nanosheet recessing, SiGe indentation, and internal spacer formation. More specifically, performing nanosheet recessing may involve back-etching the nanosheet stack (e.g., the sacrificial layer 406-2 and the nanosheet channels 406-3). Additionally, the SiGe indentation may involve a mechanical process to remove portions of the sacrificial layer 406-2 to provide sufficient space to deposit material to form the internal spacers 412-2. In addition, internal spacer formation may involve depositing a dielectric material in the space created by the SiGe indentation. For clarity, with respect to Figure 5B operation 304 is described.

[0070] Figure 5B is an exemplary manufacturing state 500B of an exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the example manufacturing state 500A, the X-view of the example manufacturing state 500B includes two trenches between the dummy gates 407-DG, thereby forming three nanosheet stacks 406. Additionally, the X-view includes a BDI layer 406-0B and an MDI layer 406-0M in the region previously occupied by the removed sacrificial layer 406-1. In addition, the X-view includes spacers 412-1 on either side of the dummy gates 407-DG and the gate hard mask 407-HM. Similar to the X-view, the Y1-view includes a BDI layer 406-0B and an MDI layer 406-0M in the region previously occupied by the removed sacrificial layer 406-1. In this way, the example manufacturing state 500B may represent the state of the semiconductor device being manufactured after operation 304 is performed.

[0071] Return to reference Figure 3A, at operation 306, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to perform placeholder patterning. Performing placeholder patterning may involve depositing a mask material (such as an organic planarization layer (OPL)), and then performing conventional lithographic patterning. Additionally, placeholder patterning involves creating trenches that pass through the OPL and into the silicon layer 402-1 and the STI layer 408. For clarity, regarding Figure 5C describe operation 306.

[0072] Figure 5C is an exemplary manufacturing state 500C of an exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500B, the X view of the exemplary manufacturing state 500C additionally includes trenches 414 and an OPL 416. As previously described, the trenches pass through the OPL 416 and into the silicon layer 402-1. In these ways, the exemplary manufacturing state 500C may represent the state of a semiconductor device being manufactured after operation 306 is performed.

[0073] Returning to reference Figure 3A , at operation 308, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to form a placeholder, perform S / D epitaxial growth, form an ILD layer, remove a dummy gate and a sacrificial layer, and form replacement HK / MGs. Forming a placeholder involves depositing a sacrificial material in the trenches 414 and recessing it flush with the BDI layer 406-0B, or forming a sacrificial placeholder 418 through a bottom-up deposition process such as selective epitaxial growth. Additionally, performing S / D epitaxial growth involves growing semiconductor S / D epitaxy from an exposed semiconductor surface (e.g., the nanosheet channel 406-3). Additionally, forming an ILD layer involves performing an interlayer dielectric (ILD) deposition on the STI layer 408 and the grown S / D epitaxy. Additionally, forming an ILD layer includes performing chemical mechanical planarization (CMP), which removes materials (e.g., the gate hard mask 407-HM, the material of the ILD layer 422) to form a flat surface. For dummy gate removal, the manufacturing tool may selectively remove the dummy gate 407-DG relative to surrounding materials (e.g., the ILD). Additionally, removing the sacrificial layer 406-2 involves SiGe release. For SiGe release, the manufacturing tool may selectively etch the sacrificial layer 406-2 (e.g., SiGe30) relative to the Si and other surrounding materials of the nanosheet channel 406-3. Additionally, forming a replacement gate involves depositing a high-k metal gate material in the space created by removing the dummy gate 407-DG and the sacrificial layer 406-2. For clarity, regarding Figure 5D describe operation 308.

[0074] Figure 5Dis an example manufacturing state 500D of an example semiconductor device 400 during manufacturing in accordance with some embodiments of the present disclosure. Compared to the example manufacturing state 500C, the X and Y1 views of the example manufacturing state 500D no longer include the dummy gate 407-DG, the gate hard mask 407-HM, and the sacrificial layer 406-2. Additionally, compared to the example manufacturing state 500C, the X view includes three gate stacks and two intervening S / D epitaxial stacks. The gate stacks include a bottom FET 406-B, which includes (from bottom to top) a BDI layer 406-0B, an inner spacer 412-2, and alternating layers of HK / MG 424 and nanosheet channels 406-3. The top FET 406-T includes an MDI layer 406-0M, an inner spacer 412-2, and alternating layers of HK / MG 424 and nanosheet channels 406-3. Additionally, the S / D epitaxial stacks include (from bottom to top) a sacrificial placeholder 418, a bottom S / D epitaxy 420-B, an ILD layer 422, a top S / D epitaxy 420-T, and an ILD layer 422. Compared to the three gate stacks in the X view, the Y1 view includes two gate stacks. These gate stacks include the components of the top FET 406-T and the bottom FET 406-B. The Y2 view contains four S / D epitaxial stacks, which are similar to the S / D epitaxial stacks described with respect to the X view. However, the second S / D epitaxial stack from the left includes a placeholder that extends beyond the right edge of the covered S / D epitaxy. In this manner, the sacrificial placeholder 418 enables the creation of a via that reaches a contact to be created in place of the sacrificial placeholder 418. Additionally, the rightmost S / D epitaxial stack does not include the sacrificial placeholder 418. In this way, Figure 5D can represent the state of the semiconductor device being manufactured after operation 308.

[0075] Return reference Figure 3A , at operation 310, the semiconductor device fabrication manager 150 can direct fabrication tools to perform ILD deposition and gate cut patterning. Performing ILD deposition involves depositing ILD material on the manufactured semiconductor device. Additionally, performing gate cut patterning involves overfilling the sacrificial material on the deposited ILD and removing the sacrificial material and the deposited ILD to create a gate cut down to the STI layer 408 and between the device regions 452. For clarity, with respect to Figure 5E and 5F operation 310 is further described.

[0076] Figure 5EIt is a block diagram of a top view 450E of an example semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The top view 450E is similar to the top view 450 and additionally includes gate cuts 456-1, 456-2, 456-3 (collectively referred to as gate cuts 456) between device regions 454.

[0077] Figure 5F It is a block diagram of an example manufacturing state 500F of an example semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared with the example manufacturing state 500D, the X, Y1, and Y2 views of the example manufacturing state 500F additionally include additional ILD and OPL 426 in the ILD layer 422. Additionally, the Y1 view additionally includes the gate cut 456-1. Similarly, the Y2 view additionally includes the gate cuts 456-1, 456-2, 456-3. In this way, Figure 5F It can represent the state of a semiconductor device being manufactured after operation 310.

[0078] Returning to the reference Figure 3A , at operation 312, the semiconductor device manufacturing manager 150 can direct a manufacturing tool to perform a dual-layer gate cut fill. Performing the dual-layer gate cut fill involves removing the OPL 426. Additionally, performing the dual-layer gate cut fill includes lining the gate cuts 456 with a first dielectric material and filling the lined gate cuts with a second dielectric material different from the first dielectric material. For example, the first dielectric material can be silicon nitride (SiN), and the second dielectric material can be silicon dioxide (SiO2). For clarity, with respect to Figure 5G , 5H Operation 312 is further described.

[0079] Figure 5G It is a block diagram of a top view 450G of an example semiconductor device 400 during manufacturing according to some embodiments of the present invention. The top view 450G is similar to the top view 450E, and the gate cuts 456 additionally include a first dielectric material 430 and a second dielectric material 432.

[0080] Figure 5H It is a block diagram of an example manufacturing state 500H of an example semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared with the example manufacturing state 500F, the X, Y1, and Y2 views of the example manufacturing state 500H no longer include the OPL 426. Additionally, the Y1 and Y2 views include the first dielectric material 430 lining the gate cuts 456 and the second dielectric filling the gate cuts 456. In this way, Figure 5H It can represent a semiconductor device being manufactured after operation 312.

[0081] Referring again to Figure 3A, at operation 314, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to perform self-aligned deep via patterning. Performing self-aligned deep via patterning involves performing a sacrificial material overfill and creating deep trenches that pass through the OPL 426, the second dielectric material 432, the STI layer 408, or into the silicon layer 402-1, or expose the sacrificial placeholder 418. For clarity, with respect to Figure 5I , Figure 5J operation 314 is further described.

[0082] Figure 5I is a block diagram of a top view 450I of an example semiconductor device 400 during manufacturing in accordance with some embodiments of the present invention. The top view 450I is similar to the top view 450G and additionally includes deep trenches 458-1, 458-2, 458-3, 458-4 (collectively referred to as deep trenches 458).

[0083] Figure 5J is a block diagram of an example manufacturing state 500J of an example semiconductor device 400 during manufacturing in accordance with some embodiments of the present disclosure. Compared to the example manufacturing state 500H, the X, Y1, and Y2 views of the example manufacturing state 500J include the OPL 426 on top of the ILD layer 422. Additionally, the Y1 view includes a deep trench 458-1 between two gate stacks. Further, the Y2 view of the example manufacturing state 500G includes a deep trench 458-3 (which exposes the sacrificial placeholder 418) between two gate stacks and a deep trench 458-4 (which extends down into the silicon layer 402-1) between the S / D epitaxial stacks. In this way, Figure 5J may represent a semiconductor device being manufactured after operation 314.

[0084] Returning to reference Figure 3A , at operation 316, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to perform contact patterning. Performing contact patterning involves removing the OPL 426 and material from the ILD layer 422 to expose the top S / D epitaxy 420-T, the HK / MGs 424, the bottom S / D epitaxy 420-B in the device region 452-3, and creating an opening for the deep via. For clarity, with respect to Figure 5K , Figure 5L operation 316 is further described.

[0085] Figure 5K is a block diagram of a top view 500K of an example semiconductor device 400 during manufacturing in accordance with some embodiments of the present disclosure. The top view 450K is similar to the top view 450I and additionally includes front contact openings 434-OA, 434-OB (also referred to as S / D epitaxy openings 434-OA and gate openings 434-OB, respectively).

[0086] Figure 5L is a block diagram of an example manufacturing state 500L of an example semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared with the example manufacturing state 500J, the X, Y1, and Y2 views of the example manufacturing state 500L no longer include the OPL 426. Additionally, the X view includes S / D contact openings 434-OA to the top S / D epitaxy 420-T. The Y1 view additionally includes gate openings 434-OB to the HK / MGs 424 of the top FETs 406-T. Additionally, the Y2 view includes three S / D openings 434-OA to the top of the respective top S / D epitaxies 420-T, and a fourth S / D opening 434-OA to one side of both the top S / D epitaxy 420-T and the bottom S / D epitaxy 420-B in the device region 452-4. The Y2 view also includes three deep via openings 428-D0: one near the middle of the Y2 view; a second near the middle of the Y2 view and exposing the sacrificial placeholder 418; and a third to the right of the second deep via in the Y2 view. In this way, Figure 5L may represent a semiconductor device being manufactured after operation 316.

[0087] Return reference Figure 3A , operation 316 shows the flow to placeholder A. Placeholder A does not represent an operation of the method, but is used to connect Figure 3A the operations described in Figure 3B with other operations of method 300, which will be described in more detail with reference to

[0088] Figure 3B is a process flow diagram of operations 318 to 334 of method 300 according to some embodiments of the present disclosure. For clarity, these operations are described with reference to Figures 5M to 5W

[0089] Figure 3B The process flow diagram of Figure 3A shows the flow from placeholder A to operation 318. As previously mentioned, placeholder A does not represent an operation of method 300, but is used to connect

[0090] ​At operation 318, the semiconductor device fabrication manager 150 may direct fabrication tools to perform middle-of-line (MOL) metallization, form the BEOL, and perform carrier wafer bonding. Performing MOL metallization includes filling the front contact openings 434-OA, 434-OB with a conductive metal to create front contacts. Additionally, performing BEOL interconnect formation may involve fabricating elements of the BEOL interconnects 436, such as multi-layer copper-based metal lines and vias. Further, carrier wafer bonding may involve bonding the carrier wafer 402-2 to the BEOL interconnects 436. For clarity, with respect to Figure 5M , Figure 5N operation 318 is further described.

[0091] Figure 5M FIG. 450M is a block diagram of a top view of an example semiconductor device 400 during fabrication in accordance with some embodiments of the present invention. The top view 450M is similar to the top view 450K and additionally includes front contacts 434-A, 434-B in place of the corresponding front contact openings 434-OA, 434-OB. For clarity, not all front contacts are labeled. Instead, the boxes indicating the front contacts 434-A, 434-B also represent similar contacts in boxes of similar size. Herein, the front contacts 434-A, 434-B are referred to as the S / D contact 434-A and the gate contact 434-B, respectively.

[0092] Figure 5N FIG. 500N is a block diagram of an example fabrication state of an example semiconductor device 400 during fabrication in accordance with some embodiments of the present disclosure. Compared to the example fabrication state 500L, the X, Y1, and Y2 views of the example fabrication state 500N additionally include the carrier wafer 402-2 and the BEOL interconnects 436. Further, the X view includes the S / D contact 434-A on the top S / D epitaxy 420-T. The Y1 view additionally includes the gate contact 434-B to the HK / MGs 424. Additionally, the Y1 view includes the deep via 440-D into the silicon layer 402-1. The Y2 view additionally includes three S / D contacts 434-A to the top of the corresponding top S / D epitaxy 420-T, and a fourth S / D contact 434-A to one side of both the top S / D epitaxy 420-T and the bottom S / D epitaxy 420-B. Additionally, the Y2 view includes two deep vias 440-D between the device regions 452-2, 452-3 and extending downward to the sacrificial placeholder 418. The second deep via 440-D extends downward into the silicon layer 402-1. In this manner, Figure 5N may represent a semiconductor device being fabricated after operation 318.

[0093] Returning to reference Figure 3A, at operation 320, the semiconductor device fabrication manager 150 may direct a fabrication tool to perform wafer flipping and substrate removal. Performing wafer flipping may involve inverting the vertical orientation of the fabricated semiconductor device. Thus, wafer flipping may expose the substrate 402-S for removal. Performing substrate removal involves an etching process of removing substrate material from the exposed surface to the etch stop layer 404. For clarity, with respect to Figure 5O Operation 320 is further described.

[0094] Figure 5O is a block diagram of an example fabrication state 500O of an example semiconductor device 400 during fabrication in accordance with some embodiments of the present disclosure. Compared to the example fabrication state 500N, the X, Y1, and Y2 views of the example fabrication state 500O no longer include the substrate 402-S. In this way, Figure 5O may represent a semiconductor device being fabricated after operation 320.

[0095] Returning to Figure 3A , at operation 322, the semiconductor device fabrication manager 150 may direct a fabrication tool to remove the etch stop layer 404 and the remaining silicon layer 402-1. Removing the etch stop layer 404 and the silicon layer 402-1 exposes the underlying sacrificial placeholder, BDI layer 406-0B, STI layer 408, and deep vias 440-D. For clarity, with respect to Figure 5P Operation 322 is further described.

[0096] Figure 5P is a block diagram of an example fabrication state 500P of an example semiconductor device 400 during fabrication in accordance with some embodiments of the present disclosure. Compared to the example fabrication state 500O, the X, Y1, and Y2 views of the example fabrication state 500P no longer include the silicon layer 402-1 and the etch stop layer 404. In the X1 view, removing these layers exposes the sacrificial placeholder 418 below the bottom S / D epitaxy 420-B. In the Y1 view, removing these layers exposes the STI layer 408, BDI layer 406-0B, and deep vias 440-D. In the Y2 view, removing these layers exposes three sacrificial placeholders 418, the rightmost deep via 440-D, and the rightmost BDI layer 406-0B. In this way, Figure 5P may represent a semiconductor device being fabricated after operation 322.

[0097] Returning to Figure 3A , at operation 324, the semiconductor device fabrication manager 150 may direct a fabrication tool to perform backside ILD deposition and CMP. Performing backside ILD deposition involves depositing ILD material on the surface exposed by removing the silicon and the etch stop layer. Performing CMP involves creating a planar surface on the deposited ILD. For clarity, with respect to Figure 5QDescribe operation 324 further.

[0098] Figure 5Q is a block diagram of an example manufacturing state 500Q of an example semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared with the example manufacturing state 500P, the X, Y1, and Y2 views of the example manufacturing state 500Q further include an ILD layer 438. In this way, Figure 5Q may represent a semiconductor device being manufactured after operation 324.

[0099] Return reference Figure 3A , at operation 326, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to remove the sacrificial placeholder 418. Removing the sacrificial placeholder 418 may involve a selective dry etching or wet etching process. For clarity, with respect to Figure 5R Describe operation 326 further.

[0100] Figure 5R is a block diagram of an example manufacturing state 500R of an example semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared with the example manufacturing state 500Q, the X, Y1, and Y2 views no longer include the sacrificial placeholder 418. A back contact opening 442 - O is left in the remaining area. In this way, Figure 5R may represent a semiconductor device being manufactured after operation 326.

[0101] Return reference Figure 3A , at operation 328, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to perform back contact metallization. Back contact metallization may include depositing a conductive metal material in the back contact opening 442 - O. In this way, some embodiments of the present disclosure may provide back contact wiring to the backside interconnect: one of the bottom S / D epitaxy 420 - B and the deep vias 440 - D, which is described in more detail below. For clarity, with respect to Figure 5S Describe operation 328 further.

[0102] Figure 5S is a block diagram of an example manufacturing state 500S of an example semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared with the example manufacturing state 500R, the X view and the Y2 view of the example manufacturing state 500S include a deep back contact (BSCA) 442 - D to replace the removed sacrificial placeholder 418. Additionally, in the X and Y2 views, the deep back contact 442 - D extends to the bottom S / D epitaxy 420 - B. However, the Y1 view remains unchanged. In this way, Figure 5S may represent a semiconductor device being manufactured after operation 328.

[0103] Return reference Figure 3A, at operation 330, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to perform selective back contact recessing. Selective back contact recessing involves performing sacrificial material overfill to form the OPL 426 and removing portions of the OPL 426. Additionally, selective back contact recessing involves removing metal of a predetermined back contact 442-D to reduce the thickness. In this manner, selective back contact recessing can be used to form a shallow back contact, such as the shallow back contact 208-S described with respect to FIG. 2. For clarity, with respect to Figure 5T 、 Figure 5U operation 330 is further described.

[0104] Figure 5T is a block diagram of a top view 450T during manufacturing of an example semiconductor device 400 in accordance with some embodiments of the present disclosure. The top view 450T is similar to the top view 450M and additionally includes a deep back contact 442-D and a shallow back contact 442-S (collectively referred to as back contacts 442). For clarity, not all back contacts are labeled. Instead, the box indicating the back contacts 442 also represents similar back contacts in boxes of similar size.

[0105] Figure 5U is a block diagram of an example manufacturing state 500U of a semiconductor device in accordance with some embodiments of the present disclosure. Compared to the example manufacturing state 500S, the X, Y1, and Y2 views of the example manufacturing state 500U all include the OPL 426, which has portions missing beneath the shallow back contact 442-S. Thus, the X view additionally includes the shallow back contact 442-S beneath the bottom S / D epitaxy 420-B located between the gate regions 454-1 and 454-2. In contrast, the Y1 view does not include other changes. However, the Y2 view additionally includes the shallow back contact 442-S for the bottom S / D epitaxy 420-B of the device region 452-2. In this manner, Figure 5U may represent a semiconductor device being manufactured after operation 330.

[0106] Returning to reference Figure 3A , at operation 332, the semiconductor device manufacturing manager 150 may direct a manufacturing tool to refill the backside ILD and perform CMP. Refilling the backside ILD and performing CMP involves removing the remaining OPL 426, depositing an ILD layer, and performing CMP on the deposited ILD layer. For clarity, with respect to Figure 5V operation 332 is further described.

[0107] Figure 5VBlock diagram of an example manufacturing state 500V of a semiconductor device in accordance with some embodiments of the present disclosure. Compared to the example manufacturing state 500U, the X, Y1, and Y2 views of the example manufacturing state 500V additionally include an ILD layer 438. In this manner, Figure 5V may represent a semiconductor device being manufactured after operation 332.

[0108] At operation 334, the semiconductor device fabrication manager 150 may direct fabrication tools to form a backside power rail and a BSPDN. Forming the backside power rail may involve fabricating a power rail in the ILD layer 438. Additionally, forming the BSPDN involves fabricating backside-interconnected elements such as metal lines and ILD materials. For clarity, with respect to Figure 5W operation 334 is further described.

[0109] Figure 5W Block diagram of an example manufacturing state 500W of a semiconductor device in accordance with some embodiments of the present disclosure. Compared to the example manufacturing state 500V, the X, Y1, and Y2 views of the example manufacturing state 500W additionally include a BSPDN 446. Additionally, the X view includes a BSPR 444-VSS that contacts the bottom S / D epitaxy 420-B located between gate regions 454-2 and 454-3. Further, the Y1 view includes three BSPRs 444 (two BSPRs 444-VSS and one BSPR 444-VDD). The BSPR 444-VDD contacts a deep via 440-D between the gate stack. Further, the Y2 view includes seven BSPRs 444 that alternate between BSPR 444-VSS and 444-VDD. The BSPRs 444-VSS in device regions 452-1, 452-3 contact corresponding deep backside contacts 442-D. Additionally, the BSPR 444-VDD in device region 452-3 contacts a deep via 440-D, which contacts a front-side contact 434-A of the top S / D epitaxy 420-T. In this manner, Figure 5W may represent a semiconductor device being manufactured after operation 334.

[0110] For the purposes of this description, certain aspects, advantages, and novel features of embodiments of the present disclosure are described herein. The disclosed processes and systems should not be construed in any way as limiting. On the contrary, the present disclosure relates to all novel and non-obvious features and aspects of the various disclosed embodiments, individually and in various combinations and sub-combinations with each other. The methods and systems are not limited to any particular aspect or feature or combination thereof, and the disclosed embodiments do not require the presence of any one or more particular advantages or problem solutions.

[0111] Although, for convenience of presentation, the operations of some of the disclosed embodiments are described in a particular order, it should be understood that such description includes rearrangements, unless a particular order is required by the specific language set forth below. For example, operations described in sequence may in some cases be rearranged or performed concurrently. Further, for simplicity, the figures may not show the various ways in which the disclosed processes may be used in conjunction with other processes. Additionally, the description sometimes uses terms such as "provide" or "implement" to describe the disclosed processes. These terms are high-level abstractions of the actual operations being performed. The actual operations corresponding to these terms may vary depending on the particular embodiment, and one of ordinary skill in the art can readily discern them.

[0112] As used in this application and the claims, the singular forms "a", "an", and "the" include plural forms unless the context clearly dictates otherwise. Additionally, the term "comprising" means "including".

[0113] The description of the various embodiments of the present disclosure has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen to explain the principles of the embodiments, the practical application, or a technical improvement over technologies found in the marketplace, or to enable one of ordinary skill in the art to understand the embodiments disclosed herein.

[0114] A non-limiting list of examples is provided below to illustrate some aspects of the present disclosure.

[0115] Example 1 is a semiconductor device. The device includes a first stacked FET that includes: a top FET disposed above a bottom FET and in electrical contact with a top source / drain epitaxy (S / D epi) and a back-end-of-line (BEOL) interconnect; and a bottom FET, where the bottom FET is in electrical contact with a bottom S / D epi; a shallow back contact in electrical contact with the bottom S / D epi; and a first deep via in electrical contact with the BEOL interconnect and the shallow back contact, where the first deep via and the shallow back contact provide a conduction path between the BEOL interconnect and the bottom S / D epi.

[0116] Example 2 includes the device of Example 1, including or excluding optional features. In this example, the device includes a second deep via in electrical contact with the top source / drain contact and a back-side power rail (BSPR). Optionally, the device includes a front contact between the first top FET and the BEOL interconnect.

[0117] Example 3 includes the apparatus of any one of Examples 1 to 2, including or excluding optional features. In this example, the depth of the shallow back contact prevents a short circuit to the backside power rail (BSPR). Optionally, the apparatus includes a third deep via in electrical contact with the BEOL interconnect and the BSPR, wherein a first dielectric element isolates the third deep via from: a first gate; and a second gate. Optionally, the apparatus includes a deep back contact, wherein the deep back contact is in electrical contact with a second bottom FET and the BSPR. Optionally, the apparatus includes a gate cut region disposed between the first gate and the third gate, wherein the gate cut region is filled with a bilayer dielectric.

[0118] Example 4 is a method for manufacturing a semiconductor device. The method includes forming a first back contact placeholder by: forming a first recess below a region for a first bottom source / drain epitaxy (S / D epi), wherein a first top S / D epi is disposed above the first bottom S / D epi; and depositing a sacrificial dielectric material in the first recess; forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi; filling the first gate cut with a bilayer dielectric filler; forming a first deep via through an internal dielectric of the bilayer dielectric filler, wherein the first deep via is in electrical contact with the first back contact placeholder; removing the first back contact placeholder; forming a shallow back contact by: generating a first deep back contact by filling a region previously occupied by the removed first back contact placeholder with a conductive metal in electrical contact with the first deep via and the first bottom S / D epi; and recessing the first deep back contact; and forming a backend-of-line (BEOL) interconnect in electrical contact with the first deep via, and wherein the depth of the shallow back contact prevents a short circuit to the backside power rail (BSPR).

[0119] Example 5 includes the method of Example 4, including or excluding optional features. In this example, the bilayer dielectric filler includes a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric includes an internal dielectric.

[0120] Example 6 includes the method of any one of Examples 4 to 5, including or excluding optional features. In this example, forming the first deep via includes removing the internal dielectric of the bilayer dielectric filler to expose the back contact placeholder.

[0121] Example 7 includes the method of any one of Examples 4 to 6, including or excluding optional features. In this example, the method includes forming a second gate cut between the second gate and the third gate, wherein the second gate cut exposes a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cut with the double-layer dielectric filler; forming a second deep via through the inner dielectric of the double-layer dielectric filler, wherein the second deep via contacts a silicon layer disposed below the STI layer; performing contact patterning to expose a second top S / D epitaxy of the second gate; forming a front contact in electrical contact with the second top S / D epitaxy and the second deep via, wherein the formed BEOL interconnect is in electrical contact with the front contact; and forming a BSPR, wherein the BSPR is in electrical contact with the second deep via. Optionally, the method includes forming a third gate cut between the first gate and the fourth gate, wherein the third gate cut exposes the STI layer between the first gate and the fourth gate; and filling the third gate cut with a double-layer dielectric filler. Optionally, the method includes forming a fourth gate cut between the fourth gate and the fifth gate, wherein the fourth gate cut exposes the STI layer between the fourth gate and the fifth gate; filling the fourth gate cut with the double-layer dielectric filler; and forming a third deep via through the inner dielectric of the double-layer dielectric filler, wherein the third deep via contacts a silicon layer disposed below the STI layer between the fourth gate and the fifth gate, wherein the third deep via is in electrical contact with the formed BEOL interconnect and the formed BSPR. Optionally, the method includes forming a second back contact placeholder by: forming a second groove below a region of a second bottom S / D epitaxy for the second gate, wherein the second bottom S / D epitaxy is disposed below the second top S / D epitaxy; and depositing the sacrificial dielectric material in the second groove; removing the second back contact placeholder; forming a second deep back contact by filling a region previously occupied by the removed second back contact placeholder with the conductive metal such that the conductive metal is in electrical contact with the second bottom S / D epitaxy, and wherein the formed BSPR is in electrical contact with the second deep back contact.

[0122] Example 8 is a computer program product that includes program instructions stored on a computer-readable storage medium. The computer-readable medium includes instructions that direct a processor to form a first back contact placeholder by: forming a first recess below an area for a first bottom source / drain epitaxy (S / D epi), wherein a first top S / D epi is disposed above the first bottom S / D epi; and depositing a sacrificial dielectric material in the first recess; forming a first gate cut between a first gate and a second gate that surround the first bottom S / D epi and the first top S / D epi; filling the first gate cut with a dual dielectric fill; forming a first deep via through an internal dielectric of the dual dielectric fill, wherein the first deep via is in electrical contact with the first back contact placeholder; removing the first back contact placeholder; forming a shallow back contact by: generating a first deep back contact by filling an area previously occupied by the removed first back contact placeholder with a conductive metal that is in electrical contact with the first deep via and the first bottom S / D epi; and recessing the first deep back contact; and forming a back-end-of-line (BEOL) interconnect that is in electrical contact with the first deep via, and wherein the depth of the shallow back contact prevents a short circuit to a back-side power rail (BSPR).

[0123] Example 9 includes the computer-readable medium of Example 8, including or excluding optional features. In this example, the dual dielectric fill includes a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric includes an internal dielectric.

[0124] Example 10 includes the computer-readable medium of any one of Examples 8-9, including or excluding optional features. In this example, forming the first deep via includes removing the internal dielectric of the dual dielectric fill to expose the back contact placeholder.

[0125] Example 11 includes the computer-readable medium of any one of Examples 8 to 10, including or excluding optional features. In this example, the computer-readable medium includes: forming a second gate cut between a second gate and a third gate, where the second gate cut exposes a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cut with the double dielectric filler; forming a second deep via through the inner dielectric of the double dielectric filler, where the second deep via contacts a silicon layer disposed below the STI layer; performing contact patterning to expose a second top S / D epitaxy of the second gate; forming a front contact that is in electrical contact with the second top S / D epitaxy and the second deep via, where the formed BEOL interconnect is in electrical contact with the front contact; and forming a BSPR, where the BSPR is in electrical contact with the second deep via. Optionally, the computer-readable medium includes: forming a third gate cut between a first gate and a fourth gate, where the third gate cut exposes the STI layer between the first gate and the fourth gate; and filling the third gate cut with a double dielectric filler. Optionally, the computer-readable medium includes: forming a fourth gate cut between a fourth gate and a fifth gate, where the fourth gate cut exposes the STI layer between the fourth gate and the fifth gate; filling the fourth gate cut with the double dielectric filler; and forming a third deep via through the inner dielectric of the double dielectric filler, where the third deep via contacts a silicon layer disposed below the STI layer between the fourth gate and the fifth gate, where the third deep via is in electrical contact with the formed BEOL interconnect and the formed BSPR.

Claims

1. A semiconductor device, comprising: A first stacked FET, comprising: A top FET, which is disposed above a bottom FET and is in electrical contact with a top source / drain epitaxy (S / D epi) and a back-end-of-line (BEOL) interconnect; and The bottom FET, wherein the bottom FET is in electrical contact with a bottom S / D epi; A shallow back contact, which is in electrical contact with the bottom S / D epi; and A first deep via, which is in electrical contact with the BEOL interconnect and the shallow back contact, wherein the first deep via and the shallow back contact provide a conductive path between the BEOL interconnect and the bottom S / D epi.

2. The semiconductor device according to claim 1, further comprising a second deep via in electrical contact with a top source / drain contact and a back-side power rail (BSPR).

3. The semiconductor device according to claim 2, further comprising a front contact between a first top FET and the BEOL interconnect.

4. The semiconductor device according to claim 1, wherein the depth of the shallow back contact prevents a short circuit to a back-side power rail (BSPR).

5. The semiconductor device according to claim 4, further comprising a deep back contact, wherein the deep back contact is in electrical contact with a second bottom FET and the BSPR.

6. The semiconductor device according to claim 5, further comprising a gate cut region disposed between the first gate and the third gate, wherein the gate cut region is filled with a dual dielectric.

7. The semiconductor device according to claim 6, further comprising a deep front contact shorting a second bottom S / D epi and a second top S / D epi.

8. A method for manufacturing a semiconductor device, the method comprising: Forming a first back contact placeholder by: Forming a first groove below a region for a first bottom source / drain epitaxy (S / D epi), wherein a first top S / D epi is disposed above the first bottom S / D epi; And Depositing a sacrificial dielectric material in the first groove; Forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi; Filling the first gate cut with a dual dielectric filler; Forming a first deep via through an inner dielectric of the dual dielectric filler, wherein the first deep via is in electrical contact with the first back contact placeholder; Removing the first back contact placeholder; Forming a shallow back contact by: Generating a first deep back contact by filling a region previously occupied by the removed first back contact placeholder with a conductive metal in electrical contact with the first deep via and the first bottom S / D epi; And Recessing the first deep back contact; And Forming a back-end-of-line (BEOL) interconnect in electrical contact with the first deep via, and wherein the depth of the shallow back contact prevents a short circuit to a back-side power rail (BSPR).

9. The method according to claim 8, wherein the double-layer dielectric filler comprises a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric comprises the internal dielectric.

10. The method according to claim 8, wherein forming the first deep through-hole comprises removing the internal dielectric of the double-layer dielectric filler to expose the back contact placeholder.

11. The method according to claim 8, further comprising: forming a second gate cut between the second gate and the third gate, wherein the second gate cut exposes a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cut with the double-layer dielectric filler; forming a second deep through-hole through the internal dielectric of the double-layer dielectric filler, wherein the second deep through-hole contacts a silicon layer disposed below the STI layer; performing contact patterning to expose a second top S / D epitaxy of the second gate; forming a front contact in electrical contact with the second top S / D epitaxy and the second deep through-hole, wherein the formed BEOL interconnect is in electrical contact with the front contact; and forming the BSPR, wherein the BSPR is in electrical contact with the second deep through-hole.

12. The method according to claim 11, further comprising: forming a third gate cut between the first gate and the fourth gate, wherein the third gate cut exposes the STI layer between the first gate and the fourth gate; and filling the third gate cut with the double-layer dielectric filler.

13. The method according to claim 12, further comprising: forming a fourth gate cut between the fourth gate and the fifth gate, wherein the fourth gate cut exposes the STI layer between the fourth gate and the fifth gate; filling the fourth gate cut with the double-layer dielectric filler; and forming a third deep through-hole through the internal dielectric of the double-layer dielectric filler, wherein the third deep through-hole contacts a silicon layer disposed below the STI layer between the fourth gate and the fifth gate, and wherein the third deep through-hole is in electrical contact with the formed BEOL interconnect and the formed BSPR.

14. The method according to claim 13, further comprising: forming a second back contact placeholder by: forming a second groove below a region of a second bottom S / D epitaxy for the second gate, wherein the second bottom S / D epitaxy is disposed below the second top S / D epitaxy; and depositing the sacrificial dielectric material in the second groove; removing the second back contact placeholder; forming a second deep back contact by filling a region previously occupied by the removed second back contact placeholder with the conductive metal such that the conductive metal is in electrical contact with the second bottom S / D epitaxy, and wherein the formed BSPR is in electrical contact with the second deep back contact.

15. A computer program product comprising program instructions stored on a computer-readable storage medium, the program instructions being executable by a processor to cause the processor to perform a method on a wafer, the method comprising: forming a first back contact placeholder by the following steps: forming a first trench below a region for a first bottom source / drain epitaxy (S / D epi), wherein a first top S / D epi is disposed above the first bottom S / D epi; and depositing a sacrificial dielectric material in the first trench; forming a first gate cut between a first gate and a second gate surrounding the first bottom S / D epi and the first top S / D epi; filling the first gate cut with a dual dielectric fill; forming a first deep via through an internal dielectric of the dual dielectric fill, wherein the first deep via is in electrical contact with the first back contact placeholder; removing the first back contact placeholder; forming a shallow back contact by the following steps: generating a first deep back contact by filling a region previously occupied by the removed first back contact placeholder with a conductive metal, the conductive metal being in electrical contact with the first deep via and the first bottom S / D epi; and recessing the first deep back contact portion; and forming a back-end-of-line (BEOL) interconnect in electrical contact with the first deep via, and wherein the depth of the shallow back contact prevents a short circuit to a back-side power rail (BSPR).

16. The computer program product according to claim 15, wherein the dual dielectric fill comprises a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric comprises the internal dielectric.

17. The computer program product according to claim 15, wherein forming the first deep via comprises removing the internal dielectric of the dual dielectric fill to expose the back contact placeholder.

18. The computer program product according to claim 15, the method further comprising: forming a second gate cut between the second gate and a third gate, wherein the second gate cut exposes a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cut with the dual dielectric fill; forming a second deep via through the internal dielectric of the dual dielectric fill, wherein the second deep via contacts a silicon layer disposed below the STI layer; performing contact patterning to expose a second top S / D epi of the second gate; forming a front contact in electrical contact with the second top S / D epi and the second deep via, wherein the formed BEOL interconnect is in electrical contact with the front contact; and forming the BSPR, wherein the BSPR is in electrical contact with the second deep via.

19. The computer program product according to claim 18, the method further comprising: forming a third gate cut between the first gate and a fourth gate, wherein the third gate cut exposes the STI layer between the first gate and the fourth gate; and Fill the third gate cut with the double dielectric filler.

20. The computer program product according to claim 19, the method further comprising: Form a fourth gate cut between the fourth gate and the fifth gate, wherein the fourth gate cut exposes the STI layer between the fourth gate and the fifth gate; Fill the fourth gate cut with the double dielectric filler; and Form a third deep via through the inner dielectric of the double dielectric filler, wherein the third deep via contacts a silicon layer disposed below the STI layer between the fourth gate and the fifth gate, wherein the third deep via is in electrical contact with the formed BEOL interconnect and the formed BSPR.

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