Method of separating semiconductor device from substrate

Abstract

A method of separating a semiconductor device from a substrate, the method comprising the steps of: providing a semiconductor structure comprising a semiconductor device, a substrate, and a porous layer of semiconductor material between the semiconductor structure and the substrate; creating a weakened region in the semiconductor structure between the semiconductor device and the substrate; cutting the semiconductor structure along the weakened region; and separating the semiconductor device from the substrate. The weakened region is created in a porous layer of semiconductor material, or in a buffer layer of semiconductor material between the substrate and the porous layer. A semiconductor structure includes a porous layer of semiconductor material and a semiconductor device bonded to a carrier wafer, where the semiconductor device is between the porous layer and the carrier wafer.

Description

Technical Field

[0001] The present invention relates to a method for separating semiconductor devices from a substrate. In particular, the present invention relates to a method for separating optoelectronic semiconductor devices or high electron mobility transistor devices from a substrate comprising a porous layer of semiconductor material. Background Art

[0002] In semiconductor device design, III-V semiconductor materials, particularly group III nitride semiconductor materials, are of particular interest.

[0003] Group III-V semiconductors include binary, ternary, and quaternary alloys of group III elements (such as Ga, Al, and In) and group V elements (such as N, P, As, and Sb), and are of particular interest in a number of applications such as electronics and optoelectronics.

[0004] Of particular interest is the class of semiconductor materials known as group III nitride materials, which includes gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), as well as their ternary and quaternary alloys. (Al, In)GaN is a term encompassing AlGaN, InGaN, and GaN. Group III nitride materials have not only achieved commercial success in solid-state lighting and power electronics, but also exhibit particular advantages in quantum light sources and light-matter interactions.

[0005] Although a variety of group III nitride materials have commercial value, gallium nitride (GaN) is widely regarded as one of the most important new semiconductor materials and is of particular interest in a number of applications.

[0006] The present invention will be described mainly with reference to GaN and InGaN, but may also be applicable to other combinations of group III nitride materials.

[0007] It is known that introducing pores into bulk group III nitrides (such as GaN) can significantly affect their material properties (optical, mechanical, electrical, and thermal, etc.). Therefore, it is of great interest to apply porous GaN in optoelectronics by adjusting various material properties of GaN and group III nitride semiconductors by changing the porosity.

[0008] The inventors of the present invention have also found that by using a porous group III nitride material as a substrate or template for epitaxial growth of additional semiconductor layers and semiconductor devices, the porous layer can provide beneficial properties such as strain relaxation for the epitaxially grown devices. However, after growing the desired semiconductor device, it may be necessary to remove the semiconductor device from the porous template and transfer the semiconductor device to another carrier to fabricate an electronic or optoelectronic device. An object of the present invention is to facilitate the safe and reliable removal of semiconductor devices from the substrate on which they are grown.

[0009] In the present invention, regions or layers of semiconductor material can be made porous by electrochemical etching, as described in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0010] Problems to be Solved

[0011] As part of semiconductor device manufacturing, it is often necessary to separate a semiconductor device from the substrate on which it is grown and transfer it to a separate wafer for further processing. Different types of semiconductor devices can be transferred to a shared carrier wafer before processing the shared wafer to complete the product. For example, it is often necessary to combine multiple different types of LEDs (which emit light at different peak wavelengths) onto a single carrier wafer to manufacture a display device.

[0012] However, traditionally, the step of transferring different semiconductor devices from their original substrates to a shared wafer has several drawbacks. First, different types of semiconductor devices are typically made of different materials, which in turn requires different lift-off processes. For example, red LEDs and blue-green LEDs are typically grown from different semiconductor materials, which require different lift-off processes to separate them from the grown substrate. This increases the difficulty and cost of device manufacturing. Second, the lift-off processes traditionally used to separate devices from their original substrates typically damage the epitaxial layers (epi-layers) of the semiconductor devices. Damage caused by the lift-off process is one of the main causes of yield loss in semiconductor device manufacturing, thereby increasing the manufacturing cost.

[0013] To simplify the LED manufacturing process and reduce large-scale production costs, Poro Technologies has released LEDs with an embedded nanoporous architecture, enabling GaN-based LEDs to output the full color range. These LEDs are described in International Patent Applications PCT / GB2021 / 050152 (published as WO2021 / 148808) and PCT / GB2021 / 052020 (published as WO2022 / 029434). Summary of the Invention

[0014] In a first aspect of the present invention, a method for separating a semiconductor device from a substrate is provided. The method includes the steps of: providing a semiconductor structure including a semiconductor device, a substrate, and a porous layer of semiconductor material between the semiconductor structure and the substrate. The method includes the steps of: creating a weakened zone in the semiconductor structure between the semiconductor device and the substrate; cutting the semiconductor structure along the weakened zone; and separating the semiconductor device from the substrate. The weakened zone may be created in the porous layer of semiconductor material or in a buffer layer of semiconductor material located between the substrate and the porous layer.

[0015] The weakened zone may be created in the porous layer of semiconductor material such that when cutting the semiconductor structure along the weakened zone, the porous layer of semiconductor material is cut. This can be achieved in a variety of ways, as described below.

[0016] Alternatively, if the semiconductor structure includes a buffer layer of semiconductor material located between the substrate and the porous layer, the weakened zone may be created in the buffer layer of semiconductor material. The step of cutting the semiconductor structure along the weakened zone thus cuts the buffer layer of semiconductor material rather than the porous layer. In this embodiment, the porous layer can advantageously act as a protective layer to protect the semiconductor device from the stresses and forces generated during the cutting and separation steps and prevent cracks generated during the cutting process from spreading into the epitaxial structure of the semiconductor device.

[0017] The porous layer of semiconductor material is preferably a porous group III nitride material layer. The porous layer is preferably a porous layer of semiconductor material that extends laterally throughout the semiconductor structure.

[0018] Preferably, the porous layer is continuously porous, for example formed by a continuous porous group III nitride material layer. Alternatively, the porous layer may be a layer of semiconductor material that includes one or more porous regions and one or more non-porous regions such that the porous material does not continuously extend throughout the semiconductor structure layer.

[0019] The porous layer is preferably a porous group III nitride material layer, such as a porous GaN, InGaN, AlGaN, or InAlGaN layer.

[0020] The semiconductor structure is preferably formed entirely of group III nitride (such as GaN, InGaN, AlGaN, or InAlGaN) material.

[0021] The weakened zone preferably includes a weakened layer that extends laterally through the semiconductor structure layer. This can advantageously ensure that the structure is cleanly cut along the weakened zone, thereby minimizing the possibility of cracks extending vertically into other layers of the semiconductor structure that do not include the weakened zone layer.

[0022] Those skilled in the art will understand that, in this context, "lateral" refers to a plane of the semiconductor structure parallel to the substrate plane, while "vertical" refers to a direction orthogonal to the substrate plane, such that successive deposited layers of the semiconductor structure are vertically stacked as they grow upward from the substrate.

[0023] The substrate can be any conventional semiconductor substrate suitable for overgrowth of a group-III nitride semiconductor structure. For example, the substrate can be a silicon, sapphire, SiC, GaN, or β-Ga2O3 wafer. The crystal orientation of the substrate can be polar, semi-polar, or non-polar. The substrate thickness typically varies between 100 μm and 1500 μm.

[0024] The semiconductor structure optionally includes one or more semiconductor material buffer layers located between the substrate and the porous layer. When a semiconductor material buffer layer is present, the semiconductor material buffer layer is preferably a non-semiconductor material porous layer that extends laterally throughout the semiconductor structure and separates the porous layer from the substrate. The one or more buffer layers can be formed of any group-III nitride semiconductor material, such as any (Al, In)GaN alloy combination. Preferably, the one or more buffer layers are formed of an undoped group-III nitride material or an unintentionally doped group-III nitride material.

[0025] In an alternative embodiment, the semiconductor structure may not include any buffer layer located between the porous layer and the substrate. In this embodiment, the porous layer can be in contact with the substrate, and the weakened region will be created in the semiconductor material porous layer.

[0026] The semiconductor structure can optionally include one or more non-semiconductor material porous layers located between the porous layer and the semiconductor device. The number, composition, and structure of these layers can vary according to the requirements of the semiconductor device.

[0027] The step of separating the semiconductor device from the substrate is preferably a "lift-off" step, in which the semiconductor device (and optionally, any additional portions still attached to the device after the cutting structure) is lifted off from the substrate (and optionally, any additional portions still attached to the substrate after the cutting structure).

[0028] The advantage of the method of the present invention is that, during the cutting and peeling process, the porous layer in the semiconductor structure acts as a structural protection layer and a compliant layer, because the porosity of the porous layer increases the ability of the porous layer to bend and absorb the stress and strain applied to the semiconductor structure during the cutting and separation process. This advantageously reduces the damage to the epitaxial layer of the semiconductor device, thereby increasing the yield of the final product. The porous layer also provides various benefits to the overgrown semiconductor device during the epitaxial growth process, and these benefits are inherited and retained even after the porous layer is cut and / or completely removed from the semiconductor device and the semiconductor device is separated from the substrate.

[0029] The step of cutting the semiconductor structure along the weakened area may include mechanically impacting the semiconductor structure to initiate a fracture.

[0030] Alternatively, creating the weakened area may initiate a fracture that propagates through the semiconductor structure to cut the structure without any mechanical initiation.

[0031] After the step of creating the weakened area in the semiconductor structure, the steps of cutting and separating the semiconductor structure may include applying a mechanical force. For example, portions of the semiconductor structure on both sides of the weakened area may be mechanically gripped and pulled apart.

[0032] The semiconductor structure is preferably bonded to a carrier wafer such that the semiconductor device and the porous layer are located between the carrier wafer and the substrate.

[0033] The method preferably includes the step of bonding the semiconductor device to a carrier wafer before and / or before cutting the semiconductor structure to form the weakened area in the semiconductor structure, such that the semiconductor device remains bonded to the carrier wafer when separated from the substrate. This helps to ensure that the semiconductor device is mechanically supported during the cutting and separation process and allows them to be safely removed from the substrate after cutting. The carrier wafer may be a temporary carrier wafer, or alternatively, the carrier wafer may be a substrate containing control circuits for processing into devices.

[0034] Laser Lift-Off

[0035] The weakened area may be created by laser lift-off (LLO). This may include the steps of guiding a laser through the substrate into the semiconductor structure, focusing the laser at a predetermined depth in the semiconductor structure, and melting the semiconductor material at the focus of the laser. Melting the semiconductor material creates a weakened area at a predetermined depth (e.g., in a selected layer) in the semiconductor structure, and then cutting can be easily and cleanly performed.

[0036] The cutting step may be performed using a laser, for example, by using a laser to completely cut the weakened area.

[0037] Laser lift-off is known in industrial LED production. In the conventional methods used today, an ultraviolet laser with a nanosecond pulse width is directed to the back side of the wafer, through the transparent substrate. At high pulse energy, the laser induces the decomposition of GaN at the substrate / GaN interface into metallic gallium and gaseous nitrogen, thereby causing the GaN layer to separate from the substrate.

[0038] To create a weakened zone extending laterally through the semiconductor structure to facilitate a clean cut, the laser is preferably focused at multiple locations within the semiconductor structure, at the same depth within the structure. For example, the laser can be sequentially focused at multiple lateral positions within the same layer of the semiconductor structure to melt the semiconductor material at multiple lateral positions. Melting the material at multiple positions throughout the layer weakens the entire layer such that the combined effect of many melting points makes the entire layer a weakened zone of the structure.

[0039] In a first preferred embodiment of the present invention, the weakened zone is created by laser lift-off in a porous layer of the semiconductor structure. The method can thus include the step of focusing the laser in the porous layer and melting the semiconductor material contained in the porous layer of the semiconductor material. Melting the semiconductor material creates a weakened zone in the porous layer of the semiconductor structure.

[0040] If the porous layer is adjacent to the substrate in the semiconductor structure, the laser can be focused in the porous layer, or at the interface between the porous layer and the substrate. Alternatively, the laser can be focused at the interface between the porous layer and a semiconductor material buffer layer located between the substrate and the porous layer.

[0041] As described above, the semiconductor structure can include one or more semiconductor material buffer layers located between the porous layer and the substrate.

[0042] In a second preferred embodiment of the present invention, the weakened zone is created by laser lift-off in a buffer layer of the semiconductor structure. The method can include the step of focusing the laser in a semiconductor material buffer layer located between the substrate and the porous layer.

[0043] The method can include the step of focusing the laser in the buffer layer.

[0044] The buffer layer can be an undoped semiconductor material layer located between the substrate and the porous layer. Preferably, the buffer layer is located near the substrate, and the method can include the step of focusing the laser at the interface between the buffer layer and the substrate.

[0045] When the weakening region is created in the buffer layer between the porous layer and the substrate, cutting the semiconductor structure along the weakening region creates a fracture in the buffer layer. In this embodiment, the porous layer is located between the fracture and the semiconductor device, and the porous layer advantageously acts as a "crack stop" layer that confines the fracture to the buffer layer and prevents the fracture from vertically propagating into the semiconductor structure. In this embodiment, the porous layer remains attached to the semiconductor device after separation, and the porous layer can act as a compliant layer that manages the stress of the semiconductor device after separation from the substrate.

[0046] Ion Implantation

[0047] In a third preferred embodiment of the present invention, the weakening region can be created by implanting doped ions into a semiconductor material layer. The implanted ions create additional atomic disorder in the semiconductor material layer by displacing some of the atoms in the crystal structure of the layer. This can advantageously weaken the implanted layer, making it easier and more uniform to cut.

[0048] The doped ions are preferably selected from the following list: H+, N+, Ga+, O+, Si+, Mg+, C+.

[0049] The method can include the step of implanting doped ions by ion bombardment, for example, by bombarding the semiconductor structure layer with an ion beam (high energy or low energy - keV - MeV). Other ion implantation methods known in the art can also be used to implant doped ions into the semiconductor structure to create a weakening region.

[0050] The doped ions are preferably implanted during the manufacturing process of the semiconductor structure before overgrowth of the semiconductor device.

[0051] The weakening region can be created by implanting doped ions into the porous layer of the semiconductor material. The ions can be implanted into the porous layer after the porous layer is formed on the substrate, such that the ion - implanted porous layer becomes the weakening region of the structure. Then, additional semiconductor material layers and semiconductor device structures can be epitaxially grown on the ion - implanted porous layer.

[0052] Alternatively, ions can be implanted into a non - porous buffer layer such that the semiconductor structure includes an ion - implanted non - porous buffer layer that acts as the weakening region of the semiconductor structure. The ion - implanted non - porous buffer layer is preferably located between the porous layer and the substrate. Optionally, the ions can be implanted into the non - porous buffer layer before the formation of the porous layer of the semiconductor structure. Then, additional semiconductor material layers and semiconductor device structures can be overgrown on the ion - implanted non - porous buffer layer and the porous layer.

[0053] The method may thus comprise the steps of providing a semiconductor structure by implanting dopant ions into a semiconductor material layer on a substrate to create a weakened zone and forming a semiconductor device on the ion-implanted layer. The method may then comprise the steps of cutting the semiconductor structure along the weakened zone and separating the semiconductor device from the substrate.

[0054] The ion implantation step of forming the weakened zone is preferably carried out during the manufacture of the semiconductor structure, before the semiconductor device is formed. The method may thus comprise the steps of providing a semiconductor structure by implanting dopant ions into a semiconductor material layer on a substrate to create a weakened zone and forming a semiconductor device on the ion-implanted layer. The method may then comprise the steps of cutting the semiconductor structure along the weakened zone and separating the semiconductor device from the substrate.

[0055] The method may comprise the steps of providing a semiconductor structure by implanting dopant ions into a porous semiconductor material layer on a substrate to create a weakened zone in the porous layer and forming a semiconductor device on the ion-implanted porous layer. The method may then comprise the steps of cutting the semiconductor structure along the weakened zone and separating the semiconductor device from the substrate.

[0056] Thermal Gradient

[0057] In a fourth preferred embodiment of the invention, the weakened zone is created by creating a thermal gradient in the porous layer, the direction of the thermal gradient being orthogonal to the plane of the porous layer. By making one side of the porous layer hotter than the other, the semiconductor material on the hotter side can expand while the semiconductor material on the colder side contracts. This difference in thermal expansion and contraction can create stress in the porous layer, which initiates a fracture that propagates through the porous layer to cut the semiconductor structure.

[0058] The thermal gradient can be created by applying a temperature difference between the semiconductor device and the substrate or between the substrate side and the device side of the porous layer.

[0059] The method may comprise the step of applying a thermal gradient of at least 50 degrees Celsius between the semiconductor device and the substrate, or the step of applying a thermal gradient of at least 60, 70, 80, 90 or 100 degrees Celsius between the semiconductor device and the substrate.

[0060] The method may comprise the step of applying a thermal gradient of at least 50 degrees Celsius per micron between the semiconductor device and the substrate, or the step of applying a thermal gradient of at least 60, 70, 80, 90 or 100 degrees Celsius per micron between the semiconductor device and the substrate.

[0061] Post-Separation Steps

[0062] Once the semiconductor structure is cut along the weakened region and the semiconductor device is separated from the substrate, the method may include additional steps of processing the separated semiconductor device into a final product.

[0063] The cutting step creates a cutting surface connected to the semiconductor device (usually through one or more layers of the semiconductor structure) and another cutting surface connected to the substrate (usually through one or more layers of the semiconductor structure). If the weakened region is formed in the porous layer, the cutting surface is formed by the cutting residue of the porous layer; if the structure is cut through the buffer layer, the cutting surface is formed by the cutting surface of the buffer layer.

[0064] Since the cutting process typically forms non-uniform cracks or fractures through the semiconductor structure, the cutting surface is usually rough after the structure is separated. Therefore, it is generally desirable to planarize the cutting surface before further processing.

[0065] The method may further include a step of planarizing the cutting surface connected to the semiconductor device after the semiconductor device is separated from the substrate. The cutting surface is typically formed on a part of the cutting layer of the semiconductor structure, or on a part of the layer adjacent to the cutting layer of the semiconductor structure (since cutting may occur along the interface between layers). For example, the cutting surface may be the remaining part of the porous layer connected to the semiconductor device (optionally connected through an intermediate layer).

[0066] The method may further include a step of planarizing the cutting surface connected to the substrate. For example, the cutting surface may be planarized, and the planarized substrate may be reused as a template for epitaxial growth of semiconductor material. This can advantageously reduce the environmental impact of device processing and lower costs.

[0067] The cutting surface may be planarized by chemical mechanical polishing (CMP) or etching.

[0068] Alternative Methods

[0069] According to a third aspect of the present invention, a method for separating a semiconductor device from a substrate is provided, the method comprising the steps of: providing a semiconductor structure comprising a semiconductor device, a substrate, and a porous layer of semiconductor material between the semiconductor structure and the substrate; bonding the semiconductor structure to a carrier wafer such that the semiconductor device and the porous layer are between the carrier wafer and the substrate; and removing the substrate by polishing, grinding, thinning, wet etching, or dry etching.

[0070] The substrate is preferably a silicon substrate.

[0071] In this case, the porous layer can act as an etch stop layer, a compliant layer, and a support layer during or after the separation process.

[0072] Semiconductor Devices

[0073] The semiconductor device can be a conventional semiconductor device that has been epitaxially grown on a semiconductor template comprising the substrate and the porous region, and preferably includes one or more porous layers of non-semiconductor material located above the porous region. The epitaxial design of such devices is well known in the art, and the present invention is not limited to any particular device type since any type of semiconductor device can be separated from the substrate using the method of the present invention.

[0074] The semiconductor device can be an optoelectronic semiconductor device, such as a light emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL). Alternatively, the semiconductor device can be an electronic or electrical component, such as a high electron mobility transistor (HEMT) or a radio frequency (RF) device.

[0075] According to a third aspect of the present invention, there is provided a semiconductor structure comprising a porous layer of semiconductor material and a semiconductor device bonded to a carrier wafer, wherein the semiconductor device is located between the porous layer and the carrier wafer. The semiconductor device preferably includes an active region, such as a light emitting active region, located between the porous layer and the carrier wafer.

[0076] Preferably, the porous layer of semiconductor material forms the outermost surface of the structure, on the side opposite the carrier wafer to the active region. Alternatively, a buffer layer of semiconductor material can form the outermost surface of the structure, with the porous layer located between the outermost buffer layer and the active region of the semiconductor device.

[0077] The semiconductor structure is preferably a product of the method according to the first or second aspect of the present invention. Thus, after separating the semiconductor device from the original substrate on which it was grown, the device is preferably bonded to the carrier wafer in a "flip-chip" configuration, with the cut surface now forming the outermost surface of the structure, on the side opposite the carrier wafer.

[0078] If the structure is cut through the porous layer, a portion of the porous layer may still be connected to the semiconductor device and form the outermost surface of the resulting semiconductor structure.

[0079] If the structure is cut through a non-porous buffer layer located between the porous layer and the substrate, the porous layer may still be connected to the semiconductor device, and one or more buffer layers may form the outermost surface of the resulting semiconductor structure. Alternatively, if the cut buffer layer is removed during the cutting process and optionally during a subsequent etching / polishing process, the porous layer may form the new outermost surface of the structure.

[0080] The semiconductor structure may include one or more porous layers of non-semiconductor material located between the porous layer and the active region of the semiconductor device.

[0081] The semiconductor device may be an optoelectronic semiconductor device, such as a light-emitting diode (LED) or a vertical-cavity surface-emitting laser (VCSEL). Alternatively, the semiconductor device may be an electronic or electrical component, such as a high electron mobility transistor (HEMT) or a radio frequency (RF) device.

[0082] In a particularly preferred embodiment, the semiconductor device may be an LED, a mini-LED, a micro-LED or a nano-LED. The LED may include a light-emitting region, which preferably includes a multiple quantum well (MQW) containing a plurality of quantum wells (QW), quantum dots, quantum wires or other quantum nanostructures.

[0083] The lateral dimensions (width and length) of the light-emitting region and / or the LED may be greater than 100 μm and less than 300 μm. In this case, the LED may be referred to as a "mini-LED". In a preferred embodiment, the mini-LED may be square, circular or square with rounded corners, and have dimensions of 300 μm × 300 μm, 200 μm × 200 μm, 100 μm × 100 μm.

[0084] The lateral dimensions (width and length) of the light-emitting region and / or the LED may be less than 100 μm. In this case, the LED may be referred to as a "micro-LED". The lateral dimension of the micro-LED is preferably less than 80 μm, 70 μm, 60 μm, 50 μm, 30 μm, 25 μm, 20 μm, 15 μm, 10 μm, 5 μm, 3 μm or 2 μm.

[0085] In a preferred embodiment, the micro-LED may be square, circular or square with rounded corners, and have dimensions of 75 μm × 75 μm, 50 μm × 50 μm, 40 μm × 40 μm, 30 μm × 30 μm, 25 μm × 25 μm, 20 μm × 20 μm, 10 μm × 10 μm, 5 μm × 5 μm, 2 μm × 2 μm, 1 μm × 1 μm, 500 nm × 500 nm or smaller.

[0086] The lateral dimensions (width and length) of the light-emitting region and / or the LED can be less than 1 μm. In this case, the LED can be referred to as a "nano-LED". The lateral dimension of the nano-LED is preferably less than 500 nm, 200 nm, 100 nm, or 50 nm.

[0087] The LED can be circular, triangular, rectangular, square, oval, rhombic, hexagonal, pentagonal, and any combination of these shapes. In the case where the pixel is designed to be an irregular shape, at least one dimension should fall within the dimension range defined above in order to classify the LED as a small LED or a micro-LED. For example, the width or diameter of the LED is preferably less than 100 μm in order to classify the LED as a micro-LED.

[0088] The porous layer can form an active component of the semiconductor device. The porous layer can form an optical component of the semiconductor device. For example, the porous layer can scatter, reflect, or transmit an optical signal or optical emission into or out of the semiconductor device. The porous layer can be configured to form an optical element, such as a grating or a plurality of cones.

[0089] Alternatively, the porous layer can form a passive component of the semiconductor device. The porous layer can, for example, act as a compliant layer or a support layer to prevent cracking of the semiconductor device, or for strain management. The porous layer can act as an etch stop layer in a further device processing step. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] Various embodiments of the present invention will be described with reference to the accompanying drawings, in which:

[0091] Figure 1A is a schematic lateral cross-sectional view of a conventional semiconductor structure;

[0092] Figure 1B is a schematic lateral cross-sectional view of a semiconductor structure including a porous layer of semiconductor material between a substrate and a semiconductor device;

[0093] Figure 1C is a schematic lateral cross-sectional view of a semiconductor structure including a porous layer of semiconductor material between a substrate and a semiconductor device, and a buffer layer between the porous layer and the substrate;

[0094] Figures 2A to 2C is a schematic lateral cross-sectional view showing a semiconductor device according to a first embodiment of the present invention, in which the semiconductor device is being separated from the substrate using laser lift-off;

[0095] Figures 3A to 3Cis a schematic side cross-sectional view showing a semiconductor device according to a second embodiment of the present invention, in which the semiconductor device is being separated from a substrate using laser lift-off;

[0096] Figures 4A to 4C is a schematic side cross-sectional view showing a semiconductor device according to a third embodiment of the present invention, in which the semiconductor device is being separated from a substrate using ion implantation;

[0097] Figures 5A to 5C is a schematic side cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention, in which the semiconductor device is being separated from a substrate using a thermal gradient. Detailed Description

[0098] Figure 1A Shows a layered semiconductor structure 10, in which a conventional semiconductor device structure 20 is epitaxially grown on a semiconductor substrate 30. The semiconductor structure 10 is formed by epitaxially depositing a semiconductor material layer on top of the semiconductor substrate 30. The substrate can be a conventional silicon, sapphire, SiC, GaN or β-Ga2O3 wafer.

[0099] Growing epitaxially upward from the substrate 30, the semiconductor structure 10 comprises:

[0100] - A buffer layer 40, which is, for example, an undoped GaN layer;

[0101] - An undoped GaN layer 50, which can act as a further buffer layer;

[0102] - A NID-GaN (non-intentionally doped GaN) layer 60;

[0103] - A semiconductor device structure 20, which is an LED in the illustrated embodiment, consisting of two doped GaN layers 70, 80 surrounding a light-emitting region 90 containing a plurality of quantum wells (MQW).

[0104] Figure 1B Shows a semiconductor structure 110 that can be used in the present invention, which corresponds to Figure 1A the structure shown, but the undoped GaN layer 50 is replaced by a porous GaN layer 130. The porous GaN layer is preferably an n-doped GaN layer that has been electrochemically porousized by known techniques. The porous region can be provided by epitaxially growing an n-doped group III nitride material region and then growing an undoped group III nitride material layer, and porousizing the n-doped region using the porousization processes in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0105] This porosity results in strain relaxation in the lattice, meaning that subsequent epitaxially grown semiconductor layers benefit from reduced compressive strain in their lattice.

[0106] The porous region can include one or more layers of one or more group III nitride materials and can have a variety of thicknesses. In a preferred embodiment, the porous region can include, for example, GaN and / or InGaN.

[0107] A variety of semiconductor device structures 20 can be overgrown on the porous layer, but a schematic LED device structure is illustrated in the figures. The device can be a high electron mobility transistor (HEMT), a radio frequency (RF) device, an LED, a mini-LED, a micro-LED, or a nano-LED.

[0108] Figure 1C A semiconductor structure 120 that can be used in the present invention is shown, which corresponds to Figure 1B the structure shown, but structure 120 includes an additional undoped GaN buffer layer 140. The buffer layer 140 is located between the porous layer 130 and the substrate 30. The buffer layer 140 is only required in certain embodiments, as described above.

[0109] To fabricate Figure 1B and Figure 1C the semiconductor structures in to separate them from their substrate 20, the topmost layer of the semiconductor device structure 20 is bonded to a carrier wafer 150 via a bonding layer 160. This helps ensure that the semiconductor devices are mechanically supported during the cutting and separation process and allows them to be safely removed from the substrate after cutting. The carrier wafer can be a temporary carrier wafer, or the carrier wafer can be a substrate that includes control circuitry for processing into a device.

[0110] Figure 2A - to Figure 2C - Laser lift-off at the porous layer

[0111] Figures 2A to 2C A first preferred embodiment of the present invention is shown, where laser lift-off (LLO) is used to separate the semiconductor device structure 20 from the substrate 30 in the porous layer 130.

[0112] As Figure 2A shown, the laser 250 is focused at a depth in the semiconductor structure that coincides with the depth of the porous layer 130. The laser then melts the semiconductor material at the focused location in the porous layer 130 to create a series of holes 160 at different locations throughout the porous layer. This weakens the entire porous layer 130 such that the combined effect of the many melted points makes the entire layer a weakened region of the structure. The nitrogen pressure generated when the porous GaN melts ultimately cuts the structure by causing the porous layer to break, as Figure 2B shown.

[0113] Once the semiconductor structure 110 is cut by fracturing the porous layer 130, a first portion 131 of the porous layer remains attached to the substrate 30, while a second portion 132 of the porous layer remains attached to the separated semiconductor structure 200 that includes the semiconductor device 20 and the carrier wafer 150, as Figure 2C shown.

[0114] Since the cutting process typically forms non-uniform cracks or fractures through the semiconductor structure, the cut surface is usually rough after the structure is separated. Thus, it is generally desirable to planarize the cut surface by chemical mechanical polishing (CMP) or etching before further processing. The first porous region 131 and the second porous region 132 can be completely removed by CMP or etching, or they can simply be smoothed to remove the roughness of the exposed cut surface.

[0115] The planarized substrate can be reused as a template for epitaxial growth of semiconductor material, and the semiconductor device 20 can be further processed into a final device.

[0116] Figures 3A to 3C - Laser lift-off at the porous layer

[0117] In a second preferred embodiment of the present invention, a weakened region is created in the buffer layer 140 of the semiconductor structure 120 by laser lift-off.

[0118] As Figure 3A shown, in this embodiment, the laser 250 is focused in the buffer layer 140, for example, at the interface between the buffer layer 140 and the substrate 30. The laser then melts the undoped GaN at multiple locations in the buffer layer 140 to weaken the buffer layer and generate nitrogen gas, thereby creating fractures in the buffer layer 140 to cut the buffer layer, as Figure 3B shown.

[0119] In this embodiment, the porous layer advantageously acts as a "crack stop" layer that confines the fracture to the buffer layer and prevents the fracture from propagating vertically through the semiconductor structure into the active layer of the device structure.

[0120] In this embodiment, the porous layer remains attached to the semiconductor device after separation, and the porous layer can act as a compliant layer that manages the stress of the semiconductor device after separation from the substrate.

[0121] As Figure 3C shown, after cutting, a first portion 141 of the buffer layer 140 remains attached to the substrate 30, while a second portion 142 of the buffer layer remains attached to the separated semiconductor structure 205, which now includes the porous layer 130, the semiconductor device 20, and the carrier wafer 150.

[0122] The separated portion of the semiconductor structure 120 can be further processed as described above with respect to Figures 2A to 2C the description.

[0123] Figures 4A to 4C - Ion implantation in the porous layer

[0124] In a third preferred embodiment of the present invention, a weakened region is created by implanting doping ions 170 into the porous layer of the semiconductor material. By replacing some of the atoms in the crystal structure of the porous layer, the implanted ions create an additional level of atomic disorder in the porous layer of the semiconductor material. This can advantageously weaken the porous layer, making it easier and more uniform to cut.

[0125] The doping ions are preferably selected from: H+, N+, Ga+, O+, Si+, Mg+, C+.

[0126] As Figure 4A shown, the doping ions are implanted into the porous layer 130 by bombarding the porous layer of the semiconductor structure with an ion beam 350 (high energy or low energy - keV - MeV). Other ion implantation methods known in the art can also be used to implant doping ions into the porous layer to create a weakened region.

[0127] The doping ions create atomic disorder in the porous layer to weaken the porous layer 130, causing it to break through the ion - implanted porous layer, as Figure 4B shown.

[0128] Once the semiconductor structure 110 is cut by breaking the porous layer 130, the first part 131 of the porous layer remains attached to the substrate 30, while the second part 132 of the porous layer remains attached to the separated semiconductor structure 200 comprising the semiconductor device 20 and the carrier wafer 150, as Figure 4C shown.

[0129] The separated part of the semiconductor structure 110 can be further processed as described above with respect to Figures 2A to 2C .

[0130] Figures 5A to 5C - Thermal gradient

[0131] In a fourth preferred embodiment of the present invention, a weakened region is created in the porous layer by creating a thermal gradient in the porous layer, the direction of the thermal gradient being orthogonal to the plane of the porous layer.

[0132] As Figure 5A shown, a thermal gradient is created by applying a temperature difference across the semiconductor structure 110, by maintaining the substrate 30 at a higher temperature than the carrier wafer 150. By making one side of the porous layer hotter than the other, the semiconductor material on the hotter side can expand while the semiconductor material on the colder side contracts. This difference in thermal expansion and contraction can create stress in the porous layer, thereby initiating a fracture (as Figure 5B shown), which propagates through the porous layer to cut the semiconductor structure.

[0133] Once the semiconductor structure 110 is cut by fracturing the porous layer 130, a first portion 131 of the porous layer remains attached to the substrate 30 while a second portion 132 of the porous layer remains attached to the semiconductor device 20 and the carrier wafer 150, as Figure 5C shown.

[0134] The separated portion of the semiconductor structure 110 can be further processed as described above with respect to Figures 2A to 2C .

[0135] After separation, thanks to the bonding of the semiconductor device 20 to the carrier wafer 150, where the active region of the semiconductor device is located between the porous layer 130 and the carrier wafer 150, the separated semiconductor structure 200 processed using these methods can be identified.

[0136] If the semiconductor structure 110 has been cut through the porous layer 130, a first portion 131 of the porous layer may still be connected to the semiconductor device and form the outermost surface of the separated semiconductor structure 200.

[0137] If the semiconductor structure 120 has been cut through a non-porous buffer layer between the porous layer and the substrate, the porous layer may still be connected to the semiconductor device, and one or more buffer layers 140 may form the outermost surface of the resulting semiconductor structure. Alternatively, if the cut buffer layer 140 is removed during the cutting process and during subsequent optional etching / polishing processes, the porous layer can form the new outermost surface of the separated semiconductor structure 200.

Claims

1. A method for separating a semiconductor device from a substrate, the method comprising the following steps: Providing a semiconductor structure, the semiconductor structure including a semiconductor device, a substrate, and a porous layer of semiconductor material between the semiconductor structure and the substrate; Creating a weakened region in the semiconductor structure between the semiconductor device and the substrate; Cutting the semiconductor structure along the weakened region; And Separating the semiconductor device from the substrate; Wherein the weakened region is created in the porous layer of semiconductor material, or in a buffer layer of semiconductor material located between the substrate and the porous layer.

2. The method according to claim 1, wherein, The weakened region includes a weakened layer extending laterally through the semiconductor structure layer.

3. The method according to claim 1 or 2, wherein The weakened region is created by laser lift-off.

4. The method according to claim 3, comprising the following steps: Guiding a laser through the substrate into the semiconductor structure; focusing the laser at a predetermined depth in the semiconductor structure; And melting the semiconductor material at the focus of the laser.

5. The method according to claim 4, comprising the following steps: Focusing the laser in the porous layer; and melting the semiconductor material contained in the porous layer of semiconductor material.

6. The method according to claim 4, comprising the following steps: Focusing the laser at the interface between the porous layer and the substrate; and melting the semiconductor material at the interface between the porous layer and the substrate.

7. The method according to claim 4, comprising the following steps: Focusing the laser at the interface between the porous layer and a buffer layer of semiconductor material, the buffer layer of semiconductor material being located between the substrate and the porous layer.

8. The method according to claim 4, comprising the following steps: Focusing the laser in a buffer layer of semiconductor material located between the substrate and the porous layer.

9. The method according to claim 4, comprising the following steps: Focusing the laser at the interface between the buffer layer and the substrate.

10. The method according to claim 7, 8 or 9, wherein The buffer layer is an undoped layer of semiconductor material located between the substrate and the porous layer, preferably, wherein the buffer layer is adjacent to the substrate.

11. The method according to any one of claims 7 to 10, wherein Cutting the semiconductor structure along the weakened region produces a fracture in the buffer layer, and the porous layer confines the fracture to the buffer layer and prevents the fracture from vertically extending into the semiconductor structure.

12. The method according to claim 1 or 2, wherein The weakened region is created by implanting doping ions into the semiconductor structure layer.

13. The method according to claim 12, wherein, The doping ions are selected from the following list: H+, N+, Ga+, O+, Si+, Mg+, C+.

14. The method according to claim 12 or 13, wherein, The method includes the step of implanting doping ions by ion bombardment.

15. The method according to claim 12, 13 or 14, wherein, The doping ions are implanted into the porous layer of the semiconductor structure.

16. The method according to claim 12, 13 or 14, wherein The doping ions are implanted into a buffer layer located between the substrate and the porous layer.

17. The method according to any one of claims 12 to 17, wherein, The doping ions are implanted into the porous layer before the semiconductor device is formed on the semiconductor structure.

18. The method according to claim 1 or 2, wherein Creating the weakened region by creating a thermal gradient in the porous layer, the direction of the thermal gradient being orthogonal to the plane of the porous layer.

19. The method according to claim 18, wherein, Creating a thermal gradient by applying a temperature difference between the semiconductor device and the substrate.

20. The method according to claim 18 or 19, comprising the steps of: Applying a thermal gradient of at least 50 degrees Celsius per micron between the semiconductor device and the substrate, or applying a thermal gradient of at least 60, 70, 80, 90, or 100 degrees Celsius per micron between the semiconductor device and the substrate.

21. The method according to claim 18, 19 or 20, comprising the steps of: Apply a thermal gradient of at least 50 degrees Celsius between the semiconductor device and the substrate, or apply a thermal gradient of at least 60, 70, 80, 90, or 100 degrees Celsius between the semiconductor device and the substrate.

22. The method according to any one of the preceding claims, wherein, Bond the semiconductor device to a carrier wafer before creating the weakened region and cutting the semiconductor structure such that the semiconductor device remains bonded to the carrier wafer when separated from the substrate.

23. The method according to any one of the preceding claims, wherein, The cutting step creates a cut surface connected to the semiconductor device, and the method further includes a step of planarizing the cut surface of the semiconductor device after the semiconductor device is separated from the substrate.

24. The method according to any one of the preceding claims, wherein, The cutting step creates a cut surface connected to the substrate, and the method further includes a step of planarizing the cut surface connected to the substrate.

25. The method according to claim 21, comprising the following steps: Reuse the planarized substrate as a template for semiconductor material regrowth.

26. The method according to any one of claims 20 to 22, wherein The cut surface is planarized by chemical mechanical polishing (CMP) or etching.

27. The method according to any one of the preceding claims, wherein, The porous layer is a porous group III nitride material layer, such as a porous GaN, InGaN, AlGaN, or InAlGaN layer.

28. The method according to any one of the preceding claims, wherein, The semiconductor device is a high electron mobility transistor (HEMT).

29. The method according to any one of claims 1 to 24, wherein The semiconductor device is a radio frequency (RF) device.

30. The method according to any one of claims 1 to 24, wherein The semiconductor device is an LED, a mini-LED, a micro-LED, or a nano-LED.

31. A method of separating a semiconductor device from a substrate, the method comprising the steps of: Provide a semiconductor structure comprising a semiconductor device, a substrate, and a porous layer of semiconductor material between the semiconductor structure and the substrate; Bond the semiconductor structure to a carrier wafer such that the semiconductor device and the porous layer are between the carrier wafer and the substrate; And Remove the substrate by polishing, grinding, thinning, wet etching, or dry etching.

32. The method according to claim 31, wherein, The substrate is a silicon substrate.

33. A semiconductor structure comprising a porous layer of semiconductor material and a semiconductor device bonded to a carrier wafer, wherein the semiconductor device is between the porous layer and the carrier wafer.

34. The semiconductor structure according to claim 33, wherein, The semiconductor device includes an active region, such as a light-emitting active region, and the active region is between the porous layer and the carrier wafer.

35. The semiconductor structure according to claim 33 or 34, wherein, The porous layer of semiconductor material forms the outermost surface of the structure on a side opposite to the active region of the semiconductor device.

36. The semiconductor structure according to claim 33 or 34, wherein A buffer layer of the semiconductor material may form the outermost surface of the structure, and the porous layer is between the outermost buffer layer and the active region of the semiconductor device.

37. The semiconductor structure according to any one of claims 33 to 36, wherein, The semiconductor device is a high electron mobility transistor (HEMT).

38. The semiconductor structure according to any one of claims 33 to 36, wherein, The semiconductor device is a radio frequency (RF) device.

39. The semiconductor structure according to any one of claims 33 to 36, wherein, The semiconductor device is an LED, a mini-LED, a micro-LED, or a nano-LED.

40. The semiconductor structure according to any one of claims 33 to 39, wherein, The porous layer forms an active component of the semiconductor device.

41. The semiconductor structure according to claim 40, wherein, The porous layer forms an optical component of the semiconductor device, such as the porous layer scatters, reflects, or transmits an optical signal or optical emission into or out of the semiconductor device.

42. The semiconductor structure according to claim 40 or 41, wherein, The porous layer is configured to form an optical element, such as a grating or a plurality of cones.

43. The semiconductor structure according to any one of claims 33 to 39, wherein, The porous layer forms a passive component of the semiconductor device.

44. The semiconductor structure according to claim 43, wherein, The porous layer serves as a compliant layer or a support layer for preventing cracks in the semiconductor device.

45. The semiconductor structure according to claim 43, wherein, The porous layer serves as an etch stop layer.

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