Systems and methods for improved signal triggering in spectrum analyzers
By introducing a combination of a leak peak detector and a hysteresis comparator into the spectrum analyzer, the error triggering problem in the spectrum analyzer is solved, achieving a more accurate signal capture and a simplified post-processing process.
Patent Information
- Application Number
- CN202411443935.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-31
- Filing Date
- 2024-10-16
- Publication Date
- 2025-08-01
AI Technical Summary
Existing spectrum analyzers are prone to error triggering during signal triggering, resulting in data loss and increased post-processing complexity, especially in signal analysis of voltage and power levels that are difficult to accurately capture specific events.
Introduced a leak peak detector (LPD) in the spectrum analyzer, by comparing the input signal with the stored attenuation value, selecting a larger value as the trigger signal, and combining with a hysteresis comparator, it suppresses error triggering and ensures that it only triggers when the signal starts.
It effectively reduces error triggers, ensures data acquisition of interest, improves the accuracy and efficiency of signal analysis, and simplifies the post-processing process.
Smart Images
Figure HDA0005087160760000011 
Figure HDA0005087160760000021 
Figure HDA0005087160760000031
Abstract
Description
Technical Field
[0001] The present disclosure generally relates to systems and methods for improving signal triggering in a spectrum analyzer and the like using a Leakage Peak Detector (LPD). Background Art
[0002] Digital Storage Oscilloscopes (DSOs) and spectrum analyzers are widely used in various fields such as electronics, telecommunications, and signal processing. These devices are designed to capture, process, and display waveform signals in digital format. They use Analog-to-Digital Converters (ADCs) to convert analog signals into digital form and then process the digitized signals to extract useful information.
[0003] One of the main components of a spectrum analyzer is an Analog-to-Digital Converter (ADC). The ADC is responsible for converting an analog input signal into a series of digital words or symbols. This conversion process is also a core component of a Digital Storage Oscilloscope (DSO). The ADC block is typically designed to utilize the full dynamic range to obtain maximum resolution and accurate measurements.
[0004] Another integral part of a spectrum analyzer is the trigger system. The trigger system establishes a time point on the input signal at which synchronous acquisition is established. This is particularly useful when analyzing signals with varying voltage and power levels such as data transmissions. The trigger system allows the user to capture specific events or changes in the signal such as the start of a transmission.
[0005] In addition, spectrum analyzers typically employ various signal conditioning processes to correctly scale the waveform within the dynamic range of the ADC and amplifier. These processes include attenuation, DC offset, and variable gain amplification. Summary of the Invention
[0006] In some aspects of the present inventive concept, there is provided a spectrum analyzer trigger system that includes a Frequency Selective Trigger (FST) configured to generate a power signal from an input digital signal, the input power signal having a high level or a low level at a given transmission interval of the input digital signal. The trigger system further includes: a hysteresis comparator configured to generate a trigger pulse at a rising edge or a falling edge of the input power signal; and a Leakage Peak Detector (LPD) configured to suppress false rising edges or falling edges of the input power signal that cause the hysteresis comparator to generate a trigger pulse.
[0007] The digital signal may be a complex IQ signal, and a power signal having an amplitude I 2 +Q 2 may be generated.
[0008] The LPD may include: a comparator configured to compare an input power signal with a current attenuation value; a multiplexer configured, under the control of the comparator, to output one of the input power signal and the current attenuation value as a trigger signal; and a memory unit configured to store the trigger signal for use in determining a next attenuation value in a subsequent operation. The multiplexer may output the larger of the input power signal and the current attenuation value as the trigger signal. Alternatively, the multiplexer outputs the smaller of the input power signal and the current attenuation value as the trigger signal. The LPD may further include a multiplier configured to multiply the trigger signal stored in the memory unit by an attenuation factor to obtain a next attenuation value. The attenuation value may be stored in a register and may be programmable.
[0009] The input power signal may be supplied at a rate of one sample per clock, and the LPD may process the input power signal at a rate of one sample per clock.
[0010] In other aspects of the inventive concept, a polyphase peak detector is provided, which includes a memory element and a plurality of leakage peak detectors (LPDs) connected in a daisy chain, the plurality of leakage peak detectors including a first LPD of the daisy chain and a last LPD of the daisy chain. Each LPD receives an input power signal of M samples per clock, where M is an integer greater than one. Each LPD is configured to compare a corresponding sample of the input power signal with an attenuation value during each clock and output a selected one of the input power signal and the attenuation value as a trigger signal. Except for the last LPD of the daisy chain, the attenuation value of each LPD of the daisy chain is forwarded to each next LPD of the daisy chain for processing. The last LPD of the daisy chain forwards its attenuation value to the memory element for storage therein, and the first LPD of the daisy chain receives the attenuation value stored in the memory element.
[0011] The attenuation value for a given clock in each LPD may be obtained by applying an attenuation factor to the trigger signal of the previous clock. The attenuation value may be stored in a register and may be programmable.
[0012] The input power signal may be derived from a complex IQ signal.
[0013] The trigger signal of the LPD may be forwarded to an edge detection circuit with hysteresis for triggering. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] With reference to the drawings, the above and other aspects and features of the inventive concept will become apparent from the following detailed description, in which:
[0015] Figure 1 is a block diagram of an exemplary digital storage oscilloscope (DSO);
[0016] Figure 2 shows an example of Figure 1 the analog input signal conditioning circuit shown;
[0017] Figure 3 is for reference in describing the Figure 1 ADC and trigger block shown;
[0018] Figure 4 is for reference in describing the Figure 1 acquisition memory and time base system example shown;
[0019] Figure 5 is for reference in describing the Figure 1 DSP display block of;
[0020] Figure 6 is a block diagram of an oscilloscope signal acquisition and processing system;
[0021] Figure 7 is a block diagram of an exemplary signal analyzer;
[0022] Figure 8 generally shows a circuit block diagram for reference in describing the decimation of the output of an ADC;
[0023] Figure 9 is a circuit diagram for reference in describing a leakage peak detector (LPD) according to at least one embodiment of the inventive concept;
[0024] Figure 10 is for reference in describing the operation of the Figure 9 LPD and hysteresis comparator according to at least one embodiment of the inventive concept; and
[0025] Figure 11 is a circuit block diagram of a polyphase peak detector according to at least one embodiment of the inventive concept. Detailed Description
[0026] In the following detailed description, for purposes of explanation and not limitation, representative embodiments that disclose specific details are set forth in order to provide a thorough understanding of the present teachings. However, it will be apparent to those of ordinary skill in the art who have benefited from the present disclosure that other embodiments that deviate from the specific details disclosed herein are still within the scope of the appended claims. In addition, descriptions of well-known devices and methods may be omitted so as not to obscure the description of the example embodiments. Such methods and devices are clearly within the scope of the present teachings. Further, throughout the drawings, like reference numerals refer to the same or similar elements.
[0027] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. The defined terms supplement the technical and scientific meanings of the defined terms that are commonly understood and accepted in the technical field of the present teachings. As used in the specification and the appended claims, the terms "a," "an," and "the" include singular and plural referents unless the context clearly dictates otherwise. Thus, for example, "a device" includes one device and plural devices. Further, for example, when an element is described as being "connected to" another element, the one element may be directly connected to the other element or indirectly connected to the other element operationally.
[0028] Individually, as is traditional in the field of the present inventive concept, example embodiments are described and shown in the drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, in the absence of a contrary indication, units and / or modules implemented by a microprocessor or the like may be programmed using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Moreover, without departing from the scope of the example embodiments, each block, unit, and / or module of the example embodiments may be physically separated into two or more interacting and discrete blocks, units, and / or modules. Conversely, without departing from the scope of the example embodiments, the blocks, units, and / or modules of the example embodiments may be physically combined into more complex blocks, units, and / or modules.
[0029] For context, a spectrum analyzer is typically used to measure data transmissions that have varying voltage and power levels as they transition between different symbols. This means that it is not uncommon for the voltage of such transmissions to have occasional errant power transitions and otherwise remain low throughout the message. It is often desirable to trigger and acquire only at the start of such transmissions, rather than in the middle, but this can be difficult due to the voltage and power differences between different symbols mentioned above, as they often look similar to the start of a transmission.
[0030] A so-called frequency-selective trigger (FST) allows triggering on the rising or falling edge of a power signal. The FST can correctly trigger at the start of a transmission and allow it to be captured, but it can also cause many false triggers around transient high-power transitions. These unwanted triggers can prevent the acquisition system from capturing the desired trigger event, resulting in the loss of useful data. Even if the desired event is found, many unwanted triggers must be removed in post-processing to make the data useful.
[0031] As described herein, the inventive concept relates to adding a leakage peak detector (LPD) to an existing FST in, for example, high-end digital oscilloscopes and spectrum analyzers. The LPD allows the inclusion of a time factor in the triggering process. This in turn allows the user to calibrate the time factor such that they can discard errant power transitions during a transmission and only consider the start of such transmissions. The LPD is an improvement over an FST alone because it allows the introduction of a time decay factor. This time factor can be used to prevent many unwanted triggers that might otherwise occur and ensure that data of interest can always be acquired.
[0032] The LPD circuit of at least some embodiments has a relatively simple circuit structure and operates at a relatively high speed. This is because the LPD uses a simple comparator to select the maximum between an input signal and its own memory. No complex integration is required. Further savings are achieved when the circuit is implemented in a polyphase design. While a slower, larger integrator might reduce the possible number of phases in a design, the simple comparator circuit allows for more phases and thus greater time resolution at the trigger output.
[0033] In some embodiments, the LPD operates on a power signal. When analyzing voltage, there is an inherent phase dependence on the signal, and a sine curve will only cross from below a threshold to above a threshold at specific phases. This is not true for the power of a signal, i.e., the power rise at the start of a transmission will be visible at the same relative time regardless of the phase of the signal. Using the power of the signal not only removes the phase dependence but also allows complex single-sided filtering operations to be performed. This filtering can be used to isolate spectral regions of interest.
[0034] As will be explained later in this document, the LPD of some embodiments works by taking an input power signal and comparing it with an attenuation value stored in a memory. The attenuation rate is programmable. It then selects the larger of the two and forwards it alone to be used as a trigger signal and the next "remembered" signal.
[0035] Before discussing additional aspects of the inventive concept in detail, as background, reference will be made to Figures 1 - 7 describe digital oscilloscopes and spectrum analyzers.
[0036] Reference Figure 1 depicts a digital storage oscilloscope (DSO) 100. The DSO 100 is a type of signal processing device for capturing, processing, and displaying waveform signals in digital format. The DSO 100 includes various components interconnected to show the path taken by an analog signal from input to display.
[0037] The analog signal first enters the DSO 100 through the analog input signal conditioning circuit 101. The analog input signal conditioning circuit 101 is configured to condition the analog signal before it is processed by the DSO 100. This can involve adjusting the amplitude, offset, frequency content, or phase of the analog signal to ensure it is within an acceptable range for the DSO 100.
[0038] After being conditioned, the analog signal is then fed into the analog-to-digital converter (ADC) 102. The ADC 102 is responsible for converting the analog signal into digital format. This involves sampling the analog signal at regular intervals and quantifying each sample to produce a digital representation of the analog signal.
[0039] The digitized signal is then stored in the acquisition memory 103. The acquisition memory 103 serves as a temporary storage area for the digitized signal. It allows the DSO 100 to store the digitized signal for later processing and analysis.
[0040] At the same time, the digitized signal is also passed to the trigger block 104. The trigger block 104 interacts with the time base system 105 to coordinate the timing of the signal processing operations performed by the DSO 100. The trigger block 104 can be configured to generate a trigger signal based on a specific event or condition in the digitized signal. This trigger signal can then be used to synchronize the processing of the digitized signal with other operations of the DSO 100.
[0041] Finally, the processed digitized signal is sent to the digital signal processor (DSP) display block 106 for visualization. The DSP display block 106 is responsible for generating a visual representation of the digitized signal. This visual representation can be displayed on a monitor or other display device, allowing the user to analyze the characteristics of the digitized signal.
[0042] Reference Figure 2 , shows an example of the analog input signal conditioning circuit 101 of Figure 1 . In this example, the analog input signal conditioning circuit 101 includes an attenuator 100a, a DC offset 100b, an amplifier 100c, and an anti-aliasing filter 100d. The attenuator 100a is used to reduce the amplitude of the incoming signal to a level that can be processed by the subsequent stages of the DSO 100. The DC offset 100b is used to shift the voltage of the signal up or down, which can be used to center the signal around a specific voltage level. The amplifier 100c is used to increase the amplitude of the signal, which can be useful for boosting a weak signal to a level that the DSO 100 can effectively process. The anti-aliasing filter 100d is a low-pass filter that is used to ensure that the signal is band-limited before sampling.
[0043] In some cases, the analog input signal conditioning circuit 101 can be configured to perform additional signal processing operations, such as filtering or modulation. These additional operations can be used to further condition the analog signal and enhance the performance and functionality of the DSO 100.
[0044] Reference Figure 3 , provides a circuit diagram to describe Figure 1 the analog-to-digital converter (ADC) 102 and the trigger block 104 shown in N . As previously mentioned, the ADC 102 is responsible for converting the analog signal into a digital format. This conversion process involves sampling the analog signal at regular intervals and quantifying each sample to produce a digital representation of the analog signal. In this example, the ADC 102 is an N-bit analog-to-digital converter, which means that it can represent an analog signal with a resolution of 2
[0045] The trigger block 104 of the example shown includes a trigger coupler 104a, a trigger comparator 104b, and trigger logic 104c. The trigger coupler 104a is used to access the analog input signal. The trigger comparator 104b is used to compare the input
[0046] signal with a reference signal to determine when a trigger event has occurred. The trigger logic 104c is used to generate a trigger signal based on the output of the trigger comparator 104b.
[0047] In some cases, when plotting trigger data from multiple sources, the marker (trigger signal) position can be used to align the data. This involves using the marker position as a reference point in the calculations to determine when to start plotting the data. This can be useful for aligning the data with other signals or events or for synchronizing the data with the operation of other components of the DSO 100.
[0048] In other cases, the marker position can be used to determine the position of the marked sample within the reduced sample set output from the acquisition circuit. This involves using the marker position as a reference point to identify the marked sample within the output data pipeline. This can be useful for tracking the marked sample as it moves through the DSO 100 or for identifying the marked sample for further processing or analysis.
[0049] Reference Figure 4 , a block diagram is provided that describes an example of the acquisition memory 103 and the timebase system 105. As previously described, the acquisition memory 103 is a component of the digital storage oscilloscope (DSO) 100 and serves as a temporary storage area for digitized signals. The acquisition memory 103 allows the DSO 100 to store digitized signals for later processing and analysis. The size of the acquisition memory 103 can vary depending on the specific requirements of the DSO 100. In some cases, the acquisition memory 103 can be large enough to store a large number (i.e., millions to billions) of samples, allowing for a more detailed analysis of the signal. In other cases, the acquisition memory 103 can be smaller, allowing for faster processing of the signal.
[0050] The timebase system 105 is another component of the DSO 100 that interacts with the trigger block 104 to coordinate the timing of the signal processing operations performed by the DSO 100. That is, the timebase system 105 controls the acquisition to store the requested number of samples before and after the marked sample. The system can also store metadata to be used in the signal processing operations. The timebase system 105 can be configured to generate a timing signal based on a specific event or condition in the digitized signal. This timing signal can then be used to synchronize the processing of the digitized signal with other operations of the DSO 100. The timebase system 105 can also be configured to adjust the decimation process to store at a lower sampling rate.
[0051] Figure 5 is a block diagram for reference in the digital signal processor (DSP) display block 106 of the digital storage oscilloscope (DSO) 100. The DSP display block 106 is responsible for generating a visual representation of the digitized signal. This visual representation can be displayed on a monitor or other display device, allowing the user to analyze the characteristics of the digitized signal.
[0052] The DSP display block 106 includes a display 106b and a display digital signal processor (DSP) 106a. The display 106b is the interface through which the visual representation of the digitized signal is presented to the user. The display digital signal processor (DSP) 106a is responsible for processing the digitized signal and generating the visual representation that is displayed on the display 106b.
[0053] The DSP display block 106 interacts with the time base system 105, the acquisition memory 103, the analog-to-digital converter (ADC) 102, the analog input signal conditioning circuit 101, and the trigger block 104. The time base system 105 coordinates the timing of the signal processing operations performed by the DSO 100. The acquisition memory 103 serves as a temporary storage area for digitized signals. The ADC 102 converts analog signals into digital format. The analog input signal conditioning circuit 101 conditions the analog signals before they are processed by the DSO 100. The trigger block 104 generates a trigger signal based on a specific event or condition in the digitized signal.
[0054] In some cases, marker positions can be used to facilitate the drawing operations of the signal processing device. This involves using the marker positions as points in calculations to determine which data in the memory 103 is to be processed and drawn. This can be useful for aligning data with other signals or events or for synchronizing data with the operations of other components of the DSO 100. For example, when drawing trigger data from multiple sources, marker positions can be used to align the triggers or to correct phase offsets introduced during signal acquisition.
[0055] Figure 6 is the overall block diagram of the digital storage oscilloscope 100 including the components described above in conjunction with Figures 2 - 5 description. Additionally, Figure 6 depicts the CPU system 107 that coordinates and directs the operations of the various components, and the bus system 108 through which the various components can communicate with each other.
[0056] Refer to Figure 7 , which shows the block diagram of an exemplary signal analyzer 500. As shown, the signal analyzer 500 includes an attenuator 501 that receives an input signal. The attenuator 501 is used to reduce the amplitude of the incoming signal to a level that can be processed by subsequent stages of the signal analyzer. The attenuated signal is then fed into a bandpass filter 502. The bandpass filter 502 is used to remove unwanted frequency components from the signal, thereby smoothing the signal and reducing noise.
[0057] After being filtered, the signal is then passed to a mixer 504. The mixer 504 also receives a signal from a local oscillator (LO) 503. The LO 503 generates a signal with a constant frequency that is used to mix with the filtered signal. The mixed signal is then processed by the frequency mixer 504. The frequency mixer 504 combines the filtered signal with the signal from the LO 503 to produce a mixed signal with an intermediate frequency that is the frequency difference between the two input signals.
[0058] Then, the mixed signal passes through an intermediate frequency (IF) filter 505. The IF filter 505 is used to further filter the mixed signal, removing unwanted frequency components and leaving the desired frequency band. Then, the filtered mixed signal is converted to digital format by an analog-to-digital converter (ADC) 506. The ADC 506 samples the filtered mixed signal at regular intervals and quantizes each sample to produce a digital representation of the signal.
[0059] The digitized signal is then processed by a digital signal processor (DSP) 507. The DSP 507 performs various signal processing operations on the digitized signal, such as filtering, decimation, and compression. The processed digitized signal is then stored in an acquisition memory 508 for later retrieval and analysis.
[0060] The signal processing apparatus also includes a trigger circuit 509 that generates a trigger signal based on a specific event or condition in the digitized signal. This trigger signal can be used to synchronize the processing of the digitized signal with other operations of the signal processing apparatus. For example, the trigger signal can be used to correct phase offsets introduced during signal acquisition.
[0061] The processed digitized signal is then displayed in various formats on a spectrum analyzer display 510. As an example, these formats can include a frequency domain view and a spectrogram view. Each of these views provides a different perspective on the signal, allowing the user to analyze the signal in various ways.
[0062] Figure 8 is a block diagram for reference in an analog-to-digital converter (ADC) 701, a decimation circuit 702, and a frequency-selective trigger (FST) 703 that can be included in a spectrum analyzer (such as Figure 7 the spectrum analyzer 500).
[0063] As previously discussed, the ADC 701 is responsible for converting the conditioned analog input signal into a series of digital words (also referred to as samples). This conversion process is a core component of the spectrum analyzer. The ADC 701 is typically designed to utilize the full dynamic range to obtain maximum resolution and accurate measurements. In some operational variants, the ADC 701 is configured to receive a broadband signal and generate a power signal based on a selected bandwidth of the broadband signal.
[0064] The decimation circuit 702, which can include a filter to reduce the signal bandwidth, is a component of the spectrum analyzer 500 that operates to reduce the sampling rate of the digital words output by the ADC 701. This is particularly useful when the ADC 701 outputs digital words at a high sampling rate, and it is desirable to process the digital words at a lower sampling rate for further processing and display. In Figure 8In this case, a downsampling by a factor of n is performed, where the output of N GSa / s from the ADC 701 is downsampled to a signal of N / n GSa / s by the downsampling circuit 702. As a non-limiting example, N can be 64 and n can be 16, such that 4 GSa / s is output from the downsampling circuit 702. The downsampling circuit 702 achieves this by bandpass filtering and discarding some of the digital words output by the ADC 701, thereby reducing the sampling rate of the digital words passed for further processing.
[0065] The FST 703 is a component of the spectrum analyzer 500 that generates power signal samples from the digital words output by the ADC 701. The FST 703 operates to calculate, for each digital word output by the downsampling circuit 702, the signal power represented as I 2 +Q 2 . The power signal samples generated by the FST 703 provide a measurement of the power of the signal within the selected bandwidth of the broadband signal received by the ADC 701. The power signal samples are then used for further processing and display.
[0066] Reference Figure 9 shows an example of the Leakage Peak Detector (LPD) 800 of the inventive concept. The LPD 800 is a component of the spectrum analyzer that operates to compare an input power signal with an attenuation value stored in a memory element (delayer) 802 and select the larger value between the input power signal and the attenuation value. The larger value is then forwarded as a trigger signal for further processing.
[0067] The LPD 800 includes a comparator 804, a multiplier 803, a multiplexer 801, and a memory element (delayer) 802. The comparator 804 is configured to compare the input power signal with the attenuation value stored in the memory element 802. Then, the larger value between the input power signal and the attenuation value is selected by the comparator 804.
[0068] In some operational variants, the attenuation value stored in the memory element 802 is obtained by applying an attenuation factor to a previously stored value in the memory element 802. This delay factor can be stored in a register 805 as shown, for example, in Figure 9 . This operational variant allows the attenuation value to be dynamically adjusted based on the previously stored value, thereby providing flexibility in processing the input power signal.
[0069] In other operational variants, the attenuation factor applied to the previously stored value in the memory element 802 to obtain the attenuation value is programmable. This operational variant provides further flexibility in processing the input power signal, as the attenuation factor can be adjusted based on specific requirements or conditions.
[0070] The larger value selected by the comparator 804 is then forwarded as a trigger signal to the hysteresis comparator 900 for triggering. The hysteresis comparator 900 is configured to receive the trigger signal and generate a trigger event based on the trigger signal. This functional variation allows the trigger signal to be used to trigger a specific event or change in the trigger signal, such as the start of a transmission.
[0071] In some configuration variations, the output of the multiplexer 801 is fed to the next block in the chain, and the first in the chain is fed with the value from the previous clock cycle. This configuration variation allows the input power signal to be processed in a sequential manner, thereby providing efficient processing of the input power signal.
[0072] In other configuration variations, the circuit is implemented as a programmable shift divider instead of a multiplier for faster operation in hardware. This configuration variation allows the circuit to operate at a higher speed, thereby improving the overall performance of the spectrum analyzer 500.
[0073] Reference Figure 10 , an example is presented comparing the benefits of having no LPD 800 with the trigger pulse generation of an implementation with LPD 800. It will be understood that the waveforms presented in these figures are for illustrative purposes only and may not be exact representations.
[0074] Figure 10 The top represents the case where no LPD800 is provided between the output of the FST 300 and the input of the hysteresis comparator 900. In this case, the output of the FST 300 ( Figure 10 the power signal in
[0075] In Figure 10 the example, the power signal is shown to have three positive transitions above the high threshold. These positive transitions are marked as circle-1, circle-2, and circle-3 in the figure. The first and third positive transitions (circle-1 and circle-3) represent the start of data transmissions that appropriately result in trigger pulses at the output of the comparator 900. However, the middle transition (circle-2) is a false trigger pulse (in Figure 10A temporary high-power transition of the error marked as X). This is because the power signal drops below the lower threshold after the first transition (cycle - 1), thereby setting (or preparing) the comparator 900. In this set state, when the power signal crosses the upper threshold during its rise to the second positive transition (cycle - 2), an error pulse is generated.
[0076] Now turning to Figure 10 the lower half of, which shows the corresponding output signal of the LPD 800. That is, as previously described, the LPD 800 compares the input power signal with the attenuation value stored in the memory element. Then the larger value between the input power signal and the attenuation value is selected and forwarded as the trigger signal.
[0077] Therefore, the rising slope of the output of the LPD 800 is determined by the rate at which the power signal increases. A flat horizontal section appears when the power is constant (or almost constant but flattened due to the leakage time constant). In other words, the rising section and the flat section of the output signal of the LPD 800 basically reflect the behavior of the power signal.
[0078] On the other hand, the negative slope of the output signal of the LPD 800 is determined by the slower of (1) the attenuation of the power signal or (2) the attenuation of the leakage peak detector. In the Figure 10 example, the attenuation of the leakage peak detector is slower than the attenuation of the power signal (shown at the top of the Figure 10 ). Thus, the negative slope of the output signal of the LPD 800 decays at a rate slower than those of the power signal. In the case of the negative slope immediately following the first positive transition (cycle - 1), the signal amplitude is prevented from dropping below the lower threshold. Thus, the comparator 900 is not set or prepared, and therefore no trigger pulse is generated when the output signal of the LPD 800 increases above the upper threshold during the second positive transition (cycle - 2).
[0079] In this way, the LPD 800 and the hysteresis comparator 900 can effectively prevent unwanted triggering caused by incorrect power transitions in the input power signal. By applying a slow decay to the power transition and using a hysteresis comparator with low and high hysteresis bands, the LPD 800 and the hysteresis comparator 900 can ensure the acquisition of data of interest and effectively filter out unwanted triggers.
[0080] Variations of the above operations will be obvious to those skilled in the art. For example, in the Figure 10In the example, the input power signal has a high level at a given transmission interval of the input digital signal. However, the input power signal may alternatively have a low level at the given transmission interval of the input digital signal. In this case, in some embodiments, the hysteresis comparator 900 may be set (or prepared) when the input power signal exceeds the upper threshold, and then triggered to output a pulse when the input power signal drops below the lower threshold. That is, instead of the LPD 800 selecting the larger of the input power signal and the attenuation value, the smaller of the input power signal and the attenuation value will be selected.
[0081] As another example, in the above embodiment, the attenuation value is obtained by multiplying the output of the multiplexer (i.e., the power signal or the previous attenuation value) by the attenuation factor. However, the inventive concept is not limited to this manner. For example, the attenuation value may be obtained by subtracting a fixed value from the multiplexer output, with clipping at 0 to prevent the signal from becoming negative. In this case, the multiplier will be replaced by a subtractor and a limiter.
[0082] Reference Figure 11 , an example of a polyphase peak detector is shown. The polyphase peak detector includes a plurality of leaky peak detectors (LPDs) 901a, 901b, 9'01c, and 901d and a memory element (delayer) 902. Here, the LPDs are daisy-chained to produce a designed polyphase version. Each phase of the peak detector forwards its signal together with the attenuation factor applied to the next phase. The final phase (LPD 901d) stores its attenuation value in the memory element 902, which is read by the first phase (LPD 901a) in the next clock cycle. Each of the LPDs 901a, 901b, 901c, and 901d may be configured as Figure 9 as in Figure 9 shown, except that the memory element 802 shown may be omitted.
[0083] In some operational variants, due to processing limitations, the circuit processes multiple samples in parallel. This operational variant allows for efficient processing of the input power signal because multiple samples can be processed simultaneously. This can be particularly useful when the input power signal contains a large number of samples, which would otherwise take a long time to process sequentially.
[0084] Each LPD in the polyphase peak detector operates in parallel with the other LPDs. This means that each LPD can process different samples of the input power signal simultaneously with the other LPDs. This parallel processing ability allows the polyphase peak detector to process multiple ( Figure 11There are M (where M is a positive integer) samples in the middle, thereby improving the overall performance of the spectrum analyzer. As a non-limiting example, M can be equal to 10. The resulting output signal can then be sent to a regular edge detection circuit with hysteresis for triggering, thereby achieving the desired time decay effect.
[0085] Although the present invention has been described and illustrated in detail in the drawings and the foregoing description, such description and illustration should be considered illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention. Although representative embodiments are disclosed herein, those of ordinary skill in the art will understand that many variations are possible according to this teaching and are still within the scope of the appended claims. Therefore, the present invention is not limited except as defined in the appended claims.
[0086] The present invention also includes the following items: 1. A spectrum analyzer (500) triggering system, comprising: A frequency selection trigger (FST(300)), configured to generate a power signal from an input digital signal, the input power signal having a high level or a low level at a given transmission interval of the input digital signal; A hysteresis comparator (900), configured to generate a trigger pulse at a rising edge or a falling edge of the input power signal; and A leakage peak detector (LPD(800)), configured to suppress false rising edges or falling edges of the input power signal that cause the hysteresis comparator (900) to generate a trigger pulse. 2. The spectrum analyzer (500) triggering system according to item 1, wherein the digital signal is a complex IQ signal, and the power signal with an amplitude of I 2 +Q 2 is generated. 3. The spectrum analyzer (500) triggering system according to item 1, wherein the LPD(800) comprises: A comparator (804), configured to compare the input power signal with a current attenuation value, A multiplexer (801), controlled by the comparator (804), configured to output one of the input power signal and the current attenuation value as a trigger signal; and A memory (103) unit, configured to store the trigger signal for use in determining the next attenuation value in subsequent operations. 4. The spectrum analyzer (500) triggering system according to item 3, wherein the input power signal has a high level at a given transmission interval of the input digital signal, and the multiplexer (801) outputs the larger of the input power signal and the current attenuation value as the trigger signal. 5. The spectrum analyzer (500) triggering system according to item 3, wherein the input power signal has a low level at a given transmission interval of the input digital signal, and the multiplexer (801) outputs the smaller of the input power signal and the current attenuation value as the trigger signal. 6. The spectrum analyzer (500) triggering system according to item 3, wherein the LPD (800) further includes a multiplier (803) configured to multiply the trigger signal stored in the memory (103) unit by an attenuation factor to obtain the next attenuation value. 7. The spectrum analyzer (500) triggering system according to item 6, further comprising a register (805) for storing the attenuation value. 8. The spectrum analyzer (500) triggering system according to item 7, wherein the attenuation factor is programmable. 9. The spectrum analyzer (500) triggering system according to item 1, wherein the input power signal is supplied at a rate of one sample per clock, and the LPD (800) processes the input power signal at a rate of one sample per clock. 10. A polyphase peak detector, comprising: A memory element (802); and A plurality of leakage peak detectors (LPDs) connected in a daisy chain, the plurality of leakage peak detectors including a first LPD (800) of the daisy chain and a last LPD (800) of the daisy chain, each LPD (800) receiving an input power signal of M samples per clock, where M is an integer greater than one, wherein each LPD (800) is configured to compare a corresponding sample of the input power signal with an attenuation value during each clock period, and output a selected one of the input power signal and the attenuation value as a trigger signal, Among them, except for the last LPD (800) of the daisy chain, the attenuation value of each LPD (800) in the daisy chain is forwarded to each next LPD (800) in the daisy chain for processing, and among them, the last LPD (800) of the daisy chain forwards its attenuation value to the memory element (802) for storage therein, and the first LPD (800) of the daisy chain receives the attenuation value stored in the memory element (802). 11. The polyphase peak detector according to item 10, wherein the attenuation value of a given clock in each LPD is obtained by applying an attenuation factor to the trigger signal of the previous clock. 12. The polyphase peak detector according to item 11, further comprising a register for storing the attenuation value. 13. The polyphase peak detector according to item 12, wherein the attenuation factor is programmable. 14. The polyphase peak detector according to item 10, wherein the input power signal is derived from a complex IQ signal. 15. The polyphase peak detector according to item 10, wherein the trigger signal of the LPD is forwarded to an edge detection circuit with hysteresis for triggering.
Claims
1. A trigger system for a spectrum analyzer (500), comprising: A frequency selection trigger (FST(300)), configured to generate a power signal from an input digital signal, the input power signal having a high level or a low level at a given transmission interval of the input digital signal; A hysteresis comparator (900), configured to generate a trigger pulse at a rising edge or a falling edge of the input power signal; And A leakage peak detector (LPD(800)), configured to suppress false rising edges or falling edges of the input power signal from causing the hysteresis comparator (900) to generate a trigger pulse.
2. The spectrum analyzer (500) triggering system according to claim 1, wherein, The digital signal is a complex IQ signal, and generates the power signal having an amplitude of I 2 +Q 2 thereof.
3. The spectrum analyzer (500) triggering system according to claim 1, wherein, The LPD(800) includes: A comparator (804), configured to compare the input power signal with a current attenuation value; A multiplexer (801), controlled by the comparator (804), configured to output one of the input power signal and the current attenuation value as a trigger signal; and A memory (103) unit, configured to store the trigger signal for use in determining a next attenuation value in a subsequent operation.
4. The spectrum analyzer (500) triggering system according to claim 3, wherein, The input power signal has a high level at a given transmission interval of the input digital signal, and the multiplexer (801) outputs the larger of the input power signal and the current attenuation value as the trigger signal.
5. The spectrum analyzer (500) triggering system according to claim 3, wherein, The input power signal has a low level at a given transmission interval of the input digital signal, and the multiplexer (801) outputs the smaller of the input power signal and the current attenuation value as the trigger signal.
6. The spectrum analyzer (500) triggering system according to claim 3, wherein, The LPD(800) further includes a multiplier (803), configured to multiply the trigger signal stored in the memory (103) unit by an attenuation factor to obtain the next attenuation value.
7. The trigger system for a spectrum analyzer (500) according to claim 6, further comprising a register (805) for storing the attenuation value.
8. The spectrum analyzer (500) triggering system according to claim 7, wherein, The attenuation factor is programmable.
9. The spectrum analyzer (500) triggering system according to claim 1, wherein, The input power signal is supplied at a rate of one sample per clock, and the LPD(800) processes the input power signal at a rate of one sample per clock.
10. A polyphase peak detector, comprising: A memory element (802); And A plurality of leakage peak detectors (LPD) connected in a daisy chain, the plurality of leakage peak detectors including a first LPD(800) of the daisy chain and a last LPD(800) of the daisy chain, each LPD(800) receiving an input power signal of M samples per clock, where M is an integer greater than one. Wherein each LPD(800) is configured to compare a corresponding sample of the input power signal with an attenuation value during each clock period, and output a selected one of the input power signal and the attenuation value as a trigger signal. Among them, except for the last LPD (800) of the daisy chain, the attenuation value of each LPD (800) of the daisy chain is forwarded to each next LPD (800) of the daisy chain for processing, and Among them, the last LPD (800) of the daisy chain forwards its attenuation value to the memory element (802) for storage therein, and the first LPD (800) of the daisy chain receives the attenuation value stored in the memory element (802).