Output current detection method, electronic equipment and storage medium thereof

Abstract

The embodiment of the invention discloses an output current detection method, electronic equipment and a storage medium thereof. The method comprises the following steps: acquiring average current of a switching tube of the switched capacitor converter in N switching periods; and obtaining the output current of the switched capacitor converter based on the duty ratio of the switching tube and the average current. According to the embodiment of the invention, the output current is obtained by detecting the current of the switching tube and the duty ratio of the corresponding switching tube according to the relation between the current of the switching tube and the output current, and a sampling resistor is prevented from being additionally arranged in an output loop, so that the system loss is reduced; the heat dissipation area is reduced, the power density of the switched capacitor converter is improved, and the possibility that a sampling result is easily influenced by switching noise interference when a sampling resistor is additionally arranged in a high-frequency switching loop is avoided.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of switched capacitors, and in particular, to a method for detecting output current, an electronic device, and a storage medium thereof. Background Art

[0002] With the rapid development of artificial intelligence technology, the surge in computing power demand has driven the evolution of hardware systems towards low voltage and high current. In this context, DrMOS (Driver-MOSFET integrated module) has become the core support technology for modern power systems due to its high integration, high efficiency, and optimized thermal management capabilities. Compared with the problems of high parasitic parameters and slow dynamic response caused by the separation of the driver and MOSFET in traditional discrete solutions, DrMOS integrates the two in a single package, significantly reducing the board area (which can be reduced to one-fourth of the traditional design), while reducing power loss by more than 15% and effectively suppressing high-frequency switching noise.

[0003] In the field of current sampling technology, DrMOS has achieved a revolutionary breakthrough. Traditional DCR sampling relies on the DC resistance of the inductor and an external RC circuit, and has defects such as accuracy problems caused by poor temperature coefficients, complex debugging, and inability to detect inductor saturation in real time. DrMOS uses a single-die current mirror technology to directly output a mirror current that is strictly proportional to the inductor current through the CS pin, achieving Cycle-by-Cycle precise monitoring with an error controllable within ±2%. This technology has the characteristic of temperature self-compensation and is independent of changes in on-resistance, duty cycle, and frequency, significantly improving the detection accuracy of each phase current. The current detection mechanism using DrMOS can replace the traditional output current detection network composed of sampling resistors, reducing system loss, reducing board area, and increasing power density.

[0004] In some specific topologies using DrMOS, such as switched-cap (switch-cap) converters, the current signal generated by DrMOS cannot directly obtain the actual required output current, causing difficulties in detecting and protecting the output current. Existing switch-cap converters generally adopt an output current detection scheme, that is, a sampling resistor R is connected in series in the inductor and output capacitor loop. CS Then, signal conversion is performed through a signal processing circuit such as an operational amplifier, and then analog-to-digital conversion is performed through the ADC of the controller to finally obtain the output current. This method requires an additional sampling resistor, additional system loss, a larger heat dissipation area, greatly reduces the power density of the power system, and the sampling resistor in the high-frequency switching loop is easily affected by switching noise, which affects the final sampling result. Summary of the Invention

[0005] The technical problem mainly solved by the embodiments of the present invention is to provide an output current detection method, an electronic device and a storage medium thereof, which can solve at least some defects existing in existing switched-capacitor converters.

[0006] In a first aspect, an embodiment of the present invention provides an output current detection method applied to a switched-capacitor converter, including: obtaining an average current of a switching transistor of the switched-capacitor converter within N switching cycles; and obtaining an output current of the switched-capacitor converter based on a duty cycle of the switching transistor and the average current.

[0007] Optionally, the switching transistor includes two main switching transistors and two synchronous rectifier transistors. The obtaining the output current of the switched-capacitor converter based on the duty cycle of the switching transistor and the average current includes: obtaining a duty cycle of the main switching transistor within the N switching cycles; obtaining an average duty cycle according to the N duty cycles of the main switching transistor; and obtaining the output current based on the average duty cycle and the average current.

[0008] Optionally, the obtaining the output current based on the average duty cycle and the average current includes: determining whether the average duty cycle is greater than 0.5; if so, using a preset first operation formula to obtain the output current according to the average duty cycle and the average current; if not, using a preset second operation formula to obtain the output current according to the average duty cycle and the average current.

[0009] Optionally, when the average current is an average value of currents of the two main switching transistors and the two synchronous rectifier switching transistors within the N switching cycles,

[0010] The first operation formula is:

[0011] I OUT =[1 / (1 + d 2 )]×I Q_all ;

[0012] The second operation formula is:

[0013] I OUT =[2 / (2 + d)]×I Q_all ;

[0014] Wherein, I OUT is the output current, d is the average duty cycle, and I Q_all is the average current value.

[0015] Optionally, when the average current is an average value of currents of the two synchronous rectifier switching transistors within the N switching cycles,

[0016] The first operation formula is as follows:

[0017] I OUT = [1 / (1 - d 2 )] × I Q_all ;

[0018] The second operation formula is as follows:

[0019] I OUT = [2 / (2 - d)] × I Q_all ;

[0020] Wherein, I OUT is the output current, d is the average duty cycle, and I Q_all is the average current value.

[0021] Optionally, obtaining the average current of the switching transistors of the switched-capacitor converter within N switching cycles includes: within the N switching cycles, obtaining the currents of the two main switching transistors and the two synchronous rectifier transistors; within each switching cycle, summing up the currents of the two main switching transistors and the two synchronous rectifier transistors to obtain the total switching current; converting the total switching current into a voltage signal; sampling the voltage signals of the N switching cycles to obtain an output data stream; and performing an integration process on the output data stream to obtain the average current.

[0022] Optionally, obtaining the average current of the switching transistors of the switched-capacitor converter within N switching cycles includes: within the N switching cycles, obtaining the currents of the two synchronous rectifier transistors; within each switching cycle, summing up the currents of the two synchronous rectifier transistors to obtain the total switching current; converting the total switching current into a voltage signal; sampling the voltage signals of the N switching cycles to obtain an output data stream; and performing an integration process on the output data stream to obtain the average current.

[0023] Optionally, performing an integration process on the output data stream to obtain the average current includes: integrating the output data stream; when the integration time reaches the N switching cycles, stopping the integration to obtain an average voltage;; converting the average voltage into the average current.

[0024] Optionally, the two main switching transistors include a first main switching transistor and a second main switching transistor; the first main switching transistor and the second main switching transistor are integrated in a first switching transistor driving integrated module, and the currents of the first main switching transistor and the second main switching transistor are obtained through an internal current mirror of the first switching transistor driving integrated module.

[0025] Optionally, the two synchronous rectifier diodes include a first synchronous rectifier diode and a second synchronous rectifier diode; the first synchronous rectifier diode and the second synchronous rectifier diode are integrated in the second switch driving integrated module, and the current of the first synchronous rectifier diode and the current of the second synchronous rectifier diode are obtained through the internal current mirror of the second switch driving integrated module.

[0026] In a second aspect, an embodiment of the present invention provides an electronic device, including: at least one processor; at least one network interface, the network interface is communicatively connected to the corresponding processor; and a memory communicatively connected to the at least one processor; wherein, the network interface is used to establish a communication connection between the processor and other external devices; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute an output current detection method as described in the first aspect.

[0027] In a third aspect, an embodiment of the present invention provides a non-volatile computer storage medium, the computer storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by one or more processors, the one or more processors can execute an output current detection method as described in the first aspect.

[0028] The beneficial effects of the embodiments of the present invention are: different from the prior art, the embodiments of the present invention are directed to a switched-capacitor converter. According to the relationship between the switch current and the output current, by detecting the switch current and the duty cycle of the corresponding switch, the output current is obtained, avoiding adding an additional sampling resistor in the output loop, thereby reducing system loss, reducing the heat dissipation area, improving the power density of the switched-capacitor converter, and also avoiding the possibility that adding a sampling resistor in the high-frequency switching loop is vulnerable to switch noise interference and affects the sampling result. Description of the Drawings

[0029] One or more embodiments are exemplarily illustrated by corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0030] Figure 1 is a schematic diagram of the output current detection structure of the existing switched-capacitor converter;

[0031] Figure 2 is the circuit schematic diagram of the switched-capacitor converter;

[0032] Figure 3 is the waveform diagram of each switch current when the duty cycle of the main switch is less than or equal to 50%;

[0033] Figure 4 It is the waveform diagram of each switching tube current when the duty ratio of the main switching tube is greater than 50%;

[0034] Figure 5 It is the schematic flow chart of an output current detection method provided by an embodiment of the present invention;

[0035] Figure 6 It is the schematic diagram of the output current detection structure of the first switching capacitor converter provided by an embodiment of the present invention;

[0036] Figure 7 It is the schematic diagram of the output current detection structure of the second switching capacitor converter provided by an embodiment of the present invention;

[0037] Figure 8 It is the schematic diagram of the output current detection structure of the third switching capacitor converter provided by an embodiment of the present invention;

[0038] Figure 9 It is the schematic diagram of the output current detection structure of the fourth switching capacitor converter provided by an embodiment of the present invention;

[0039] Figure 10 It is the schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Embodiment

[0040] For the convenience of understanding the present application, the present application will be described in more detail below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is expressed as "fixed to" another element, it can be directly on the other element, or there can be one or more intermediate elements therebetween. When an element is expressed as "connected to" another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween. The terms "upper", "lower", "inner", "outer", "bottom", etc. used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0041] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in this specification in the description of the present application are only for the purpose of describing specific embodiments and are not used to limit the present application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0042] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0043] The technical solutions in the present application will be described below in conjunction with the accompanying drawings.

[0044] Figure 1 Shown is the output current detection structure diagram of a traditional switch-cap converter, which is a prior art and not the technical solution proposed by the present application.

[0045] Refer to Figure 1 , the switched-capacitor converters in the prior art mainly include: a main circuit part and a control and detection part. The main circuit part includes: a power input terminal V IN , switching transistors Q1, Q5, Q2, Q6, flying capacitor C FLY , inductors L1, L2, output capacitor C O and load resistor R LOAD ; the control and detection part includes: a sampling resistor R CS connected in series in the output current path, a signal processing module 10 and a control module 20. The control module 20 internally includes an analog-to-digital conversion unit 210 and a data conversion unit 220.

[0046] The working principle of the switched-capacitor converter in the prior art is as follows: the power supply voltage V IN passes through the high-frequency switching actions of switching transistors Q1, Q5, Q2, Q6, and transfers energy to the output terminal via the flying capacitor C FLY and inductors L1, L2 to form a stable output voltage V OUT for the load R LOAD to use. During the operation of the switched-capacitor converter, the four switching transistors are switched according to a specific control strategy to achieve efficient energy transfer.

[0047] For the detection of the output current, the method adopted in the prior art is: a sampling resistor R O is connected in series in the loop of inductors L1, L2 and output capacitor C CS . When the current I OUT flows through the sampling resistor R CS , a voltage drop proportional to the current will be generated across it. This voltage signal is conditioned and amplified by the signal processing module 10, and then sent to the analog-to-digital conversion unit 210 (such as an ADC) inside the control module 20 for analog-to-digital conversion. The converted digital signal is processed by the data conversion unit 220, and finally a digital value representing the output current I OUT is obtained.

[0048] The signal processing module 10 in the prior art usually includes signal processing circuits such as operational amplifiers, and mainly performs the following functions: Amplification of voltage signals: Since the resistance value of the sampling resistor R CS is usually small (in the milliohm range), the generated voltage signal is relatively weak and needs to be amplified; Signal filtering: Remove high-frequency switching noise and extract the true current signal; Level conversion: Adjust the signal to the input range acceptable to the ADC of the control module 20; Common-mode rejection: Reduce common-mode interference through a differential structure; The analog-to-digital conversion unit 210 in the control module 20 is responsible for converting the analog voltage signal into a digital signal, while the data conversion unit 220 is responsible for processing the digital signal into the actual output current value according to a preset algorithm.

[0049] Although the above solution can achieve the detection of the output current, there are multiple technical defects: First, the series sampling resistor R CS will cause additional power loss. Especially in high-current application scenarios, even if a very small resistance value sampling resistor (such as 1 mΩ) is used, significant power loss (P = I 2 R) will occur under the condition of dozens of amperes of current; Second, the heat generated by the sampling resistor requires additional heat dissipation design, increasing the demand for heat dissipation area; Third, additional components such as sampling resistors and signal conditioning circuits significantly increase the circuit board occupation area and reduce the power density of the power supply system; Fourth, the sampling resistor is in a high-frequency switching loop and is easily affected by switching transients and electromagnetic interference (EMI), reducing the sampling accuracy; Finally, parameters such as the temperature coefficient and parasitic inductance of the sampling resistor will also affect the measurement accuracy, especially in a working environment with large temperature changes.

[0050] For modern power supply systems, especially for the power supply requirements of high-performance computing devices such as artificial intelligence hardware, power density, efficiency, and accurate current monitoring become increasingly important. Under the trend of low voltage and high current, the disadvantages of the traditional sampling resistor scheme become more obvious. For example, in a typical AI accelerator power supply scenario with a 12V input and a 1V / 100A output, the sampling resistor scheme may cause an additional 1-3% efficiency loss, and at the same time increase the heat dissipation design difficulty by 30-50%.

[0051] Example of power loss calculation introduced by the sampling resistor: Assume a 1 mΩ sampling resistor is used, and at 100A current, the power loss is P = I 2 R = 100 2 ×0.001 = 10W. And the output power of the entire power supply system is P = V×I = 1V×100A = 100W. Then the loss ratio introduced by the sampling resistor is 10 / 100 = 10%, significantly reducing the system efficiency. At the same time, a heat dissipation scheme needs to be designed for the additional 10W of heat, increasing the system volume and cost.

[0052] The signal processing flow of the prior art solution is also relatively complex: First, the current signal must be converted into a voltage signal, then amplified and filtered, then converted into a digital signal through an ADC, and finally the output current value is obtained through data processing. The multi-stage signal processing not only increases the design complexity but also may introduce various errors and delays, affecting the dynamic performance and protection response speed of the system.

[0053] Refer to Figure 2 , the main circuit block diagram structure of the switched-capacitor converter includes: input voltage terminal VIN, first main switch Q1, first synchronous rectifier switch Q5, second main switch Q2, second synchronous rectifier switch Q6, flying capacitor C FLY , first inductor L1, second inductor L2, output capacitor C O and load resistor R LOAD . Figure 2 also marks the key current paths, including first inductor current I1, second inductor current I2, and output current I OUT .

[0054] The working mode of the switched-capacitor converter is as follows: The first main switch Q1 and the second main switch Q2 are used as the main control switches. The duty cycles of their conduction in one switching period are equal, and the switching signals of the two are 180 degrees out of phase. The first synchronous rectifier switch Q5 is complementary to the conduction state of the first main switch Q1, and the second synchronous rectifier switch Q6 is complementary to the conduction state of the second main switch Q2. Through the coordinated operation of the four switches, efficient energy transfer from the input end to the output end is achieved.

[0055] In the switched-capacitor converter, the flying capacitor C FLY acts as a charge pump. Through the switching of the switches for charging and discharging, cooperating with the two inductors L1 and L2, a specific electric energy conversion path is formed. When the circuit operates stably, the currents I1 and I2 in the two inductors L1 and L2 will be directly related to the output current I OUT , that is, the output current I OUT is equal to the sum of the two inductor currents I1 and I2.

[0056] It should be noted that the inductor L1 and the inductor L2 can be two windings of a coupled inductor or two independent inductors.

[0057] According to the different duty cycles of the main switch, the working states of the switched-capacitor converter can be divided into two cases: the case where the duty cycle is less than or equal to 50% and the case where the duty cycle is greater than 50%. Refer to Figure 3 and Figure 4 , the following will analyze the two cases in detail.

[0058] As Figure 3As shown, when the duty cycle d of the main switch Q1 and the main switch Q2 is less than or equal to 50%, within a complete switching cycle T PRD the circuit goes through four different operating phases (I, II, III, IV). Figure 3 Shows the control signals (PWM1, PWM5, PWM2, PWM6) of the four switches and the current waveforms of each path, including the inductor currents i1(t) and i2(t), and the current combinations i M1 (t) and i M2 (t).

[0059] When the duty cycle is less than or equal to 50%, a switching cycle can be divided into the following four phases:

[0060] Phase I (0 - d): The first main switch Q1 is turned on, and the second synchronous rectifier switch Q6 is turned on;

[0061] Phase II (d - 0.5): The first synchronous rectifier switch Q5 is turned on, and the second synchronous rectifier switch Q6 is turned on;

[0062] Phase III (0.5 - 0.5 + d): The first synchronous rectifier switch Q5 is turned on, and the second main switch Q2 is turned on;

[0063] Phase IV (0.5 + d - 1): The first synchronous rectifier switch Q5 is turned on, and the second synchronous rectifier switch Q6 is turned on.

[0064] The currents flowing through the switches Q1, Q2, Q5, and Q6 in each switching phase are shown in the following table:

[0065]

[0066] Table 1

[0067] Analyze the currents flowing through each switch in each phase:

[0068] The first main switch Q1: Conducts only in Phase I, and the current is i1(t); The second main switch Q2: Conducts only in Phase III, and the current is i2(t); The first synchronous rectifier switch Q5: Conducts in Phases II, III, and IV, and the currents are i1(t), i1(t) + i2(t), and i1(t) respectively; The second synchronous rectifier switch Q6: Conducts in Phases I, II, and IV, and the current is i2(t).

[0069] If i M1 (t) represents the sum of the currents of the first main switch Q1 and the first synchronous rectifier switch Q5, then i M1(t) is i1(t) throughout the entire cycle and only includes the part of i2(t) in Stage III. If the current sum of the second main switch Q2 and the second synchronous rectifier switch Q6 is represented by i M2 (t), then i M2 (t) is i2(t) throughout the entire cycle.

[0070] Calculate the total current I flowing through the four switches within a complete switching cycle Q_all : I Q_all = I1 + (1 + d)I2, where I1 and I2 are the average values of the two inductor currents i1(t) and i2(t) within the switching cycle respectively, and d is the duty cycle of the switching cycle. Since the output current I OUT = I1 + I2, and under steady-state conditions, when the duty cycle is less than or equal to 50%, the two inductor currents are equal: I1 = I2. Therefore, it can be deduced that: I OUT = [2 / (2 + d)]×I Q_all .

[0071] As Figure 4 shown, when the duty cycles of the main switches Q1 and Q2 are greater than 50%, the circuit also experiences four different operating stages, but the durations of each stage are different from before:

[0072] Stage I (0~d - 0.5): The first main switch Q1 and the second main switch Q2 are turned on simultaneously;

[0073] Stage II (d - 0.5~0.5): The first main switch Q1 and the second synchronous rectifier switch Q6 are turned on;

[0074] Stage III (0.5~d): The first main switch Q1 and the second main switch Q2 are turned on;

[0075] Stage IV (d~1): The first synchronous rectifier switch Q5 and the second main switch Q2 are turned on.

[0076] The currents flowing through the switches Q1, Q2, Q5, and Q6 in each switching stage are shown in the following table:

[0077]

[0078] Table 2

[0079] Analyze the currents flowing through each switch in each stage:

[0080] The first main switch Q1: Turns on in Stages I, II, and III, and the currents are i1(t) + i2(t), i1(t), and i1(t) + i2(t) respectively;

[0081] The second main switch Q2: Conducts in phases I and III, with currents i2(t) and i2(t) respectively;

[0082] The first synchronous rectifier switch Q5: Conducts in phase IV, with current i1(t) + i2(t);

[0083] The second synchronous rectifier switch Q6: Conducts in phase II, with current i2(t);

[0084] The total current I flowing through the four switches Q_all Is also: I Q_all = I1 + (1 + d)I2. Under steady-state conditions, when the duty cycle is greater than 50%, the inductor current satisfies the relation: dI1 = (1 - d)I2. Combining with the output current I OUT = I1 + I2, it can be deduced that: I OUT = [1 / (1 + d 2 )] × I Q_all .

[0085] From the above analysis, it can be concluded that in the switched-capacitor converter, there is a fixed mathematical relationship between the total switching-period average current IQ_all of the four switches and the output current IOUT, and this relationship is directly related to the duty cycle d:

[0086] When the duty cycle d ≤ 0.5: I OUT = [2 / (2 + d)] × I Q_all ;

[0087] When the duty cycle d > 0.5: I OUT = [1 / (1 + d 2 )] × I Q_all .

[0088] The above mathematical relationship has important physical significance. By measuring the total current of the four switches and knowing the duty cycle d, the actual output current of the switched-capacitor converter can be accurately calculated without inserting an additional sampling resistor in the output loop.

[0089] It should be noted in particular that the inductor currents i1(t) and i2(t) usually show a triangular wave form and have fluctuations in the actual circuit. However, due to the usually high switching frequency (from several hundred kHz to several MHz), the filtering effect of the output filter capacitor CO makes the output current I OUT Almost pure DC, so the above mathematical relationship based on average value analysis has high accuracy in practical applications.

[0090] Similarly, if only the currents of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 are sampled, it can be obtained that when the duty cycle is less than or equal to 50%:

[0091] I Q_56 =(1 - d)I1 + I2;

[0092] When the duty cycle is greater than 50%:

[0093] I Q_56 =(1 - d)I1 + 2(1 - d)I2.

[0094] Therefore, the output current I of the switched - capacitor converter OUT and the average value of the switching period of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 can be expressed as:

[0095] When the duty cycle d ≤ 0.5: I OUT =[2 / (2 - d)]×I Q_all ;

[0096] When the duty cycle d > 0.5: I OUT =[1 / (1 - d 2 )]×I Q_all .

[0097] Through Figure 2 , Figure 3 , Figure 4 analysis, it can be seen that due to the specific topology and switching timing of the switched - capacitor converter, there is a deterministic relationship between the switch current and the output current. This embodiment uses a method that combines the switch current information and the duty - cycle information, and without the traditional output - current sampling resistor, it can achieve accurate measurement of the output current, providing a lossless output - current detection scheme for the switched - capacitor converter.

[0098] Referring to Figure 5 , the flowchart of a method for detecting output current provided by this application. This method is applied to a switched - capacitor converter and mainly includes the following two steps:

[0099] Step S100: Obtain the average current of the switch of the switched - capacitor converter within N switching cycles;

[0100] The acquisition of the average current of the switch in step S100 is the basis of the whole method. This method is different from the traditional method of detecting current by connecting a sampling resistor in series in the output loop. Instead, it directly measures the current flowing through the switch during conduction and then calculates its average value within N switching cycles through a specific method. Among them, N is an integer greater than or equal to 1, and usually can take values such as 1, 2, 4, 8, 16, etc. A larger N value helps to improve the sampling accuracy and anti - interference ability, but will increase the sampling delay. In practical applications, the value of N needs to comprehensively consider the balance between the accuracy requirement and the system response speed.

[0101] There are multiple ways to obtain the switch - tube current. In a preferred embodiment, the built - in current - detection function of DrMOS (Driver - MOSFET integrated module) can be utilized. Through the single - die current - mirror technology, DrMOS can monitor the on - current of the internal MOSFET in real time and output a signal proportional to the actual current through a dedicated pin. This signal is usually in the form of current and can be converted into a voltage signal via an external resistor and then sent to the analog - to - digital converter of the controller for sampling.

[0102] For the sampling of the switch - tube current, this method adopts the switch - cycle average - sampling technology, that is, within N complete switch cycles, the average value of the switch - tube current is obtained. The switch - cycle average - sampling can effectively suppress the interference of the switching frequency and its harmonic components and improve the measurement accuracy. Specifically, a Σ / Δ - type analog - to - digital converter can be used to sample the switch - tube current signal at a high frequency and then perform an average calculation in the digital domain.

[0103] If the switched - capacitor converter includes multiple switch tubes (such as Figure 2 the four switch tubes Q1, Q2, Q5, Q6 shown), then the average current of the switch tubes can be a specific combination of the currents of multiple switch tubes. For example, it can be the sum of the currents of the four switch tubes, or only the currents of the synchronous - rectification switch tubes (Q5, Q6) can be collected. Different collection methods correspond to different mathematical models, but the core principle is the same.

[0104] Step S200: Obtain the output current of the switched - capacitor converter based on the duty cycle and the average current of the switch tube.

[0105] The calculation of the output current is based on two key parameters: the duty cycle of the switch tube and the average current obtained in step S100. The duty cycle refers to the proportion of the conduction time of the main switch tube in one switch cycle to the total cycle, usually denoted by d, and its value range is between 0 and 1.

[0106] In the switched - capacitor converter, the controller generates a PWM (pulse - width modulation) signal to drive the switch tube, so the controller naturally knows the duty - cycle value of each switch cycle. For N switch cycles, the average duty cycle d can be calculated as an input parameter of the mathematical model.

[0107] According to the foregoing analysis, there is a deterministic mathematical relationship between the average current of the switch tube and the output current, and this relationship is directly related to the duty cycle d. The specific relationship is as follows:

[0108] When the average duty cycle d ≤ 0.5: I OUT =[2 / (2 + d)]×I Q_all ;

[0109] When the average duty cycle d > 0.5: I OUT =[1 / (1 + d2 )]×I Q_all 。

[0110] Among them, I OUT is the output current, and I Q_all is the average current of the switching transistor within N switching cycles.

[0111] If only the currents of the synchronous rectifier switching transistors (Q5, Q6) are collected, the mathematical relationship becomes:

[0112] When the average duty cycle d ≤ 0.5: I OUT = [2 / (2 - d)] × I Q_all ;

[0113] When the average duty cycle d > 0.5: I OUT = [1 / (1 - d 2 )] × I Q_all 。

[0114] Among them, I Q_all is I Q_56 , and I Q_56 is the average current of the synchronous rectifier switching transistor within N switching cycles.

[0115] The controller can select an appropriate formula to calculate the accurate output current value based on the actually sampled switching transistor current and the current average duty cycle d. Since the relationship between the switching transistor current and the output current has been accurately established through a mathematical model, this method does not require inserting an additional sampling resistor in the output loop, avoiding the power loss problem of the traditional solution.

[0116] In some embodiments of the present application, step S100 specifically includes the following steps:

[0117] Step S110: Obtain the currents of two main switching transistors and two synchronous rectifier transistors within N switching cycles.

[0118] In Figure 6 , it can be seen that the four switching transistors Q1, Q5, Q2, and Q6 are respectively marked with current detection points IS1, IS5, IS2, and IS6. These detection points are used to obtain the current signals flowing through each switching transistor during conduction.

[0119] There are many possible specific implementation methods: for example, lead wires are drawn out from the source or drain electrodes of the switching transistors, and the current is directly measured through a current sensor (such as a Hall sensor, a current transformer, etc.) in the signal processing module 10. Or a current detection circuit is integrated in the signal processing module to realize the separate detection of the currents of the high-side switching transistors (Q1 / Q2) and the low-side switching transistors (Q5 / Q6).

[0120] In this step, the current signals of the four switching tubes need to be acquired within N consecutive switching cycles. The selection of N affects the measurement accuracy and response speed. A larger value of N can improve the measurement accuracy but increase the detection delay; a smaller value of N is beneficial for fast response but may reduce the accuracy. According to the specific application scenario, N can take values such as 1, 2, 4, 8, 16, etc.

[0121] The acquisition frequency of the current signal needs to be significantly higher than the switching frequency to ensure that the detailed changes in the current waveform can be captured. For example, for a switching frequency of 100 kHz, the current sampling frequency may need to reach 10 MHz or higher to ensure that there are enough sampling points within each switching cycle.

[0122] Step S120: Within each switching cycle, sum up the currents of the two main switching tubes and the two synchronous rectifier tubes to obtain the total switching current.

[0123] In this step, the current signals of the four switching tubes need to be summed up to form the total switching current. Figure 6 As can be seen, the signals of the four current detection points (IS1, IS5, IS2, IS6) are introduced into the signal processing module 10 for summing up and processing.

[0124] The specific summing methods may be as follows: For example, inside the signal processing module 10, the four-way current signals are directly added through a current mirror or a current adder circuit to form the total current signal. Or the current signals of each switching tube are first converted into voltage signals, and then summed up through an adder circuit composed of operational amplifiers.

[0125] In Figure 6 the shown embodiment, a hardware summing method is adopted. The current signals of the four switching tubes are introduced into the signal processing module 10 and directly summed up into the total current signal through the internal circuit. It should be noted that due to the timing characteristics of the switching tube currents (as shown in Figure 3 and Figure 4 ), only some of the switching tubes may be in the conducting state at different times. Therefore, the signal processing module 10 needs to have the ability to process discontinuous signals.

[0126] Step S130: Convert the total switching current into a voltage signal.

[0127] From Figure 6 it can be seen that the output of the signal processing module 10 is connected to the control module 20 through two ports CS+ and CS-. This indicates that the signal processing module 10 converts the summed current signal into a differential voltage signal for subsequent analog-to-digital conversion processing.

[0128] The current-to-voltage conversion is usually achieved through a precision sampling resistor R CSImplementation. Different from traditional solutions, the sampling resistor here is not located in the power loop but inside the signal processing circuit. Therefore, the power loss on the resistor is extremely small and will not significantly affect the system efficiency.

[0129] The conversion circuit may include the following functional blocks: a current-voltage converter that converts the current signal into a voltage signal, where the conversion ratio is determined by the sampling resistor R CS (V = I × R CS ); a differential amplifier that converts a single-ended voltage signal into a differential signal to improve the anti-interference ability; a filter circuit that removes high-frequency noise and extracts the effective components of the current signal; and a level adjustment circuit that ensures the output signal is within the input range of the analog-to-digital conversion unit 210, maximizes the utilization of the dynamic range of the analog-to-digital conversion unit 210, and improves the measurement accuracy. It should be noted that the current-voltage conversion process will introduce a certain gain coefficient, which needs to be compensated in subsequent data processing to ensure the accuracy of the final calculation result.

[0130] Step S140: Sample the voltage signals of N switching cycles to obtain an output data stream.

[0131] This step is completed by the analog-to-digital conversion unit 210 within the control module 20. As Figure 6 shown, the CS+ and CS- differential signals are input to the analog-to-digital conversion unit 210 for high-speed sampling and conversion into a digital signal stream.

[0132] Preferably, a Σ / Δ ADC (Sigma-Delta ADC) is used for sampling here. The Σ / Δ ADC has the following characteristics: Through oversampling and noise shaping techniques, it can achieve a relatively high number of effective bits (such as 16 - 24 bits) to meet the requirements of precision current measurement; compared with other types of ADCs, the Σ / Δ ADC has better linearity, reducing measurement errors; the internal digital filter can effectively suppress high-frequency noise and improve the signal-to-noise ratio; it is particularly suitable for measuring relatively slowly varying signals such as current.

[0133] The working principle of the Σ / Δ ADC is to sample the input signal at a high frequency (much higher than the Nyquist sampling rate), push the quantization noise to the high-frequency region, and then remove the high-frequency noise through a digital filter to finally obtain a high-resolution digital output.

[0134] In this step, the Σ / Δ ADC samples the voltage signal at a high frequency and outputs a 1-bit high-speed data stream, where the density of "1" is proportional to the amplitude of the input signal. This 1-bit data stream will be further processed in the next step.

[0135] It should be noted that the ADC for sampling the average current of the switching period is not limited to the Σ / Δ ADC alone, and can also be replaced by other types of ADCs that can achieve sampling of the average current of the switching period, and the same purpose can be achieved.

[0136] Step S150: Integrate the output data stream to obtain the average current.

[0137] This step is completed by the data conversion unit 220 in the control module 20. As Figure 6 shown, the output of the analog-to-digital conversion unit 210 is sent to the data conversion unit 220 for processing, and finally a digital value representing the average current is output.

[0138] The key to the integration process is to ensure that the integration window is strictly aligned with the switching period. The reason is as follows. If a fixed integration time TAVG is used, when TAVG is not an integer multiple of the switching period TSW, the integration result will not accurately represent the average value of an integer number of switching periods. Therefore, the data conversion unit 220 needs to be able to accurately track the switching period and intercept the integration result at an integer number of switching periods.

[0139] It should also be noted that in combination with the switch driver integration module, step S110 also has the following implementation methods. Referring to Figure 7 , this embodiment of the present application shows a specific implementation method for detecting the output current of a switched-capacitor converter using two half-bridge DrMOS modules. Figure 7 Details of the overall structure of the system are presented, including the DrMOS module integrating the switch, the connection structure, and the control module 20. Below, the DrMOS built-in current mirror technology will be described in detail in combination with Figure 7 this.

[0140] As Figure 7 shown, the four switch transistors in the switched-capacitor converter are integrated in two half-bridge DrMOS modules: DrMOS1 integrates the first main switch transistor Q1(D1) and the first synchronous rectifier switch transistor Q5(S1); DrMOS2 integrates the second main switch transistor Q2(D2) and the second synchronous rectifier switch transistor Q6(S2). Each DrMOS module includes the following key pins: PWM: used to receive the pulse width modulation control signal; IMON: current monitoring output pin, outputting a mirror current proportional to the current of the internal switch transistor; IREF: current reference setting pin, used to provide a common-mode voltage for IMON to facilitate the generation of a negative current signal; other functional pins: such as GND (ground), power input, etc.

[0141] The working principle of the DrMOS built-in current mirror technology is as follows: Next to each MOSFET, a mirror MOSFET with a very small area ratio (usually 1:500 to 1:2000) is integrated inside the DrMOS chip. This mirror MOSFET shares the same gate drive signal with the main MOSFET and thus has exactly the same switching characteristics.

[0142] Since the area of the mirror MOSFET is much smaller than that of the main MOSFET, but both bear the same gate-source voltage, the current flowing through the mirror MOSFET is in a strict proportional relationship with the main MOSFET current, and this ratio is equal to the area ratio of the two. For example, if the area of the mirror MOSFET is 1 / 1000 of the main MOSFET, the mirror current is 1 / 1000 of the main current.

[0143] DrMOS integrates the main MOSFET and the mirror MOSFET on the same silicon chip, ensuring that both have exactly the same temperature coefficient and process parameters, thus achieving excellent temperature stability and accuracy.

[0144] In a half-bridge structure, the high-side MOSFET (main switching transistor) and the low-side MOSFET (synchronous rectification switching transistor) usually conduct complementarily. The internal circuit of DrMOS can automatically track which MOSFET is currently conducting and output the corresponding mirror current to the IMON pin.

[0145] As Figure 7 shown, the IMON pins of two DrMOS modules are connected together and converted into a voltage signal through a shared sampling resistor R CS This connection method realizes the automatic summation of the currents of the four switching transistors, forming a comprehensive signal representing the total switching transistor current.

[0146] Specific implementation details include: The mirror currents output by the IMON pins of the two DrMOS are naturally summed up and flow through the shared sampling resistor R CS , generating a voltage signal proportional to the total mirror current. The generated voltage signal is input to the analog-to-digital conversion unit 210 of the control module 20 through differential connection (CS+ and CS-). The control module 20 sends control signals to the two DrMOS modules through the PWM1 and PWM2 pins to control the switching states of the four switching transistors. The IREF pin of each DrMOS module is connected to a reference voltage source or a resistor network to set the proportionality coefficient of the current mirror and ensure the accuracy of the measurement results.

[0147] It should also be noted that the integrated switching transistor current detection function can be not only DrMOS, but also other discrete circuits with switching transistor current detection functions, switching transistor driver chips with integrated switching transistor current detection functions, etc.

[0148] In some other embodiments of the present application, step S100 specifically includes the following steps:

[0149] Step S160: Obtain the currents of two synchronous rectifier diodes within N switching cycles.

[0150] As Figure 8 shown, in this embodiment, only the currents of two synchronous rectifier switches Q5 and Q6 are concerned, and the corresponding current detection points are IS5 and IS6. This solution has the following advantages compared to the Figure 6 solution shown: It reduces the number of current detection points and simplifies the complexity of the signal processing circuit; the synchronous rectifier switches Q5 and Q6 are low-side switches (source grounded), and compared with high-side switches (Q1 and Q2), the low-side current detection technology is more mature and reliable, and the implementation difficulty is lower.

[0151] In Figure 8 , the current detection points IS5 and IS6 can be implemented in the following several ways: Detect the current by inserting a tiny resistor at the source of the synchronous rectifier switch or using the PCB trace resistance, and cooperate with a dedicated current detection amplifier to obtain the current signal. Or place a Hall effect sensor near the current path of the synchronous rectifier switch to measure the current non-contact.

[0152] Similar to the four-switch solution, in this step, the current signals of the synchronous rectifier switches need to be obtained within consecutive N switching cycles. The selection of N still needs to balance the measurement accuracy and response speed, and usually values such as 1, 2, 4, 8, 16, etc. can be selected.

[0153] Step S170: In each switching cycle, sum up the currents of the two synchronous rectifier diodes to obtain the total switching current.

[0154] In this step, the current signals of the two synchronous rectifier switches Q5 and Q6 need to be summed up to form the total switching current. As can be seen from Figure 8 , the signals of the two current detection points (IS5 and IS6) are introduced into the signal processing module 10 for summing up and processing.

[0155] Compared with the four-switch solution, the summing-up process in this embodiment is simpler and only needs to process two current signals. The summing-up methods include: directly adding the two current signals through a current mirror or a current adder circuit to form a total current signal. Or since Q5 and Q6 usually do not conduct simultaneously, a time-division multiplexing method can be adopted to selectively process the current signal of the currently conducting synchronous rectifier switch according to the switching timing.

[0156] According to Figure 3 and Figure 4For the switch timing shown, synchronous rectifier switching transistors Q5 and Q6 have different conduction states at different stages. The signal processing module 10 needs to be able to accurately capture these state changes to ensure that the aggregated result can correctly reflect the current contributions of the two synchronous rectifier switching transistors during the entire switching cycle.

[0157] In addition, since only the currents of the synchronous rectifier switching transistors are collected and the currents of the main switching transistors (Q1 and Q2) are not collected, the subsequent mathematical model needs to be adjusted accordingly to accurately calculate the output current.

[0158] Step S130: Convert the total switch current into a voltage signal.

[0159] As Figure 8 shown, the signal processing module 10 converts the aggregated current signal into a voltage signal through two differential ports CS+ and CS- and outputs it to the control module 20.

[0160] In the embodiment where only the currents of the synchronous rectifier switching transistors are collected, the current-voltage conversion process is basically the same as that of the four-switching-transistor scheme, but there may be the following characteristics: Since only the currents of the synchronous rectifier switching transistors are processed, the sampling resistor and the amplification circuit can be optimized according to the characteristics of this part of the current to improve the dynamic range and measurement accuracy of the signal; The sources of the synchronous rectifier switching transistors Q5 and Q6 are usually grounded, which enables the current detection circuit to adopt a single-ended structure with a ground reference, simplifying the circuit design; Although the current detection of the synchronous rectifier switching transistors can theoretically adopt a single-ended structure, Figure 8 differential signals (CS+ and CS-) are still used for output, which helps to suppress common-mode noise and improve measurement accuracy.

[0161] The current-voltage conversion process also needs to consider gain calibration and temperature compensation to ensure the accuracy and stability of the measurement results. In addition, the signal processing module 10 may also need to include a low-pass filter circuit to remove high-frequency switching noise and extract the effective components of the current signal.

[0162] Step S140: Sample the voltage signals of N switching cycles to obtain an output data stream.

[0163] This step is completed by the analog-to-digital conversion unit 210 in the control module 20. As Figure 8 shown, the CS+ and CS- differential signals are input to the analog-to-digital conversion unit 210 for high-speed sampling and conversion into a digital signal stream.

[0164] Similar to the four-switch scheme, this embodiment also preferably uses a Σ / Δ ADC for sampling. The output of the analog-to-digital conversion unit 210 is a 1-bit high-speed data stream, where the density of "1" is proportional to the amplitude of the input voltage signal. This 1-bit data stream will be further processed in the next step to be converted into a digital result with multi-bit resolution.

[0165] It should be noted that since this embodiment only measures the current of the synchronous rectifier switch, its waveform characteristics are different from those of the four-switch scheme, and the parameter settings of the ADC (such as sampling rate, filter bandwidth, etc.) may need to be adjusted accordingly to optimize the measurement effect.

[0166] Step S150: Integrate the output data stream to obtain the average current.

[0167] This step is completed by the data conversion unit 220 in the control module 20. As Figure 8 shown, the output of the analog-to-digital conversion unit 210 is sent to the data conversion unit 220 for processing, and finally a digital value representing the average current is output. The integration process is similar to that of the four-switch scheme.

[0168] The key to the integration process is to ensure that the integration window is strictly aligned with the switching period. The reasons are as follows: If a fixed integration time TAVG is used, when TAVG is not an integer multiple of the switching period TSW, the integration result will not accurately represent the average value of an integer number of switching periods. Therefore, the data conversion unit 220 needs to be able to accurately track the switching period and intercept the integration result at an integer number of switching periods.

[0169] It should also be noted that in combination with the switch driver integration module, there is also the following implementation method for step S160. Referring to Figure 9 , this embodiment of the present application shows a specific implementation method for detecting the current of the synchronous rectifier switch using two half-bridge DrMOS modules. Different from the embodiment shown in Figure 7 , the implementation method in Figure 9 particularly focuses on the current detection of the synchronous rectifier switches (Q5 and Q6), and uses the built-in low-side current mirror technology of DrMOS to achieve high-precision and lossless current detection.

[0170] As Figure 9 shown, the switched-capacitor converter is constructed using two half-bridge DrMOS modules: DrMOS1 integrates the first main switch Q1 (D1) and the first synchronous rectifier switch Q5 (S1); DrMOS2 integrates the second main switch Q2 (D2) and the second synchronous rectifier switch Q6 (S2). The key connections and components of the system include: the input voltage terminal V IN is connected to the two DrMOS modules, and the flying capacitor C FLYConnected between two half - bridges, the first inductor L1 and the second inductor L2 are respectively connected to the output capacitor C O and the load R LOAD , the control module 20 sends control signals to the DrMOS module through the PWM1 and PWM2 pins. The IMON pin of the DrMOS outputs the mirror current, which is connected to the sampling resistor R CS , and the CS + and CS - differential signals are connected to the analog - to - digital conversion unit 210 of the control module 20.

[0171] Different from Figure 7 the key point is that Figure 9 the DrMOS in Figure 9 is configured to output only the current information of the synchronous rectification switch (low - side MOSFET), without including the current information of the main switch (high - side MOSFET). The first synchronous rectification switch and the second synchronous rectification switch are integrated in the second switch - tube driving integrated module, and the current information is obtained through the internal current mirror of this module. In the embodiment of

[0172] the working principle of the DrMOS low - side current mirror is as follows: The DrMOS integrates a scaled - down mirror MOSFET in the low - side MOSFET (synchronous rectification switch) chip. This mirror MOSFET shares the same gate - drive signal with the main MOSFET and has exactly the same switching characteristics.

[0173] The area of the mirror MOSFET is usually 1 / 500 to 1 / 2000 of the main MOSFET, so the current flowing through the mirror MOSFET has an exact proportional relationship with the main MOSFET.

[0174] Since the mirror MOSFET and the main MOSFET are integrated on the same silicon chip, they have exactly the same temperature coefficient, ensuring a stable proportional relationship when the temperature changes.

[0175] The DrMOS can usually be configured to select to output the current information of the low - side MOSFET, high - side MOSFET, or both. In the embodiment of Figure 9 the DrMOS is configured to output only the current information of the low - side MOSFET (synchronous rectification switch).

[0176] In Figure 9 the implementation shown, the IMON pins of the two DrMOS modules are connected together, and the output mirror current flows through the shared sampling resistor R CS , and is converted into a differential voltage signal (CS + and CS -) and input into the control module 20.

[0177] Compared with detecting the currents of all four switching transistors, detecting only the current of the synchronous rectifier switching transistor has the following significant advantages: The current detection technology for the low-side MOSFET is more mature, and the implementation difficulty is much lower than that of the high-side MOSFET current detection. The high-side MOSFET is at a floating potential, and current detection is more complex. The reliability of the low-side current mirror technology is higher, and it is less affected by factors such as temperature and voltage fluctuations. Almost all DrMOS products support low-side current detection, while some early or low-cost products may not support high-side current detection. The source of the low-side MOSFET is grounded, and the common-mode noise of the current detection signal is smaller, and the signal quality is usually higher.

[0178] In some embodiments of the present application, step S150 specifically includes the following steps:

[0179] Step S151: Integrate the output data stream.

[0180] The "integration" in this step refers to the accumulation process of the data stream output by the analog-to-digital conversion unit 210 (usually a Σ / Δ ADC). The specific content is as follows:

[0181] The Σ / Δ ADC outputs a high-speed 1-bit data stream composed of "0" and "1". The density of "1" (i.e., the frequency of "1" appearance) in this data stream is proportional to the amplitude of the input analog signal. For example, when the input signal amplitude is 80% of the full scale, approximately 80% of the bits in the data stream will be "1".

[0182] In the digital domain, "integration" actually refers to counting and accumulating the "1" in the data stream. This can be achieved by a digital accumulator, which continuously accumulates the input 1-bit data.

[0183] In hardware implementation, a binary counter can be used to record the total number of "1" in the data stream; in software implementation, a variable can be used to continuously accumulate the value (0 or 1) of each sampling point.

[0184] The bit width of the accumulator needs to be determined according to the expected integration time and target resolution to avoid overflow. For example, for a 20MHz sampling rate and a 10ms integration time, the maximum accumulated value can reach 200,000, and at least an 18-bit accumulator is required.

[0185] The integration process itself has a low-pass filtering characteristic, which can effectively suppress high-frequency noise. The longer the integration time, the better the filtering effect, but it will increase the system response delay.

[0186] Step S152: When the integration time reaches N switching cycles, stop the integration and obtain the average voltage.

[0187] To avoid errors caused by the mismatch between the integration time and the switching period, the truncation time of the integration result should be an integer multiple of the switching period. This is because the current signal in the switching power supply has significant periodic characteristics, and non-integer period integration will lead to inaccurate measurement results.

[0188] The system accurately calculates the number of switching periods by tracking the PWM signal. When it detects that N complete switching periods have been completed, the integration process stops. The choice of N needs to balance measurement accuracy and response speed, usually being 1, 2, 4, or 8.

[0189] To achieve precise synchronization, the controller needs to accurately track the switching period boundary, which is achieved in the following ways: using the period overflow flag of the PWM counter; monitoring the rising or falling edge of the PWM signal; using a dedicated period synchronization circuit.

[0190] When the preset N periods are reached, the system records the value of the current accumulator, which represents the average voltage within N complete switching periods.

[0191] Assume the switching frequency is fsw and the switching period is TSW = 1 / fsw, then the integration time Tint = N × TSW. For example, for a 100 kHz switching frequency and N = 4, the integration time is 40 μs.

[0192] Step S153: Convert the average voltage to the average current.

[0193] Convert the average value in the voltage domain to the required current value to complete the entire measurement process. The specific content is as follows: There is a deterministic conversion relationship between the average voltage and the switch tube current, which is mainly determined by the following factors:

[0194] The resistance value of the current sampling resistor R CS : V = I × R CS ;

[0195] The proportionality coefficient of the current mirror inside DrMOS: usually from 1:500 to 1:2000;

[0196] The gain of the signal processing circuit: if there are signal amplification or attenuation links.

[0197] Assume the current mirror ratio is 1 and the sampling resistor is R CS , and the signal processing gain is G, then there is: I Q_all = (average voltage / G) / R CS × K where I Q_all is the actual average current of the switch tube. For example, if the current mirror ratio is 1:1000, the sampling resistor is 10 Ω, the signal processing gain is 2, and the average voltage is 0.8 V, then: I Q_all = (0.8 V / 2) / 10 Ω × 1000 = 40 A.

[0198] In some embodiments of the present application, step S200 specifically includes the following steps:

[0199] Step S210: Obtain the duty cycle of the main switch tube within N switching cycles.

[0200] The duty cycle is a key parameter in the control of switching power supplies, defined as the ratio of the conduction time of the switch tube to the switching cycle. The purpose of this step is to obtain the real-time duty cycle values of the main switch tubes (Q1 and Q2) within N consecutive switching cycles. The specific content is as follows:

[0201] The duty cycle d = conduction time (ton) / switching cycle (Tsw), and its value range is from 0 to 1 (or 0% to 100%). In a switched-capacitor converter, the duty cycles of the main switch tubes Q1 and Q2 are usually equal, but are staggered by 180 degrees in phase. The duty cycle directly determines the proportion of energy transfer and is a key parameter for determining the output voltage and current.

[0202] When the controller generates a PWM signal, it is necessary to set the duty cycle value. Therefore, the duty cycle value can be directly read from the configuration register of the PWM module; or the duty cycle can be calculated by measuring the ratio of the high-level duration of the PWM to the total period; or by detecting the rising edge and falling edge of the PWM signal and calculating the ratio of the time difference between them to the period to calculate the duty cycle.

[0203] Step S220: Obtain the average duty cycle based on the N duty cycles of the main switch tube.

[0204] The most commonly used method is simple arithmetic mean, where the N duty cycle values are added and then divided by N; for specific applications, weighted average can be used, assigning different weights according to the importance of different cycles; or moving average can be used to continuously update the average value, reduce the influence of a single value, and improve stability.

[0205] Step S230: Obtain the output current based on the average duty cycle and the average current.

[0206] In some embodiments of the present application, step S230 specifically includes the following steps:

[0207] Step S231: Determine whether the average duty cycle is greater than 0.5.

[0208] It is necessary to determine whether the average duty cycle d exceeds the 0.5 (50%) threshold. The judgment result determines which mathematical formula is used to calculate the output current, and the judgment needs to consider the accuracy problem. A comparator with hysteresis can be used to avoid repeated switching near 0.5. If the average duty cycle is greater than 0.5, then step S232 is executed; if the average duty cycle is less than or equal to 0.5, then step S233 is executed.

[0209] Step S232: Using a preset first operation formula, obtain the output current according to the average duty cycle and the average current.

[0210] When sampling the currents of four switching tubes, that is, the average current is the sum of the currents of two main switching tubes and two synchronous rectifier switching tubes, and is the average value within N switching cycles, the output current is obtained according to the following formula:

[0211] I OUT =[1 / (1 + d 2 )]×I Q_all ;

[0212] When sampling the currents of two synchronous rectifier switching tubes, that is, the average current is the sum of the currents of two synchronous rectifier switching tubes, and is the average value within N switching cycles, the output current is obtained according to the following formula:

[0213] I OUT =[1 / (1 - d 2 )]×I Q_all ;

[0214] Among them, I OUT is the output current, d is the average duty cycle, and I Q_all is the average current value.

[0215] Step S233: Using a preset second operation formula, obtain the output current according to the average duty cycle and the average current.

[0216] When sampling the currents of four switching tubes, that is, the average current is the sum of the currents of two main switching tubes and two synchronous rectifier switching tubes, and is the average value within N switching cycles, the output current is obtained according to the following formula:

[0217] I OUT =[2 / (2 + d)]×I Q_all ;

[0218] When sampling the currents of two synchronous rectifier switching tubes, that is, the average current is the sum of the currents of two synchronous rectifier switching tubes, and is the average value within N switching cycles, the output current is obtained according to the following formula:

[0219] I OUT =[2 / (2 - d)]×I Q_all ;

[0220] Among them, I OUT is the output current, d is the average duty cycle, and I Q_all is the average current value.

[0221] Different from the prior art, in an embodiment of the present invention, for a switched-capacitor converter, according to the relationship between the switch current and the output current, by detecting the switch current and the duty cycle of the corresponding switch, the output current is obtained, avoiding the additional sampling resistor in the output loop, thereby reducing the system loss, decreasing the heat dissipation area, improving the power density of the switched-capacitor converter, and also avoiding the possibility that the sampling resistor added in the high-frequency switching loop is vulnerable to switching noise interference and affects the sampling result.

[0222] An embodiment of the present invention also provides an electronic device based on the above output current detection method. The schematic structural diagram is as Figure 10 shown. The electronic device 700 includes:

[0223] One or more processors 701, a network interface 702, and a memory 703. Figure 10 Here, one processor 701, one network interface 702, and one memory 703 are taken as examples.

[0224] The network interface 702 is communicatively connected to the corresponding processor 701. The processor 701 and the memory 702 can be connected through a bus or other means. Figure 10 Here, the connection through the bus is taken as an example.

[0225] The network interface 702 is used to establish a communication connection between the processor 701 and other external devices, including the following types: RJ-45 interface, SC fiber optic interface, AUI interface, FDDI interface, and Console interface, etc.

[0226] The memory 703, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 701 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions, and units stored in the memory 703, that is, implementing the output current detection method in the above method embodiment.

[0227] The memory 103 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the electronic device, etc. In addition, the memory 703 may include a high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 703 may optionally include a memory remotely set relative to the processor 701, and these remote memories can be connected to the electronic device through a network. Examples of the above networks include but are not limited to the Internet, an enterprise internal network, a local area network, a mobile communication network, and combinations thereof.

[0228] The one or more units are stored in the memory 703 and, when executed by one or more processors 701, perform the output current detection method in any of the above method embodiments. For example, perform the method steps S100 to S200 described above. Figure 5 in the method.

[0229] The above electronic device can execute the output current detection method provided by the embodiments of the present invention, and has corresponding program modules and beneficial effects for executing the method. For technical details not described in detail in the electronic device embodiments, reference can be made to the output current detection method provided by the embodiments of the present invention.

[0230] The embodiments of the present invention also provide a non-volatile computer-readable storage medium, which may be included in the device described in the above embodiments; or may exist separately without being assembled into the device. The above non-volatile computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the output current detection method of the embodiments of the present disclosure is implemented.

[0231] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above. For the sake of brevity, they are not provided in detail; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for detecting output current, applied to a switched-capacitor converter, characterized in that Including: Obtain the average current of the switching transistors of the switched-capacitor converter within N switching cycles; Based on the duty cycle of the switching transistors and the average current, obtain the output current of the switched-capacitor converter.

2. The method according to claim 1, wherein The switching transistors include two main switching transistors and two synchronous rectifier transistors. The obtaining the output current of the switched-capacitor converter based on the duty cycle of the switching transistors and the average current includes: Obtain the duty cycle of the main switching transistors within the N switching cycles; Based on the N duty cycles of the main switching transistors, obtain the average duty cycle; Based on the average duty cycle and the average current, obtain the output current.

3. The method according to claim 2, characterized in that The obtaining the output current based on the average duty cycle and the average current includes: Judge whether the average duty cycle is greater than 0.5; If so, use a preset first operation formula to obtain the output current according to the average duty cycle and the average current; If not, use a preset second operation formula to obtain the output current according to the average duty cycle and the average current.

4. The method according to claim 3, wherein When the average current is the average value of the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors within the N switching cycles, The first operation formula is: I OUT = [1 / (1 + d 2 )] × I Q_all ; The second operation formula is: I OUT = [2 / (2 + d)] × I Q_all ; Wherein, I OUT is the output current, d is the average duty cycle, and I Q_all is the average current value.

5. The method according to claim 3, wherein When the average current is the average value of the sum of the currents of the two synchronous rectifier switching transistors within the N switching cycles, The first operation formula is: I OUT = [1 / (1 - d 2 )] × I Q_all ; The second operation formula is: I OUT = [2 / (2 - d)] × I Q_all ; Among them, I OUT is the output current, d is the average duty cycle, and I Q_all is the average current value.

6. The method according to claim 2, wherein The obtaining the average current of the switching transistors of the switched-capacitor converter within N switching cycles includes: Within the N switching cycles, obtain the currents of the two main switching transistors and the two synchronous rectifier transistors; Within each switching cycle, sum up the currents of the two main switching transistors and the two synchronous rectifier transistors to obtain the total switching current; Convert the total switching current into a voltage signal; Sample the voltage signals of the N switching cycles to obtain an output data stream; Perform an integration process on the output data stream to obtain the average current.

7. The method according to claim 2, characterized in that, The obtaining the average current of the switching transistors of the switched-capacitor converter within N switching cycles includes: Within the N switching cycles, obtain the currents of the two synchronous rectifier transistors; Within each switching cycle, sum up the currents of the two synchronous rectifier transistors to obtain the total switching current; Convert the total switching current into a voltage signal; Sample the voltage signals of the N switching cycles to obtain an output data stream; Perform an integration process on the output data stream to obtain the average current.

8. The method according to claim 6 or 7, characterized in that, The performing an integration process on the output data stream to obtain the average current includes: Integrate the output data stream; When the integration time reaches the N switching cycles, stop the integration to obtain the average voltage; Convert the average voltage into the average current.

9. The method according to claim 8, characterized in that The two main switching transistors include a first main switching transistor and a second main switching transistor; The first main switching transistor and the second main switching transistor are integrated in a first switching transistor driving integrated module, and the current of the first main switching transistor and the current of the second main switching transistor are obtained through an internal current mirror of the first switching transistor driving integrated module.

10. The method according to claim 8, wherein The two synchronous rectifier transistors include a first synchronous rectifier transistor and a second synchronous rectifier transistor; The first synchronous rectifier transistor and the second synchronous rectifier transistor are integrated in a second switching transistor driving integrated module, and the current of the first synchronous rectifier transistor and the current of the second synchronous rectifier transistor are obtained through an internal current mirror of the second switching transistor driving integrated module.

11. An electronic device, characterized in that, Comprising: At least one processor; At least one network interface, the network interface being communicatively connected to the corresponding processor; And, A memory communicatively connected to the at least one processor; wherein, The network interface is used to establish a communication connection between the processor and other external devices; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute an output current detection method according to any one of claims 1-10.

12. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors, enabling the one or more processors to execute an output current detection method according to any one of claims 1-10.

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