Integrated circuit test method and system

Abstract

The invention relates to the technical field of circuit testing, in particular to an integrated circuit testing method and system. The method comprises the following steps: acquiring integrated circuit structure data; performing key node screening on the integrated circuit structure data to obtain a power supply pin and an input pin; performing static bias voltage setting on the power supply pin and the input pin to generate static bias voltage setting data; performing bias voltage acquisition on the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data; carrying out low-amplitude high-frequency noise source superposition on the bias voltage acquisition data of the standard integrated circuit to obtain voltage acquisition noise data; and performing power supply interference simulation on the bias voltage acquisition data of the standard integrated circuit through the voltage acquisition noise data to generate circuit power supply interference simulation data. According to the invention, through key node screening, parasitic effect evaluation, multi-dimensional data analysis and cloud visualization, the accuracy of circuit testing is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit testing, and in particular, to an integrated circuit testing method and system. Background Art

[0002] Early IC testing mainly relied on manual operation and simple function testers, which could detect basic open and short circuit problems. This method was applicable to ICs with small scale and low complexity. However, with the emergence of large-scale integrated circuits (LSIs) and very large-scale integrated circuits (VLSIs), traditional manual testing could no longer meet the requirements. Automatic test equipment (ATE) began to be widely used, realizing the automation of IC testing and improving the testing efficiency and accuracy. ATE can comprehensively check the functions, timing, and electrical parameters of chips through pre-written test programs. However, as the process nodes continue to shrink, the complexity of IC design has increased significantly, and the testing time and cost of ATE have become new challenges. In recent years, design-based testing (DFT) technologies have gradually matured, such as scan chain testing, built-in self-test (BIST), and logic diagnosis technologies. These technologies embed test structures in the design stage, reducing the testing complexity and cost. However, currently, conventional methods of traditional IC testing are difficult to comprehensively simulate power supply noise and interference effects, have insufficient coverage of the actual working environment, and fail to accurately evaluate the impact of parasitic effects on circuit performance, thereby resulting in low accuracy of circuit testing. Summary of the Invention

[0003] Based on this, it is necessary to provide an integrated circuit testing method and system to solve at least one of the above technical problems.

[0004] To achieve the above object, an integrated circuit testing method includes the following steps:

[0005] Step S1: Obtain integrated circuit structure data; screen key nodes from the integrated circuit structure data to obtain power pins and input pins; set static bias voltages for the power pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage collection data;

[0006] Step S2: Superimpose a low-amplitude high-frequency noise source on the standard integrated circuit bias voltage collection data to obtain voltage collection noise data; simulate power supply interference on the standard integrated circuit bias voltage collection data through the voltage collection noise data to generate circuit power supply interference simulation data; calculate the circuit parasitic index from the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit;

[0007] Step S3: Based on the actual parasitic data of the integrated circuit, perform leakage current tests on the standard integrated circuit bias voltage acquisition data to obtain integrated circuit leakage current data; perform extreme temperature tests on the integrated circuit through the integrated circuit leakage current data to obtain integrated circuit extreme temperature test data; perform batch marking on the integrated circuit based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate type-one integrated circuit marking data and type-two integrated circuit marking data;

[0008] Step S4: Upload the type-one integrated circuit marking data and the type-two integrated circuit marking data to the cloud platform for data visualization, generate an integrated circuit test storage report, and execute the complete integrated circuit test operation.

[0009] Through key node screening, the present invention focuses the tests on the power pins and input pins, avoiding interference from unnecessary nodes, and improving the test efficiency and resource utilization rate. The static bias voltage setting ensures the unity and standardization of the data, laying a foundation for the accuracy and comparability of subsequent test results. The generated standard bias voltage data can be used in various test scenarios, such as interference simulation and leakage current tests, enhancing the test applicability. By superimposing low-amplitude high-frequency noise, the working state of the integrated circuit in a complex electromagnetic environment is truly reproduced, improving the comprehensiveness of the test. The power supply interference simulation data provides a basis for evaluating the impact of power supply fluctuations on circuit performance, helping to optimize the circuit design. The parasitic index calculation quantifies the impact of parasitic effects, providing data support for circuit improvement and defect location, especially applicable to problem diagnosis in high-density circuit designs. Conducting leakage current and extreme temperature tests based on parasitic data can deeply understand the performance boundaries and potential risks of the integrated circuit. The comprehensive analysis combining parasitic data, leakage current data, and extreme temperature data provides a panoramic view of the integrated circuit performance. By intelligently marking type-one and type-two products, the efficiency of product classification and quality control is significantly improved, while reducing the error rate of human intervention. The batch marking data supports the traceability of the production chain, providing a basis for subsequent improvement and product grading. After uploading to the cloud platform for visualization, it is convenient for quickly understanding and evaluating the test results, providing an intuitive reference for decision-making. Cloud storage and report generation support cross-departmental collaboration, improving the data sharing efficiency and reducing the risk of information silos. The storage report includes multi-dimensional test results and marking data, providing rich basis for subsequent optimized design and improved test processes. The cloud visualization of the data enhances the transparency of the entire test process, contributing to quality control and the establishment of customer trust. Therefore, through key node screening, parasitic effect evaluation, multi-dimensional data analysis, and cloud visualization, the present invention improves the accuracy of circuit testing.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Obtain the integrated circuit structure data;

[0012] Step S12: Perform circuit pin analysis on the integrated circuit structure data to generate integrated circuit pin data; based on the integrated circuit pin data, screen key nodes of the integrated circuit structure to obtain key nodes of the integrated circuit, where the key nodes of the integrated circuit include power pins and input pins.

[0013] Step S13: Set static bias voltages for the power pins and input pins to generate static bias voltage setting data; use a voltage sensor to collect bias voltages for the static bias voltage setting data to obtain integrated circuit bias voltage acquisition data.

[0014] Step S14: Perform data preprocessing on the integrated circuit bias voltage acquisition data to generate standard integrated circuit bias voltage acquisition data, where the data preprocessing includes data cleaning, data denoising, filling missing data values, and data standardization.

[0015] Through detailed circuit pin analysis and key node screening of the integrated circuit structure data, the present invention can ensure the accuracy of circuit design. Especially when identifying key nodes such as power pins and input pins, it can effectively assist in the functional analysis and optimization of subsequent circuits. By setting static bias voltages for the power pins and input pins and collecting voltage data through a voltage sensor, it helps to ensure the electrical stability of the integrated circuit in the design and that the voltage requirements meet the system needs, avoiding circuit instability or failures caused by improper voltages. Data preprocessing (including data cleaning, denoising, filling missing values, and standardization) can effectively improve the quality of the collected data, remove noise, correct missing parts, and ensure the accuracy and reliability of subsequent analysis, which is crucial for further circuit performance evaluation, fault detection, and optimization. By processing and standardizing the integrated circuit bias voltage acquisition data, it can provide high-quality basic data for subsequent circuit function evaluation, performance optimization, and fault tolerance analysis, further supporting circuit design verification and improvement.

[0016] Preferably, setting static bias voltages for the power pins and input pins includes:

[0017] Define the operating voltage range for the power pins to obtain the power pin operating voltage range; define the normal logic level range for the input pins to obtain the input pin normal logic level range.

[0018] Based on the power pin operating voltage range and the input pin normal logic level range, expand the bias voltage range for the key nodes of the integrated circuit to generate bias voltage range expansion data; perform test voltage step setting on the key nodes of the integrated circuit according to the bias voltage range expansion data to generate a serialized list of test points.

[0019] Static bias voltage setting is performed on the power pins and input pins according to the serialized list of test points based on a preset stabilization time, generating static bias voltage setting data.

[0020] In the present invention, by respectively defining the operating voltage range and normal logic level range for the power pins and input pins, it is ensured that the voltage requirements of the circuit match the actual power supply output and the logic requirements of the input signal, thereby providing guarantee for the normal operation of the circuit. Based on the operating voltage range of the power pins and the normal logic level range of the input pins, the bias voltage range of the key nodes of the integrated circuit is extended to ensure that the bias voltage covers the possible operating states of the circuit. This extension can improve the adaptability of the circuit in different operating environments, reduce circuit failures caused by voltage instability. The generated test voltage step setting and serialized list provide ordered and accurate test steps for subsequent tests, ensuring sufficient voltage verification at different test points, which helps to improve the comprehensiveness and systematicness of the test, reducing omissions and errors. By performing static bias voltage setting on the power pins and input pins within a preset stabilization time, the electrical stability of the circuit in the real operating environment can be simulated, and it is ensured that the circuit will not fail due to voltage instability during long-term use. The static bias voltage setting data provides basic data for subsequent circuit optimization and debugging. Through the systematic voltage range and test settings, it can help engineers quickly locate voltage-related problems in the circuit and provide support for improving the performance of the circuit.

[0021] Preferably, step S2 includes the following steps:

[0022] Step S21: Add a low-amplitude high-frequency noise source to the bias voltage acquisition data of the standard integrated circuit to obtain voltage acquisition noise data; perform power supply interference simulation on the bias voltage acquisition data of the standard integrated circuit through the voltage acquisition noise data to generate circuit power supply interference simulation data;

[0023] Step S22: Use an oscilloscope to measure the output waveform of the circuit power supply interference simulation data, and perform abnormal output response discrimination on the measured output waveform to obtain an abnormal output response discrimination strategy;

[0024] Step S23: Adjust the signal frequency of the circuit power supply interference simulation data according to the abnormal output response discrimination strategy to generate a circuit power supply interference adjustment signal;

[0025] Step S24: Perform cyclic power supply interference simulation on the bias voltage acquisition data of the standard integrated circuit through the circuit power supply interference adjustment signal to generate circuit power supply interference cyclic simulation data; calculate the circuit parasitic index of the circuit power supply interference cyclic simulation data to obtain the actual parasitic data of the integrated circuit.

[0026] The present invention can effectively restore the power supply interference situation faced by integrated circuits in the actual working environment through the superposition of low-amplitude high-frequency noise sources and power supply interference simulation. This simulation helps to evaluate in advance the anti-interference ability of the circuit in a complex environment, so as to optimize the design to improve the circuit robustness. Measuring the output waveform with an oscilloscope and performing abnormal output response discrimination can quickly identify the abnormal behaviors (such as waveform distortion or function abnormality) of the circuit under power supply interference. Through the abnormal output response discrimination strategy, a clear direction can be provided for further circuit optimization and debugging. The signal frequency adjustment generates a circuit power supply interference adjustment signal through the adaptive optimization of interference characteristics, which helps to enhance the adaptability of the circuit to different interference frequencies, thereby improving the performance stability of the circuit in various interference scenarios. The cyclic power supply interference simulation can comprehensively test the performance of the circuit in a long-term interference environment, ensure that the design has long-term stability and reliability, and avoid functional failures or malfunctions caused by occasional interference. The calculation of the circuit parasitic index can quantitatively analyze the actual impact of interference on the circuit, provide intuitive data support, and these parasitic data provide a scientific basis for optimizing the circuit layout, design or material selection, thereby reducing the potential risks brought by parasitic effects.

[0027] Preferably, the abnormal output response discrimination for the measured output waveform includes:

[0028] Calculating the waveform average value and standard deviation of the measured output waveform to obtain the output waveform average value and the output waveform standard deviation; performing waveform amplitude abnormality discrimination on the measured output waveform according to the output waveform average value and the output waveform standard deviation to generate waveform amplitude abnormality discrimination data;

[0029] Performing waveform timing analysis on the measured output waveform to generate output waveform timing data; performing time delay overrun discrimination on the measured output waveform based on the output waveform timing data to generate waveform timing abnormality discrimination data;

[0030] Performing waveform shape analysis on the measured output waveform to generate output waveform shape data; performing waveform shape distortion discrimination on the measured output waveform based on the output waveform shape data to generate waveform morphology abnormality discrimination data;

[0031] Performing abnormal output response discrimination on the measured output waveform based on the waveform amplitude abnormality discrimination data, the waveform timing abnormality discrimination data and the waveform morphology abnormality discrimination data to obtain the abnormal output response discrimination strategy.

[0032] By calculating the average value and standard deviation of the waveform, the present invention can quickly obtain the statistical characteristics of the waveform amplitude, accurately judge whether the waveform amplitude is abnormal, and provide a reliable data basis for anomaly recognition. Waveform timing analysis and waveform shape analysis cover the characteristics of the waveform in two dimensions of time and shape, ensuring that no abnormal factors are missed in the discrimination process, and further improving the overall discrimination accuracy and comprehensiveness. Through the amplitude statistical characteristics (average value and standard deviation), abnormal situations where the voltage amplitude exceeds the normal range can be quickly detected. Through waveform timing analysis and delay discrimination, delay problems existing in the signal transmission process can be identified, which is particularly crucial for high-speed circuits. Based on the analysis of waveform shape data, waveform distortion phenomena caused by interference or design defects can be effectively detected, ensuring the morphological integrity of the signal. Based on the discrimination results in three dimensions of waveform amplitude, timing, and shape, an abnormal output response discrimination strategy is comprehensively generated to provide global guidance. This strategy can help the R & D team quickly locate the root cause of the problem and optimize the circuit design or operating conditions accordingly. Through multi-dimensional anomaly detection means, the quality of signal output can be significantly improved, circuit failures caused by signal anomalies can be reduced, and the stability and reliability of circuit operation can be ensured. Especially in complex environments, the risk of output anomalies caused by interference or other external factors in the circuit can be effectively reduced. Automated anomaly discrimination and strategy generation greatly shorten the time for analyzing and solving output anomalies during the design and debugging process, helping the design team optimize product performance more efficiently.

[0033] Preferably, calculating the circuit parasitic index for the circuit power supply interference cycle simulation data includes:

[0034] Screening the circuit transistor structure from the integrated circuit structure data to obtain the circuit transistor structure data; analyzing the change in the transistor threshold voltage of the circuit transistor structure data based on the circuit power supply interference cycle simulation data to generate the circuit transistor threshold voltage change data;

[0035] Analyzing the change in the gate length of the transistors in the integrated circuit according to the circuit transistor threshold voltage change data to generate the transistor gate length change data; performing parasitic effect tests through the circuit power supply interference cycle simulation data to generate the integrated circuit parasitic effect test data;

[0036] Calculating the actual parasitic index of the integrated circuit for the integrated circuit parasitic effect test data using the transistor gate length change data to obtain the actual parasitic data of the integrated circuit, where the formula for calculating the actual parasitic index of the circuit is as follows:

[0037]

[0038] Wherein, P represents the actual parasitic data of the integrated circuit, α represents the influence coefficient of capacitance on the circuit performance, β represents the influence coefficient of resistance on the circuit performance, K represents the proportionality factor, W represents the transistor width, and L g,act represents the actual transistor gate length, and L g represents the designed length of the transistor gate, R0 represents the constant of the drain-source resistance, and B represents the test value of the integrated circuit parasitic effect.

[0039] Based on the formula The present invention can quantify the influence of parasitic effects on the circuit performance, provide intuitive and quantifiable actual parasitic index data. This precise calculation helps to deeply understand the characteristics of parasitic effects and their potential threats to the circuit function. The analysis of the change in the transistor threshold voltage and the change in the gate length provides a fine-grained study of the transistor structure, revealing the dynamic changes of the transistor in a power interference environment, which can help engineers locate specific performance bottlenecks and optimization directions. By combining the power interference cycle simulation data and the parasitic effect test data, a closed-loop analysis from the simulation environment to the actual test is achieved, improving the accuracy of the parasitic effect calculation and ensuring that the results are more in line with the real application scenario. The influence coefficients α and β in the formula respectively characterize the different influences of capacitance and resistance on the parasitic effect, enabling the calculation to comprehensively consider the contributions of these two key parameters to the circuit performance and providing comprehensive guidance for circuit design. The analysis of the change in the gate length provides an optimization basis for the transistor structure design. By studying the deviation between the actual gate length and the designed length, the transistor geometric parameters can be optimized to reduce the influence of parasitic effects on the circuit performance. The parasitic effect test and the actual parasitic index calculation help designers better understand and control the influence of parasitic effects on the circuit, ensuring that the circuit still has high reliability in a high-interference environment and reducing the risk of failure.

[0040] Preferably, step S3 includes the following steps:

[0041] Step S31: Perform the lowest static power consumption analysis on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to generate the lowest static power consumption data of the integrated circuit; perform a leakage current test on the lowest static power consumption data of the integrated circuit to obtain the leakage current data of the integrated circuit;

[0042] Step S32: Perform an extreme temperature test on the integrated circuit through the leakage current data of the integrated circuit to obtain the extreme temperature test data of the integrated circuit; perform test data balancing according to the actual parasitic data of the integrated circuit, the leakage current data of the integrated circuit, and the extreme temperature test data of the integrated circuit to obtain the integrated circuit comprehensive evaluation index;

[0043] Step S33: Compare the integrated circuit comprehensive evaluation index with the preset standard integrated circuit comprehensive evaluation threshold. When the integrated circuit comprehensive evaluation index is greater than or equal to the preset standard integrated circuit comprehensive evaluation threshold, batch mark the corresponding integrated circuit to generate a type of integrated circuit marking data;

[0044] Step S34: When the integrated circuit comprehensive evaluation index is less than the preset standard integrated circuit comprehensive evaluation threshold, batch mark the corresponding integrated circuit to generate a type two integrated circuit marking data.

[0045] Through the lowest static power consumption analysis of the standard bias voltage data based on the actual parasitic data of the integrated circuit, the static power consumption level can be quantified to ensure the optimal energy consumption of the circuit under normal working conditions, providing strong data support for low-power design. The current leakage situation of the integrated circuit is obtained through the leakage current test, revealing potential design defects or material problems in the circuit, which helps to improve the durability and reliability of the circuit. The extreme temperature test combined with the leakage current data comprehensively reveals the performance of the integrated circuit in an extreme thermal environment, providing a reliable basis for the application optimization in a high-temperature working environment. The parasitic data, leakage current data, and extreme temperature data are balanced and integrated into an integrated circuit comprehensive evaluation index, forming a unified standard for quantifying performance, providing an efficient tool for batch evaluation, and reducing subjective judgment. According to the comparison between the comprehensive evaluation index and the preset threshold, the type one and type two integrated circuit data are automatically marked to ensure that circuits with excellent performance are assigned to key tasks, while the circuits that need improvement are classified for processing, improving the overall product quality. The marking system combines the results of the comprehensive evaluation, facilitating rapid classification and screening in large-scale production, improving efficiency while reducing the risk of defective product circulation. The test data balancing process takes into account multi-dimensional performance data, ensuring the stability and scientific nature of the evaluation results, thereby enhancing the fault tolerance of the circuit in complex usage environments. The full-process analysis and evaluation guide the design optimization, contributing to the low-power and high-reliability goals of the circuit, meeting the current technological trend of green energy conservation in the electronics industry.

[0046] Preferably, the lowest static power consumption analysis of the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit includes:

[0047] Measure the node capacitance of the actual parasitic data of the integrated circuit to generate node capacitance value data; perform a distributed network modeling on the node capacitance value data to generate parasitic capacitance distribution network data;

[0048] Identify the current flow path of the standard integrated circuit bias voltage acquisition data through the parasitic capacitance distribution network data to generate current flow path characteristic data; extract the critical path from the current flow path characteristic data to generate critical path data;

[0049] Perform bottleneck analysis on critical path data to generate bottleneck feature data; calculate the static power consumption of the standard integrated circuit bias voltage acquisition data through the bottleneck feature data to obtain the integrated circuit static power consumption data; extract the extreme values from the integrated circuit static power consumption data to obtain the lowest static power consumption data of the integrated circuit.

[0050] The present invention generates accurate node capacitance value data through node capacitance measurement, providing basic support for subsequent parasitic capacitance network modeling and helping to more comprehensively analyze the impact of capacitance on circuit power consumption. Using the node capacitance value data for distributed network modeling, the generated parasitic capacitance distribution network data can clearly present the parasitic capacitance distribution in the circuit, providing an intuitive basis for optimization design. Based on the parasitic capacitance distribution network data, through current flow path identification, current flow path feature data is generated, which can effectively track the specific path of the current flowing through the circuit and discover the power consumption key points. Extract critical path data and focus on analyzing the path with the greatest impact on static power consumption, thereby avoiding over-optimization of non-critical paths and improving resource utilization efficiency. Perform bottleneck analysis on the critical path to generate bottleneck feature data, which can intuitively locate the power consumption bottleneck area and provide directional guidance for power consumption reduction. Calculate the static power consumption of the integrated circuit through the bottleneck feature data, and the obtained integrated circuit static power consumption data provides a comprehensive circuit power consumption evaluation result for designers, supporting more efficient power consumption optimization. Extract extreme values from the static power consumption data to generate the lowest static power consumption data of the integrated circuit, setting a clear performance benchmark for the optimization target and promoting the realization of low-power design. The full-process analysis provides a scientific basis for design optimization, especially in the identification and improvement of power consumption bottleneck areas, significantly improving the power consumption efficiency and reliability of the circuit. By optimizing the lowest static power consumption, not only the total energy consumption of the circuit is reduced, but also the performance fluctuations caused by thermal effects are reduced, enhancing the stability and lifespan of the circuit.

[0051] Preferably, step S4 includes the following steps:

[0052] Step S41: Upload the first-class integrated circuit labeled data and the second-class integrated circuit labeled data to the cloud platform for circuit test data storage to generate integrated circuit test storage data;

[0053] Step S42: Visualize the integrated circuit test storage data to generate an integrated circuit test storage report to execute the complete integrated circuit test job.

[0054] The present invention realizes centralized storage of circuit test data by uploading marked data to the cloud platform, generates integrated circuit test storage data, ensures classified management and convenient invocation of type-I and type-II integrated circuit data, and improves data management efficiency. The cloud platform has high reliability and redundancy, can effectively prevent data loss, ensure long-term preservation and efficient backup of integrated circuit test storage data, and enhance data security. The integrated circuit data storage based on the cloud platform supports multi-party real-time sharing and collaboration, simplifies the circulation process of circuit test data among R & D teams, and promotes efficient collaborative operation. The test storage data is converted into a test storage report, which enhances the comprehensibility and intuitiveness of the data through charts, trend analysis, and key indicators, and helps with quick analysis and decision-making. The generation of the test report marks the completion of the complete operation of integrated circuit testing, provides comprehensive test results and key performance indicators, and provides data support for subsequent improvement. The test report visually presents the performance comparison and anomaly analysis of type-I and type-II integrated circuits, helps quickly locate problem areas and formulate improvement measures, and improves the performance and quality of integrated circuits. The test data and reports are stored in the cloud, facilitating subsequent R & D personnel to call historical data for analysis, and providing strong support for product iteration and quality tracking.

[0055] In this specification, an integrated circuit test system is provided for performing the above-mentioned integrated circuit test method. The integrated circuit test system includes:

[0056] A bias voltage setting module, configured to obtain integrated circuit structure data; screen key nodes from the integrated circuit structure data to obtain power pins and input pins; perform static bias voltage setting on the power pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data;

[0057] A power supply interference simulation module, configured to superimpose a low-amplitude high-frequency noise source on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; perform power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the voltage acquisition noise data to generate circuit power supply interference simulation data; calculate circuit parasitic indices from the circuit power supply interference simulation data to obtain actual integrated circuit parasitic data;

[0058] A hierarchical test module, configured to perform leakage current testing on the standard integrated circuit bias voltage acquisition data based on the actual integrated circuit parasitic data to obtain integrated circuit leakage current data; perform extreme temperature testing on the integrated circuit through the integrated circuit leakage current data to obtain integrated circuit extreme temperature testing data; perform batch marking on the integrated circuit based on the actual integrated circuit parasitic data, the integrated circuit leakage current data, and the circuit extreme temperature testing data to generate type-I integrated circuit marking data and type-II integrated circuit marking data;

[0059] A data visualization module for uploading a first type of integrated circuit marking data and a second type of integrated circuit marking data to a cloud platform for data visualization, generating an integrated circuit test storage report, and performing a complete integrated circuit test operation.

[0060] The beneficial effects of the present invention are as follows: By screening the power pins and input pins of the integrated circuit structure data, it ensures that the tests focus on the most critical nodes, improving the pertinence and effectiveness of the data. It realizes the unified setting of the static bias voltage, generates high-quality standard bias voltage acquisition data, and provides a stable reference benchmark for subsequent tests. By collecting standardized bias voltage data, it reduces the influence of external interference on the initial data, laying a foundation for the reliability of the subsequent module test results. By superimposing a low-amplitude high-frequency noise source, it simulates the power supply interference in the actual working environment, enhancing the authenticity and comprehensiveness of the tests. Through parasitic index calculation, it quantitatively analyzes the specific impact of parasitic effects on circuit performance, provides a scientific basis for optimizing design and fault diagnosis, and the generated circuit power supply interference simulation data helps to evaluate the anti-interference ability of the integrated circuit to different noise levels, improving the robustness of the product. Combining leakage current testing with extreme temperature testing comprehensively evaluates the performance boundaries and reliability of the integrated circuit under extreme conditions. Based on the integrated analysis of parasitic data, leakage current data, and temperature test data, it can deeply excavate circuit defects and potential risks, improving the test coverage rate. Through batch marking of the test results, it realizes product classification management, supports efficient quality control and rapid anomaly traceability. Uploading the classification marking data to the cloud platform simplifies the analysis and interpretation of complex test data through visualization means, improving the user experience. The storage report supports cross-departmental sharing and collaborative operations, enhancing the work efficiency and transparency of all links in the production chain. The visualization and storage of data provide an important basis for subsequent product optimization and production process improvement, while enhancing the traceability and management capabilities of the test work. Therefore, the present invention improves the accuracy of circuit testing through key node screening, parasitic effect evaluation, multi-dimensional data analysis, and cloud visualization. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 It is a schematic diagram of the step flow of an integrated circuit test method;

[0062] Figure 2 It is Figure 1 a detailed implementation step flow diagram of step S2 in

[0063] Figure 3 It is Figure 1 a detailed implementation step flow diagram of step S3 in

[0064] The realization, functional characteristics, and advantages of the object of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. Detailed implementation mode

[0065] The technical method of the present invention patent will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work belong to the scope of protection of the present invention.

[0066] In addition, the accompanying drawings are only schematic diagrams of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0067] It should be understood that although terms such as "first" and "second" may be used here to describe each unit, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be called the second unit, and similarly the second unit may be called the first unit. The term "and / or" used here includes any and all combinations of one or more of the listed associated items.

[0068] To achieve the above object, please refer to Figures 1 to 3 , an integrated circuit testing method, the method includes the following steps:

[0069] Step S1: Obtain integrated circuit structure data; screen key nodes from the integrated circuit structure data to obtain power pins and input pins; set static bias voltages for the power pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage collection data;

[0070] Step S2: Superimpose a low-amplitude high-frequency noise source on the standard integrated circuit bias voltage collection data to obtain voltage collection noise data; simulate power supply interference on the standard integrated circuit bias voltage collection data through the voltage collection noise data to generate circuit power supply interference simulation data; calculate the circuit parasitic index from the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit;

[0071] Step S3: Based on the actual parasitic data of the integrated circuit, perform leakage current tests on the standard integrated circuit bias voltage acquisition data to obtain integrated circuit leakage current data; perform extreme temperature tests on the integrated circuit through the integrated circuit leakage current data to obtain integrated circuit extreme temperature test data; perform batch marking on the integrated circuit based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate type-one integrated circuit marking data and type-two integrated circuit marking data;

[0072] Step S4: Upload the type-one integrated circuit marking data and the type-two integrated circuit marking data to the cloud platform for data visualization, generate an integrated circuit test storage report, and execute the complete integrated circuit test operation.

[0073] In the present invention, through key node screening, the tests are concentrated on the power pins and input pins, avoiding the interference of unnecessary nodes, and improving the test efficiency and resource utilization rate. The static bias voltage setting ensures the unity and standardization of the data, laying a foundation for the accuracy and comparability of subsequent test results. The generated standard bias voltage data can be used in various test scenarios, such as interference simulation and leakage current tests, enhancing the test applicability. By superimposing low-amplitude high-frequency noise, the working state of the integrated circuit in a complex electromagnetic environment is truly reproduced, improving the comprehensiveness of the test. The power interference simulation data provides a basis for evaluating the impact of power fluctuations on circuit performance, contributing to optimizing the circuit design. The parasitic index calculation quantifies the impact of parasitic effects, providing data support for circuit improvement and defect location, especially applicable to problem diagnosis in high-density circuit designs. Performing leakage current and extreme temperature tests based on parasitic data can deeply understand the performance boundaries and potential risks of the integrated circuit. The comprehensive analysis combining parasitic data, leakage current data, and extreme temperature data provides a panoramic view of the integrated circuit performance. By intelligently marking type-one and type-two products, the efficiency of product classification and quality control is significantly improved, while reducing the error rate of human intervention. The batch marking data supports the traceability of the production chain, providing a basis for subsequent improvement and product grading. After uploading to the cloud platform for visualization, it is convenient for quickly understanding and evaluating the test results, providing an intuitive reference for decision-making. Cloud storage and report generation support cross-departmental collaboration, improving the data sharing efficiency and reducing the risk of information silos. The storage report includes multi-dimensional test results and marking data, providing rich basis for subsequent optimized design and improved test processes. The cloud visualization of the data enhances the transparency of the entire test process, contributing to quality control and the establishment of customer trust. Therefore, the present invention improves the accuracy of circuit testing through key node screening, parasitic effect evaluation, multi-dimensional data analysis, and cloud visualization.

[0074] In the embodiment of the present invention, with reference to Figure 1As shown, it is a schematic diagram of the step flow of a method for testing an integrated circuit according to the present invention. In this example, the method for testing an integrated circuit includes the following steps:

[0075] Step S1: Obtain integrated circuit structure data; screen key nodes from the integrated circuit structure data to obtain power pins and input pins; perform static bias voltage setting on the power pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data;

[0076] In an embodiment of the present invention, the integrated circuit structure data is imported from a design file or a simulation tool, and common formats include SPICE files, Verilog files, or other hardware description language files. Parse the structure data to extract the following key information: the node connection information of the circuit, the logical description of the functional modules, the input and output pins and power pins of each module. If the structure data contains noise or incomplete information, use a circuit parsing tool (such as HSPICE or Cadence Virtuoso) for data cleaning and integrity checking. Parse the connection network of the integrated circuit and screen the nodes: Mark the nodes directly connected to the circuit power rails (VDD / GND). Mark the nodes connected to the external signal source or the interfaces of other modules. Use a graph traversal algorithm (such as depth-first search) to identify the nodes connected to the power supply and input. Classify and mark the node types to generate power pin data and input pin data. According to the circuit design specifications and actual test requirements, determine the following parameters: the target voltage value of the power pin (such as 1.8V, 3.3V). The bias voltage range of the input pin (such as a static value between 0V and the logic high level). Apply a static bias voltage to the pins using a test tool (such as an automated test instrument ATE). Power pin: Provide a constant voltage through a stable power supply module. Input pin: Set the bias voltage through a precision signal generator, record the bias voltage value of each pin, and generate static bias voltage setting data. Use a high-precision voltage acquisition instrument (such as a digital multimeter or a data acquisition module DAQ) to collect the actual bias voltage of each pin. Check whether the collected voltage value is within the error range (such as ±1%). If there is a deviation, adjust the voltage setting until the collected value is consistent with the target value. Save the collected voltage data as standard integrated circuit bias voltage acquisition data, including: pin number and type (power / input), the actually collected bias voltage value, and the deviation information from the target value (such as error range, deviation rate).

[0077] Step S2: Superimpose a low - amplitude high - frequency noise source on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; perform power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the voltage acquisition noise data to generate circuit power supply interference simulation data; calculate the circuit parasitic index for the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit;

[0078] In the embodiments of the present invention, an appropriate noise source model (such as Gaussian white noise or pseudo - random signal) is selected to generate low - amplitude high - frequency noise. The noise amplitude range is set to ±1% of the standard bias voltage. The noise frequency range is set to be 1.5 times higher than the circuit operating frequency. The generated noise signal is superimposed on the standard integrated circuit bias voltage acquisition data, and the formula is used: V_noise(t)=V_bias(t)+N(t); where V_bias(t) is the original bias voltage data and N(t) is the noise signal, to generate voltage acquisition noise data containing noise. A power supply interference model is constructed based on the voltage acquisition noise data. Common models include: power supply ripple interference: superimpose a sine - wave interference signal. Random interference: superimpose a low - frequency random fluctuation signal. The simulated power supply interference formula is: V_interference(t)=V_noise(t)+A·sin(2πft)+R(t), where A is the amplitude of the interference signal, f is the frequency of the interference signal, and R(t) is the low - frequency random signal. Use a simulation tool (such as MATLAB or SPICE simulator) to dynamically simulate the power supply interference. Use a circuit network analysis tool to identify parasitic capacitance and parasitic inductance. Extract the voltage and current fluctuation characteristics caused by the interference, calculate the amplitude and distribution of the parasitic parameters, and generate the actual parasitic data of the integrated circuit

[0079] Step S3: Perform a leakage current test on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to obtain the integrated circuit leakage current data; perform an extreme temperature test on the integrated circuit through the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; perform batch marking on the integrated circuit based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate a first - type integrated circuit marking data and a second - type integrated circuit marking data;

[0080] In the embodiments of the present invention, a static bias voltage is applied by using a standard test device (such as a DC source measurement unit, SMU). The temperature of the test environment is controlled at room temperature (25 °C). According to the actual parasitic data of the integrated circuit, a static bias voltage is applied at key nodes (such as power pins and input pins). The leakage current values of each node are measured, and the leakage current data is normalized to remove accidental errors. The leakage current characteristics of each key node are recorded, including the current amplitude and time stability. A hot stage (or environmental test chamber) is used to set the temperature range: from -40 °C to 125 °C (meeting industrial standards). Pressure is applied according to the bias voltage conditions during the leakage current test. The temperature is gradually increased in steps of 10 °C, and the leakage current values and key circuit parameters are recorded at each step. The temperature is decreased from high to low, and the measurements and data recordings are repeated. The gradient of the leakage current of the key node with respect to temperature change is calculated, and the nodes that fail or have a significant performance degradation at the limit temperature are marked. Based on the following formula, the parasitic data, leakage current data, and limit temperature data are comprehensively analyzed: CI = α·PI + β·ILavg + γ·Tmax; where CI is the comprehensive evaluation index, PI is the parasitic index, ILavg is the average leakage current, Tmax is the limit temperature point, and α, β, γ are weight coefficients, which are adjusted according to the test requirements. When CI ≥ the threshold value, it is marked as a high-performance integrated circuit; when CI < the threshold value, it is marked as an ordinary-performance integrated circuit. The marked data is stored in a database, and a marked report is generated for each batch of circuits.

[0081] Step S4: Upload the marked data of the first-class integrated circuits and the marked data of the second-class integrated circuits to the cloud platform for data visualization, and generate an integrated circuit test storage report to execute the complete integrated circuit test operation.

[0082] In the embodiments of the present invention, a connection is made to the cloud platform by using a standard cloud storage interface (such as REST API). A security authentication mechanism (such as OAuth2 or key authentication) is configured to ensure the security of data transmission. The marked data of the first-class integrated circuits and the marked data of the second-class integrated circuits are uploaded in JSON or CSV format. Each piece of data contains the following fields: marked category (such as first-class or second-class), test metrics (such as leakage current, limit temperature), timestamp, batch number. After the upload is completed, a data integrity check is performed to ensure that there is no data loss or damage. A professional data visualization tool (such as Tableau, Power BI) or the built-in visualization module of the cloud platform is used. A bar chart or pie chart is used to display the quantity distribution of the first-class and second-class integrated circuits. A line chart is used to show the trend of the leakage current changing with temperature. A scatter plot is used to compare the performance differences of different batches of integrated circuits.

[0083] Preferably, step S1 includes the following steps:

[0084] Step S11: Obtain the integrated circuit structure data;

[0085] Step S12: Perform circuit pin analysis on the integrated circuit structure data to generate integrated circuit pin data; based on the integrated circuit pin data, screen the key nodes of the integrated circuit structure to obtain the key nodes of the integrated circuit, where the key nodes of the integrated circuit include power pins and input pins;

[0086] Step S13: Set static bias voltages for the power pins and input pins to generate static bias voltage setting data; use a voltage sensor to collect bias voltages for the static bias voltage setting data to obtain integrated circuit bias voltage acquisition data;

[0087] Step S14: Perform data preprocessing on the integrated circuit bias voltage acquisition data to generate standard integrated circuit bias voltage acquisition data, where the data preprocessing includes data cleaning, data denoising, filling missing data values, and data standardization.

[0088] In the embodiments of the present invention, circuit structure data is extracted from integrated circuit design files (such as GDSII files or Verilog codes). These data can be extracted through EDA tools (such as Cadence, Synopsys). Information such as the layout, hierarchy, component distribution, and pin layout of the circuit is obtained. This data includes the geometries, connection relationships, and electrical parameters (such as resistance, capacitance, etc.) of all integrated circuit components. Each component of the integrated circuit is analyzed to lead out the pins connected to the circuit board or other components. This process can be automated through graphics processing algorithms or EDA tools. According to the circuit design rules, key nodes such as power pins, input pins, output pins, and ground pins are identified. Algorithms (such as graph theory analysis) can be used to filter the key nodes in the circuit. Based on the filtered key nodes, a pin dataset is created to record information such as the position, function (power supply, input, output, etc.), and electrical characteristics of each pin. Static bias voltage values are assigned to each power pin and input pin. Usually, these voltage values are set according to the operating voltage and design specifications of the circuit. For example, low-voltage logic circuits require a 3.3V or 5V power supply, while analog circuits require more precise voltage values. A voltage configuration file is created to record the static bias voltage values of each pin. This file can be in the form of a spreadsheet, JSON format, or database for subsequent analysis and verification. Voltage sensors (such as digital oscilloscopes, multimeters, etc.) are deployed to measure the voltages of the key nodes of the integrated circuit. The sensors should have high precision and low noise characteristics to ensure the reliability of the measurement data. Voltage data of the power pins and input pins are collected, and the actual voltage values and acquisition timestamps of each node are recorded. These data will be used for subsequent bias voltage analysis. Invalid data (such as abnormal data points caused by sensor failures) is removed. Standard data cleaning techniques such as removing extreme values and filtering can be used. Appropriate noise filtering methods (such as mean filtering, Kalman filtering, etc.) are used to reduce the noise in the collected data to ensure the accuracy of the voltage data. For missing voltage data, interpolation algorithms (such as linear interpolation, Lagrange interpolation, etc.) can be used to fill it to maintain the continuity of the data. The voltage data is normalized to a unified range, usually [0,1] or a standard normal distribution (mean 0, standard deviation 1) for subsequent data analysis and modeling.

[0089] Preferably, the static bias voltage setting for the power pins and input pins includes:

[0090] Defining the operating voltage range for the power pins to obtain the power pin operating voltage range; defining the normal logic level range for the input pins to obtain the input pin normal logic level range;

[0091] Based on the operating voltage range of the power supply pin and the normal logic level range of the input pin, expand the bias voltage range for the key nodes of the integrated circuit to generate bias voltage range expansion data; according to the bias voltage range expansion data, perform test voltage step setting on the key nodes of the integrated circuit to generate a serialized list of test points;

[0092] According to the serialized list of test points, perform static bias voltage setting on the power supply pin and the input pin based on the preset stabilization time to generate static bias voltage setting data.

[0093] In the embodiments of the present invention, the operating voltage range of the power supply pins is obtained from the integrated circuit design files or specifications, which generally depends on the type of the integrated circuit (e.g., digital circuit, analog circuit) and the design standards. For example, low-voltage logic circuits usually adopt power supply voltages such as 3.3V and 5V, while high-performance analog circuits require ±15V or higher voltages. When defining the power supply voltage range, the rated voltage of the power supply pins, the allowable voltage fluctuation range, and the minimum / maximum operating voltages of the power supply voltage should be considered. Record the operating voltage range of the power supply pins in the form of a table or other data structures, including the minimum voltage, the maximum voltage, and the recommended operating voltage. Define the normal logic levels of the input pins based on the design standards. For example, logic "0" can be 0V, and logic "1" can be 3.3V or 5V, depending on the operating voltage of the system. Generally, the low-level logic level (V_Low) range can be from 0V to 0.8V, and the high-level logic level (V_High) range can be from 2V to 3.3V. Standardize the definition of the logic levels of the input pins according to the data sheet or the circuit design document. When defining the logic level range of the input pins, it is necessary to ensure that when the circuit operates within this range, the signal is stable and meets the logical requirements (e.g., appropriate threshold voltage). According to the operating voltage range of the power supply pins and the normal logic level range of the input pins, the bias voltage range of the key nodes (such as power supply pins, input pins) of the integrated circuit can be extended. The extended voltage range should include the upper / lower boundaries of the power supply voltage and the logic level range of the input pins, so that the circuit can operate normally within a larger voltage range, considering the possible errors or fluctuations of the circuit. Generate the voltage extension range of each node through programming or algorithms. For example, for the power supply pins, the extension range is [the lowest power supply voltage, the highest power supply voltage]; for the input pins, the extension range is [the lowest voltage of logic 0, the highest voltage of logic 1], and generate a data table or list containing the extended voltage ranges of each circuit node. The data includes the name of the node, the voltage type (power supply, voltage bias, etc.), the extension range (minimum value, maximum value), etc. According to the extended data of the bias voltage range, define the voltage step size of each test node. The step value is usually determined according to the size of the voltage range and the test accuracy requirements. For example, if the voltage range is large (e.g., 0V to 10V), the step can be 0.1V or 0.2V; if the voltage range is small (e.g., 3.3V to 5V), the step can be 0.05V or smaller. According to the minimum value, the maximum value, and the step size of the range, calculate the voltage values of each test point through a program. For example, start from the minimum voltage value and increase by the step value each time until the maximum voltage value. Arrange the test voltage points in ascending order of voltage to form a list containing voltage values. Each test point includes information such as the voltage value, the corresponding test node, and the voltage state.If the test point range is [3V, 5V] and the step is 0.1V, then the serialized list of test points is: [3.0V, 3.1V, 3.2V,..., 5.0V]. A stabilization time is defined for each test point, which is to ensure that the circuit operates stably at each voltage point. Usually, the stabilization time depends on the response speed of the circuit and ranges from a few microseconds to a few milliseconds. This parameter can be determined through experience or calculation based on the circuit model. Assume that the stabilization time for each test point is set to 10 milliseconds. Through an automated test system or a hardware interface, a static bias voltage is set at each test point. After each voltage adjustment, the system waits for the preset stabilization time to ensure that the circuit operates stably at that voltage. After the settings at each voltage point are completed, the voltage value of the node and its corresponding stabilization time are recorded to form the static bias voltage setting data. For example, the data table records the following information: Node: Power pin 1, Input pin 2, Voltage: 3.0V, 3.1V, 3.2V…, Stabilization time: 10ms.

[0094] As an example of the present invention, refer to Figure 2 shown. In this example, step S2 includes:

[0095] Step S21: Superimpose a low-amplitude high-frequency noise source on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data through the voltage acquisition noise data to generate circuit power supply interference simulation data;

[0096] Step S22: Use an oscilloscope to measure the output waveform of the circuit power supply interference simulation data, and judge the abnormal output response of the measured output waveform to obtain an abnormal output response discrimination strategy;

[0097] Step S23: Adjust the signal frequency of the circuit power supply interference simulation data according to the abnormal output response discrimination strategy to generate a circuit power supply interference adjustment signal;

[0098] Step S24: Perform cyclic power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the circuit power supply interference adjustment signal to generate circuit power supply interference cyclic simulation data; calculate the circuit parasitic index of the circuit power supply interference cyclic simulation data to obtain the actual parasitic data of the integrated circuit.

[0099] In the embodiments of the present invention, by defining a noise source, a low-amplitude high-frequency noise source generally refers to a noise signal with a relatively low amplitude (e.g., 10 mV to 100 mV) and a relatively high frequency (such as dozens of MHz to hundreds of MHz). Such a noise signal can simulate high-frequency noise from interference sources such as power supplies and ground wires. A signal generator or a digital signal processor (DSP) is used to generate the required noise signal. The high-frequency noise source can be simulated by a random noise signal or a white noise source. The generated low-amplitude high-frequency noise signal is superimposed on the bias voltage acquisition data of a standard integrated circuit. This process can be implemented through hardware (such as an oscilloscope) or software simulation. Through simple superimposition operations, the noise signal is added to the voltage data. Through the above superimposition operation, voltage acquisition data with noise is finally obtained, that is, voltage acquisition noise data, which simulates the power supply interference and noise effects on the integrated circuit during operation. The interference simulation target is to simulate the noise or power supply fluctuations that occur in the power supply or circuit, especially the interference caused by factors such as high-frequency noise and ground wire return. The noise signal output by the signal generator can be utilized, or a power supply noise interference model can be added by performing modeling and simulation in computer software. Simulation software (such as Spice, ADS) can be used for power supply interference modeling, or the interference can be achieved by actually superimposing noise signals on hardware. Interference simulation is performed on the bias voltage acquisition data of the integrated circuit through the voltage acquisition noise data. The specific process can be through time-domain or frequency-domain analysis, applying the noise signal to key nodes in the circuit (such as power pins, input pins, etc.) to generate a voltage data set with interference. Finally, circuit power supply interference simulation data is obtained, including the voltage changes and responses of the integrated circuit under the action of power supply interference. Connect an oscilloscope to the output node of the integrated circuit (such as the output pin, key signal node, etc.) to measure the output waveform of the circuit after power supply interference simulation. The oscilloscope can capture the output signal in real time and display the waveform. Measure the basic parameters of the output waveform, including amplitude, frequency, waveform distortion, rise time, fall time, etc. Pay particular attention to the noise, amplitude fluctuations, and non-linear responses in the waveform. By analyzing the measured output waveform, determine whether the circuit exhibits an abnormal response. Abnormal responses are manifested as waveform distortion, excessive noise, excessive voltage fluctuations, etc. Use a threshold method (such as setting an allowable noise range) or a model-based method (such as comparing with the expected normal waveform) to determine whether the waveform is abnormal. A discriminant strategy can be trained through a machine learning model to identify waveforms that do not conform to normal operation. Finally, a set of abnormal output response discriminant strategies is obtained, which defines which waveform features represent abnormal behavior of the circuit under power supply interference. According to the discriminant abnormal response strategy, adjust the frequency of the power supply interference signal to observe the impact of frequency on the circuit performance. The purpose of frequency adjustment is to test the stability and response ability of the circuit under power supply interference at different frequencies. The frequency of the power supply interference signal can be dynamically adjusted through a signal generator or software tool, scanning different frequency ranges from low frequency to high frequency.For example, it can be adjusted in the frequency range from 1 MHz to 100 MHz to observe how the output waveform changes. New power interference signal data is generated according to the adjusted frequency range. This signal data contains power interference simulation information at different frequencies and can be applied to further testing of the circuit. At different power interference signal frequencies, power interference is periodically simulated to test the stability of the circuit under continuous interference. By applying power interference signals with different frequencies to the power port and input port, the influence of continuous power disturbance on the circuit performance is simulated. The power interference signal will be repeatedly applied within multiple cycles to simulate a continuous interference environment. Through multiple simulations of the interference signal, circuit simulation data containing cyclic power interference effects at different frequencies is finally obtained. The circuit parasitic index refers to a quantitative index of the circuit parasitic effect caused by factors such as power supply, ground wire, and capacitance, and is usually related to voltage fluctuations, current anomalies, impedance changes, etc. By analyzing the response of the circuit under different interference signals, methods such as frequency-domain analysis and time-domain waveform fitting are used to calculate the parasitic index. Mathematical models (such as RC and RL circuit models) can be used to model the parasitic effect, and parasitic parameters are extracted from the simulation data. According to the calculation results of the circuit parasitic index, parasitic data of the integrated circuit in the actual working environment is obtained, and these data can be used to optimize the circuit design and improve the anti-interference ability.

[0100] Preferably, the discrimination of the abnormal output response for the measured output waveform includes:

[0101] Calculating the waveform average value and standard deviation of the measured output waveform to obtain the output waveform average value and the output waveform standard deviation; discriminating the waveform amplitude abnormality of the measured output waveform according to the output waveform average value and the output waveform standard deviation to generate waveform amplitude abnormality discrimination data;

[0102] Performing waveform timing analysis on the measured output waveform to generate output waveform timing data; discriminating the time delay overrun of the measured output waveform based on the output waveform timing data to generate waveform timing abnormality discrimination data;

[0103] Performing waveform shape analysis on the measured output waveform to generate output waveform shape data; discriminating the waveform shape distortion of the measured output waveform based on the output waveform shape data to generate waveform morphology abnormality discrimination data;

[0104] Based on the waveform amplitude abnormality discrimination data, the waveform timing abnormality discrimination data, and the waveform morphology abnormality discrimination data, discriminating the abnormal output response of the measured output waveform to obtain the abnormal output response discrimination strategy.

[0105] In the embodiment of the present invention, by acquiring the measured output waveform data and performing discretization processing on it, a waveform data sequence is obtained. Waveform average value calculation: where μ is the waveform average value, N is the total number of data points, and x i is the i-th data point in the waveform data sequence. The waveform standard deviation is calculated as follows: where σ is the waveform standard deviation and μ is the average value of the output waveform. The average value and standard deviation of the output waveform are obtained and named "output waveform average value" and "output waveform standard deviation" respectively. The amplitude threshold is set according to the average value and standard deviation of the output waveform. If the amplitude of the waveform exceeds a certain predetermined normal range (for example, a range exceeding 3 times the standard deviation), the waveform amplitude is considered abnormal. The amplitude abnormality discrimination formula is: A = max(x) - min(x); where A is the amplitude of the waveform, and max(x) and min(x) are the maximum and minimum values of the waveform data respectively. If A > k×σ, it is determined that the waveform amplitude is abnormal. k is the multiple factor for amplitude abnormality discrimination (for example, k = 3), and "waveform amplitude abnormality discrimination data" is generated to record whether amplitude abnormality occurs. Time-domain analysis is used to calculate the timing characteristics of the waveform such as rise time, fall time, and periodicity. Mathematical models (such as Fourier transform, timing correlation analysis, etc.) are used to extract the timing data. Feature extraction such as periodicity and time delay of the waveform is performed. The moving average across a time window or the timing analysis method based on zero-crossing points can be used to generate the output waveform timing data, and the maximum allowable time delay threshold is set. The time delay of the output waveform is discriminated based on the timing data. If the rise time, fall time, or propagation delay is greater than the predetermined threshold, it is determined that the time delay is abnormal. Whether it exceeds the normal range is judged according to the rise time, fall time, and signal delay in the timing data. This includes but is not limited to the period, delay, rise, and fall times of the waveform, etc., and "waveform timing abnormality discrimination data" is generated to record whether time delay exceeds the limit. The output waveform is fitted and matched, for example, using high-order polynomial fitting or Fourier analysis-based methods, to obtain the ideal shape of the waveform. By comparing the error between the actual waveform and the fitted waveform, or by calculating the characteristics such as the peak value, trough value, and symmetry of the waveform, it is determined whether the shape is distorted. If the difference between the waveform and the normal shape exceeds the set threshold (for example, the fitting error exceeds a certain threshold), the waveform shape is considered distorted, and "waveform shape abnormality discrimination data" is generated to record whether waveform shape distortion occurs. The three discrimination results of waveform amplitude abnormality, timing abnormality, and shape abnormality are comprehensively analyzed. If any one of the discrimination results is abnormal, it is determined that the output response is abnormal. The comprehensive discrimination formula is: abnormal output response = amplitude abnormality ∨ timing abnormality ∨ shape abnormality, and the "abnormal output response discrimination strategy" is obtained, that is, it is comprehensively determined whether there is an abnormal response in the output waveform.

[0106] Preferably, calculating the circuit parasitic index for the circuit power supply interference cycle simulation data includes:

[0107] Screen the circuit transistor structure data from the integrated circuit structure data to obtain the circuit transistor structure data; perform an analysis of the change in the transistor threshold voltage on the circuit transistor structure data based on the circuit power supply interference cycle simulation data to generate the circuit transistor threshold voltage change data;

[0108] Perform an analysis of the change in the gate length of the transistors in the integrated circuit based on the circuit transistor threshold voltage change data to generate the transistor gate length change data; conduct a parasitic effect test through the circuit power supply interference cycle simulation data to generate the integrated circuit parasitic effect test data;

[0109] Use the transistor gate length change data to calculate the actual parasitic index of the circuit for the integrated circuit parasitic effect test data to obtain the actual parasitic data of the integrated circuit, where the formula for calculating the actual parasitic index of the circuit is as follows:

[0110]

[0111] In the formula, P represents the actual parasitic data of the integrated circuit, ɑ represents the influence coefficient of capacitance on the circuit performance, β represents the influence coefficient of resistance on the circuit performance, K represents the proportionality factor, W represents the transistor width, L g,act represents the actual transistor gate length, L g represents the designed length of the transistor gate, R0 represents the constant of the drain-source resistance, and B represents the integrated circuit parasitic effect test value.

[0112] In the embodiments of the present invention, the transistor structure information in integrated circuit design includes the type, size, gate length, connection of source and drain of the transistor, etc. According to the integrated circuit design specifications, all transistor nodes are extracted, and the transistors affected by power supply interference are screened out. Specifically, the netlist data in the design file can be used to screen according to the type and connection of the transistors, and the screened circuit transistor structure data set is obtained, recording the type, size parameters, etc. of each transistor. The power supply interference cycle simulation data is used to analyze the working state of the transistors under different power supply interference conditions. By applying periodic interference to the power input terminal, the voltage change in the circuit is simulated. According to the results of the power supply interference simulation, the change of the threshold voltage of the transistor under different interference conditions is calculated. The threshold voltage can be extracted by measuring the source voltage and drain voltage, and using the current-voltage (I-V) characteristic curve to generate the circuit transistor threshold voltage change data, recording the change of the threshold voltage of each transistor under different power supply interferences. The change of the threshold voltage is closely related to the gate length of the transistor. During the change of the threshold voltage, the influence of the change of the gate length on the transistor can be analyzed. By modifying the gate length parameter in the circuit simulation environment, its influence on the threshold voltage is observed. Based on the transistor threshold voltage change data, the influence of the change of the gate length is deduced. The device-level simulation tool (such as SPICE) can be used for analysis, calculating the change of the electrical performance under different gate lengths, generating the transistor gate length change data, and recording the influence of the change of the transistor gate length under different power supply interference conditions. By simulating different types of power supply interference (such as voltage noise, current noise, etc.), the influence of power supply interference on the circuit parasitic effect is evaluated. Dynamic simulation (such as through time-domain simulation) or frequency-domain simulation can be used to analyze how power supply noise affects the circuit parasitic effect. The power supply interference simulation data is cycled in the simulation environment, and the circuit is tested for power supply interference multiple times. The test results are recorded, especially the changes in current and voltage and the noise spectrum, generating the integrated circuit parasitic effect test data and recording the parasitic effect generated by the power supply interference on the circuit. According to the influence of the change of the transistor gate length and the power supply interference on the circuit parasitic effect, the actual parasitic index of the integrated circuit is calculated. The actual parasitic index of the circuit is calculated using the following formula: where P represents the actual parasitic data of the integrated circuit, ɑ represents the influence coefficient of capacitance on the circuit performance, β represents the influence coefficient of resistance on the circuit performance, K represents the proportionality factor, W represents the transistor width, L g,act represents the actual transistor gate length, L gis denoted as the designed length of the transistor gate, R0 is denoted as the constant of the drain-source resistance, and B is denoted as the test value of the parasitic effect of the integrated circuit. According to the previously obtained data on the change of the transistor gate length and the simulation data of power supply interference, substitute them into the formula to calculate the parasitic index of each transistor or circuit node, generate the actual parasitic data of the integrated circuit, and record the parasitic effect of the circuit under power supply interference.

[0113] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes:

[0114] Step S31: Perform the lowest static power consumption analysis on the collected data of the standard integrated circuit bias voltage based on the actual parasitic data of the integrated circuit to generate the lowest static power consumption data of the integrated circuit; perform a leakage current test on the lowest static power consumption data of the integrated circuit to obtain the leakage current data of the integrated circuit;

[0115] Step S32: Perform an extreme temperature test on the integrated circuit through the leakage current data of the integrated circuit to obtain the extreme temperature test data of the integrated circuit; perform test data balancing according to the actual parasitic data of the integrated circuit, the leakage current data of the integrated circuit, and the extreme temperature test data of the integrated circuit to obtain the comprehensive evaluation index of the integrated circuit;

[0116] Step S33: Compare the comprehensive evaluation index of the integrated circuit with the preset standard integrated circuit comprehensive evaluation threshold. When the comprehensive evaluation index of the integrated circuit is greater than or equal to the preset standard integrated circuit comprehensive evaluation threshold, batch mark the corresponding integrated circuit to generate the first-class integrated circuit mark data;

[0117] Step S34: When the comprehensive evaluation index of the integrated circuit is less than the preset standard integrated circuit comprehensive evaluation threshold, batch mark the corresponding integrated circuit to generate the second-class integrated circuit mark data.

[0118] In the embodiments of the present invention, by using the actual parasitic data of the integrated circuit, which are derived from the parasitic resistance, capacitance of the circuit, and the variation of the transistor threshold voltage, etc. Based on these data, the power consumption of the circuit in the working state is calculated through a power consumption model (such as a static power consumption model or a power consumption estimation formula). Usually in static power consumption analysis, the working state of the circuit can be defined as the power consumption under the lowest load, and the minimum static power consumption is usually the total power consumption related to the source-drain current and leakage current of the transistor at the power supply voltage, generating the lowest static power consumption data of the integrated circuit and recording the power consumption value under the minimum working load condition. According to the lowest static power consumption data, combined with the leakage current of each transistor in the circuit (the leakage current is mainly determined by the power supply voltage, working temperature, and transistor characteristics), the leakage current is measured. A dedicated leakage current test device (such as a precision current detector) can be used to test the leakage current of the circuit. By adjusting the bias voltage and measuring the leakage current of the integrated circuit, its energy efficiency in the minimum load state is judged, and the leakage current data of the integrated circuit, that is, the leakage current value in the lowest power consumption state, is obtained. According to the leakage current data of the integrated circuit, the integrated circuit is subjected to a temperature cycle test at different temperatures. The test temperature range should cover the extreme temperature of the circuit's working environment (such as high temperature 150°C, low temperature -40°C). At different temperatures, by controlling the temperature change of the test environment, the change of the leakage current is observed. The change of temperature usually affects the leakage current of the transistor, so the change of the leakage current at different temperatures is crucial for evaluating the performance of the circuit. An environmental temperature control device (such as a temperature control box, hot plate) is used to simulate the extreme working temperature under laboratory conditions, recording the current change of the circuit at different temperatures, obtaining the extreme temperature test data of the integrated circuit, and recording the change of the leakage current and the stability of the circuit performance under different temperature conditions. Using data standardization and normalization techniques, different test data (leakage current, temperature, parasitic effect, etc.) are converted into a unified standard format. Based on the following formula, the data is balanced: Comprehensive evaluation index = w1 · standardized leakage current value + w2 · standardized temperature influence value + w3 · standardized parasitic effect value, where w1, w2, and w3 are the weights of each data in the comprehensive evaluation, usually adjusted through data analysis or expert experience, generating the comprehensive evaluation index of the integrated circuit, and this index reflects the comprehensive performance of the integrated circuit in multiple aspects (static power consumption, leakage current, temperature influence, etc.). The calculated comprehensive evaluation index of the integrated circuit is compared with the preset standard integrated circuit comprehensive evaluation threshold. If the comprehensive evaluation index is greater than or equal to the preset standard threshold, it is considered that the performance of the integrated circuit meets the standard requirements and is suitable for mass production. If the comprehensive evaluation index is less than the preset standard, it is considered that the integrated circuit has performance problems and needs to be improved or is not suitable for mass production, generating type I integrated circuit marking data (circuits that meet the standard requirements) or type II integrated circuit marking data (circuits that do not meet the standard requirements). Batch marking is carried out on the integrated circuits whose comprehensive evaluation index of the integrated circuit is less than the standard threshold.Integrated circuits of this batch will be classified as Class II integrated circuits and are not suitable for mass production. Generate Class II integrated circuit marker data for relevant teams to conduct performance analysis, improve the design, or modify the production process.

[0119] Preferably, the lowest static power consumption analysis of the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit includes:

[0120] Measure the node capacitance of the actual parasitic data of the integrated circuit to generate node capacitance value data; perform distributed network modeling on the node capacitance value data to generate parasitic capacitance distribution network data;

[0121] Identify the current flow path of the standard integrated circuit bias voltage acquisition data through the parasitic capacitance distribution network data to generate current flow path characteristic data; extract the critical path from the current flow path characteristic data to generate critical path data;

[0122] Conduct bottleneck analysis on the critical path data to generate bottleneck characteristic data; calculate the static power consumption of the standard integrated circuit bias voltage acquisition data through the bottleneck characteristic data to obtain the integrated circuit static power consumption data; extract the extreme value from the integrated circuit static power consumption data to obtain the lowest static power consumption data of the integrated circuit.

[0123] In the embodiments of the present invention, capacitance measurements are performed on each node of an integrated circuit by using a capacitance measurement tool (such as a capacitance meter or circuit simulation software). Direct capacitance measurements are made on each node in the integrated circuit (such as the source, drain, gate of a transistor, etc.) or the capacitance value is calculated through a simulation tool. The output result is capacitance value data for each node, including information such as the capacitance value of each node and the capacitance coupling between nodes, obtaining node capacitance value data, and recording the capacitance value of each node. Based on the node capacitance value data, a coupling network model of the capacitances in the circuit is established by using circuit simulation software (such as SPICE or a custom model). Each capacitance node can be capacitively coupled to other nodes to form a distributed capacitance network. During the modeling process, the parasitic capacitance effect needs to be considered, that is, each capacitance node is not only directly capacitively coupled to adjacent nodes, but also the mutual influence in the global capacitance network needs to be considered, generating parasitic capacitance distribution network data, including a detailed description of the capacitance coupling relationship between nodes and the capacitance network structure in the circuit. Based on the parasitic capacitance distribution network data, using a current flow simulation algorithm, identify the paths along which current flows in the circuit, and these paths reflect the power consumption hotspots and the direction of current flow in the circuit. Use current tracing technology to track the current paths, from the power supply to the load and between each capacitance node, identify the main current paths, generating current flow path characteristic data, describing the main paths, flow direction, and flow intensity of current flowing in the circuit. Based on the current flow path characteristic data, use critical path analysis technology to identify the paths that contribute the most to power consumption from the current paths. Usually, these paths are the paths that flow through the power supply, input pins, and main loads. When extracting the critical paths, current density analysis can be used to identify the paths with higher current density, and these paths contribute more to the static power consumption. Factors such as capacitance, transistor characteristics, and input voltage can also be considered to further determine the most important current paths, generating critical path data, including the main current flow paths that affect the static power consumption. Based on the critical path data, analyze at which nodes, which capacitances, or transistor components there are performance bottlenecks during current flow. Use a power consumption bottleneck analysis method to evaluate in different operating states which current paths have current limitations and excessive power consumption. Bottlenecks occur in areas with high current density, non-linear components, high voltage areas, or paths with long current flow, generating bottleneck characteristic data, describing the location of the power consumption bottleneck and the reasons for the bottleneck. Based on the bottleneck characteristic data, calculate the power consumption of the circuit in the static state. At this time, the power consumption is jointly determined by the capacitance of each node, the leakage current, and the current density of the current path. Use a power consumption calculation model to comprehensively calculate factors such as the current, power loss, and capacitance coupling on each current path to obtain the static power consumption of the integrated circuit, obtaining the static power consumption data of the integrated circuit, that is, the power consumption of each current path under static conditions.Extract the extreme values from the static power consumption data of the integrated circuit to find the lowest power consumption value, which is usually the minimum static power consumption under the optimal conditions of power supply voltage, input voltage, and current path. Use data analysis methods (such as minimum value extraction, extreme value search algorithm) to extract the minimum value from the power consumption data and confirm the working state corresponding to this minimum value to obtain the lowest static power consumption data of the integrated circuit, that is, the static power consumption under the optimal conditions.

[0124] Preferably, step S4 includes the following steps:

[0125] Step S41: Upload the first-class integrated circuit marking data and the second-class integrated circuit marking data to the cloud platform for storing circuit test data, and generate integrated circuit test storage data;

[0126] Step S42: Visualize the integrated circuit test storage data to generate an integrated circuit test storage report to execute the complete integrated circuit test job.

[0127] In the embodiment of the present invention, by organizing the first-class integrated circuit marking data and the second-class integrated circuit marking data into a structured format, usually in JSON, XML, or CSV format. The data format should include the following content: the category of integrated circuit marking (such as first-class, second-class), test parameter data (such as leakage current, power consumption, temperature, etc.), test timestamp, test environment, device information, etc. Preprocess the data to ensure that there are no missing values before uploading, and perform necessary cleaning and formatting. Select a cloud platform that supports big data storage and fast reading (such as AWS, Azure, Google Cloud). Use the data upload API provided by the cloud platform, such as AWS S3, Google Cloud Storage, Azure Blob Storage, to upload the data. During the upload process, ensure the security and encryption of the data to prevent data loss or leakage. When uploading the data, utilize the metadata storage function of the cloud platform (such as creating data tags or indexes) for quick retrieval and management of the data, and generate integrated circuit test storage data, that is, all the first-class and second-class integrated circuit test data uploaded to and stored in the cloud platform. Use the data extraction interface of the cloud platform (such as AWS Athena, Google BigQuery) to retrieve the test storage data from the storage. Convert the data into a format suitable for visual display, usually using Pandas or SQL to clean, normalize, fill in missing values, etc. Ensure that the data contains important metrics, such as test parameters like power consumption, temperature, voltage, etc., and the classification marks for each type of integrated circuit. Use a data visualization tool (such as Tableau, Power BI, Matplotlib or Seaborn in Python) to visualize the integrated circuit test data.

[0128] In this specification, an integrated circuit test system is provided for performing the above-mentioned integrated circuit test method. The integrated circuit test system includes:

[0129] A bias voltage setting module, configured to obtain integrated circuit structure data; screen key nodes from the integrated circuit structure data to obtain power pins and input pins; perform static bias voltage setting on the power pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data;

[0130] A power supply interference simulation module, configured to superimpose a low-amplitude high-frequency noise source on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; perform power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the voltage acquisition noise data to generate circuit power supply interference simulation data; calculate circuit parasitic indices from the circuit power supply interference simulation data to obtain actual integrated circuit parasitic data;

[0131] A hierarchical test module, configured to perform leakage current tests on the standard integrated circuit bias voltage acquisition data based on the actual integrated circuit parasitic data to obtain integrated circuit leakage current data; perform extreme temperature tests on the integrated circuit through the integrated circuit leakage current data to obtain integrated circuit extreme temperature test data; perform batch marking on the integrated circuit based on the actual integrated circuit parasitic data, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate first-class integrated circuit marking data and second-class integrated circuit marking data;

[0132] A data visualization module, configured to upload the first-class integrated circuit marking data and the second-class integrated circuit marking data to a cloud platform for data visualization, generating an integrated circuit test storage report to execute a complete integrated circuit test operation.

[0133] The beneficial effects of the present invention are as follows: By screening the power pins and input pins of the integrated circuit structure data, it ensures that the tests focus on the most critical nodes, improving the pertinence and effectiveness of the data. It realizes the unified setting of the static bias voltage, generates high-quality standard bias voltage acquisition data, and provides a stable reference benchmark for subsequent tests. By collecting standardized bias voltage data, it reduces the influence of external interference on the initial data, laying a foundation for the reliability of the subsequent module test results. By superimposing a low-amplitude high-frequency noise source, it simulates the power supply interference in the actual working environment, enhancing the authenticity and comprehensiveness of the tests. Through parasitic index calculation, it quantitatively analyzes the specific impact of parasitic effects on circuit performance, provides a scientific basis for optimizing design and fault diagnosis, and the generated circuit power supply interference simulation data helps to evaluate the anti-interference ability of the integrated circuit to different noise levels, improving the robustness of the product. Combining leakage current testing and extreme temperature testing comprehensively evaluates the performance boundary and reliability of the integrated circuit under extreme conditions. Based on the integrated analysis of parasitic data, leakage current data, and temperature test data, it can deeply explore circuit defects and potential risks, improving the test coverage rate. By batch-marking the test results, it realizes product classification management, supports efficient quality control and rapid anomaly tracing. Uploading the classified marked data to the cloud platform simplifies the analysis and interpretation of complex test data through visualization means, improving the user experience. The storage report supports cross-departmental sharing and collaborative operations, enhancing the work efficiency and transparency of all links in the production chain. The visualization and storage of data provide an important basis for subsequent product optimization and production process improvement, while enhancing the traceability and management ability of the test work. Therefore, the present invention improves the accuracy of circuit testing through key node screening, parasitic effect evaluation, multi-dimensional data analysis, and cloud visualization.

[0134] Therefore, from any perspective, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to encompass all changes within the meaning and scope of the equivalent elements of the application document within the present invention.

[0135] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features invented herein.

Claims

1. An integrated circuit testing method, characterized in that, It includes the following steps: Step S1: Obtain the integrated circuit structure data; screen the key nodes of the integrated circuit structure data to obtain the power pins and input pins; Set static bias voltages for the power pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data; Step S2: Superimpose low-amplitude high-frequency noise sources on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data through the voltage acquisition noise data to generate circuit power supply interference simulation data; calculate the circuit parasitic index from the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit; Step S3: Perform leakage current tests on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to obtain the leakage current data of the integrated circuit; perform extreme temperature tests on the integrated circuit through the leakage current data of the integrated circuit to obtain the extreme temperature test data of the integrated circuit; perform batch marking on the integrated circuit based on the actual parasitic data of the integrated circuit, the leakage current data of the integrated circuit, and the extreme temperature test data of the circuit to generate type I integrated circuit marking data and type II integrated circuit marking data; Step S4: Upload the type I integrated circuit marking data and type II integrated circuit marking data to the cloud platform for data visualization to generate an integrated circuit test storage report to execute the complete integrated circuit test operation.

2. The integrated circuit testing method according to claim 1, wherein Step S1 includes the following steps: Step S11: Obtain the integrated circuit structure data; Step S12: Analyze the circuit pins of the integrated circuit structure data to generate integrated circuit pin data; screen the key nodes of the integrated circuit structure data based on the integrated circuit pin data to obtain the key nodes of the integrated circuit, where the key nodes of the integrated circuit include power pins and input pins; Step S13: Set static bias voltages for the power pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data using a voltage sensor to obtain the bias voltage acquisition data of the integrated circuit; Step S14: Perform data preprocessing on the bias voltage acquisition data of the integrated circuit to generate standard integrated circuit bias voltage acquisition data, where the data preprocessing includes data cleaning, data denoising, filling missing data values, and data standardization.

3. The integrated circuit testing method according to claim 2, wherein Setting static bias voltages for the power pins and input pins includes: Define the operating voltage range for the power pins to obtain the operating voltage range of the power pins; define the normal logic level range for the input pins to obtain the normal logic level range of the input pins; Expand the bias voltage range for the key nodes of the integrated circuit based on the operating voltage range of the power pins and the normal logic level range of the input pins to generate bias voltage range expansion data; set the test voltage step for the key nodes of the integrated circuit according to the bias voltage range expansion data to generate a serialized list of test points; Static bias voltage settings are performed on the power pins and input pins according to the serialized list of test points through a preset stabilization time, generating static bias voltage setting data.

4. The integrated circuit testing method according to claim 3, wherein Step S2 includes the following steps: Step S21: Add a low-amplitude high-frequency noise source to the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; perform power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the voltage acquisition noise data to generate circuit power supply interference simulation data; Step S22: Use an oscilloscope to measure the output waveform of the circuit power supply interference simulation data, and perform abnormal output response discrimination on the measured output waveform to obtain an abnormal output response discrimination strategy; Step S23: Adjust the signal frequency of the circuit power supply interference simulation data according to the abnormal output response discrimination strategy to generate a circuit power supply interference adjustment signal; Step S24: Perform cyclic power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the circuit power supply interference adjustment signal to generate circuit power supply interference cyclic simulation data; calculate the circuit parasitic index of the circuit power supply interference cyclic simulation data to obtain the actual parasitic data of the integrated circuit.

5. The integrated circuit testing method according to claim 4, wherein Performing abnormal output response discrimination on the measured output waveform includes: Calculate the waveform average value and standard deviation of the measured output waveform to obtain the output waveform average value and the output waveform standard deviation; perform waveform amplitude abnormality discrimination on the measured output waveform according to the output waveform average value and the output waveform standard deviation to generate waveform amplitude abnormality discrimination data; Perform waveform timing analysis on the measured output waveform to generate output waveform timing data; perform time delay overrun discrimination on the measured output waveform based on the output waveform timing data to generate waveform timing abnormality discrimination data; Perform waveform shape analysis on the measured output waveform to generate output waveform shape data; perform waveform shape distortion discrimination on the measured output waveform based on the output waveform shape data to generate waveform morphology abnormality discrimination data; Perform abnormal output response discrimination on the measured output waveform based on the waveform amplitude abnormality discrimination data, the waveform timing abnormality discrimination data, and the waveform morphology abnormality discrimination data to obtain an abnormal output response discrimination strategy.

6. The integrated circuit testing method according to claim 4, wherein Calculating the circuit parasitic index of the circuit power supply interference cyclic simulation data includes: Screen the circuit transistor structure from the integrated circuit structure data to obtain circuit transistor structure data; perform transistor threshold voltage change analysis on the circuit transistor structure data based on the circuit power supply interference cyclic simulation data to generate circuit transistor threshold voltage change data; Perform gate length change analysis on the transistors in the integrated circuit according to the circuit transistor threshold voltage change data to generate transistor gate length change data; perform parasitic effect testing through the circuit power supply interference cyclic simulation data to generate integrated circuit parasitic effect testing data; Use the transistor gate length change data to calculate the actual circuit parasitic index of the integrated circuit parasitic effect testing data to obtain the actual parasitic data of the integrated circuit, where the formula for calculating the actual circuit parasitic index is as follows: Wherein, P represents the actual parasitic data of the integrated circuit, α represents the influence coefficient of capacitance on the circuit performance, β represents the influence coefficient of resistance on the circuit performance, K represents the proportionality factor, W represents the transistor width, and L g,act represents the actual transistor gate length, and L g represents the designed length of the transistor gate, R0 represents the constant of the drain-source resistance, and B represents the test value of the integrated circuit parasitic effect.

7. The integrated circuit testing method according to claim 1, wherein Step S3 includes the following steps: Step S31: Perform the lowest static power consumption analysis on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to generate the lowest static power consumption data of the integrated circuit; perform a leakage current test on the lowest static power consumption data of the integrated circuit to obtain the leakage current data of the integrated circuit; Step S32: Perform an extreme temperature test on the integrated circuit through the leakage current data of the integrated circuit to obtain the extreme temperature test data of the integrated circuit; perform test data balancing based on the actual parasitic data of the integrated circuit, the leakage current data of the integrated circuit, and the extreme temperature test data of the integrated circuit to obtain the comprehensive evaluation index of the integrated circuit; Step S33: Compare the comprehensive evaluation index of the integrated circuit with the preset standard integrated circuit comprehensive evaluation threshold. When the comprehensive evaluation index of the integrated circuit is greater than or equal to the preset standard integrated circuit comprehensive evaluation threshold, batch mark the corresponding integrated circuit to generate a type I integrated circuit mark data; Step S34: When the comprehensive evaluation index of the integrated circuit is less than the preset standard integrated circuit comprehensive evaluation threshold, batch mark the corresponding integrated circuit to generate a type II integrated circuit mark data.

8. The integrated circuit testing method according to claim 7, wherein, Performing the lowest static power consumption analysis on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit includes: Measure the node capacitance of the actual parasitic data of the integrated circuit to generate node capacitance value data; perform a distributed network modeling on the node capacitance value data to generate parasitic capacitance distribution network data; Identify the current flow path of the standard integrated circuit bias voltage acquisition data through the parasitic capacitance distribution network data to generate current flow path characteristic data; extract the critical path from the current flow path characteristic data to generate critical path data; Perform a bottleneck analysis on the critical path data to generate bottleneck characteristic data; calculate the static power consumption of the standard integrated circuit bias voltage acquisition data through the bottleneck characteristic data to obtain the static power consumption data of the integrated circuit; extract the extreme value from the static power consumption data of the integrated circuit to obtain the lowest static power consumption data of the integrated circuit.

9. The integrated circuit testing method according to claim 1, wherein Step S4 includes the following steps: Step S41: Upload the type I integrated circuit mark data and the type II integrated circuit mark data to the cloud platform for circuit test data storage to generate integrated circuit test storage data; Step S42: Visualize the integrated circuit test storage data to generate an integrated circuit test storage report to execute the complete integrated circuit test operation.

10. An integrated circuit test system, characterized in that, An integrated circuit test system for performing the integrated circuit test method as claimed in claim 1, the integrated circuit test system includes: A bias voltage setting module, configured to obtain the integrated circuit structure data; screen the key nodes of the integrated circuit structure data to obtain the power supply pin and the input pin; set the static bias voltage for the power supply pin and the input pin to generate static bias voltage setting data; collect the bias voltage of the static bias voltage setting data to obtain the standard integrated circuit bias voltage acquisition data; A power interference simulation module is used to superimpose a low-amplitude high-frequency noise source on the collected data of the standard integrated circuit bias voltage to obtain voltage acquisition noise data; perform power interference simulation on the collected data of the standard integrated circuit bias voltage through the voltage acquisition noise data to generate circuit power interference simulation data; calculate the circuit parasitic index for the circuit power interference simulation data to obtain the actual parasitic data of the integrated circuit; A hierarchical testing module is used to perform leakage current testing on the collected data of the standard integrated circuit bias voltage based on the actual parasitic data of the integrated circuit to obtain the leakage current data of the integrated circuit; perform extreme temperature testing on the integrated circuit through the leakage current data of the integrated circuit to obtain the extreme temperature testing data of the integrated circuit; perform batch marking on the integrated circuit based on the actual parasitic data of the integrated circuit, the leakage current data of the integrated circuit, and the extreme temperature testing data of the circuit to generate a type I integrated circuit marking data and a type II integrated circuit marking data; A data visualization module is used to upload the type I integrated circuit marking data and the type II integrated circuit marking data to the cloud platform for data visualization, generate an integrated circuit test storage report, so as to execute the complete integrated circuit test operation.

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