Band-gap reference circuit and band-gap reference circuit self-adaptive starting method

Abstract

The invention provides a band-gap reference circuit and a self-adaptive starting method of the band-gap reference circuit. The band-gap reference circuit comprises a biasing circuit, an operational amplifier circuit, a first NMOS (N-channel Metal Oxide Semiconductor) tube and a band-gap reference voltage generation circuit, the input end of the biasing circuit is connected with a voltage source and a current source; when the band-gap reference voltage generating circuit works at a zero-current working point, the first NMOS tube is in a closed state, the second NMOS tube is in a conducting state, and current is provided for the band-gap reference voltage generating circuit, so that the band-gap reference voltage generating circuit works at a normal working point; the first output end and the second output end of the band-gap reference voltage generation circuit are connected with the second input end and the third input end of the operational amplifier circuit respectively, and the band-gap reference voltage generation circuit and the operational amplifier circuit form a feedback loop, so that the band-gap reference circuit outputs target voltage. According to the band-gap reference circuit provided by the invention, the band-gap reference circuit can automatically enter a normal working point to work, so that the band-gap reference circuit outputs correct reference voltage.

Description

Technical Field

[0001] The present application relates to the field of analog integrated circuit technology, and particularly relates to a bandgap reference circuit and a method for self-adaptive startup of the bandgap reference circuit. Background Art

[0002] A bandgap reference circuit is a circuit used to generate a stable voltage, and it can output an accurate and stable voltage. The bandgap reference circuit has two steady-state operating points, namely the 0-current operating point and the normal operating point. When the bandgap reference circuit operates at the 0-current operating point, the bandgap reference circuit cannot normally generate the target voltage; when the bandgap reference circuit operates at the normal operating point, the circuit can work normally to generate a stable target voltage. Therefore, it is necessary to control the bandgap reference circuit to operate at the normal operating point rather than the 0-current operating point.

[0003] Currently, the commonly used method is to use the startup circuit in the bandgap reference circuit to ensure that the bandgap reference circuit can enter the normal operating point. However, the startup circuit will occupy the area on the chip, and additional power consumption will be generated when the startup circuit works. The addition of the startup circuit also makes the overall circuit more complex. Summary of the Invention

[0004] In view of this, the present application provides a bandgap reference circuit and a method for self-adaptive startup of the bandgap reference circuit, so as to enable the bandgap reference circuit to automatically enter the normal operating point to work and generate a stable voltage.

[0005] Specifically, the present application is implemented through the following technical solutions:

[0006] The first aspect of the present application provides a bandgap reference circuit, which includes: a bias circuit, an operational amplifier circuit, a first NMOS transistor, and a bandgap reference voltage generation circuit;

[0007] The input end of the bias circuit is connected to a voltage source and a current source, the output end of the bias circuit is connected to the subsequent circuit, and the bias circuit provides a bias voltage for the subsequent circuit;

[0008] The first input end of the operational amplifier circuit is connected to the bias circuit, the second input end and the third input end of the operational amplifier circuit are respectively connected to the first output end and the second output end of the bandgap reference voltage generation circuit, and the first output end of the operational amplifier circuit is connected to the input end of the bandgap reference voltage generation circuit;

[0009] The gate of the first NMOS transistor is connected to the first output end of the operational amplifier circuit, the drain of the first NMOS transistor is connected to the second output end in the operational amplifier circuit, and the source of the first NMOS transistor is connected to the third output end of the operational amplifier circuit;

[0010] When the first NMOS transistor is in the off state and the second NMOS transistor is in the on state when the bandgap reference voltage generation circuit operates at the zero-current operating point, the second NMOS transistor provides current for the bandgap reference voltage generation circuit, causing the bandgap reference voltage generation circuit to enter the normal operating point;

[0011] The first output terminal and the second output terminal of the bandgap reference voltage generation circuit are respectively connected to the second input terminal and the third input terminal of the operational amplifier circuit, and are used to form a feedback loop with the operational amplifier circuit, so that the bandgap reference circuit outputs a target voltage.

[0012] A second aspect of the present application provides a method for self-adaptive startup of a bandgap reference circuit, the method comprising:

[0013] Identifying the operating state of the bandgap reference generation circuit; the bandgap reference circuit is the circuit provided in the first aspect of the present application;

[0014] If the bandgap reference voltage generation circuit operates at the zero-current operating point, the first NMOS transistor is in the off state, so that the second NMOS transistor of the operational amplifier circuit supplies power to the bandgap reference voltage generation circuit, and the bandgap reference circuit returns to the normal operating point;

[0015] If the bandgap reference voltage generation circuit in the bandgap reference circuit operates at the normal operating point, the second NMOS transistor of the operational amplifier circuit supplies power to the bandgap reference voltage generation circuit, and the first NMOS transistor monitors the operating point of the bandgap reference circuit.

[0016] The provided bandgap reference circuit and the method for adaptive startup of the bandgap reference circuit utilize adding a first NMOS transistor to a general operational amplifier, eliminating the need for a startup circuit in a traditional bandgap reference circuit, and achieving the function of stably maintaining the bandgap reference voltage generation circuit at the normal operating point. Specifically, in the first aspect, adding the first NMOS transistor in the circuit senses the operating state of the bandgap reference generation circuit, enabling the reference generation circuit to avoid the 0-current operating point and enter the correct operating point. Only one component can replace the function of the startup circuit, and at the same time, this component can perform other functions in the operational amplifier circuit, that is, realizing the reuse of the original components, simplifying the overall circuit design, reducing additional circuit elements and connections, and lowering the design complexity and cost. In the second aspect, when the bandgap reference voltage generation circuit operates at the 0-current operating point, the first NMOS transistor turns off, and the gate voltage of the second NMOS transistor rises to provide current for the bandgap reference voltage generation circuit. This enables the bandgap reference voltage generation circuit to break away from the 0-current operating state, quickly start up, and enter the normal operating mode. Compared with designs that require an external startup circuit, this adaptive startup method can save chip circuit area and improve system reliability. In the third aspect, once the bandgap reference circuit enters the normal operating state, the first NMOS transistor and the second NMOS transistor will automatically adjust according to the circuit operating conditions, ensuring that the bandgap reference voltage generation circuit always operates at the correct operating point. This adaptive mechanism can effectively resist the influence of external environmental changes and circuit parameter fluctuations, maintaining the stability of the output reference voltage. In the fourth aspect, the bandgap reference circuit can adapt to different operating conditions and load changes without manual adjustment of the startup circuit or other parameters, having good versatility and adaptability. Description of the Drawings

[0017] Figure 1 Schematic diagram of the first embodiment of the bandgap reference circuit provided by this application;

[0018] Figure 2 Circuit diagram of the bandgap reference circuit shown in an exemplary embodiment of this application;

[0019] Figure 3 Circuit diagram of the bandgap reference voltage generation circuit shown in an exemplary embodiment of this application;

[0020] Figure 4 Circuit diagram of the operational amplifier shown in an exemplary embodiment of this application;

[0021] Figure 5 Flowchart of the first embodiment of the method for adaptive startup of the bandgap reference circuit provided by this application.

[0022] Description of the Reference Numerals:

[0023] 1: Bias circuit;

[0024] 2: Operational amplifier circuit;

[0025] 3: First NMOS transistor;

[0026] 4: Bandgap reference voltage generation circuit;

[0027] 21: Differential input circuit;

[0028] 22: Intermediate stage circuit;

[0029] 23: Output amplifier circuit;

[0030] 24: Output stage circuit;

[0031] Rb1: First bias resistor;

[0032] Rb2: Second bias resistor;

[0033] Rb3: Third bias resistor;

[0034] Rb4: Fourth bias resistor;

[0035] Rb5: Fifth bias resistor;

[0036] Q1: First transistor;

[0037] Q2: Second transistor;

[0038] Q3: Third transistor;

[0039] Q4: Fourth transistor;

[0040] PM1: First PMOS transistor;

[0041] PM2: Second PMOS transistor;

[0042] PM3: Third PMOS transistor;

[0043] PM4: Fourth PMOS transistor;

[0044] PM5: Fifth PMOS transistor;

[0045] NM2: Second NMOS transistor;

[0046] NM3: Third NMOS transistor;

[0047] NM4: Fourth NMOS transistor;

[0048] NM5: Fifth NMOS transistor;

[0049] R1: First resistor;

[0050] R2: Second resistor;

[0051] R3: The third resistor;

[0052] R4: The fourth resistor;

[0053] R5: The fifth resistor;

[0054] R6: The sixth resistor;

[0055] R7: The seventh resistor. Detailed implementation manners

[0056] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application.

[0057] The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0058] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0059] Specific embodiments are given below to introduce the technical solutions of the present application in detail.

[0060] Figure 1 It is a schematic diagram of the first embodiment of the bandgap reference circuit provided by the present application. Figure 2 It is a circuit diagram of the bandgap reference circuit shown in an exemplary embodiment of the present application. Please refer to Figure 1 and Figure 2 simultaneously. The circuit provided in this embodiment includes: a bias circuit 1, an operational amplifier circuit 2, a first NMOS transistor 3, and a bandgap reference voltage generation circuit 4;

[0061] The input end of the bias circuit 1 is connected to a voltage source and a current source, the output end of the bias circuit 1 is connected to the subsequent circuit, and the bias circuit 1 provides a bias voltage for the subsequent circuit;

[0062] The first input terminal of the operational amplifier circuit 2 is connected to the bias circuit 1. The second input terminal and the third input terminal of the operational amplifier circuit are respectively connected to the first output terminal and the second output terminal of the bandgap reference voltage generation circuit 4. The first output terminal of the operational amplifier circuit 2 is connected to the input terminal of the bandgap reference voltage generation circuit 4;

[0063] The gate of the first NMOS transistor 3 is connected to the first output terminal of the operational amplifier circuit 2. The drain of the first NMOS transistor 3 is connected to the second output terminal in the operational amplifier circuit 2. The source of the first NMOS transistor 3 is connected to the third output terminal of the operational amplifier circuit 2;

[0064] When the bandgap reference voltage generation circuit 4 operates at the zero-current operating point, the first NMOS transistor 3 is in the off state, and the second NMOS transistor NM2 is in the on state, providing current for the bandgap reference voltage generation circuit 4 to enable the bandgap reference voltage generation circuit 4 to enter the normal operating point;

[0065] The first output terminal and the second output terminal of the bandgap reference voltage generation circuit 4 are respectively connected to the second input terminal and the third input terminal of the operational amplifier circuit 2, for forming a feedback loop with the operational amplifier circuit 2 to enable the bandgap reference circuit to output the target voltage.

[0066] Optionally, when the bandgap reference voltage generation circuit 4 operates at the zero-current operating point, the gate voltage signal of the first NMOS transistor 3 is a low voltage signal, and the first NMOS transistor 3 is in the off state; when the bandgap reference voltage generation circuit 4 operates at the normal operating point, the gate voltage signal of the first NMOS transistor 3 is a high voltage signal, and the first NMOS transistor 3 is in the on state.

[0067] Optionally, the first NMOS transistor 3 is cascaded with the second NMOS transistor NM2. The source of the second NMOS transistor NM2 is connected to the input terminal of the bandgap reference voltage generation circuit 4, and the drain of the second NMOS transistor NM2 is connected to the voltage source.

[0068] Optionally, when the bandgap reference voltage generation circuit 4 operates at the normal operating point, the output voltage signal of the bandgap reference circuit is the target voltage;

[0069] When the bandgap reference voltage generation circuit 4 operates at the zero-current operating point, the output voltage signal of the bandgap reference circuit is a low voltage signal, the gate voltage signal of the first NMOS transistor 3 is a low voltage signal, the drain voltage signal of the first NMOS transistor 3 is a high voltage signal, and the first NMOS transistor 3 becomes in the off state;

[0070] When the bandgap reference voltage generation circuit 4 operates at the 0-current operating point, the gate voltage signal of the second NMOS transistor NM2 becomes a high voltage signal, the second NMOS transistor NM2 becomes conducting, and the bandgap reference circuit returns to the normal operating point.

[0071] Specifically, a bandgap reference circuit is a circuit used to generate a stable voltage that is relatively insensitive to changes in temperature and power supply voltage. The stable voltage generated by it can provide a voltage reference for other circuits or electronic components to ensure the stability of other circuits or electronic components.

[0072] Specifically, please refer to Figure 1 , the bias circuit 1 is connected to a voltage source and a current source to provide a bias voltage for subsequent circuits. It should be noted that the subsequent circuits refer to the operational amplifier circuit 2, the first NMOS transistor 3, and the bandgap reference voltage generation circuit 4.

[0073] The operational amplifier circuit 2 is arranged between the bias circuit 1 and the bandgap reference voltage generation circuit 4. The operational amplifier circuit 2 is used to amplify the voltage signal in the bandgap reference circuit so that the amplified voltage signal can drive the subsequent bandgap reference voltage generation circuit 4. Further, the source of the second NMOS transistor NM2 in the operational amplifier circuit 2 is the first output terminal of the operational amplifier circuit 2, and the first end of the fourth resistor R4 in the bandgap reference voltage generation circuit 4 is the input port of the bandgap reference voltage generation circuit 4.

[0074] Further, please refer to Figure 2 , in the circuit provided in this embodiment, by controlling the conduction state of the first NMOS transistor 3, the working state of the bandgap reference voltage generation circuit 4 is adjusted. When the bandgap reference voltage generation circuit 4 operates at the 0-current operating point, the first NMOS transistor 3 is controlled to be in the off state, so that the second NMOS transistor NM2 in the operational amplifier circuit 2 is in the conducting state, providing current for the bandgap reference voltage generation circuit 4, and making the bandgap reference voltage generation circuit 4 operate at the normal operating point. This can ensure that the bandgap reference circuit can operate stably and output the target voltage at different operating points.

[0075] Optionally, in a possible implementation manner, the operational amplifier circuit 2 includes an output circuit, and the output circuit at least includes the first NMOS transistor 3;

[0076] When the bandgap reference circuit is in the normal working state, the first NMOS transistor 3 is used to realize the voltage output of the operational amplifier circuit 2;

[0077] When the operating point of the bandgap reference voltage generating circuit 4 is the 0-current operating point, the first NMOS transistor 3 is used to change the operating state of the second NMOS transistor NM2 so that it supplies power to the bandgap reference voltage generating circuit 4.

[0078] Specifically, it can be understood that when the bandgap reference voltage generating circuit 4 operates at the 0-current operating point, at this time, the output voltage of the bandgap reference circuit is a low-voltage signal. Therefore, the first NMOS transistor 3 determines whether the bandgap reference voltage generating circuit 4 operates at the 0-current operating point by sensing the output voltage of the bandgap reference circuit. If the bandgap reference voltage generating circuit 4 operates at the 0-current operating point, the first NMOS transistor 3 is turned off, the gate voltage of the second NMOS transistor NM2 increases, and the current flows into the bandgap reference voltage generating circuit 4 from the second NMOS transistor NM2, thereby enabling the bandgap reference voltage generating circuit 4 to resume operation at the normal operating point.

[0079] Furthermore, when the bandgap reference voltage generating circuit 4 operates at the normal operating point, the gate voltage signal of the first NMOS transistor 3 is a high-voltage signal, the drain voltage signal of the first NMOS transistor 3 is a low-voltage signal, and the current flows through the second NMOS transistor NM2 to the bandgap reference voltage generating circuit 4; when the bandgap reference voltage generating circuit 4 operates at the 0-current operating point, the gate voltage signal of the first NMOS transistor 3 is a low-voltage signal, the drain voltage signal of the first NMOS transistor 3 is a high-voltage signal, the gate voltage signal of the second NMOS transistor NM2 is a high-voltage signal, the drain voltage signal of the second NMOS transistor NM2 is a low-voltage signal, and the current flows through the second NMOS transistor NM2 to the bandgap reference voltage generating circuit 4, and the bandgap reference voltage generating circuit 4 returns from the 0-current operating point to the normal operating point.

[0080] Therefore, it can be understood that regardless of whether the bandgap reference voltage generating circuit 4 operates at the normal operating point or the 0-current operating point, through the action of the foregoing first NMOS transistor 3, the current will flow into the bandgap reference voltage generating circuit 4 to ensure that the bandgap reference voltage generating circuit 4 avoids operating at the 0-current operating point and operates at the normal operating point.

[0081] Among them, the gate of the first NMOS transistor 3 is connected to the first output terminal of the operational amplifier circuit 2, the drain of the first NMOS transistor 3 is connected to the second output terminal of the operational amplifier circuit 2, and the source of the first NMOS transistor 3 is connected to the third output terminal in the operational amplifier circuit 2.

[0082] Specifically, the bandgap reference voltage generation circuit 4 plays a crucial role in the bandgap reference circuit. The input terminals of the bandgap reference voltage generation circuit 4 are respectively connected to the gate of the first NMOS transistor 3 and the first output terminal of the operational amplifier circuit 2. The output terminal of the bandgap reference voltage generation circuit 4 (i.e., the first output terminal and the second output terminal in the bandgap reference voltage generation circuit 4, collectively referred to as the output terminal of the bandgap reference voltage generation circuit 4) is connected to the operational amplifier circuit 2, thereby forming a feedback loop with the operational amplifier circuit 2 to enable the bandgap reference circuit to output a target voltage. It should be noted that different bandgap reference circuits have different target voltage values. For example, in one embodiment, the target voltage is 1.2V.

[0083] The bandgap reference circuit provided in this embodiment realizes the function of the bandgap reference voltage generation circuit stably maintaining operation at the normal operating point by using the first NMOS transistor to replace the startup circuit in the traditional bandgap reference circuit. The specific manifestations are as follows: First, it simplifies the overall circuit design, reduces additional circuit components and connections, and lowers the design complexity and cost. Second, when the bandgap reference voltage generation circuit operates at the zero-current operating point, the first NMOS transistor is turned off, and the second NMOS transistor is turned on to provide current for the bandgap reference voltage generation circuit. This enables the bandgap reference voltage generation circuit to quickly get out of the zero-current operating state and enter the normal operating mode. Compared with the design that requires an external startup circuit, this self-adaptive startup method can save the circuit area on the chip and reduce the complexity, improving the reliability of the system. Third, once the bandgap reference circuit enters the normal operating state, the first NMOS transistor and the second NMOS transistor will automatically adjust according to the operating conditions of the circuit to ensure that the bandgap reference voltage generation circuit always operates at the correct operating point. This self-adaptive mechanism can effectively resist the influence of external environmental changes and circuit parameter fluctuations and maintain the stability of the output reference voltage.

[0084] Please continue to refer to Figure 1 , optionally, the bias circuit 1 includes a first PMOS transistor PM1 and a first bias resistor Rb1. The source of the first PMOS transistor PM1 is connected to the current source to form the input terminal of the bias circuit 1;

[0085] The gate and drain of the first PMOS transistor PM1 are connected to each other and connected to the voltage source to form the output terminal of the bias circuit 1, providing a bias voltage for the subsequent circuit.

[0086] Figure 3 For the circuit diagram of the bandgap reference voltage generation circuit shown in an exemplary embodiment of this application, please refer to Figure 3 , the bandgap reference voltage generation circuit 4 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, and a second transistor Q2;

[0087] The first resistor R1 and the second resistor R2 are connected in series, and the third resistor R3 and the fourth resistor R4 are connected in series;

[0088] One end of the first resistor R1 is connected to the emitter of the first transistor Q1, and the other end of the first resistor R1 is connected to one end of the second resistor R2, forming the first output terminal of the bandgap reference voltage generating circuit 4;

[0089] The other end of the second resistor R2 is connected between the third resistor R3 and the fourth resistor R4;

[0090] One end of the third resistor R3 is connected to the emitter of the second transistor Q2, forming the second output terminal of the bandgap reference voltage generating circuit 4; the other end of the third resistor R3 is connected to one end of the fourth resistor R4;

[0091] The other end of the fourth resistor R4 forms the input terminal of the bandgap reference voltage generating circuit 4;

[0092] The base and collector of the first transistor Q1 and the base and collector of the second transistor Q2 form the ground terminal of the bandgap reference voltage generating circuit 4, and the ground terminal is grounded.

[0093] Figure 4 The circuit diagram of the operational amplifier circuit shown in an exemplary embodiment of the present application is shown in Figure 4 , the operational amplifier circuit 2 includes: a differential input circuit 21, an intermediate stage circuit 22, an output amplifier circuit 23, and an output stage circuit 24; <U+

[0094] The input terminals of the differential input circuit 21 form the second input terminal and the third input terminal of the operational amplifier circuit 2, and are respectively connected to the first output terminal and the second output terminal of the bandgap reference voltage generating circuit 4, and are used to receive the feedback voltage of the bandgap reference voltage generating circuit 4 and generate an error signal;

[0095] The output terminal of the intermediate stage circuit 22 is connected to the input terminal of the output amplifier circuit 23, and is used to amplify the error signal;

[0096] The output terminal of the output amplifier circuit 23 is connected to the input terminal of the output stage circuit 24, and is used to further amplify the error signal output by the intermediate stage circuit 22 and generate a control voltage for driving the output stage circuit 24;

[0097] The output terminal of the output stage circuit 24 is connected to the input terminal of the bandgap reference voltage generation circuit 4, and the output terminal of the output stage circuit 24 constitutes the first output terminal of the operational amplifier circuit 2 and the output terminal of the bandgap reference circuit.

[0098] Specifically, the first NMOS transistor 3 is connected to the second NMOS transistor NM2 in the output circuit 24, and the operating point of the bandgap reference voltage generation circuit 4 is determined by detecting the output voltage of the second NMOS transistor NM2.

[0099] Optionally, the differential input circuit 21 includes a second PMOS transistor PM2, a second bias resistor Rb2, a third transistor Q3, a fourth transistor Q4, a fifth resistor R5, and a sixth resistor R6; the gate of the second PMOS transistor PM2 is connected to the output terminal of the bias circuit 1 to form the input terminal of the differential input circuit 21; the collectors of the third transistor Q3 and the fourth transistor Q4 form the output terminal of the differential input circuit 21;

[0100] The intermediate stage circuit 22 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third bias resistor Rb3, and a fourth bias resistor Rb4; the source of the third NMOS transistor NM3 is connected to the collector of the third transistor Q3, and the source of the fourth NMOS transistor NM4 is connected to the collector of the fourth transistor Q4 to form the input terminal of the intermediate stage circuit 22; the drain of the fourth NMOS transistor NM4 forms the output terminal of the intermediate stage circuit 22;

[0101] The output amplifier circuit 23 includes a fifth NMOS transistor NM5, a fifth PMOS transistor PM5, a seventh resistor R7, and a fifth bias resistor Rb5; the gate of the fifth PMOS transistor PM5 forms the input terminal of the output amplifier circuit 23; the drain of the fifth PMOS transistor PM5 forms the second output terminal of the operational amplifier circuit 2, and the drain of the fifth NMOS transistor NM5 forms the third output terminal of the operational amplifier circuit 2.

[0102] Corresponding to the foregoing embodiment of a bandgap reference circuit, the present application also provides an embodiment of a method for self-adaptive startup of a bandgap reference circuit.

[0103] Figure 5 It is a flowchart of Embodiment 1 of the method for self-adaptive startup of the bandgap reference circuit provided by the present application.

[0104] Please refer to Figure 5 , the method provided in this embodiment includes:

[0105] S101. Identify the operating current of the bandgap reference circuit.

[0106] Specifically, the bandgap reference circuit is the bandgap reference circuit provided in the first aspect of the present application.

[0107] S102. If the bandgap reference voltage generation circuit operates at the 0-current operating point, the first NMOS transistor is in the off state, so that the second NMOS transistor of the operational amplifier circuit supplies power to the bandgap reference voltage generation circuit.

[0108] S103. If the bandgap reference voltage generation circuit in the bandgap reference circuit operates at the normal operating point, the second NMOS transistor of the operational amplifier circuit supplies power to the bandgap reference voltage generation circuit, and the first NMOS transistor monitors the operating point of the bandgap reference circuit.

[0109] Specifically, the specific implementation principle and implementation process are similar to the above description and will not be elaborated here.

[0110] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A bandgap reference circuit, characterized in that The bandgap reference circuit includes: a bias circuit, an operational amplifier circuit, a first NMOS transistor, and a bandgap reference voltage generation circuit; The input terminal of the bias circuit is connected to a voltage source and a current source, and the output terminal of the bias circuit is connected to a subsequent circuit. The bias circuit provides a bias voltage for the subsequent circuit; The first input terminal of the operational amplifier circuit is connected to the bias circuit, the second input terminal and the third input terminal of the operational amplifier circuit are respectively connected to the first output terminal and the second output terminal of the bandgap reference voltage generation circuit, and the first output terminal of the operational amplifier circuit is connected to the input terminal of the bandgap reference voltage generation circuit; The gate of the first NMOS transistor is connected to the first output terminal of the operational amplifier circuit, the drain of the first NMOS transistor is connected to the second output terminal in the operational amplifier circuit, and the source of the first NMOS transistor is connected to the third output terminal of the operational amplifier circuit; When the bandgap reference voltage generation circuit operates at the 0-current operating point, the first NMOS transistor is in the off state, and the second NMOS transistor is in the on state, providing current for the bandgap reference voltage generation circuit to make the bandgap reference voltage generation circuit enter the normal operating point; The first output terminal and the second output terminal of the bandgap reference voltage generation circuit are respectively connected to the second input terminal and the third input terminal of the operational amplifier circuit, and are used to form a feedback loop with the operational amplifier circuit to make the bandgap reference circuit output a target voltage.

2. The circuit according to claim 1, wherein The operational amplifier circuit includes an output circuit, and the output circuit includes at least the first NMOS transistor; When the bandgap reference circuit is in the normal operating state, the first NMOS transistor is used to realize the voltage output of the operational amplifier circuit; When the operating point of the bandgap reference voltage generation circuit is the 0-current operating point, the first NMOS transistor is used to change the operating state of the second NMOS transistor to supply power to the bandgap reference voltage generation circuit.

3. The circuit according to claim 1, characterized in that, When the bandgap reference voltage generation circuit operates at the 0-current operating point, the gate voltage signal of the first NMOS transistor is a low voltage signal, and the first NMOS transistor is in the off state; When the bandgap reference voltage generation circuit operates at the normal operating point, the gate voltage signal of the first NMOS transistor is a high voltage signal, and the first NMOS transistor is in the on state.

4. The circuit according to claim 1, wherein The first NMOS transistor is cascaded with the second NMOS transistor. The source of the second NMOS transistor is connected to the input terminal of the bandgap reference voltage generation circuit, and the drain of the second NMOS transistor is connected to the voltage source.

5. The circuit according to claim 1, wherein When the bandgap reference voltage generation circuit operates at the normal operating point, the output voltage signal of the bandgap reference circuit is a normal target voltage; When the bandgap reference voltage generation circuit operates at the 0-current operating point, the output voltage signal of the bandgap reference circuit is a low voltage signal, the gate voltage signal of the first NMOS transistor is a low voltage signal, the drain voltage signal of the first NMOS transistor is a high voltage signal, and the first NMOS transistor becomes in the off state; When the bandgap reference voltage generation circuit operates at the 0-current operating point, the gate voltage signal of the second NMOS transistor becomes a high-voltage signal, the second NMOS transistor becomes conducting, and the bandgap reference circuit returns to the normal operating point.

6. The circuit according to claim 1, wherein The bias circuit includes a first PMOS transistor and a first bias resistor. The source of the first PMOS transistor is connected to the current source, forming the input terminal of the bias circuit. The gate and drain of the first PMOS transistor are connected and connected to the voltage source, forming the output terminal of the bias circuit to provide a bias voltage for the subsequent circuit.

7. The circuit according to claim 1, characterized in that, The bandgap reference voltage generation circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first transistor, and a second transistor. The first resistor is connected in series with the second resistor, and the third resistor is connected in series with the fourth resistor. One end of the first resistor is connected to the emitter of the first transistor, and the other end of the first resistor is connected to one end of the second resistor, forming the first output terminal of the bandgap reference voltage generation circuit. The other end of the second resistor is connected between the third resistor and the fourth resistor. One end of the third resistor is connected to the emitter of the second transistor, forming the second output terminal of the bandgap reference voltage generation circuit; the other end of the third resistor is connected to one end of the fourth resistor. The other end of the fourth resistor forms the input terminal of the bandgap reference voltage generation circuit. The base and collector of the first transistor and the base and collector of the second transistor form the ground terminal of the bandgap reference voltage generation circuit, and the ground terminal is grounded.

8. The circuit according to claim 1, characterized in that The operational amplifier circuit includes: a differential input circuit, an intermediate stage circuit, an output amplifier circuit, and an output stage circuit. The input terminals of the differential input circuit form the second input terminal and the third input terminal of the operational amplifier circuit, and are respectively connected to the first output terminal and the second output terminal of the bandgap reference voltage generation circuit to receive the feedback voltage of the bandgap reference voltage generation circuit and generate an error signal. The output terminal of the intermediate stage circuit is connected to the input terminal of the output amplifier circuit to amplify the error signal. The output terminal of the output amplifier circuit is connected to the input terminal of the output stage circuit to further amplify the error signal output by the intermediate stage circuit and generate a control voltage for driving the output stage circuit. The output terminal of the output stage circuit is connected to the input terminal of the bandgap reference voltage generation circuit, and the output terminal of the output stage circuit forms the first output terminal of the operational amplifier circuit and the output terminal of the bandgap reference circuit.

9. The circuit according to claim 8, characterized in that, The differential input circuit includes a second PMOS transistor, a second bias resistor, a third transistor, a fourth transistor, a fifth resistor, and a sixth resistor; the gate of the second PMOS transistor is connected to the output terminal of the bias circuit, forming the bias voltage input terminal of the differential input circuit; the collectors of the third transistor and the fourth transistor form the output terminal of the differential input circuit. The intermediate-stage circuit includes a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third bias resistor, and a fourth bias resistor; the source of the third NMOS transistor is connected to the collector of the third transistor, and the source of the fourth NMOS transistor is connected to the collector of the fourth transistor, constituting the input end of the intermediate-stage circuit; the drain of the fourth NMOS transistor constitutes the output end of the intermediate-stage circuit; The output amplifier circuit includes a fifth NMOS transistor, a fifth PMOS transistor, a seventh resistor, and a fifth bias resistor; the gate of the fifth PMOS transistor is connected to the output end of the bias circuit; the drain of the fifth PMOS transistor constitutes the second output end of the operational amplifier circuit, and the drain of the fifth NMOS transistor constitutes the third output end of the operational amplifier circuit.

10. A method for adaptive startup of a bandgap reference circuit, characterized in that, The method includes: Identifying the working state of the bandgap reference circuit; the bandgap reference circuit is the bandgap reference circuit provided in any one of claims 1-9; If the bandgap reference voltage generation circuit operates at the 0-current operating point, the first NMOS transistor is in the off state, so that the second NMOS transistor of the operational amplifier circuit supplies power to the bandgap reference voltage generation circuit, and the bandgap reference circuit returns to the normal operating point; If the bandgap reference voltage generation circuit in the bandgap reference circuit operates at the normal operating point, the second NMOS transistor of the operational amplifier circuit supplies power to the bandgap reference voltage generation circuit, and the first NMOS transistor monitors the operating point of the bandgap reference circuit.

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