Ultra-wide power linear voltage stabilizer based on BCD high-voltage process

Abstract

The invention belongs to the technical field of complementary metal-oxide-semiconductor analog circuits, and particularly relates to an ultra-wide power linear voltage stabilizer based on a BCD high-voltage process. Comprising a high-voltage-to-low-voltage biasing circuit, a low-voltage self-starting circuit, a band-gap reference circuit, a high-voltage source linear voltage stabilizer and an instantaneous pulse breakdown locking circuit. The high-voltage-to-low-voltage bias circuit provides bias voltage for the whole circuit, the low-voltage self-starting circuit automatically starts the circuit when the circuit is in a low-voltage condition to ensure stable operation of the circuit, the band-gap reference circuit provides stable reference voltage for the high-voltage source linear voltage stabilizer, the high-voltage source linear voltage stabilizer comprises a two-stage operational amplifier, and the two-stage operational amplifier is connected with the high-voltage source linear voltage stabilizer. And the secondary operational amplifier compares the reference voltage with the divided output voltage and outputs a feedback signal, thereby realizing adjustment of the output voltage. And the instantaneous pulse breakdown locking circuit is used for preventing breakdown under the abnormal condition that the circuit load impulse is low. When the VBAT of the power supply is in the range of 1.1 V to 5 V and the temperature is-55 DEG C to 150 DEG C, the output absolute value follows the VBA.

Description

Technical Field

[0001] The present invention belongs to the technical field of complementary metal-oxide-semiconductor analog circuits, and particularly relates to an ultra-wide power supply linear voltage regulator based on BCD high-voltage process. Background Art

[0002] In recent years, new energy vehicles have developed rapidly. The core power source for new energy applications is the 12V / 24V / 48V battery. The central nervous system for intelligent driving and in-vehicle entertainment control is the chip, which operates in the low voltage range (1.2V to 5V). Therefore, a power supply chip is required to convert and control the battery to provide appropriate voltage and current for the normal operation of the load. Usually, power conversion chips are divided into two categories: DC-DC and LDO. The present invention mainly focuses on the low dropout linear regulator (LDO).

[0003] LDO is widely used in voltage conversion of in-vehicle systems and works at a specific point on the output characteristic curve according to the design requirements. Compared with DC-DC chips, LDO has the advantages of lower noise, fewer external passive devices, simpler circuit, and lower EMC interference. In-vehicle LDOs are divided into two types: general-purpose LDO and follower LDO. The general-purpose LDO means that the output voltage is relatively constant within the set range, or has a small change. The follower LDO means that its output changes with the change of another voltage.

[0004] Currently, the main in-vehicle LDO chip manufacturers in the market include: Silan Microelectronics, Huada Semiconductor, Lingxin, Shengbang Micro, etc. Their products include general-purpose LDO and follower LDO. However, its general-purpose LDO is greatly affected by the power supply in actual applications. When the power supply voltage drops outside a certain range of the normal operating voltage of the LDO, the LDO drops sharply, and in more serious cases, the LDO output is undervoltage. The output of the follower LDO can make up for this shortcoming, but the output value of the existing follower LDO only changes linearly with the battery voltage. When the battery voltage drops to 3V, the output can only be maintained at about 0.65V, and the efficiency is low.

[0005] On one hand, the present invention solves the problem that the output value of a general LDO drops sharply when the battery voltage drops outside the normal operating voltage range of the LDO. On the other hand, it solves the problem that the absolute deviation value between the output value of a follower LDO and the battery voltage is relatively large. Based on the 60V CMOS BCD process, when the power supply VBAT is in the range of 1.1V to 5V and the temperature is -55°C to 150°C, the output closely follows VBAT; when the power supply VBAT is in the range of 5V to 60V and the temperature is -55°C to 150°C, the output is stable near the LDO set value; the normal operating power consumption of the circuit is less than 4μA, and the output load capacity can reach up to 170mA when the battery supplies 12V. When the power supply voltage is 1.6V and the output load is 1mA, the LDO output value is 1.58V. When the power supply voltage is 1.6V and the output load is 10mA, the LDO output value is 1.46V. When the power supply drops to 1.1V, the output drives 200μA, and the LDO output value is 990mV, with relatively weak driving ability. Summary of the Invention

[0006] The present invention provides a ultra-wide power supply linear voltage regulator based on the BCD high-voltage process to solve the technical problems existing in the prior art, such as the output of the existing in-vehicle general LDO drops sharply or even has undervoltage when the power supply voltage decreases, and the follower LDO has low output efficiency when the input voltage is low, which makes it difficult to meet the requirements of in-vehicle chips for stable power conversion and high-efficiency output.

[0007] To achieve the above object, the present invention adopts the following technical solutions: An ultra-wide power supply linear voltage regulator based on BCD high-voltage process, characterized in that it includes a high-voltage to low-voltage bias circuit, a bandgap reference circuit and a high-voltage source linear voltage regulator. The high-voltage to low-voltage bias circuit includes a series-connected first PMOS transistor PHV1 and a first resistor RH. The first resistor RH is connected to the gates of a first NMOS transistor NHV1 and a second NMOS transistor NHV2. The drain of the second NMOS transistor NHV2 is the output terminal of the high-voltage to low-voltage bias circuit, and the output terminal of the high-voltage to low-voltage bias circuit is connected to the input terminal of the high-voltage source linear voltage regulator; the bandgap reference circuit includes a bandgap reference cascode current source load composed of a second PMOS transistor PHV2, a third PMOS transistor PHV3, a fourth PMOS transistor PHV4 and a fifth PMOS transistor PHV5. The output terminal of the bandgap reference circuit is the noed4 node. The high-voltage source linear voltage regulator includes a two-stage operational amplifier. The two-stage operational amplifier includes a mirror tail current source composed of a fourth NMOS field-effect transistor NM_ULVT1 and a fifth NMOS field-effect transistor NM_ULVT2, and an input pair composed of a sixth NMOS field-effect transistor NHV_LVT3 and a seventh NMOS field-effect transistor NHV_LVT4. The gate of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the node4 node. The gate of the seventh NMOS field-effect transistor NHV_LVT4 is connected to one end of a second resistor R1 and one end of a third resistor R2. The gate of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the gate of a tenth PMOS transistor PHV10. The drain of the tenth PMOS transistor PHV10 is connected to the output voltage VLDO.

[0008] In the high-voltage to low-voltage bias circuit, the source of the first PMOS transistor PHV1 is connected to VBAT. After the gate and drain of the first PMOS transistor PHV1 are short-circuited, the drain of the first PMOS transistor PHV1 is connected to one end of the first resistor RH. The other end of the first resistor RH is short-circuited to the gate and drain of the first NMOS transistor NHV1, and the other end of the first resistor RH is simultaneously connected to the gate of the second NMOS transistor NHV2. The first resistor RH is selected as a high-voltage and high-square-resistance device. When VBAT is relatively high, a relatively large current flows through the first resistor RH. The first resistor RH and the first PMOS transistor PHV1 cooperate to divide the voltage of VBAT. The divided voltage is input to the gates of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, quickly reducing the gate voltages of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, and realizing the preliminary reduction of the voltage amplitude.

[0009] The source of the first NMOS transistor NHV1 is connected to a first PMOS clamping diode PM1, a second PMOS clamping diode PM2, and a third PMOS clamping diode PM3. The series-connected first PMOS clamping diode PM1, second PMOS clamping diode PM2, and third PMOS clamping diode PM3 form a series clamping diode. The source of the clamping diode is connected to the source of the first NMOS transistor NHV1, and the drain of the clamping diode is grounded. When VBAT is low, after a relatively low current flows through the first resistor RH, the self-conducting characteristic of the series clamping diode is used to limit the minimum voltage of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, preventing the voltages of the first NMOS transistor NHV1 and the second NMOS transistor NHV2 from being too low and ensuring the normal operation of the device.

[0010] The source of the first NMOS transistor NHV1 is connected to the source of the first normal-voltage PMOS clamping diode PM1. The drain of the first PMOS clamping diode PM1 is connected to the source of the second PMOS clamping diode PM2. The drain of the second PMOS clamping diode PM2 is connected to the source of the third PMOS clamping diode PM3. The drain of the third PMOS clamping diode PM3 is connected to ground. The source of the first NMOS transistor NHV1 is short-circuited to the gate of the first PMOS clamping diode PM1. The drain of the first PMOS clamping diode PM1 is short-circuited to the gate of the second PMOS clamping diode PM2. The drain of the second PMOS clamping diode PM2 is short-circuited to the gate of the third PMOS clamping diode PM3.

[0011] In the high-voltage source linear regulator, the gates of the fourth NMOS field-effect transistor NM_ULVT1 and the fifth NMOS field-effect transistor NM_ULVT2 are short-circuited. The sources of the fourth NMOS field-effect transistor NM_ULVT1 and the fifth NMOS field-effect transistor NM_ULVT2 are connected to ground. The drain of the fifth NMOS field-effect transistor NM_ULVT2 is connected to the sources of a sixth NMOS field-effect transistor NHV_LVT3 and a seventh NMOS field-effect transistor NHV_LVT4. The gate of the sixth NMOS field-effect transistor NHV_LVT is connected to the node4 node. The gate of the seventh NMOS field-effect transistor NHV_LVT4 is connected to one end of the second resistor R1 and one end of the third resistor R2. The sixth NMOS field-effect transistor NHV_LVT3 and the seventh NMOS field-effect transistor NHV_LVT4 of the secondary operational amplifier simultaneously receive the reference voltage generated by the bandgap reference circuit output at the node4 node and the feedback signal obtained by dividing the output voltage VLDO by the second resistor R1 and the third resistor R2. The secondary operational amplifier compares the reference voltage and the feedback signal, amplifies the difference between the two, and outputs a corresponding drive signal. The drive signal controls the gate voltage of the tenth PMOS transistor PHV10 to adjust the conduction degree of the tenth PMOS transistor PHV10.

[0012] A Miller compensation capacitor HV_CAP is connected between the output terminal of the secondary operational amplifier and the drain of the tenth PMOS transistor PHV10. The Miller compensation capacitor HV_CAP is selected as a high-voltage-resistant device. The Miller compensation capacitor HV_CAP can provide phase compensation to avoid high-frequency oscillation caused by the feedback loop in the circuit and ensure the stable operation of the circuit.

[0013] The drain of the fourth NMOS field-effect transistor NM_ULVT1 is connected to the source of the eighth NMOS field-effect transistor NHV_LVT2. The drain of the eighth NMOS field-effect transistor NHV_LVT2 is connected to the drain of the seventh PMOS transistor PHV7. The source of the seventh PMOS transistor PHV7 is connected to the drain of the sixth PMOS transistor PHV6. The source of the sixth PMOS transistor PHV6 is connected to VBAT. The sixth PMOS transistor PHV6 and the seventh PMOS transistor PHV7 form a current mirror, and the current of the sixth PMOS transistor PHV6 is mirrored to the seventh PMOS transistor PHV7 to ensure the stability of the gate and drain currents of the eighth NMOS field-effect transistor NHV_LVT2. The gate voltage of the eighth NMOS field-effect transistor NHV_LVT2 is provided by the drain of the sixth PMOS transistor PHV6. Under the current mirroring action of the sixth PMOS transistor PHV6 and the seventh PMOS transistor PHV7, the source and gate voltages of the eighth NMOS field-effect transistor NHV_LVT2 are stabilized at specific values, thereby providing a stable bias voltage for the secondary operational amplifier circuit. The drain of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the drain of the eighth PMOS transistor PHV8. The drain of the seventh NMOS field-effect transistor NHV_LVT4 is connected to the drain of the ninth PMOS transistor PHV9. The gates of the eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 are short-circuited, and the sources of the eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 are connected to VBAT. The drain of the ninth PMOS transistor PHV9 is short-circuited to the gate of the eighth PMOS transistor PHV8. The eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 form a bias circuit structure to provide bias voltages for the sixth NMOS field-effect transistor NHV_LVT3 and the seventh NMOS field-effect transistor NHV_LVT4. Through the interconnected feedback mechanism, the influence of power supply voltage fluctuation and temperature change on the input-stage current of the secondary operational amplifier is reduced.

[0014] The ultra-wide power supply linear voltage regulator further includes an instantaneous pulse breakdown circuit, which includes a number of series-connected isolation diodes. The P end of the first isolation diode HV_DIO1 is connected to VBAT, the N end of the first isolation diode HV_DIO1 is connected to the P end of the Nth isolation diode HV_DION. There are a number of isolation diodes between the first isolation diode HV_DIO1 and the Nth isolation diode HV_DION. The number of isolation diodes form a series diode queue in sequence until the Nth isolation diode HV_DION. The N end of the Nth isolation diode HV_DION is connected to the node3 node, and the N end of the Nth isolation diode HV_DION is connected to the gate of the tenth PMOS transistor PHV10 through the node3 node.

[0015] In the bandgap reference circuit, the sources of the second PMOS transistor PHV2 and the third PMOS transistor PHV3 are connected to VBAT, the gates of the second PMOS transistor PHV2 and the third PMOS transistor PHV3 are short-circuited, the gates of the fourth PMOS transistor PHV4 and the fifth PMOS transistor PHV5 are short-circuited. The drain of the second PMOS transistor PHV2 is connected to the source of the fourth PMOS transistor PHV4, and the drain of the third PMOS transistor PHV3 is connected to the source of the fifth PMOS transistor PHV5. Among them, the drain of the third PMOS transistor PHV3 and the fifth PMOS transistor PHV5 are connected in a diode connection with the gate and drain short-circuited. The drain of the second PMOS transistor PHV2 and the fourth PMOS transistor PHV4 are mirror transistors. The drain of the fourth PMOS transistor PHV4 is connected to the drain of the first NMOS field-effect transistor NHV_DEP, and the drain of the fifth PMOS transistor PHV5 is connected to the drain of the second NMOS field-effect transistor NHV_LVT1. The gates of the first NMOS field-effect transistor NHV_DEP and the second NMOS field-effect transistor NHV_LVT1 are short-circuited, and the short-circuit between them is the node2 node. The source of the first NMOS field-effect transistor NHV_DEP is connected to the collector of the first NPN transistor NPN1 and the gate of the third NMOS field-effect transistor NHV_LVT5. The source of the third NMOS field-effect transistor NHV_LVT5 is the output node node4 of the bandgap reference circuit.

[0016] Compared with the prior art, the present invention has the following beneficial effects: A super-wide power supply linear voltage regulator based on BCD high-voltage process uses a high-voltage PMOS transistor and a high-resistance high-voltage resistor to cooperate in voltage division, converting the input high voltage into a bias voltage that the subsequent low-voltage devices can withstand, avoiding the risk of high-voltage breakdown, and ensuring the stable operation of the reference circuit and the voltage regulator when the high voltage is input. The series PMOS clamping diode limits the lowest gate voltage during low-voltage input, preventing device failure caused by too low bias voltage, and ensuring that the bias circuit continuously provides effective drive for the subsequent modules under low voltage; the input differential pair selects low-threshold high-voltage NMOS devices to adapt to the reference voltage, and can provide sufficient drive ability even when the low voltage is input. Through the negative feedback mechanism, the power transistor is driven to adjust the conduction degree, forcing the output voltage to be stabilized at the set value, and avoiding the sudden drop of the output caused by power supply fluctuations; when the low voltage is input, the output voltage of the bias circuit directly drives the gate of the power transistor, making the output voltage closely follow the input voltage, reducing the voltage loss in the intermediate conversion link, and improving the output efficiency in the low-voltage scenario; an extremely low-threshold NMOS is used as the tail current source to ensure the stability of the circuit startup and bias current under low voltage; combined with the depletion-type high-voltage NMOS to retain the key node voltage at low voltage, maintaining the gate voltages of the reference circuit and the drive transistor in the effective working state, and avoiding the output attenuation caused by too high threshold voltage of the traditional follower; the high-resistance voltage division structure of the high-resistance high-voltage resistor and the PMOS clamping diode greatly reduces the current of the bias circuit; in the low-voltage mode, unnecessary modules are turned off, and only the basic bias path is retained to achieve low-power operation. The use of the Miller compensation capacitor provides phase compensation, suppresses high-frequency oscillation of the feedback loop, and ensures the stable operation of the circuit. In the instantaneous pulse breakdown locking circuit, a series high-voltage isolation diode clamps the gate-source voltage of the power transistor, avoiding device breakdown caused by load pulses, and improving the anti-transient interference ability. Description of the Drawings

[0017] Figure 1 : Low-power voltage regulation LDO circuit diagram applicable to super-wide power supply; Figure 2 : Low-voltage follower output simulation; Figure 3 : Low-voltage input load capacity simulation; Figure 4 : Linear change power supply output stability simulation; Figure 5 : Normal pressure input load capacity simulation; Figure 6 : Transient pulse clamping protection simulation; Figure 7 : LDO output using low-temperature drift reference. Detailed Implementation Manner

[0018] To further understand the content of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are only for explaining the present invention and not for limiting it.

[0019] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] This embodiment proposes an ultra-wide power supply linear voltage regulator based on BCD high-voltage process, as Figure 1 shown in the circuit structure diagram of a low-power linear voltage regulator applicable to ultra-wide power supply based on BCD high-voltage process of the present invention, which includes a high-voltage to low-voltage bias circuit, a low-voltage self-starting circuit, a bandgap reference circuit, a high-voltage source linear voltage regulator, and an instantaneous pulse breakdown locking circuit.

[0021] The high-voltage to low-voltage bias circuit includes a first PMOS transistor PHV1. The source of the first PMOS transistor PHV1 is connected to VBAT, where VBAT is the battery power supply with a working range covering 1.1V to 60V. After the gate and drain of the first PMOS transistor PHV1 are short-circuited, the drain of the first PMOS transistor PHV1 is connected to one end of the first resistor RH. The other end of the first resistor RH is short-circuited to the gate and drain of the first NMOS transistor NHV1. The other end of the first resistor RH is also connected to the gate of the second NMOS transistor NHV2. The source of the first NMOS transistor NHV1 is successively connected in series with a first normal-pressure PMOS clamping diode PM1, a second normal-pressure PMOS clamping diode PM2, and a third normal-pressure PMOS clamping diode PM3. The source of the first NMOS transistor NHV1 is connected to the source of the first normal-pressure PMOS clamping diode PM1. The drain of the first normal-pressure PMOS clamping diode PM1 is connected to the source of the second normal-pressure PMOS diode. The drain of the second normal-pressure PMOS clamping diode PM2 is connected to the source of the third normal-pressure PMOS clamping diode PM3. The drain of the third normal-pressure PMOS clamping diode PM3 is connected to the ground. The source of the first NMOS transistor NHV1 is short-circuited to the gate of the first normal-pressure PMOS clamping diode PM1. The drain of the first normal-pressure PMOS clamping diode PM1 is short-circuited to the gate of the second normal-pressure PMOS clamping diode PM2. The drain of the second normal-pressure PMOS clamping diode PM2 is short-circuited to the gate of the third normal-pressure PMOS clamping diode PM3.

[0022] The first PMOS transistor PHV1, the first resistor RH, the first NMOS transistor NHV1, the second NMOS transistor NHV2, the first PMOS clamping diode PM1, the second PMOS clamping diode PM2, and the third PMOS clamping diode PM3 form a high-voltage to low-voltage biasing circuit. The three PMOS clamping diodes PM1, PM2, and PM3 are connected in series to limit the lowest voltage of the gates of the first NMOS transistor NHV1 and the second NMOS transistor NHV2. The drain output terminal of the second NMOS transistor NSV2 serves as the bias voltage output node node1 to provide bias for the subsequent circuit. VBAT provides the voltage source for the circuit, generating a low-voltage DC operating point with the same trend as VBAT at the source of the second NMOS transistor NHV2. Its characteristic is that the resistance value of the first resistor RH is relatively high, about 10 MΩ. In this embodiment, the first resistor RH is selected as a high-voltage-resistant and high-square-resistance device. When VBAT is relatively high, a relatively large current flows through the first resistor RH. The first resistor RH and the first PMOS transistor PHV1 cooperate to divide the voltage of VBAT. The divided voltage is input to the gates of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, quickly reducing the gate voltages of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, achieving a preliminary reduction in the voltage amplitude. The series-connected first PMOS clamping diode PM1, second PMOS clamping diode PM2, and third PMOS clamping diode PM3 form a series clamping diode. The source of the clamping diode is connected to the source of the first NMOS transistor NHV1, and the drain of the clamping diode is grounded. When VBAT is relatively low, after a relatively low current flows through the first resistor RH, the self-conduction characteristic of the series clamping diode is used to limit the lowest voltage of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, preventing the voltages of the first NMOS transistor NHV1 and the second NMOS transistor NHV2 from being too low and ensuring the normal operation of the device. In typical data, when VBAT is 60V, the voltage at the node1 does not exceed 5.5V. After the above voltage division and clamping diode processing, at the drain output terminal of the second NMOS transistor NHV2, that is, at the node1, a low-voltage bias voltage with the same trend as VBAT but with a reduced amplitude is output, providing a suitable bias for the subsequent circuit so that it can operate stably under a wide voltage input.

[0023] The low-voltage self-starting circuit includes a first inverse ratio transistor PM4, a second inverse ratio transistor PM5, and a third inverse ratio transistor PM6. The first inverse ratio transistor PM4, the second inverse ratio transistor PM5, and the third inverse ratio transistor PM6 form a series inverse ratio transistor. The source of the first inverse ratio transistor PM4 is connected to the node1 node. The drain of the first inverse ratio transistor PM4 is connected to the source of the second inverse ratio transistor PM5. The drain of the second inverse ratio transistor PM5 is connected to the source of the third inverse ratio transistor PM6. The drain of the third inverse ratio transistor PM6 is connected to the drain of the third NMOS transistor NM1 and the gate of the fourth NMOS transistor NM2. The source of the third NMOS transistor NM1 is connected to the ground. The gate of the third NMOS transistor NM1 is connected to the base of the first NPN transistor NPN1. The emitter of the first NPN transistor NPN1 is connected to the ground through the second resistor Rb. The base of the first NPN transistor NPN1 is connected to the base of the second NPN transistor NPN2. The emitter of the second NPN transistor NPN2 is connected to one end of the third resistor Rs. The other end of the third resistor Rs is connected in series with the second resistor Rb. The other end of the second resistor Rb is connected to the ground. The emitter of the second NPN transistor NPN2 is connected to the ground through the third resistor Rs and the second resistor Rb. The collector of the second NPN transistor NPN2 is connected to the node4 node. At the moment when the voltage VBAT is applied, the whole circuit is in the initial state, and the base potentials of the first NPN transistor NPN1 and the second NPN transistor NPN2 are relatively low. At this time, the third NMOS transistor NM1 is turned off, and the series inverse ratio transistor composed of the first inverse ratio transistor PM4, the second inverse ratio transistor PM5, and the third inverse ratio transistor PM6 pulls up the gate voltage of the fourth NMOS transistor NM2. Since the fourth NMOS transistor NM2 is diode-connected, its source is turned on, thereby increasing the base voltages of the first NPN transistor NPN1 and the second NPN transistor NPN2, realizing low-voltage self-starting. When the circuit is working normally, there may also be abnormal situations that cause the bases of the first NPN transistor NPN1 and the second NPN transistor NPN2 to be pulled down, affecting the normal operation of the whole circuit. Through the low-voltage self-starting circuit, the first-order high-voltage source bandgap reference circuit can operate normally, providing a stable reference voltage for the whole linear regulator.

[0024] The bandgap reference circuit includes a bandgap reference cascode current source load composed of a second PMOS transistor PHV2, a third PMOS transistor PHV3, a fourth PMOS transistor PHV4, and a fifth PMOS transistor PHV5. The sources of the second PMOS transistor PHV2 and the third PMOS transistor PHV3 are connected to VBAT. The gates of the second PMOS transistor PHV2 and the third PMOS transistor PHV3 are shorted. The gates of the fourth PMOS transistor PHV4 and the fifth PMOS transistor PHV5 are shorted. The drain of the second PMOS transistor PHV2 is connected to the source of the fourth PMOS transistor PHV4. The drain of the third PMOS transistor PHV3 is connected to the source of the fifth PMOS transistor PHV5. Among them, the drain of the third PMOS transistor PHV3 and the fifth PMOS transistor PHV5 are connected in a diode connection with the gate and drain shorted. The drain of the second PMOS transistor PHV2 and the fourth PMOS transistor PHV4 are mirror transistors. The drain of the fourth PMOS transistor PHV4 is connected to the drain of the first NMOS field-effect transistor NHV_DEP. The drain of the fifth PMOS transistor PHV5 is connected to the drain of the second NMOS field-effect transistor NHV_LVT1. The gates of the first NMOS field-effect transistor NHV_DEP and the second NMOS field-effect transistor NHV_LVT1 are shorted, and the node between the short is node2. The source of the first NMOS field-effect transistor NHV_DEP is connected to the collector of the first NPN transistor NPN1 and the gate of the third NMOS field-effect transistor NHV_LVT5. The source of the third NMOS field-effect transistor NHV_LVT5 is the output node of the bandgap reference circuit, that is Figure 1For the node4 node shown, the input of the high-voltage source linear voltage regulator is connected to the node4 node. The drain of the third NMOS field-effect transistor NHV_LVT5 is connected to VBAT. The source of the second NMOS field-effect transistor NHV_LVT1 is connected to the collector of the second NPN transistor NPN2, and the base of the second NPN transistor NPN2 is connected to the node4 node. The bandgap reference cascode current source load composed of the second PMOS transistor PHV2, the third PMOS transistor PHV3, the fourth PMOS transistor PHV4, and the fifth PMOS transistor PHV5 provides a stable energy source for the circuit. When current flows through the bandgap reference circuit, the electric potential will be distributed according to the circuit design to form a specific voltage point. The first NMOS field-effect transistor NHV_DEP is a 60V high-voltage depletion-type NMOS field-effect transistor, and this device cannot be replaced by a depletion-type high-voltage NMOS. The second NMOS field-effect transistor NHV_LVT1 is a 60V low-threshold high-voltage NMOS field-effect transistor, which can ensure that when VBAT is relatively low, the voltage at the node2 node is retained to the greatest extent, ensuring that the gate voltage of NHV_LVT5 remains in the saturation state, so as to ensure that the subsequent circuit can work normally. The drains of the second PMOS transistor PHV2 and the fourth PMOS transistor PHV4 are mirror transistors, which can achieve current mirroring and proportional distribution. The current flowing through the drains of the second PMOS transistor PHV2 and the fourth PMOS transistor PHV4 is copied to other branches by mirroring, so as to achieve precise control of the current. When the circuit starts to work, the high-voltage to low-voltage biasing circuit provides an initial biasing current for the bandgap reference circuit. As the current flows and the voltage is established, the bandgap reference circuit gradually enters a stable state and starts to generate a stable reference voltage. This reference voltage will be fed back to the subsequent circuit to achieve the voltage stabilization and regulation functions of the entire circuit.

[0025] The high-voltage source linear regulator includes a two-stage operational amplifier. The two-stage operational amplifier includes a fourth NMOS field-effect transistor NM_ULVT1 and a fifth NMOS field-effect transistor NM_ULVT2. The gates of the fourth NMOS field-effect transistor NM_ULVT1 and the fifth NMOS field-effect transistor NM_ULVT2 are short-circuited, and the sources of the fourth NMOS field-effect transistor NM_ULVT1 and the fifth NMOS field-effect transistor NM_ULVT2 are connected to ground. The fourth NMOS field-effect transistor NM_ULVT1 and the fifth NMOS field-effect transistor NM_ULVT2 form a mirror tail current source of the two-stage operational amplifier. The drain of the fifth NMOS field-effect transistor NM_ULVT2 is connected to the sources of a sixth NMOS field-effect transistor NHV_LVT3 and a seventh NMOS field-effect transistor NHV_LVT4. The sixth NMOS field-effect transistor NHV_LVT3 and the seventh NMOS field-effect transistor NHV_LVT4 form the input pair transistors of the two-stage operational amplifier. The gate of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the node4. Since the voltage at the node4 is only 1.2V, the sixth NMOS field-effect transistor NHV_LVT3 and the seventh NMOS field-effect transistor NHV_LVT4 are selected as low-threshold high-voltage-tolerant devices. Such devices are difficult to provide sufficient overdrive voltage for ordinary high-voltage MOS / Bipolar devices, which affects the output accuracy / function. The input pair transistors of the two-stage operational amplifier receive the output at the node4. The gate of the seventh NMOS field-effect transistor NHV_LVT4 is connected to one end of a second resistor R1 and one end of a third resistor R2. The other end of the third resistor R2 is grounded. The gate of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the gate of a tenth PMOS transistor PHV10 through the node3. The tenth PMOS transistor PHV10 is the output terminal of the high-voltage source linear regulator. The drain of the tenth PMOS transistor PHV10 is connected to the output voltage VLDO through the node5. The source of the tenth PMOS transistor PHV10 is connected to VBAT. The drain of the tenth PMOS transistor PHV10 is connected to the other end of the second resistor. The sixth NMOS field-effect transistor NHV_LVT3 and the seventh NMOS field-effect transistor NHV_LVT4 of the two-stage operational amplifier simultaneously receive the reference voltage generated by the bandgap reference circuit output at the node4 and the feedback signal after the output voltage VLDO is divided by the second resistor R1 and the third resistor R2. The two-stage operational amplifier compares the reference voltage and the feedback signal, amplifies the difference between the two, and outputs a corresponding drive signal. The drive signal controls the gate voltage of the tenth PMOS transistor PHV10 through the node3 to adjust the conduction degree of the tenth PMOS transistor PHV10. The tenth PMOS transistor PHV10 adjusts its drain current according to the drive signal, thereby changing the output voltage VLDO.In the above circuit, the feedback signal is formed by dividing the output voltage VLDO through the second resistor R1 and the third resistor R2. The feedback signal is input to one input terminal of the second-stage operational amplifier to form a closed-loop control. This feedback mechanism enables the voltage regulator to monitor the change in the output voltage in real time and make adjustments according to the change situation, so that the output voltage is stabilized near the set value.

[0026] A Miller compensation capacitor HV_CAP is short-circuited between the output terminal of the second-stage operational amplifier and the node5. The Miller compensation capacitor HV_CAP is selected as a high-voltage-resistant device, and the voltage difference across the two ends of the Miller compensation capacitor HV_CAP is as high as 55V under normal circumstances. The Miller compensation capacitor HV_CAP can provide phase compensation to avoid high-frequency oscillation caused by the feedback loop in the circuit and ensure the stable operation of the circuit.

[0027] The source of the sixth PMOS transistor PHV6 is connected to VBAT. The drain of the sixth PMOS transistor PHV6 is connected to the source of the seventh PMOS transistor PHV7. The gate of the sixth PMOS transistor PHV6 is connected to the short - circuit node of the gates of the second PMOS transistor PHV2 and the third PMOS transistor PHV3. The gate of the seventh PMOS transistor PHV7 is connected to the short - circuit node of the gates of the fourth PMOS transistor PHV4 and the fifth PMOS transistor PHV5. The drain of the seventh PMOS transistor PHV7 is connected to the drain of the eighth NMOS field - effect transistor NHV_LVT2. The eighth NMOS field - effect transistor NHV_LVT2 is a 60V low - threshold high - voltage - tolerant NMOS transistor, and this device cannot be replaced by a depletion - type high - voltage NMOS. The source of the eighth NMOS field - effect transistor NHV_LVT2 is connected to the drain of the fourth NMOS field - effect transistor NM_ULVT1 and the gate of the fifth NMOS field - effect transistor NM_ULVT2. The fourth NMOS field - effect transistor NM_ULVT1 is a self - biased current mirror with its gate and drain short - circuited. The fifth NMOS field - effect transistor NM_ULVT2 is an NMOS transistor with a normal operating voltage and an extremely low threshold, and its threshold voltage is only about 200mV. The sixth PMOS transistor PHV6 and the seventh PMOS transistor PHV7 form a current mirror, and the current of the sixth PMOS transistor PHV6 is mirrored to the seventh PMOS transistor PHV7 to ensure the stability of the gate and drain currents of the eighth NMOS field - effect transistor NHV_LVT2. The gate voltage of the eighth NMOS field - effect transistor NHV_LVT2 is provided by the drain of the sixth PMOS transistor PHV6. Under the current - mirroring effect of the sixth PMOS transistor PHV6 and the seventh PMOS transistor PHV7, the source and gate voltages of the eighth NMOS field - effect transistor NHV_LVT2 are stabilized at specific values, thereby providing a stable bias voltage for the second - stage operational amplifier circuit. The eighth NMOS field - effect transistor NHV_LVT2 uses a low - threshold high - voltage - tolerant NMOS field - effect transistor. Its low - threshold characteristic enables the eighth NMOS field - effect transistor NHV_LVT2 to operate at a lower voltage. Through the synergistic effect of the sixth PMOS transistor PHV6 and the seventh PMOS transistor PHV7, the eighth NMOS field - effect transistor NHV_LVT2 provides a stable bias voltage for the second - stage operational amplifier, thereby improving the efficiency and stability of the circuit.

[0028] The gates of the eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 are short - circuited. The sources of the eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 are connected to VBAT. The drain of the eighth PMOS transistor PHV8 is connected to the drain of the sixth NMOS field - effect transistor NHV_LVT3. The drain of the ninth PMOS transistor PHV9 is short - circuited to the gate of the eighth PMOS transistor PHV8. The drain voltage of the ninth PMOS transistor PHV9 can directly feedback and regulate the gate voltage of the eighth PMOS transistor PHV8, thereby affecting the working state of the entire bias circuit. The drain of the ninth PMOS transistor PHV9 is connected to the drain of the seventh NMOS field - effect transistor NHV_LVT4. The eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 form a bias circuit structure, providing bias voltages for the sixth NMOS field - effect transistor NHV_LVT3 and the seventh NMOS field - effect transistor NHV_LVT4. Through the interconnected feedback mechanism, it reduces the influence of power supply voltage fluctuations and temperature changes on the input - stage current of the second - stage operational amplifier, thereby improving the amplification accuracy and stability of the operational amplifier and ensuring that the operational amplifier can accurately amplify the input signal.

[0029] The instantaneous pulse breakdown circuit includes a number of serially connected isolation diodes. The P - end of the first isolation diode HV_DIO1 is connected to VBAT, the N - end of the first isolation diode HV_DIO1 is connected to the P - end of the Nth isolation diode HV_DION. There are a number of isolation diodes between the first isolation diode HV_DIO1 and the Nth isolation diode HV_DION. These isolation diodes form a series - diode queue in sequence until the Nth isolation diode HV_DION. The N - end of the Nth isolation diode HV_DION is connected to the node3 node, and the N - end of the Nth isolation diode HV_DION is connected to the gate of the tenth PMOS transistor PHV10 through the node3 node. When the output voltage VLDO has a transient pulse drop, the gate voltage of the tenth PMOS transistor PHV10 drops sharply. This sharply - dropping voltage may cause the gate - source voltage of the tenth PMOS transistor PHV10 to exceed its breakdown voltage, resulting in breakdown and device damage. To prevent this situation, the instantaneous pulse breakdown locking circuit clamps the gate voltage of the tenth PMOS transistor PHV10 through a number of serially connected isolation diodes. These diodes do not conduct during normal operation, but when the gate voltage drops sharply, the diodes conduct, and the VBAT voltage directly clamps the gate voltage of the tenth PMOS transistor PHV10 through the conducting serially connected isolation diodes, preventing it from further dropping and clamping the gate voltage of the tenth PMOS transistor PHV10 within a safe voltage range, thereby protecting the tenth PMOS transistor PHV10 from breakdown.

[0030] Perform a low-voltage follower output simulation on a low-voltage follower high-voltage regulated LDO circuit proposed by the present invention. As Figure 2 shown, it is the low-voltage follower output simulation result of the present invention. No load is connected to the output terminal of the circuit. At this time, the output is no-load. VBAT rises from 0V to 4.5V all the way. VLDO is the output of the circuit. To reflect the low-voltage follower effect, the VBAT-VLDO curve is supplemented. It can be seen that under no-load conditions, when VBAT rises to 1V, the output can follow, and the following ability is very prominent. Figure 3 It is the simulation result of the load capacity when the input voltage is low. The left half is the curve of the output voltage value VLDO changing with VBAT after loading, and the right figure is the result of the overall working current and load current of the module. After adding a 1kΩ resistor load, the overall following speed decreases. When VBAT reaches 1.5V, the maximum load capacity is about 1.5mA. As VBAT rises, the 1kΩ load is very stable; taking the difference between the overall working current and the load current of the module from the right figure, it can be obtained that when VBAT is 1.5V, the no-load power consumption of the module is 1.11μA.

[0031] Figure 4 It is the result of normal pressure input / output. At this time, the output is no-load. VBAT rises from 0V to 60V all the way. VLDO is the output of the circuit. The typical output value is 5V. It can be seen that after VBAT is greater than 5V, VLDO is basically stable. Figure 5 It is the simulation diagram of the load capacity of the corresponding normal pressure output. The stable value of the output load current is 90.042mA. At this time, the no-load 5V VLDO is stable at 4.84252V, which is limited by the driving ability of the PHV_10 device.

[0032] Figure 6 It is the verification result of the transient pulse clamping protection function. When a transient pulse appears at the output terminal and pulls down, there is a risk of a sharp drop in the gate of PHV10 at this time. In severe cases, it will cause the gate-source breakdown of PHV10 and lead to circuit failure. In the figure, node3 represents the voltage change of the gate voltage of PHV10 with the high-voltage diode clamping circuit as VLDO1 is pulled down to 0V. The gate-source voltage variable is about 4.45V, which is lower than the gate-source breakdown voltage; node3 / without DIODE represents the voltage change of the gate voltage of PHV10 without the high-voltage diode clamping circuit as VLDO2 is pulled down to 0V. The gate-source voltage variable is about 60V. At this time, the gate-source of PHV10 has been broken down.

[0033] Figure 7 The present invention design adopts a low-temperature drift reference design. The typical value of the reference output is about 2.197V. The temperature drift of the LDO output is about 1.66ppm / ℃ in the range of -55℃ to 150℃, and the output is stable near 5V. The temperature drift is about 1.5ppm / ℃ in the range of -55℃ to 125℃, and the temperature drift is about 2.18ppm / ℃ in the range of -55℃ to 150℃.

[0034] This paper designs a super-wide power supply applicable low-power linear voltage regulator based on BCD high-voltage process. This circuit has the advantages of good low-voltage following performance, high-voltage stability, low power consumption, configurable output, strong driving ability, etc., and is very suitable for current in-vehicle LDO power supply applications.

[0035] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention fall within the protection scope of the claims of the present invention.

Claims

1. An ultra-wide power linear voltage regulator based on BCD high-voltage process, characterized in that It includes a high-voltage to low-voltage bias circuit, a bandgap reference circuit, and a high-voltage source linear regulator. The high-voltage to low-voltage bias circuit includes a series-connected first PMOS transistor PHV1 and a first resistor RH. The first resistor RH is connected to the gates of a first NMOS transistor NHV1 and a second NMOS transistor NHV2. The drain of the second NMOS transistor NHV2 is the output terminal of the high-voltage to low-voltage bias circuit, and the output terminal of the high-voltage to low-voltage bias circuit is connected to the input terminal of the high-voltage source linear regulator. The bandgap reference circuit includes a bandgap reference cascode current source load composed of a second PMOS transistor PHV2, a third PMOS transistor PHV3, a fourth PMOS transistor PHV4, and a fifth PMOS transistor PHV5. The output terminal of the bandgap reference circuit is the noed4 node. The high-voltage source linear regulator includes a two-stage operational amplifier. The two-stage operational amplifier includes a mirror tail current source composed of a fourth NMOS field-effect transistor NM_ULVT1 and a fifth NMOS field-effect transistor NM_ULVT2, and an input pair of transistors composed of a sixth NMOS field-effect transistor NHV_LVT3 and a seventh NMOS field-effect transistor NHV_LVT4. The gate of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the node4 node. The gate of the seventh NMOS field-effect transistor NHV_LVT4 is connected to one end of a second resistor R1 and one end of a third resistor R2. The gate of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the gate of a tenth PMOS transistor PHV10. The drain of the tenth PMOS transistor PHV10 is connected to the output voltage VLDO.

2. The ultra-wide power supply linear voltage regulator based on the BCD high-voltage process according to claim 1, wherein In the high-voltage to low-voltage bias circuit, the source of the first PMOS transistor PHV1 is connected to VBAT. After the gate and drain of the first PMOS transistor PHV1 are short-circuited, the drain of the first PMOS transistor PHV1 is connected to one end of the first resistor RH. The other end of the first resistor RH is short-circuited to the gate and drain of the first NMOS transistor NHV1, and the other end of the first resistor RH is simultaneously connected to the gate of the second NMOS transistor NHV2. The first resistor RH is selected as a high-voltage and high-square-resistance device. When VBAT is relatively high, a relatively large current flows through the first resistor RH. The first resistor RH and the first PMOS transistor PHV1 cooperate to divide the voltage of VBAT, and the divided voltage is input to the gates of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, quickly reducing the gate voltages of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, and realizing the preliminary reduction of the voltage amplitude.

3. The ultra-wide power supply linear voltage regulator based on BCD high-voltage process according to claim 2, wherein The source of the first NMOS transistor NHV1 is connected to a first PMOS clamping diode PM1, a second PMOS clamping diode PM2, and a third PMOS clamping diode PM3. The series-connected first PMOS clamping diode PM1, second PMOS clamping diode PM2, and third PMOS clamping diode PM3 form a series clamping diode. The source of the clamping diode is connected to the source of the first NMOS transistor NHV1, and the drain of the clamping diode is grounded. When VBAT is low, after a lower current flows through the first resistor RH, the self-conduction characteristic of the series clamping diode is used to limit the minimum voltages of the first NMOS transistor NHV1 and the second NMOS transistor NHV2, preventing the voltages of the first NMOS transistor NHV1 and the second NMOS transistor NHV2 from being too low and ensuring the normal operation of the device.

4. The ultra-wide power supply linear voltage regulator based on the BCD high-voltage process according to claim 3, wherein, The source of the first NMOS transistor NHV1 is connected to the source of the first normal-pressure PMOS clamping diode PM1. The drain of the first PMOS clamping diode PM1 is connected to the source of the second PMOS clamping diode PM2. The drain of the second PMOS clamping diode PM2 is connected to the source of the third PMOS clamping diode PM3. The drain of the third PMOS clamping diode PM3 is connected to ground. The source of the first NMOS transistor NHV1 is short-circuited to the gate of the first PMOS clamping diode PM1. The drain of the first PMOS clamping diode PM1 is short-circuited to the gate of the second PMOS clamping diode PM2. The drain of the second PMOS clamping diode PM2 is short-circuited to the gate of the third PMOS clamping diode PM3.

5. A super-wide power supply linear voltage regulator based on BCD high-voltage process according to claim 1, characterized in that, In the high-voltage source linear regulator, the gates of the fourth NMOS field-effect transistor NM_ULVT1 and the fifth NMOS field-effect transistor NM_ULVT2 are short-circuited. The sources of the fourth NMOS field-effect transistor NM_ULVT1 and the fifth NMOS field-effect transistor NM_ULVT2 are connected to ground. The drain of the fifth NMOS field-effect transistor NM_ULVT2 is connected to the sources of the sixth NMOS field-effect transistor NHV_LVT3 and the seventh NMOS field-effect transistor NHV_LVT4. The gate of the sixth NMOS field-effect transistor NHV_LVT3 is connected to the node4 node. The gate of the seventh NMOS field-effect transistor NHV_LVT4 is connected to one end of the second resistor R1 and one end of the third resistor R2. The sixth NMOS field-effect transistor NHV_LVT3 and the seventh NMOS field-effect transistor NHV_LVT4 of the second-stage operational amplifier simultaneously receive the reference voltage generated by the bandgap reference circuit output at the node4 node and the feedback signal after the output voltage VLDO is divided by the second resistor R1 and the third resistor R2. The second-stage operational amplifier compares the reference voltage and the feedback signal, amplifies the difference between the two, and outputs a corresponding drive signal. The drive signal controls the gate voltage of the tenth PMOS transistor PHV10 to adjust the conduction degree of the tenth PMOS transistor PHV10.

6. The ultra-wide power supply linear voltage regulator based on BCD high-voltage process according to claim 5, wherein, A Miller compensation capacitor HV_CAP is connected between the output terminal of the second-stage operational amplifier and the drain of the tenth PMOS transistor PHV10. The Miller compensation capacitor HV_CAP is selected as a high-voltage-resistant device. The Miller compensation capacitor HV_CAP can provide phase compensation to avoid high-frequency oscillation caused by the feedback loop in the circuit and ensure the stable operation of the circuit.

7. An ultra-wide power supply linear voltage regulator based on BCD high-voltage process according to claim 5, characterized in that, The drain of the fourth NMOS transistor NM_ULVT1 is connected to the source of the eighth NMOS transistor NHV_LVT2. The drain of the eighth NMOS transistor NHV_LVT2 is connected to the drain of the seventh PMOS transistor PHV7. The source of the seventh PMOS transistor PHV7 is connected to the drain of the sixth PMOS transistor PHV6. The source of the sixth PMOS transistor PHV6 is connected to VBAT. The sixth PMOS transistor PHV6 and the seventh PMOS transistor PHV7 form a current mirror, and the current of the sixth PMOS transistor PHV6 is mirrored to the seventh PMOS transistor PHV7 to ensure the stability of the gate and drain currents of the eighth NMOS transistor NHV_LVT2. The gate voltage of the eighth NMOS transistor NHV_LVT2 is provided by the drain of the sixth PMOS transistor PHV6. Under the action of the current mirror of the sixth PMOS transistor PHV6 and the seventh PMOS transistor PHV7, the source and gate voltages of the eighth NMOS transistor NHV_LVT2 are stabilized at specific values, thereby providing a stable bias voltage for the second-stage operational amplifier circuit.

8. An ultra-wide power supply linear voltage regulator based on BCD high-voltage process according to claim 5, characterized in that, The drain of the sixth NMOS transistor NHV_LVT3 is connected to the drain of the eighth PMOS transistor PHV8. The drain of the seventh NMOS transistor NHV_LVT4 is connected to the drain of the ninth PMOS transistor PHV9. The gates of the eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 are short-circuited. The sources of the eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 are connected to VBAT. The drain of the ninth PMOS transistor PHV9 is short-circuited to the gate of the eighth PMOS transistor PHV8. The eighth PMOS transistor PHV8 and the ninth PMOS transistor PHV9 constitute a bias circuit structure to provide a bias voltage for the sixth NMOS transistor NHV_LVT3 and the seventh NMOS transistor NHV_LVT4. Through the interconnected feedback mechanism, the influence of power supply voltage fluctuation and temperature change on the input-stage current of the second-stage operational amplifier is reduced.

9. The ultra-wide power supply linear voltage regulator based on BCD high-voltage process according to claim 1, characterized in that, The ultra-wide power supply linear voltage regulator further includes an instantaneous pulse breakdown circuit, which includes a number of series-connected isolation diodes. The P terminal of the first isolation diode HV_DIO1 is connected to VBAT, the N terminal of the first isolation diode HV_DIO1 is connected to the P terminal of the Nth isolation diode HV_DION, and there are a number of isolation diodes between the first isolation diode HV_DIO1 and the Nth isolation diode HV_DION. The number of isolation diodes form a series diode queue in sequence until the Nth isolation diode HV_DION. The N terminal of the Nth isolation diode HV_DION is connected to the node3 node, and the N terminal of the Nth isolation diode HV_DION is connected to the gate of the tenth PMOS transistor PHV10 through the node3 node.

10. An ultra-wide power supply linear voltage regulator based on BCD high-voltage process according to claim 1, characterized in that, In the bandgap reference circuit, the sources of the second PMOS transistor PHV2 and the third PMOS transistor PHV3 are connected to VBAT, the gates of the second PMOS transistor PHV2 and the third PMOS transistor PHV3 are short-circuited, the gates of the fourth PMOS transistor PHV4 and the fifth PMOS transistor PHV5 are short-circuited. The drain of the second PMOS transistor PHV2 is connected to the source of the fourth PMOS transistor PHV4, and the drain of the third PMOS transistor PHV3 is connected to the source of the fifth PMOS transistor PHV5. The drain of the third PMOS transistor PHV3 and the fifth PMOS transistor PHV5 are connected in a diode connection with the gate and drain short-circuited. The drain of the second PMOS transistor PHV2 and the fourth PMOS transistor PHV4 are mirror transistors. The drain of the fourth PMOS transistor PHV4 is connected to the drain of the first NMOS field effect transistor NHV_DEP, and the drain of the fifth PMOS transistor PHV5 is connected to the drain of the second NMOS field effect transistor NHV_LVT1. The gates of the first NMOS field effect transistor NHV_DEP and the second NMOS field effect transistor NHV_LVT1 are short-circuited, and the node2 node is between the short circuit. The source of the first NMOS field effect transistor NHV_DEP is connected to the collector of the first NPN transistor NPN1 and the gate of the third NMOS field effect transistor NHV_LVT5. The source of the third NMOS field effect transistor NHV_LVT5 is the output node node4 of the bandgap reference circuit.

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