Region write and maintenance for memory systems

Abstract

The invention relates to region write and maintenance for memory systems. The memory system may support partitioned write operations in which data associated with a preferred region may be written with a first cursor and data associated with other regions may be written with one or more second cursors. For example, an area associated with the highest access frequency may be written using a single-level cell cursor, and other areas may be written using a higher-level cursor, such as a three-level cursor. After writing the regions to a number of virtual blocks, a maintenance operation may be performed to reorder the regions within the number of virtual blocks according to access frequencies for the regions. In addition, performing the maintenance operation may include performing discarded item collection for the regions such that invalid regions may be erased and valid regions may be recombined within the number of virtual blocks.

Description

[0001] Cross-reference

[0002] This patent application claims the benefit of U.S. Patent Application No. 19 / 020,941, filed on January 14, 2025, entitled "Zone Writing and Maintenance for Memory Systems" by Lu et al., and U.S. Patent Application No. 63 / 627,601, filed on January 31, 2024, entitled "Zone Writing and Maintenance for Memory Systems" by Lu et al., and the entire content of each of the aforementioned applications is hereby incorporated by reference in its entirety.

[0003] The technical field relates to zone writing and maintenance of memory systems. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) the state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic DRAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selective memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described according to a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain the stored logical state for an extended period even in the absence of an external power source. Memory cells configured in a volatile configuration can lose the stored state when disconnected from an external power source. Summary of the Invention

[0006] Describe a memory system. The memory system may include: one or more memory devices; and a processing circuitry coupled to the one or more memory devices and configured to cause the memory system to: write first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of the memory system using a first write cursor; write second data associated with one or more second regions of the plurality of regions to the plurality of virtual blocks using a second write cursor; and perform a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder the plurality of regions within the plurality of virtual blocks at least in part based on a respective access frequency associated with each region.

[0007] Describe a non-transitory computer-readable medium storing code. The code includes instructions executable by one or more processors to cause a memory system to: write first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of the memory system using a first write cursor; write second data associated with one or more second regions of the plurality of regions to the plurality of virtual blocks using a second write cursor; and perform a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder the plurality of regions within the plurality of virtual blocks at least in part based on a respective access frequency associated with each region.

[0008] Describe a method. The method may include: writing first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of the memory system using a first write cursor; writing second data associated with one or more second regions of the plurality of regions to the plurality of virtual blocks using a second write cursor; and performing a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder the plurality of regions within the plurality of virtual blocks at least in part based on a respective access frequency associated with each region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Show an example of a system supporting region writing and maintenance of a memory system according to the examples disclosed herein.

[0010] Figure 2 Show an example of a region architecture supporting region writing and maintenance of a memory system according to the examples disclosed herein.

[0011] Figure 3 Show an example of a maintenance diagram supporting region writing and maintenance of a memory system according to the examples disclosed herein.

[0012] Figure 4 A block diagram of a memory system that supports regional writing and maintenance of a memory system in accordance with an example disclosed herein.

[0013] Figure 5 A flowchart that illustrates a method or methods for supporting regional writing and maintenance of a memory system in accordance with an example disclosed herein. DETAILED DESCRIPTION

[0014] Some memory systems may implement a partitioned architecture in which data may be written as part of one or more open regions (e.g., up to a certain number of open regions) of the memory system. For example, a memory system may support a certain number of open regions, and the memory system may implement a certain number of cursors (e.g., write pointers) for writing data associated with the number of open regions (e.g., a cursor for each open region) to a memory array. In some cases, writing data may include opening a block (e.g., a virtual block) of the memory array and allocating a portion of a write buffer for writing data. In some such cases, data may be temporarily written to the write buffer using a cursor associated with the corresponding region and then transferred to the open block. However, implementing a relatively large number of open regions may involve using a relatively large number of cursors. Similarly, implementing a relatively large number of open regions may involve consuming a relatively large amount of write buffer storage capacity. Thus, implementing a partitioned architecture may involve relatively high system resource utilization, which can increase challenges such as system overhead and processing time for completing a partitioned write operation of the memory system.

[0015] According to an example as described herein, a memory system may support a partitioned write operation, where data associated with a preferred region (e.g., temperature) may be written with a first cursor, and data associated with other regions may be written with one or more second cursors. For example, a region associated with the highest access frequency (e.g., the highest temperature) may be designated as the preferred region and may be written to the memory system using a first cursor (e.g., a single-level cell (SLC) cursor) such that data associated with the preferred region is written to the SLC of the memory system. In some such examples, other regions may be written to the memory system using a second cursor (e.g., a three-level cell (TLC) cursor, a four-level cell (QLC) cursor, or some other multi-level cell (MLC) cursor and other examples) such that data associated with the other regions is written to the TLC, MLC, or QLC of the memory system and other examples. After writing data associated with regions (e.g., the preferred region and other regions) to a number of virtual blocks of the memory system (e.g., using corresponding cursors), the data may be partitioned to separate the data into the corresponding regions, and a maintenance operation may be performed to reorder the regions (e.g., and corresponding data) within the number of virtual blocks according to the access frequency of the regions. The access frequency may be related to the temperature of the regions and other access frequency metrics. Additionally, performing the maintenance operation may include performing garbage collection for the regions such that invalid regions may be erased and valid regions may be reconsolidated within the number of virtual blocks. In some cases, performing the maintenance operation may include folding data associated with the preferred region from one region to another, e.g., from SLC to TLC. Implementing the partitioned write operation as described herein may support a reduced number of cursors and / or reduced consumption of write buffer storage capacity for writing region data, thereby reducing system resource utilization and system overhead. Additionally or alternatively, performing the partitioned write operation may support a reduced garbage collection frequency, a reduced address map table size associated with accessing region data, and improved random read latency and other benefits.

[0016] In addition to its applicability in a memory system as described herein, techniques for regional writing and maintenance in a memory system can generally be implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, can be associated with relatively high processing requirements to meet user expectations. Thus, improving the processing capabilities of an electronic device by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, and other performance metrics can improve the user experience or attractiveness. Implementing the techniques described herein can improve the performance of an electronic device by establishing a partitioned architecture with relatively reduced system resource utilization, which can reduce processing or latency time, improve response time, or otherwise improve the user experience and other benefits.

[0017] The features of the present disclosure are illustrated and described in the context of systems, devices, and circuits. The features of the present disclosure are further illustrated and described in the context of a regional architecture, maintenance diagrams, and flowcharts.

[0018] Figure 1 An example of a system 100 that supports regional writing and maintenance of a memory system according to an example as disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110. System 100 can be included in a computing device such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., a train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0019] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash memory device, a Universal Serial Bus (USB) flash memory device, a Secure Digital (SD) card, a solid state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other devices.

[0020] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations in accordance with the instances described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory subsystem 110, for example, to write data to and read data from the memory system 110. Although Figure 1 a memory system 110 is shown, the host system 105 may be coupled to any number of memory systems 110.

[0021] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, USF interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM socket interfaces that support DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be included in the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110, or otherwise support between the host system controller 106 and the memory system controller 115. In some instances, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0022] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices 130-a and 130-b are shown in the example of Figure 1 , the memory system 110 may include any number of memory devices 130. In addition, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0023] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130 and other such operations, which may generally be referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to commands from the host system 105 or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert a response (e.g., a data packet or other signal) associated with the memory device 130 into a corresponding signal for the host system 105.

[0024] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0025] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or combinations thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic for performing the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0026] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operation codes (e.g., executable instructions) executable by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for, e.g., internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to the memory device 130, the data may be stored in the local memory 120 and the data may be available in the local memory 120 for subsequent retrieval or manipulation (e.g., update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0027] Although Figure 1 the example of the memory system 110 in [[ ]] has been illustrated as including the memory system controller 115, in some cases, the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may be located inside the memory device 130 respectively, to perform the functions attributed herein to the memory system controller 115. Generally, in some cases, one or more of the functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash memory) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash memory) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, memory device 130 may include (e.g., on the same die, within the same package) local controller 135, which may perform operations on one or more memory cells of the corresponding memory device 130. Local controller 135 may operate in conjunction with memory system controller 115 or may perform one or more functions ascribed herein to memory system controller 115. For example, as Figure 1 illustrated, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash memory device). Storage device 130 may be or include die 160 (e.g., memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some instances, die 160 may be an electronic device-level semiconductor wafer cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if the memory cells are configured to each store two bits of information, three-level cells (TLCs) if the memory cells are configured to each store three bits of information, four-level cells (QLCs) if the memory cells are configured to each store four bits of information, or more generally referred to as multi-level memory cells. Relative to SLC memory cells, multi-level memory cells may provide greater storage density, but in some cases, may involve narrower read or write margins or greater complexity of the support circuitry.

[0032] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on the memory cells within different blocks 170 as long as the different blocks 170 are in different planes 165. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may be referred to as a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 17-a, 170-b, 170-c, and 170-d located in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, the blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations on different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on the memory cells within different pages 175 having the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, a block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, the memory cells within the same page 175 may share a common word line (e.g., coupled thereto), and the memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level or a portion thereof), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest memory unit (e.g., group of memory cells) that can be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and block 170 can be the smallest memory unit (e.g., group of memory cells) that can be independently erased (e.g., concurrently erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Thus, for example, in some cases, page 175 in use may not be updated until the entire block 170 containing page 175 has been erased.

[0035] In some cases, to update some data within block 170 while preserving other data within block 170, memory device 130 can copy the data to be preserved to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 can mark or otherwise designate the data remaining in the old block 170 as invalid or obsolete, and can update the logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) of the data with the new valid block 170 instead of the old invalid block 170. In some cases, for example, due to latency or wear considerations, this copy and remapping can be performed instead of erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table can be stored within the memory cells of memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by local controller 135 or memory system controller 115.

[0036] In some cases, the L2P mapping table can be maintained, and data can be marked as valid or invalid at the page granularity level, and page 175 can contain valid data, invalid data, or no data. Invalid data can be obsolete data, which can be due to a more recent or updated version of the data stored in a different page 175 of memory device 130. The invalid data may have been previously programmed to the invalid page 175, but may no longer be associated with a valid logical address, such as a logical address referenced by host system 105. Valid data can be the most recent version of such data stored on memory device 130. A page 175 that does not contain data can be a page 175 that has not been written to or has been erased.

[0037] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, erasure, block scanning, health monitoring, or others, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in the block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called "garbage collection" may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example: selecting a block 170 containing both valid and invalid data; selecting a page 175 within the block that contains valid data; copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected page 175 as invalid; and erasing the selected block 170. Thus, the number of erased blocks 170 can be increased so that more blocks 170 are available for storing subsequent data (e.g., data subsequently received from the host system 105).

[0038] In some cases, the memory system 110 may utilize the memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or within-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] System 100 may include any number of non-transitory computer-readable media that support regional writing and maintenance of the memory system. For example, the host system 105 (e.g., the host system controller 106), the memory system 110 (e.g., the memory system controller 115), or the memory device 130 (e.g., the local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., by the host system controller 106), the memory system 110 (e.g., by the memory system controller 115), or the memory device 130 (e.g., by the local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions as described herein.

[0040] According to an example as described herein, the memory system 110 may support a partitioned write operation, where data associated with a preferred region may be written with a first cursor, and data associated with other regions may be written with one or more second cursors. For example, a region associated with the highest access frequency (e.g., highest temperature) may be designated as the preferred region and written to the memory system using an SLC cursor such that data associated with the preferred region is written to the SLC of the memory system 110. In some such examples, other regions may be written to the memory system using a TLC cursor, an MLC cursor, or a QLC cursor (e.g., or an SLC cursor) such that data associated with the other regions is written to the TLC, MLC, or QLC (e.g., or SLC) of the memory system 110. After writing data associated with regions (e.g., the preferred region and other regions) to a number of virtual blocks of the memory system 110 (e.g., using corresponding cursors), the data in the regions may be partitioned, resulting in all the data in the regions being sequentially arranged into corresponding, separate, and re-ordered regions within the number of virtual blocks according to the access frequency (e.g., temperature) of the regions. Additionally or alternatively, performing the maintenance operation may include performing garbage collection for the regions such that invalid regions may be erased and valid regions may be re-consolidated within the number of virtual blocks. In some cases, performing the maintenance operation may include folding data associated with the preferred region from the SLC to the TLC based on the data originally being written with the SLC cursor. Implementing the partitioned write operation as described herein may support a reduced number of cursors and / or a reduced consumption of write buffer storage capacity for writing region data, thereby reducing system resource utilization and system overhead. Additionally or alternatively, performing the partitioned write operation may support a reduced garbage collection frequency, the size of the address mapping table associated with accessing region data, and improved random read latency, among other benefits.

[0041] Figure 2 An example of a region architecture 200 that supports region write and maintenance of a memory system according to an example disclosed herein is shown. The region architecture 200 may illustrate aspects or operations of a system that may be an example of system 100, as referenced Figure 1 as described. For example, the region architecture 200 illustrates operations associated with performing a region write operation at the memory system 110, as referenced Figure 1 as described. The region architecture 200 illustrates a diagram for performing region write operations and maintenance operations.

[0042] The region architecture 200 may be implemented to write data to the memory system 110. As referenced Figure 1As described, the memory system 110 may include one or more dies 160, each die 160 including one or more non-volatile memory arrays (e.g., NAND memory arrays). Each non-volatile memory array may include one or more planes 165, where each plane 165 may include a corresponding set of blocks 170. The blocks 170 may be physical blocks associated with a set of memory cells. The memory system 110 may also include a set of virtual blocks 180, each virtual block 180 including one or more blocks 170 from each plane 165 of each die 160. In some cases, the memory cells of the memory system 110 may be non-volatile memory cells, such as NAND memory cells. In some instances, the memory system 110 may support different granularities of memory cells. In some such instances, a portion of the memory cells may be implemented as SLC, and a portion of the memory cells may be implemented as TLC, or some other multi-level cell (e.g., MLC, QLC). For example, the memory system 110 may include TLC memory 230, which includes TLC configured to store data. In some embodiments, the memory system 110 may configure the memory cells to operate as SLC, TLC, or some other multi-level cell.

[0043] The memory system 110 may support a regional architecture 200, where data is written to the memory system 110 and organized by region (e.g., data segments). In some cases, data may be written by sequentially writing the data to consecutive addresses (e.g., logical addresses, physical addresses) associated with the corresponding regions. In some cases, data associated with multiple regions may be written to one or more virtual blocks 180 of the memory system 110. For example, a virtual block 180 may include multiple regions, and the size of each region may be greater than or less than the size of each virtual block 180 (e.g., based on host requirements). Since each virtual block 180 includes one or more blocks 170 from each plane 165 of each die 160, each region may span multiple planes 165 and multiple dies 160. Each region may be associated with an access frequency and may include data corresponding to the respective access frequency. For example, a region associated with a relatively high access frequency may include data that is accessed relatively frequently. In some cases, each region may be associated with a temperature classification (e.g., hot, moderately hot, medium, moderately cold, cold, or other temperature categories) corresponding to the access frequency of the respective region. For example, a hot region may be a region associated with a relatively high access frequency, while a cold region may be a region associated with a relatively low access frequency. In some cases, the memory system 110 may be organized by logical components that may map to partitioned physical components 205 and unpartitioned physical components 210. For example, the partitioned physical components 205 have been partitioned (e.g., organizing data into regions), while the unpartitioned physical components 210 have not been partitioned.

[0044] Memory system 110 may include cursors for writing data to virtual block 180 of memory system 110. Each cursor may be an instance of a write pointer and may be configured to write data to the memory cells of memory system 110. In some cases, writing data to the memory cells of memory system 110 may include writing data to a write buffer of memory system 110 and then writing the data to the non-volatile memory cells of memory system 110. In some such cases, the cursor may be configured to facilitate writing data to the write buffer or writing data to the non-volatile memory cells, or a combination thereof. In some cases, the cursor may be associated with a granularity such that different cursors may be associated with different granularities. For example, memory system 110 may include one or more SLC cursors 215 configured to write data to SLCs using a granularity associated with SLC, and one or more TLC cursors 220 (e.g., MLC cursors, QLC cursors) configured to write data to TLCs (e.g., MLC, QLC) using a granularity associated with TLC (e.g., MLC, QLC). Memory system 110 may also include a write booster (WB) cursor 225. The WB cursor 225 may be an instance of an SLC cursor such that the WB cursor 225 is configured to write non-preferred region data using a granularity associated with SLC. In some cases, in response to enabling a performance write mode, the WB cursor 225 may be used to write non-preferred region data during a region write operation.

[0045] Memory system 110 may also include one or more address mapping tables. The one or more address mapping tables may be associated with different granularities. For example, memory system 110 may include an address mapping table for address granularity (e.g., PPT3) and an address mapping table for region granularity (e.g., PPT2). In some such instances, the address mapping table may be part of a logical-to-physical (L2P) table such that each address mapping table may represent a different level of the L2P table. In some embodiments, the address mapping table associated with the address granularity may include a mapping between the logical block address and the physical block address of memory system 110. In some embodiments, the address mapping table associated with the region granularity may include a mapping associated with a region of memory system 110.

[0046] Memory system 110 may support a regional write operation according to the implementation regional architecture 200. The regional write operation may include writing data to the memory system 110 using the SLC cursor 215, the TLC cursor 220, the WB (e.g., SLC) cursor 225, or a combination thereof. In some cases, the cursor selected for writing data may be associated with the access frequency of the region associated with the data. For example, the memory system 110 may select the SLC cursor 215 for writing data associated with a region, and may select the TLC cursor 220 for writing data associated with another region.

[0047] In some cases, the memory system 110 may select a single region for writing with the SLC cursor 215. For example, data associated with a preferred region (e.g., a preferred temperature region) may be written using the SLC cursor 215. In some such instances, the preferred region may be selected from the regions according to the access frequency of the preferred region. In some embodiments, the preferred region may be a region determined to be associated with a relatively highest access frequency. That is, the preferred region may have a hot temperature classification. Writing data associated with the preferred region using the SLC cursor 215 may include writing the data to the write buffer of the memory system 110 and then writing the data to the SLC (e.g., SLC memory). Additionally, writing the data to the SLC may include writing the data to one or more virtual blocks 180 of the memory system 110. In some instances, if the preferred region is accessed most frequently and the TLC is associated with a relatively low access latency, then the memory system 110 may use the SLC cursor 215 to write data associated with the preferred region. Thus, implementing the SLC for storing data associated with the preferred region enables the data to be accessed with relatively reduced system overhead.

[0048] In some cases, the memory system 110 may select other regions for writing with the TLC cursor 220 (e.g., MLC cursor, QLC cursor). For example, data associated with other regions (e.g., non-preferred regions) may be written using the TLC cursor 220. In some such instances, the other regions may be associated with an access frequency relatively lower than that of the preferred region. Writing data associated with the other regions using the TLC cursor 220 may include writing the data to the write buffer of the memory system 110 and then writing the data to the TLC memory 230 (e.g., TLC memory 230-b). Additionally, writing the data to the TLC may include writing the data to one or more virtual blocks 180 of the memory system 110. In some instances, if the access frequency of the other regions is lower than that of the preferred region, then the memory system 110 may use the TLC cursor 220 to write data associated with the other regions.

[0049] In some cases, the memory system 110 may select a single region for writing with the WB cursor 225. For example, data associated with a secondary region (e.g., a secondary preferred temperature region) may be written using the WB cursor 225. In some such instances, the secondary region may be selected from the regions based on the access frequency of the secondary region. In some embodiments, the secondary region may be the region determined to be associated with the second highest access frequency (e.g., after the preferred region). Writing data associated with the secondary region using the WB cursor 225 may include writing the data to the write buffer of the memory system 110, writing the data to the SLC (e.g., SLC memory), and subsequently folding (e.g., flushing) the data to the TLC memory 230. In some instances, if the memory system 110 is operating in a performance write mode (e.g., write boost mode), then the memory system 110 may use the WB cursor 225 to write data associated with the secondary region. For example, as described with reference to Figure 1 the host system 105 may initiate a performance write mode, and the memory system 110 may use the WB cursor 225 to write data associated with the secondary region in response to the initiation of the performance write mode.

[0050] The memory system 110 may support maintenance operations according to the implemented region architecture 200. The memory system 110 may perform maintenance operations based on the activity level of the memory system 110 or based on the periodicity for performing maintenance operations, or both. For example, maintenance operations may be performed in response to the memory system 110 being in an idle state (e.g., not actively performing access operations). Additionally or alternatively, maintenance operations may be performed in response to the duration since the previous maintenance operation that met a threshold duration has elapsed (e.g., at night, when the user is sleeping and not actively interacting with the memory system 110, and other instances). In some instances, maintenance operations may be performed in response to the memory system 110 receiving a command from the host system 105 to perform a maintenance operation.

[0051] The maintenance operation may include performing partitioning, which includes separating (e.g., ordering, sorting, reordering) data stored in the virtual block 180 into corresponding regions. For example, data written using the TLC cursor 220 may be written such that data associated with various regions may be intermixed (e.g., interleaved) within the virtual block 180. However, for each data segment, the partitioning of the data may identify the region associated with the corresponding data segment. The data may be rewritten continuously with other data segments associated with the corresponding region. The maintenance operation may also include reordering (e.g., reorganizing) regions within the virtual block 180 of the memory system 110 according to the access frequency of the regions. In some cases, each virtual block 180 may be associated with storing data having similar access frequencies such that each virtual block 180 may store one or more regions having the same temperature classification.

[0052] The maintenance operation may include performing garbage collection at the region granularity. For example, the memory system 110 may identify regions containing valid data (e.g., valid regions) and regions containing invalid data (e.g., invalid regions), and then merge the regions containing valid data and erase the regions containing invalid data. In some such instances, merging regions may include relocating regions within the virtual block 180 (e.g., multiple virtual blocks 180). In some embodiments, each region may contain either valid or invalid data (e.g., all data in the region may be valid or all data in the region may be invalid) such that if all data in the region is invalid, then the region may be identified as an invalid region. In some cases, performing partitioning or garbage collection may include performing partitioning or garbage collection at the TLC memory 230-b (e.g., where the TLC memory 230-b is the TLC memory 230-a), or may include transferring data associated with the region to another TLC memory 230-a and performing partitioning or garbage collection at the TLC memory 230-a. In some embodiments, the memory system 110 may support a reduced garbage collection frequency according to the performance of the maintenance operation.

[0053] The maintenance operation may include folding data associated with a preferred region from the SLC to the TLC memory 230. For example, data associated with a preferred region may be initially written by the SLC cursor 215 to the SLC, and then after initiating the maintenance operation, the memory system 110 may fold the data from the SLC to the TLC memory 230. In some such instances, folding the data may include merging the data from SLC granularity to TLC granularity such that each bit of data (e.g., from a respective SLC) may be combined with two other bits of data (e.g., from other respective SLCs), and the resulting three data bits may be stored to the TLC of the TLC memory 230. In some cases, the data may be folded from the SLC to the TLC memory 230 before performing partitioning during the maintenance operation such that the preferred region may be reordered with other regions.

[0054] The memory system 110 may access data associated with a region in accordance with performing a maintenance operation. In some cases, in response to performing partitioning and garbage collection, the memory system may use an address mapping table associated with a region granularity (e.g., PPT2) to access data (e.g., in response to an access command, as part of an access operation). That is, because regions are rewritten sequentially (e.g., and merged during garbage collection), the data associated with a region may be sequential and thus accessed using an address mapping table associated with the region granularity. In some cases, because an address mapping table associated with a region granularity may be used to access data, the memory system 110 may support a reduced size of the L2P table. In some cases, the memory system 110 may access data before performing a maintenance operation, where the region written by the TLC cursor 220 and the WB cursor 225 is associated with the unpartitioned physical component 210. In some such cases, the memory system 110 may use an address mapping table associated with an address granularity (e.g., PPT3) to access data. For example, at this time the region may not be sequential and thus may not be accessed using an address mapping table associated with a region granularity (e.g., PPT2).

[0055] Performing region write operations and maintenance operations as described herein may support implementing fewer cursors. For example, the memory system 110 may support the SLC cursor 215, the TLC cursor 220, and the WB cursor 225 for writing data instead of implementing a cursor for writing data associated with each region. Thus, among other benefits, the memory system 110 may use fewer system resources and overhead to perform write operations.

[0056] Figure 3An example of maintenance diagram 300 that supports regional writing and maintenance of a memory system according to an example disclosed herein is shown. Maintenance diagram 300 may illustrate aspects or operations of a system, which may be an example of system 100, as referenced Figure 1 as described. For example, maintenance diagram 300 illustrates operations associated with performing maintenance operations at memory system 110, as referenced Figure 1 as described. Maintenance diagram 300 includes operations 301, 302, 303, and 304 associated with performing partitioning and garbage collection.

[0057] Operation 301 illustrates initially writing data to memory system 110 according to a regional writing operation as referenced Figure 2 as described. For example, operation 301 includes writing data associated with respective regions 310 to virtual block 305 of memory system 110, and virtual block 305 may be an example of virtual block 180, as referenced Figure 1 as described. In some such examples, writing data may include writing data to virtual block 305-a, virtual block 305-b, and virtual block 305-c such that each virtual block 305 may be configured to store data associated with one or more regions 310. Although not shown as such, in some cases, regions 310 may be shared among virtual blocks 305. For example, a portion of region 310 may be written to virtual block 305-a and another portion of region 310 may be written to virtual block 305-b. In some cases, data associated with region 310 may be written with a cursor, such as SLC cursor 215, TLC cursor 220 (e.g., MLC cursor, QLC cursor), WB cursor 225, or any combination thereof, as referenced Figure 2As described. For example, data associated with one of regions 310 (e.g., a preferred region, region 310-a) can be written with SLC cursor 215, data associated with another region 310 (e.g., a secondary region, region 310-b) can be written with WB cursor 225, and data associated with other regions 310 (e.g., region 310-d, region 310-c, region 310-e, region 310-f) can be written with TLC cursor 220. In some such cases, data written with SLC cursor 215, WB cursor 225, or both can be written in an ordered manner. For example, one or more virtual blocks 305 (e.g., virtual block 305-a) can contain preferred temperature regions. In some instances, data written with SLC cursor 215 can be sequentially written according to the corresponding region 310 (e.g., region 310-a). In some such instances, data written with SLC cursor 215 can be partitioned (e.g., separated into respective regions) during the writing of the data. Similarly, data written with WB cursor 225 can also be partitioned during the writing of the data. However, data written with TLC cursor 220 can be written such that data initially mixes from multiple regions (e.g., data from each region can be interleaved with data from other regions). For example, the data in virtual blocks 305-b and 305-c can be unpartitioned data 315 (e.g., unpartitioned data 315-a and unpartitioned data 315-b, respectively), which contains interleaved or mixed data from multiple regions that has not been partitioned during the writing of the data.

[0058] In some cases, operation 301 can illustrate the preferred region 310 (e.g., region 310-a) after folding data associated with the preferred region 310 from SLC to TLC (e.g., after initially writing region 310-a with SLC cursor 215). That is, region 310 can be written to virtual block 305, where virtual block 305 can be associated with TLC memory (e.g., TLC memory 230, as referenced Figure 2 as described). However, the preferred region 310 can be written to SLC memory and then folded to virtual block 305.

[0059] Operation 302 illustrates the partitioning of unpartitioned data 315. That is, operation 302 illustrates separating the unpartitioned data 315 written by TLC cursor 220 to virtual blocks 305-b and 305-c into corresponding regions 310. For example, data associated with region 310-c may initially be written mixed with data from region 310-d into virtual block 305-b as unpartitioned data 315-a. Then, the data associated with region 310-c may be continuously identified and rewritten to separate the data associated with region 310-c from the data associated with region 310-d. Similarly, data associated with region 310-e may initially be written mixed with data from region 310-f into virtual block 305-c as unpartitioned data 315-b. Then, the data associated with region 310-e may be continuously identified and rewritten to separate the data associated with region 310-e from the data associated with region 310-f.

[0060] In some cases, after initially performing the partitioning, regions 310 may or may not be sorted within virtual block 305 according to access frequency. That is, each region 310 may be associated with a corresponding access frequency corresponding to a respective temperature classification (e.g., hot, medium, cold), but regions 310 may not initially be sorted by access frequency. Similarly, regions 310 may not be sorted within virtual block 305 such that each virtual block 305 contains data with the same respective temperature classification. In some cases, operations 302 and 303 may be performed simultaneously in a single operation.

[0061] Operation 303 illustrates reordering regions 310 within virtual block 305. For example, operation 303 illustrates performing a maintenance operation that may include reordering regions 310 within virtual block 305 according to the access frequency of regions 310. For example, regions 310 may be repositioned within virtual block 305 in the order of access frequency such that more frequently accessed regions 310 may be first in the order, while less frequently accessed regions 310 may be last in the order. That is, regions 310 may be reordered according to the temperature classification of regions 310. For example, region 310-a may be accessed most frequently and thus may be sorted first within virtual block 305; while region 310-e may be accessed least frequently and thus may be sorted last within virtual block 305. In some cases, each virtual block 305 may be configured to store data associated with similar access frequencies. For example, each virtual block 305 may store data associated with regions of the same or similar temperature classification.

[0062] Operation 304 describes performing garbage collection at the region granularity. Performing garbage collection can include identifying regions 310 that contain valid data and regions 310 that contain invalid data. In some embodiments, each region can contain either valid or invalid data, such that if all the data in a region is valid, then the region can be identified as a valid region, or if all the data in a region is invalid, then the region can be identified as an invalid region. The invalid regions can be erased or garbage collected. If the size of an invalid region is equal to the size of a virtual block 305, or if a single invalid region 310 is mapped to a single virtual block 305, then the region 310 can be simply erased. In some other cases, if the size of the invalid region 310 is less than the size of the virtual block 305, then the virtual block 305 can contain multiple regions 310, some of which can be valid. Thus, to erase the invalid region 310 from the virtual block 305, any valid regions in the virtual block 305 can be transferred to another virtual block 305, and the invalid region can be erased by erasing the virtual block 305. The valid regions can be merged within the virtual block 305 such that the regions 310 can be repositioned within the virtual block 305.

[0063] For example, operation 304 describes identifying regions 310-d and 310-e as invalid regions and erasing regions 310-d and 310-e by erasing virtual block 305-c. However, if region 310-e is identified as a valid region and region 310-d is identified as an invalid region, then region 310-e can be transferred to another virtual block 305 (e.g., a new virtual block not shown in Figure 3 before erasing virtual block 305-c (e.g., erasing region 310-b). That is, each virtual block 305 can be erased at the block granularity such that each region 310 stored within the virtual block 305 can be erased during the erasure of the virtual block 305. In some such instances, the regions 310 can be merged within the virtual block 305 such that one or more regions 310 can be transferred between virtual blocks 305 (e.g., from virtual block 305-b to virtual block 305-a, from virtual block 305-c to virtual block 305-b). In some cases, performing garbage collection can create “empty” space (e.g., space that does not store data) within the virtual block 305 for storing additional data. In some such cases, the memory system 110 can write subsequent host data to the “empty” space, such as data associated with other regions, or unpartitioned data (e.g., data not associated with a region).

[0064] Figure 4 FIG. 400 is a block diagram of a memory system 420 that supports region writes and maintenance in a memory system according to an example as disclosed herein. The memory system 420 can be as described with reference to Figures 1 to 3Examples of aspects of the described memory system. Memory system 420 or its various components can be examples of components for performing various aspects of area writing and maintenance of a memory system as described herein. For example, memory system 420 can include a write component 425, a maintenance component 430, a determination component 435, a mode component 440, an access component 445, a folding component 450, or any combination thereof. Components of each of these components or sub-components (e.g., one or more processors, one or more memories) can communicate directly or indirectly with each other (e.g., via one or more buses).

[0065] Write component 425 can be configured to or otherwise support components for writing first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of a memory system using a first write cursor. In some instances, write component 425 can be configured to or otherwise support components for writing second data associated with one or more second regions of a plurality of regions to the plurality of virtual blocks using a second write cursor. Maintenance component 430 can be configured to or otherwise support components for performing a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder a plurality of regions within the plurality of virtual blocks at least in part based on a respective access frequency associated with each region.

[0066] In some instances, determination component 435 can be configured to or otherwise support components for determining that one or more first regions are associated with a first access frequency, wherein writing the first data to the plurality of virtual blocks using the first write cursor is at least in part based on the one or more first regions being associated with the first access frequency.

[0067] In some instances, the first access frequency is greater than an access frequency associated with one or more second regions.

[0068] In some instances, to support writing a plurality of regions to a plurality of virtual blocks, write component 425 can be configured to or otherwise support components for writing the first data with a first granularity associated with single-level cells at least in part based on using the first write cursor. In some instances, to support writing a plurality of regions to a plurality of virtual blocks, write component 425 can be configured to or otherwise support components for writing the second data with a second granularity associated with multi-level cells at least in part based on using the second write cursor.

[0069] In some instances, folding component 450 can be configured to or otherwise support components for folding the first data from the first granularity to the second granularity at least in part based on performing the maintenance operation.

[0070] In some instances, to support performing maintenance operations, the maintenance component 430 may be configured to or otherwise support a component for erasing one or more of the plurality of virtual blocks based at least in part on one or more virtual blocks including one or more regions associated with invalid data. In some instances, to support performing maintenance operations, the maintenance component 430 may be configured to or otherwise support a component for recording an indication that the one or more regions are invalid based at least in part on the one or more regions being associated with invalid data.

[0071] In some instances, the mode component 440 may be configured to or otherwise support a component for enabling a performance write mode of the memory system. In some instances, the write component 425 may be configured to or otherwise support a component for writing third data associated with a third region among the plurality of regions to the plurality of virtual blocks using a third write cursor based at least in part on enabling the performance write mode.

[0072] In some instances, the maintenance operation is performed based at least in part on an activity level of the memory system and a duration since a previous maintenance operation that has been executed for a threshold duration. In some instances, the first write cursor is a single-level cell (SLC) cursor, and the second write cursor is a triple-level cell (TLC) cursor. In some instances, each region includes corresponding data associated with a corresponding access frequency.

[0073] In some instances, the access component 445 may be configured to or otherwise support a component for initiating an access operation for data stored in one of the plurality of regions. In some instances, the access component 445 may be configured to or otherwise support a component for accessing a first address mapping table among one or more address mapping tables based at least in part on initiating the access operation, wherein after performing the maintenance operation, the first address mapping table is accessed based at least in part on each of the plurality of regions being sequential.

[0074] In some instances, the first address mapping table is associated with a first granularity corresponding to the plurality of regions, and a second address mapping table among the one or more address mapping tables is associated with a second granularity corresponding to a plurality of addresses associated with the memory system.

[0075] In some instances, each region is associated with a corresponding temperature classification. In some instances, each temperature classification corresponds to an access frequency of a corresponding region.

[0076] In some instances, the described functionality of the memory system 420 or its various components may be supported by at least a portion of at least one processor, or may refer to at least a portion of at least one processor, where the at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more such elements). In some instances, the described functionality of the memory system 420 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) executable by the at least one processor.

[0077] Figure 5 FIG. 500 is a flow diagram illustrating a method 500 for supporting region writes and maintenance in a memory system according to an example as disclosed herein. Operations of method 500 may be implemented by a memory system or its components as described herein. For example, operations of method 500 may be performed by a memory system as described with reference to Figures 1 to 4 the described memory system. In some instances, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0078] At 505, the method may include writing first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of the memory system using a first write cursor. In some instances, aspects of operation 505 may be performed by a write component 425 as described with reference to Figure 4 the described write component.

[0079] At 510, the method may include writing second data associated with one or more second regions of a plurality of regions to the plurality of virtual blocks using a second write cursor. In some instances, aspects of operation 510 may be performed by a write component 425 as described with reference to Figure 4 the described write component.

[0080] At 515, the method may include performing a maintenance operation based at least in part on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder a plurality of regions within the plurality of virtual blocks based at least in part on a respective access frequency associated with each region. In some instances, aspects of operation 515 may be performed by a maintenance component 430 as described with reference to Figure 4 the described maintenance component.

[0081] In some instances, a device as described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0082] Aspect 1: A method, device, or non-transitory computer-readable medium that includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: writing first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of a memory system using a first write cursor; writing second data associated with one or more second regions of the plurality of regions to the plurality of virtual blocks using a second write cursor; and performing a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder the plurality of regions within the plurality of virtual blocks at least in part based on a respective access frequency associated with each region.<000>

[0083] Aspect 2: The method, device, or non-transitory computer-readable medium according to aspect 1, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: determining that the one or more first regions are associated with a first access frequency, wherein writing the first data to the plurality of virtual blocks using the first write cursor is at least in part based on the one or more first regions being associated with the first access frequency.

[0084] Aspect 3: The method, device, or non-transitory computer-readable medium according to aspect 2, wherein the first access frequency is greater than an access frequency associated with the one or more second regions.

[0085] Aspect 4: The method, device, or non-transitory computer-readable medium according to any one of aspects 1 to 3, wherein writing the plurality of regions to the plurality of virtual blocks includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: writing the first data with a first granularity associated with single-level cells at least in part based on using the first write cursor; and writing the second data with a second granularity associated with multi-level cells at least in part based on using the second write cursor.

[0086] Aspect 5: The method, device, or non-transitory computer-readable medium according to aspect 4, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: folding the first data from the first granularity to the second granularity at least in part based on performing the maintenance operation.

[0087] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, wherein performing the maintenance operation includes operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: erasing one or more of the plurality of virtual blocks at least in part based on the one or more virtual blocks including one or more regions associated with invalid data.

[0088] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein performing the maintenance operation includes operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: recording an indication that one or more regions are invalid at least in part based on the one or more regions being associated with invalid data.

[0089] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: enabling a performance write mode of the memory system; and writing third data associated with a third region of the plurality of regions to the plurality of virtual blocks at least in part based on enabling the performance write mode using a third write cursor.

[0090] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, wherein the maintenance operation is performed at least in part based on an activity level of the memory system and a duration since a previous maintenance operation that has been performed for a threshold duration.

[0091] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, wherein the first write cursor is a single-level cell (SLC) cursor and the second write cursor is a triple-level cell (TLC) cursor.

[0092] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 10, wherein each region includes corresponding data associated with a corresponding access frequency.

[0093] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 11, further comprising operations, features, circuitry, logic, components, or instructions for the following, or any combination thereof: initiating an access operation for data stored in one of the plurality of regions; and accessing a first address mapping table in one or more address mapping tables at least in part based on initiating the access operation, wherein after performing the maintenance operation, the first address mapping table is accessed at least in part based on each of the plurality of regions being sequential.

[0094] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to aspect 12, wherein the first address mapping table is associated with a first granularity corresponding to the plurality of regions, and a second address mapping table in the one or more address mapping tables is associated with a second granularity corresponding to a plurality of addresses associated with the memory system.

[0095] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 13, wherein each region is associated with a corresponding temperature classification, and each temperature classification corresponds to an access frequency of the corresponding region.

[0096] Note that the described techniques include possible implementations, and the operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0097] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate the signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0098] The terms “electrically connected,” “electrically contacting,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electrically connected (or in electrical contact or connected or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are electrically connected (or in electrical contact or connected or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components may be interrupted, for example, using one or more intermediate components (such as switches or transistors) at a point in time.

[0099] The term "couple" (e.g., "electrically couple") can refer to a condition that changes from an open-circuit relationship between components (where a signal cannot currently be communicated between components through a conductive path) to a closed-circuit relationship between components (where a signal can be communicated between components through a conductive path). If a component (e.g., a controller) couples other components together, then the component initiates a change that allows a signal to flow between the other components through a conductive path that previously did not permit signal flow.

[0100] The terms "if," "when," "based on," or "at least partially based on" can be used interchangeably. In some instances, the terms can be interchangeable if they are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0101] The term "responsive to" can refer to a condition or action that occurs at least in part (if not entirely) as a result of a previous condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least in part as a result of the previous condition or action occurring (whether after one or more other intermediate conditions or actions that occur immediately after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0102] The devices (including memory arrays) discussed herein can be formed on a semiconductor substrate (such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). The doping can be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0103] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material such as metal. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “on” or “activated”. If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “off” or “deactivated”.

[0104] The descriptions set forth herein describe example configurations in conjunction with the drawings and do not represent all examples that may be implemented or that are within the scope of the claims. The term “exemplary” as used herein means “serving as an example, instance, or illustration” and not “preferred” or “better than other examples”. The detailed description includes specific details to provide an understanding of the described technology. However, the technology may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0105] In the figures, similar components or features may have the same reference labels. Additionally, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that differentiates the similar components. When only the first reference label is used in the specification, the description may apply to any one of the similar components having the same first reference label, regardless of the second reference label.

[0106] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software, hardware, firmware, hardwiring, or any combination thereof. The features implementing the functions may be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0107] The illustrative blocks and modules described herein may be implemented or performed with one or more processors, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof, designed to perform the functions described herein. The processor may be an instance of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0108] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items that begins with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C, for example, represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0109] As used herein (including in the claims), the article "a" before a noun is open-ended and is understood to refer to "at least one of" the noun or "one or more of" the noun. Thus, the terms "a", "at least one", "one or more", "at least one of one or more" may be used interchangeably. For example, if a claim recites a "component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Thus, the term "component" having a characteristic or performing a function may refer to "at least one of one or more components" having the particular characteristic or performing the particular function. A reference to a component introduced subsequently using the terms "the" or "said" together with the article "a" may refer to any one or all of one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and a reference to the "component" subsequently in the claim may be understood to be equivalent to a reference to "at least one of one or more components". Similarly, a reference to a component introduced subsequently using the terms "the" or "said" together with "one or more components" may refer to any one or all of one or more components. For example, a reference to "one or more components" subsequently in the claim may be understood to be equivalent to a reference to "at least one of one or more components".

[0110] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium, the communication medium including any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, the non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0111] The description provided herein enables a person of ordinary skill in the art to make or use the present disclosure. Those of ordinary skill in the art will understand that various modifications to the present disclosure can be made, and that the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: one or more memory devices; and a processing circuitry coupled to the one or more memory devices and configured to cause the memory system to: write first data associated with one or more first regions among a plurality of regions to a plurality of virtual blocks of the memory system using a first write cursor; write second data associated with one or more second regions among the plurality of regions to the plurality of virtual blocks using a second write cursor; and perform a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder the plurality of regions within the plurality of virtual blocks at least in part based on a respective access frequency associated with each region.

2. The memory system according to claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine that the one or more first regions are associated with a first access frequency, wherein writing the first data to the plurality of virtual blocks using the first write cursor is at least in part based on the one or more first regions being associated with the first access frequency.

3. The memory system according to claim 2, wherein the first access frequency is greater than an access frequency associated with the one or more second regions.

4. The memory system according to claim 1, wherein writing the plurality of regions to the plurality of virtual blocks includes the processing circuitry being configured to cause the memory system to: write the first data with a first granularity associated with single-level cells at least in part based on using the first write cursor; and write the second data with a second granularity associated with multi-level cells at least in part based on using the second write cursor.

5. The memory system according to claim 4, wherein the processing circuitry is further configured to cause the memory system to: fold the first data from the first granularity to the second granularity at least in part based on performing the maintenance operation.

6. The memory system according to claim 1, wherein performing the maintenance operation includes the processing circuitry being configured to cause the memory system to: erase one or more of the plurality of virtual blocks at least in part based on the one or more virtual blocks including one or more regions associated with invalid data.

7. The memory system according to claim 1, wherein performing the maintenance operation includes the processing circuitry being configured to cause the memory system to: record an indication that the one or more regions are invalid at least in part based on the one or more regions among the plurality of regions being associated with invalid data.

8. The memory system according to claim 1, wherein the processing circuitry is further configured to cause the memory system to: enable a performance write mode of the memory system; and write third data associated with a third region among the plurality of regions to the plurality of virtual blocks using a third write cursor at least in part based on enabling the performance write mode.

9. The memory system according to claim 1, wherein the maintenance operation is performed at least in part based on an activity level of the memory system and a duration since a previous maintenance operation that has been self-executed for a threshold duration.

10. The memory system according to claim 1, wherein the first write cursor is a single-level cell (SLC) cursor and the second write cursor is a triple-level cell (TLC) cursor.

11. The memory system according to claim 1, wherein each region includes corresponding data associated with a corresponding access frequency.

12. The memory system according to claim 1, wherein the processing circuitry is further configured to cause the memory system to: initiate an access operation to data stored in one of the plurality of regions; and access a first address mapping table in one or more address mapping tables at least in part based on initiating the access operation, wherein after performing the maintenance operation, the first address mapping table is accessed at least in part based on each of the plurality of regions being sequential.

13. The memory system according to claim 12, wherein the first address mapping table is associated with a first granularity corresponding to the plurality of regions, and a second address mapping table in the one or more address mapping tables is associated with a second granularity corresponding to a plurality of addresses associated with the memory system.

14. The memory system according to claim 1, wherein: each region is associated with a corresponding temperature classification, and each temperature classification corresponds to an access frequency of the corresponding region.

15. A non-transitory computer-readable medium storing code, the code including instructions executable by one or more processors to: write first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of a memory system using a first write cursor; write second data associated with one or more second regions of the plurality of regions to the plurality of virtual blocks using a second write cursor; and perform a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder the plurality of regions within the plurality of virtual blocks at least in part based on corresponding access frequencies associated with each region.

16. The non-transitory computer-readable medium according to claim 15, wherein the instructions are further executable by the one or more processors to: determine that the one or more first regions are associated with a first access frequency, wherein writing the first data to the plurality of virtual blocks using the first write cursor is at least in part based on the one or more first regions being associated with the first access frequency.

17. The non-transitory computer-readable medium according to claim 16, wherein the first access frequency is greater than an access frequency associated with the one or more second regions.

18. The non-transitory computer-readable medium according to claim 15, wherein the instructions to write the plurality of regions to the plurality of virtual blocks are executable by the one or more processors to: Writing the first data with a first granularity associated with single-level cells, at least in part based on using the first write cursor; and Writing the second data with a second granularity associated with multi-level cells, at least in part based on using the second write cursor.

19. The non-transitory computer-readable medium of claim 18, wherein the instructions are further executable by the one or more processors to: Fold the first data from the first granularity to the second granularity, at least in part based on performing the maintenance operation.

20. The non-transitory computer-readable medium of claim 15, wherein the instructions for performing the maintenance operation are executable by the one or more processors to: Erase one or more of the plurality of virtual blocks, at least in part based on one or more of the plurality of virtual blocks including one or more regions associated with invalid data.

21. The non-transitory computer-readable medium of claim 15, wherein the instructions for performing the maintenance operation are further executable by the one or more processors to: Record an indication that one or more of the regions are invalid, at least in part based on one or more of the plurality of regions being associated with invalid data.

22. The non-transitory computer-readable medium of claim 15, wherein the instructions are further executable by the one or more processors to: Enable a performance write mode of the memory system; and Write third data associated with a third region of the plurality of regions to the plurality of virtual blocks, at least in part based on enabling the performance write mode, using a third write cursor.

23. The non-transitory computer-readable medium of claim 15, wherein the maintenance operation is performed at least in part based on an activity level of the memory system and a duration since a previous maintenance operation that has been executed for a threshold duration.

24. The non-transitory computer-readable medium of claim 15, wherein the first write cursor is a single-level cell (SLC) cursor and the second write cursor is a triple-level cell (TLC) cursor.

25. A method performed by a memory system, comprising: Writing first data associated with one or more first regions of a plurality of regions to a plurality of virtual blocks of the memory system, using a first write cursor; Writing second data associated with one or more second regions of the plurality of regions to the plurality of virtual blocks, using a second write cursor; and Performing a maintenance operation at least in part based on writing the first data using the first write cursor and writing the second data using the second write cursor to reorder the plurality of regions within the plurality of virtual blocks, at least in part based on a respective access frequency associated with each region.

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