Storage control circuit, chip, electronic equipment and data processing method

Abstract

The invention relates to the technical field of integrated circuits, in particular to a storage control circuit, a chip, electronic equipment and a data processing method, a first storage control unit is used for controlling a first storage unit, and a second storage control unit is used for controlling a second storage unit; the first bus interface unit is in communication connection with the first storage control unit, and the first operation instruction is sent to the first storage control unit through the first bus interface unit; the second bus interface unit is in communication connection with the first storage control unit and the second storage control unit, and the second operation instruction is sent to the first storage control unit or the second storage control unit through the second bus interface unit; through the mode, the first bus interface unit is configured by the first operation of the first storage control unit, and the second bus interface unit is shared by the second operation of the first storage control unit and the second operation of the second storage control unit, so that the bus resource consumption is favorably reduced, and the circuit area is favorably reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular, to a storage control circuit, a chip, an electronic device, and a data processing method. Background Art

[0002] For example, a firmware program such as a startup program is stored in a read-only memory (ROM) inside the chip. This firmware program needs to be solidified in the chip before chip fabrication, and it cannot be changed after chip fabrication; an application program is stored in a non-volatile memory (NVM) inside the chip, and this application program can be changed after chip fabrication.

[0003] Currently, the read-only memory and the non-volatile memory are respectively provided with corresponding bus interface structures separately, which is not conducive to reducing bus resource consumption and is not conducive to reducing the circuit area. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a storage control circuit, a chip, an electronic device, and a data processing method to solve the above technical problems that are not conducive to reducing bus resource consumption and are not conducive to reducing the circuit area.

[0005] In a first aspect, an embodiment of this application provides a storage control circuit, including:

[0006] A first storage control unit for controlling a first storage unit;

[0007] A second storage control unit for controlling a second storage unit;

[0008] A first bus interface unit communicatively connected to the first storage control unit for sending a first operation instruction to the first storage control unit;

[0009] A second bus interface unit communicatively connected to the first storage control unit and the second storage control unit respectively for sending a second operation instruction to the first storage control unit or the second storage control unit.

[0010] In a second aspect, an embodiment of this application provides a chip, and the chip includes the above storage control circuit.

[0011] In a third aspect, an embodiment of this application provides an electronic device, and the electronic device includes the above chip.

[0012] In a fourth aspect, an embodiment of this application provides a data processing method applied to the above chip, and the data processing method includes:

[0013] When a first operation instruction is received, send the first operation instruction to the first storage control unit;

[0014] When a second operation instruction is received, send the second operation instruction to the first storage control unit or the second storage control unit.

[0015] In the storage control circuit, chip, electronic device, and data processing method provided by the embodiments of the present application, the first storage control unit is used to control the first storage unit, and the second storage control unit is used to control the second storage unit; the first bus interface unit is communicatively connected to the first storage control unit, and the first operation instruction is sent to the first storage control unit through the first bus interface unit; the second bus interface unit is communicatively connected to the first storage control unit and the second storage control unit respectively, and the second operation instruction is sent to the first storage control unit or the second storage control unit through the second bus interface unit; in the above manner, the first operation of the first storage control unit configures the first bus interface unit, and the second operation of the first storage control unit and the second operation of the second storage control unit share a second bus interface unit, which is beneficial to reducing the consumption of bus resources and reducing the circuit area.

[0016] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. Description of the Drawings

[0017] Figure 1 Shows a schematic structural diagram of the storage control circuit provided by the embodiments of the present application.

[0018] Figure 2 Shows a schematic structural diagram of the switch circuit in the storage control circuit provided by the embodiments of the present application.

[0019] Figure 3 Shows an application scenario diagram of the storage control circuit provided by the embodiments of the present application.

[0020] Figure 4 Shows a schematic structural diagram of the chip provided by the embodiments of the present application.

[0021] Figure 5 Shows a schematic structural diagram of the electronic device provided by the embodiments of the present application.

[0022] Figure 6 Shows a schematic flowchart of the data processing method provided by the embodiments of the present application. Detailed Embodiments

[0023] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0024] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present application.

[0025] In the embodiments of the present application, it should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0026] Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0027] In the description of the embodiments of the present application, words such as "example" or "for example" are used to represent examples, explanations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0028] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B and C, then what is included can be A, B, C, A and B, A and C, B and C, or A, B and C.

[0029] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0030] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0031] An embodiment of the present application provides a storage control circuit 100. Figure 1 As shown, the storage control circuit 100 of this embodiment includes: a first storage control unit 11 , a second storage control unit 12 , a first bus interface unit 21 and a second bus interface unit 22 .

[0032] The first storage control unit 11 is used to control the first storage unit 32 , and the second storage control unit 12 is used to control the second storage unit 32 .

[0033] In an optional embodiment, the first storage unit 31 can be a non-volatile storage unit, which is used to store firmware programs, for example, the firmware program can include at least one application; the second storage unit 32 can be a read-only storage unit, which is used to store firmware programs, for example, the firmware program can include a startup program (Startup Software, SSW) and / or security authentication related programs.

[0034] The first bus interface unit 21 is in communication with the first storage control unit 11 , and is configured to send the first operation instruction to the first storage control unit 11 .

[0035] The second bus interface unit 22 is communicatively connected to the first storage control unit 11 and the second storage control unit 12 respectively, and is used to send the second operation instruction to the first storage control unit 11 or the second storage control unit 12 .

[0036] The first operation instruction is used to perform a first operation on the first storage unit 31, and the second operation instruction is used to perform a second operation on the first storage unit 31 or the second storage unit 32. For example, the first operation may be an operation involving data modification, for example, the first operation may include a programming (data writing) operation and / or an erasing operation; the second operation may be an operation not involving data modification, for example, the second operation may include a data reading operation.

[0037] Exemplarily, the startup program stored in the second storage unit 32 can be used to boot the firmware program stored in the first storage unit 31 when the chip is powered on or reset. In this application scenario, first, the startup program is read from the second storage unit 32 through the second bus interface unit 22; subsequently, after the startup program is executed, the fixed program is read from the first storage unit 31 through the second bus interface unit 22.

[0038] Exemplarily, the program related to security authentication stored in the second storage unit 32 can be used to perform security authentication on user operations when the user starts the first firmware program stored in the first storage unit 31. In this application scenario, first, the fixed program is read from the first storage unit 31 through the second bus interface unit 22; subsequently, the program related to security authentication is read from the second storage unit 32 through the second bus interface unit 22; subsequently, after the program related to security authentication is executed, the fixed program is continuously read from the first storage unit 31 through the second bus interface unit 22.

[0039] In this embodiment, the first operation of the first storage control unit configures the first bus interface unit, and the second operation of the first storage control unit and the second operation of the second storage control unit share a second bus interface unit. Only two bus interface units are configured for the two storage control units, which is beneficial to reducing the consumption of bus resources and reducing the circuit area.

[0040] As an implementation manner, the second operation instruction may be a third instruction whose address information points to the first storage unit 31 or a fourth instruction whose address information points to the second storage unit 32; the second bus interface unit 22 is configured to send the third instruction to the first storage control unit 11 when the second operation instruction is the third instruction; and send the fourth instruction to the second storage control unit 12 when the second operation instruction is the fourth instruction.

[0041] In this implementation manner, since the first storage control unit and the second storage control unit share a second bus interface unit, the address information of the second operation instruction represents whether it points to the first storage unit or the second storage unit.

[0042] In some implementation manners, the addresses of the first storage unit 31 and the second storage unit 32 are consecutive.

[0043] Specifically, the virtual addresses of the first storage unit 31 and the second storage unit 32 are consecutive, that is, the end address of the second storage unit 32 is consecutive with the start address of the first storage unit 31, or the end address of the first storage unit 31 is consecutive with the start address of the second storage unit 32. The address information included in the first operation instruction or the address information included in the second operation instruction may be a virtual address, and the address used when executing a program may be a virtual address. The physical address is the access address of the real physical storage space. The physical address of the first storage unit 31 can be mapped to a virtual address and the physical address of the second storage unit 32 can be mapped to a virtual address through Memory-Map (memory mapping). An address mapping table for recording the mapping relationship between the physical address and the virtual address may be stored, for example.

[0044] Exemplarily, the virtual address of the second storage unit 32 is 0FFF_C000 to 0FFF_FFFF, its start address is 0FFF_C000, its end address is 0FFF_FFFF, and the size of its storage space is 16 KB; the virtual address of the first storage unit 31 is 1000_0000 to 103F_FFFF, its start address is 1000_0000, its end address is 103F_FFFF, and the size of its storage space is 4 KB. The end address of the second storage unit 32 is consecutive with the start address of the first storage unit 31.

[0045] In some embodiments, as shown in Figure 2 the storage control circuit 100 further includes a third bus interface unit 23. The third bus interface unit 23 is respectively connected to the first bus interface unit 21 and the second bus interface unit 22. The third bus interface unit 23 is configured to receive first operation data sent by an external electronic device and send a first operation instruction corresponding to the first operation data to the first bus interface unit 21. The third bus interface unit 23 is configured to receive second operation data sent by the external electronic device and send a second operation instruction corresponding to the second operation data to the second bus interface unit 22.

[0046] The third bus interface unit 23 is connected to an external electronic device. The external electronic device may be, for example, an electronic device or a processor of an electronic device. For example, the external electronic device may be a central processing unit (CPU) of a laptop computer, and the external electronic device may also be a peripheral device of a laptop computer such as a mouse or a keyboard.

[0047] Exemplarily, the third bus interface unit 23 may include a NIC (Network Interface Card) interface.

[0048] In some embodiments, an external electronic device sends operation data to the third bus interface unit 23. The third bus interface unit 23 analyzes the operation data, and is configured to determine whether the operation data is first operation data or second operation data according to the content information of the operation data.

[0049] Among them, the first operation instruction may be the same as the first operation data. The third bus interface unit 23 receives the first operation data, analyzes the first operation data, and determines that it is related to the first operation according to its content information. It can directly output the first operation data as the first operation instruction to the first bus interface unit 21.

[0050] Among them, the first operation instruction may be different from the first operation data. The third bus interface unit 23 receives the first operation data, analyzes the first operation data, and determines that it is related to the first operation according to its content information. A corresponding first operation instruction is generated according to the first operation data, and the first operation instruction is output to the first bus interface unit 21.

[0051] Among them, the second operation instruction may be the same as the second operation data. The third bus interface unit 23 receives the second operation data, analyzes the second operation data, and determines that it is related to the second operation according to its content information. It can directly output the second operation data as the second operation instruction to the second bus interface unit 22.

[0052] Among them, the second operation instruction may be different from the first operation data. The third bus interface unit 23 receives the second operation data, analyzes the second operation data, and determines that it is related to the second operation according to its content information. A corresponding second operation instruction is generated according to the second operation data, and the first operation instruction is output to the second bus interface unit 22.

[0053] In this embodiment, the operation data is analyzed by the third bus interface unit, and then the operation instruction corresponding to the operation data is sent to the first bus interface unit or the second bus interface unit according to the analysis result.

[0054] In some embodiments, in addition to analyzing the content information of the operation instruction, the third bus interface unit 23 also analyzes the address information of the operation instruction to determine the target object pointed to by the operation instruction; if the address information of the operation instruction points to the virtual address of the first storage unit 31, the target object pointed to is the first storage unit 31; if the address information of the operation instruction points to the virtual address of the second storage unit 32, the target object pointed to is the second storage unit 32.

[0055] In some embodiments, the third bus interface unit 23 is configured to determine that the target object pointed to by the operation instruction is the first storage unit 31 or the second storage unit 32 according to the address information of the operation instruction when the operation instruction is the second operation instruction.

[0056] Exemplarily, when the addresses of the first storage unit and the second storage unit are consecutive, the difficulty of the third bus interface unit in parsing the address information can be reduced.

[0057] Exemplarily, the address information in the operation instruction can be consecutive addresses, or the address information in the operation instruction can be discrete addresses. Specifically, when the address information is discrete addresses, the discrete address information may include a reference address and a plurality of discrete offsets. The reference address can be specified by a scalar, and the discrete offset can be specified by a vector. Adding the reference address and each discrete offset respectively can obtain a plurality of access addresses, and the plurality of access addresses are discrete and without any pattern.

[0058] In some embodiments, please continue to refer to Figure 2 As shown, the storage control circuit 100 further includes a first register 40. The first register 40 is connected to the first bus interface unit 21, and the first register 40 is respectively connected to the first storage control unit 11 and the second storage control unit 12. The first register 40 is configured to store the configuration data of the first storage unit 31 or the configuration data of the second storage unit 32.

[0059] Wherein, the third bus interface unit 23 receives operation data, which includes an operation instruction and the operation configuration data of the operation instruction. While analyzing the operation instruction, the third bus interface unit 23 also parses the operation configuration data of the operation instruction, and sends the operation configuration data of the operation instruction to the first register 40 for storage through the first bus interface unit 21.

[0060] Exemplarily, if the second operation is a read operation, when the address information of the second operation instruction points to the first storage unit 31, at this time, configure the state of the first storage unit 31 as read enabled, and configure the state of the second storage unit 32 as read protected to shield the return of the read data of the second storage unit 32; when the address information of the second operation instruction points to the second storage unit 32, at this time, configure the state of the second storage unit 32 as read enabled, and configure the state of the first storage unit 31 as read protected to shield the return of the read data of the first storage unit 31.

[0061] In this embodiment, the first operation of the first register and the first storage unit share a first bus interface unit, which is beneficial to further reducing the consumption of bus resources and further reducing the circuit area. Moreover, after the first operation instruction is sent to the first storage control unit, it will not affect the access to the first register.

[0062] In some embodiments, the first register 40 includes a first storage area, a second storage area, and a third storage area. The first storage area is used to store the configuration data of the second operation instruction of the first storage unit 31. The second storage area is used to store the configuration data of the second operation instruction of the second storage unit 32. The third storage area is used to store the configuration data of the first operation instruction pointing to the first storage unit 31.

[0063] In some embodiments, the virtual addresses of the first storage area and the second storage area are consecutive, and the virtual addresses of the second storage area and the third storage area are consecutive. Exemplarily, the virtual address of the first storage area is from 0xC110_0000 to 0xC110_3FFF, its starting address is 0xC110_0000, its ending address is 0xC110_3FFF, and the size of its storage space is 16KB. The virtual address of the second storage area is from 0xC110_4000 to 0xC110_7FFF, its starting address is 0xC110_4000, its ending address is 0xC110_7FFF, and the size of its storage space is 16KB. The virtual address of the third storage area is from 0xC110_8000 to 0xC110_FFFF, its starting address is 0xC110_8000, its ending address is 0xC110_FFFF, and the size of its storage space is 32KB.

[0064] As an embodiment, the first storage control unit 11 and the second bus interface unit 22 are connected by a first bus, and the second storage control unit 12 and the second bus interface unit 22 are connected by a first bus. The first bus includes a first data channel for transmitting the second operation instruction and a second data channel for transmitting the data pointed to by the second operation instruction. The transmission direction of the first data channel is from the second bus interface unit 22 to the first storage control unit 11 or the second storage control unit 12. The transmission direction of the second data channel is from the first storage control unit 11 or the second storage control unit 12 to the second bus interface unit 22.

[0065] In this embodiment, the first bus adapted to the second bus interface unit has two data channels with opposite transmission directions, and the sending of the second operation instruction and the return of the data pointed to by the second operation instruction can be parallel, which is beneficial to increasing the data processing efficiency.

[0066] Exemplarily, the second bus interface unit 22 may include an AXIS (Advanced eXtensible Interface Stream) bus interface. The first data channel is a read address channel, and the second data channel is a read data channel.

[0067] As an implementation, the first storage control unit 11 and the first bus interface unit 21 are connected by a second bus, and the second bus includes a third data channel for transmitting the first operation instruction.

[0068] Among them, the transmission direction of the third data channel is from the first bus interface unit 21 to the first storage control unit 11.

[0069] In this implementation, the second bus adapted to the first bus interface unit has a third data channel for writing data, which can adapt to operations (the first operation) involving data changes, further facilitating reducing bus resource consumption and reducing the circuit area while ensuring data processing efficiency.

[0070] Exemplarily, the first bus interface unit 21 may include an AHB (Advanced High-performance Bus) bus interface.

[0071] In some implementations, the first register 40 and the first bus interface unit 21 are connected by a second bus, and the second bus includes a third data channel for transmitting operation configuration data of the operation instruction.

[0072] Exemplarily, the first storage unit 31 may include a flash memory (Flash), and the second storage unit 32 may include a read-only memory (ROM). For example, the second storage unit 32 may include a boot read-only memory (BootROM).

[0073] The storage control circuit 100 provided by this application may be applied to Figure 3 the laptop computer 200 shown in the figure. The laptop computer 200 includes a central processing unit 201. The storage control circuit 100 is connected to the central processing unit 201, and the storage control circuit is used to process the operation instructions sent by the central processing unit 201.

[0074] An embodiment of this application provides a chip 300. Please refer to Figure 4As shown, the chip 300 includes the above-mentioned storage control circuit 100. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a SOC (System on Chip) chip, a SIP (system in package) chip.

[0075] For the chip of this embodiment, the first operation of the first storage control unit configures the first bus interface unit, and the second operation of the first storage control unit and the second operation of the second storage control unit share a second bus interface unit. Only two bus interface units are configured for the two storage control units, which is beneficial to reducing the consumption of bus resources and reducing the circuit area.

[0076] An embodiment of the present application further provides an electronic device 400. Please refer to Figure 5 As shown, the electronic device 400 includes a device body and the chip 300 as described above disposed within the device body. The electronic device can be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, a pulse oximeter, a body composition analyzer, a display, a USB (Universal Serial Bus) docking station, a vehicle, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop computer, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart light.

[0077] For the electronic device of this embodiment, the first operation of the first storage control unit configures the first bus interface unit, and the second operation of the first storage control unit and the second operation of the second storage control unit share a second bus interface unit. Only two bus interface units are configured for the two storage control units, which is beneficial to reducing the consumption of bus resources and reducing the circuit area.

[0078] An embodiment of the present application provides a data processing method, which is applied to the above-mentioned chip 300. Please refer to Figure 6 As shown, the data processing method includes the following steps S11 to S13:

[0079] Step S11: When a first operation instruction is received, send the first operation instruction to the first storage control unit;

[0080] Step S12: When the second operation instruction is received, send the second operation instruction to the first storage control unit or the second storage control unit. In this embodiment, the first operation of the first storage control unit configures the first bus interface unit, and the second operation of the first storage control unit and the second operation of the second storage control unit share a second bus interface unit. Only two bus interface units are configured for the two storage control units, which helps reduce the consumption of bus resources and the circuit area.

[0081] As an implementation manner, the second operation instruction is the third instruction whose address information points to the first storage unit or the fourth instruction whose address information points to the second storage unit.

[0082] In step S12, the step of sending the second operation instruction to the first storage control unit or the second storage control unit specifically includes:

[0083] Step S121: When the second operation instruction is the third instruction, send the third instruction to the first storage control unit;

[0084] Step S122: When the second operation instruction is the fourth instruction, send the fourth instruction to the second storage control unit.

[0085] As an implementation manner, in step S12, sending the second operation instruction to the first storage control unit includes: sending the second operation instruction to the first storage control unit through the first data channel of the first bus.

[0086] In step S13, sending the second operation instruction to the second storage control unit includes: sending the second operation instruction to the second storage control unit through the first data channel of the first bus.

[0087] Correspondingly, after sending the second operation instruction to the first storage control unit or the second storage control unit, it further includes:

[0088] The first storage control unit or the second storage control unit sends the data pointed to by the second operation instruction to the second bus interface unit through the second data channel of the first bus.

[0089] As an implementation manner, in step S11, sending the first operation instruction to the first storage control unit includes: sending the first operation instruction to the first storage control unit through the third data channel of the second bus.

[0090] As an implementation manner, before step S11, the data processing method further includes:

[0091] Step S101: Receive operation data, and determine whether the operation data is the first operation data or the second operation data according to the content information of the operation data;

[0092] Step S102: When the operation data is the second operation data, determine that the target object pointed to by the operation data is the first storage unit or the second storage unit according to the address information of the operation data;

[0093] Step S103: When the operation data is the first operation data, generate a first operation instruction according to the first operation data; when the operation data is the second operation data, generate a second operation instruction according to the second operation data.

[0094] The above are only the implementation manners of the present application. It should be noted here that for those of ordinary skill in the art, without departing from the creative concept of the present application, improvements can still be made, but these all belong to the protection scope of the present application.

Claims

1. A storage control circuit, characterized in that, Including: A first storage control unit for controlling a first storage unit; A second storage control unit for controlling a second storage unit; A first bus interface unit communicatively connected to the first storage control unit for sending a first operation instruction to the first storage control unit; A second bus interface unit communicatively connected to the first storage control unit and the second storage control unit respectively for sending a second operation instruction to the first storage control unit or the second storage control unit.

2. The storage control circuit according to claim 1, wherein The second operation instruction is a third instruction with an address information pointing to the first storage unit or a fourth instruction with an address information pointing to the second storage unit; The second bus interface unit is configured to send the third instruction to the first storage control unit when the second operation instruction is the third instruction; and send the fourth instruction to the second storage control unit when the second operation instruction is the fourth instruction.

3. The storage control circuit according to claim 2, wherein The addresses of the first storage unit and the second storage unit are consecutive.

4. The storage control circuit according to claim 2, wherein The storage control circuit further includes a third bus interface unit respectively connected to the first bus interface unit and the second bus interface unit. The third bus interface unit is configured to receive first operation data sent by an external electronic device and send the first operation instruction corresponding to the first operation data to the first bus interface unit; Receive the second operation data sent by the external electronic device and send the second operation instruction corresponding to the second operation data to the second bus interface unit.

5. The storage control circuit according to claim 4, characterized in that The third bus interface unit is configured to determine whether the operation instruction is the first operation instruction or the second operation instruction according to the content information of the operation instruction.

6. The storage control circuit according to claim 4, wherein The third bus interface unit is configured to determine whether the target object pointed to by the operation instruction is the first storage unit or the second storage unit according to the address information of the operation instruction when the operation instruction is the second operation instruction.

7. The storage control circuit according to claim 1, characterized in that, The storage control circuit further includes a first register connected to the first bus interface unit. The first register is respectively connected to the first storage control unit and the second storage control unit. The first register is configured to store the configuration data of the first storage unit or the configuration data of the second storage unit.

8. The storage control circuit according to claim 7, wherein The first register includes a first storage area, a second storage area and a third storage area. The first storage area is configured to store the configuration data of the second operation instruction of the first storage unit. The second storage area is configured to store the configuration data of the second operation instruction of the second storage unit. The third storage area is configured to store the configuration data of the first operation instruction pointing to the first storage unit.

9. The storage control circuit according to claim 1, wherein The first storage control unit and the second bus interface unit, and the second storage control unit and the second bus interface unit are respectively connected by a first bus. The first bus includes a first data channel for transmitting the second operation instruction and a second data channel for transmitting the data pointed to by the second operation instruction.

10. The storage control circuit according to claim 1, wherein The first storage control unit and the first bus interface unit are connected by a second bus, and the second bus includes a third data channel for transmitting the first operation instruction.

11. A chip, characterized in that, The chip includes the storage control circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that, The electronic device includes the chip according to claim 11.

13. A data processing method, characterized in that Applied to the chip according to claim 11, the data processing method includes: When a first operation instruction is received, sending the first operation instruction to the first storage control unit; When a second operation instruction is received, sending the second operation instruction to the first storage control unit or the second storage control unit.

14. The data processing method according to claim 13, wherein The second operation instruction is a third instruction whose address information points to the first storage unit or a fourth instruction whose address information points to the second storage unit; Sending the second operation instruction to the first storage control unit or the second storage control unit includes: When the second operation instruction is the third instruction, sending the third instruction to the first storage control unit; When the second operation instruction is the fourth instruction, sending the fourth instruction to the second storage control unit.

15. The data processing method according to claim 13, wherein Sending the second operation instruction to the first storage control unit or the second storage control unit includes: Sending the second operation instruction to the first storage control unit or the second storage control unit through a first data channel of the first bus; Correspondingly, after sending the second operation instruction to the first storage control unit or the second storage control unit, it further includes: The first storage control unit or the second storage control unit sends the data pointed to by the second operation instruction to the second bus interface unit through a second data channel of the first bus.

16. The data processing method according to claim 13, characterized in that, Sending the first operation instruction to the first storage control unit includes: Sending the first operation instruction to the first storage control unit through a third data channel of the second bus.

17. The data processing method according to claim 13, wherein The data processing method further includes: Receiving operation data, and determining whether the operation data is the first operation data or the second operation data according to the content information of the operation data; When the operation data is the second operation data, determining that the target object pointed to by the operation data is the first storage unit or the second storage unit according to the address information of the operation data; When the operation data is the first operation data, generating the first operation instruction according to the first operation data; When the operation data is the second operation data, generating the second operation instruction according to the second operation data.

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