Multi-core access memory management system

Abstract

The invention discloses a multi-core access memory management system, and belongs to the technical field of data security. Comprising a memory access management module, and the memory access management module is connected with a security configuration register module, a plurality of memory blocks and a plurality of CPU cores; and the memory access management module is used for performing access management and mapping on the memory access space, so that the target CPU core can access the target memory block only in a preset mode. A memory access management module is added between cache blocks on an SoC (System on Chip) accessed by a CPU (Central Processing Unit), and management and mapping of different memory access spaces are realized through the memory access management module, so that access of different cores and access management of the same core on the on-chip cache in different modes are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of data security, and in particular to a multi-core access memory management system. Background Art

[0002] In traditional embedded SoC chips, the way for the CPU to access the on-chip cache is to directly access according to the address mapping. Different CPU cores can access the same on-chip cache according to the SoC design. Thus, if a certain CPU core is attacked, the on-chip cache data will be leaked, posing a great security risk. RSIC-V CPUs optionally support the PMP (Physical Memory Protection) function, so that the on-chip cache of the SoC can be divided into multiple blocks as needed, and each block can be protected by PMP. The memory protected by PMP can only be accessed by the CPU core in machine mode and cannot be accessed in other modes of the CPU core, thus playing a role in protecting the memory access. However, the current PMP technology can only implement memory access control for different modes of the same CPU core. Even if PMP protection is set, it still cannot prevent other CPU cores from accessing this memory, which makes the PMP technology have a large security vulnerability for malicious memory access by other CPU cores. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a multi-core access memory management system.

[0004] The purpose of the present invention is achieved through the following technical solutions: A multi-core access memory management system includes a memory access management module, and the memory access management module is connected to a security configuration register module, multiple memory blocks, and multiple CPU cores; the memory access management module is used to manage and map the memory access space to enable the target CPU core to access the target memory block only in a preset mode.

[0005] Preferably, the memory access management module includes multiple first memory management circuits and / or second memory management circuits, and each CPU core is connected to a first memory management circuit or a second memory management circuit.

[0006] Preferably, the first memory management circuit includes a first comparator, a second comparator, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first OR gate, and a first inverter; a first terminal of the first comparator is connected to a front-end input, a second terminal of the first comparator is connected to the front-end input and a first terminal of the second comparator, and an output terminal of the first comparator is connected to a first terminal of the first AND gate; a second terminal of the second comparator is connected to the front-end input, and an output terminal of the second comparator is connected to a second terminal of the first AND gate; an output terminal of the first AND gate is connected to a first terminal of the third AND gate; a first terminal of the second AND gate is connected to the front-end input and an input terminal of the first inverter, a second terminal of the second AND gate is connected to the front-end input, and an output terminal of the second AND gate is connected to a second terminal of the third AND gate; an output terminal of the third AND gate is connected to a first terminal of the first OR gate; an output terminal of the first inverter is connected to a second terminal of the first OR gate; an output terminal of the first OR gate is connected to a first terminal of the fourth AND gate; a second terminal of the fourth AND gate is connected to the front-end input, and an output terminal of the fourth AND gate is connected to a back-end output.

[0007] Preferably, when the memory access management mode is enabled, the security firmware in the ROM is initialized and the memory start address strt_addr and the memory end address end_addr are configured to the first terminal of the first comparator and the second terminal of the second comparator to form an address space range; then the register signal pmp_init_done is configured to 1 and input to the first terminal of the second AND gate. At this time, the memory start address strt_addr and the memory end address end_addr cannot be changed; when the target CPU core is in a preset mode, the input signal core0_mch_mod at the second terminal of the second AND gate is at a high level. At this time, the address signal addr_in is input to the second terminal of the first comparator and the first terminal of the second comparator for comparison. If the address signal addr_in is within the address space range, both the first comparator and the second comparator output a high level; at this time, the output signal sram0_acc_en of the first OR gate is at a high level, allowing reading and writing of the target memory block; when the target CPU core is in a preset mode, if the address signal addr_in is not within the address space range, the output signal sram0_acc_en of the first OR gate is at a low level and the input signal core0_sram0_re at the second terminal of the fourth AND gate are ANDed to be at a low level, thereby preventing illegal access; when the target CPU core is not in the preset mode, the input signal core0_mch_mod at the second terminal of the second AND gate is at a low level and the register signal pmp_init_done are ANDed to be at a low level, so that the output signal sram0_acc_en of the first OR gate is at a low level. sram0_acc_en and the input signal core0_sram0_re at the second terminal of the fourth AND gate are ANDed to be at a low level, thereby preventing illegal access.

[0008] Preferably, the second memory management circuit includes a third comparator, a fourth comparator, a fifth AND gate, a sixth AND gate, a seventh AND gate, a second OR gate, and a second inverter; a first end of the third comparator is connected to a front-end input, a second end of the third comparator is connected to the front-end input and a first end of the fourth comparator, and an output end of the third comparator is connected to a first end of the fifth AND gate; a second end of the fourth comparator is connected to the front-end input, and an output end of the fourth comparator is connected to a second end of the fifth AND gate; an output end of the fifth AND gate is connected to a first end of the sixth AND gate; a second end of the sixth AND gate is connected to the front-end input, and an output end of the sixth AND gate is connected to a first end of the second OR gate; an input end of the second inverter is connected to the front-end input, and an output end of the second inverter is connected to a second end of the second OR gate; an output end of the second OR gate is connected to a first end of the seventh AND gate; a second end of the seventh AND gate is connected to the front-end input, and an output end of the seventh AND gate is connected to a back-end output.

[0009] Preferably, when the memory access management mode is enabled, the secure firmware in the ROM is initialized and the memory start address strt_addr and the memory end address end_addr are configured to the first end of the third comparator and the second end of the fourth comparator to form an address space range; then the register signal pmp_init_done is configured to 1 and input to the second end of the sixth AND gate and the input end of the second inverter. At this time, the memory start address strt_addr and the memory end address end_addr cannot be changed; at this time, the address signal addr_in is input to the second end of the third comparator and the first end of the fourth comparator for comparison. If the address signal addr_in is within the address space range, both the first comparator and the second comparator output a high level; at this time, the output signal sram1_acc_en of the second OR gate is a high level, allowing reading and writing of the target memory block; when the target CPU core is in the preset mode, if the address signal addr_in is not within the address space range, the output signal sram1_acc_en of the second OR gate is a low level and the input signal core1_sram1_re to the second end of the seventh AND gate is ANDed to a low level, thereby preventing illegal access.

[0010] The beneficial effects of the present invention are: 1) An additional memory access management module is added between the CPU accessing each cache block on the SoC chip. Through the memory access management module, the management and mapping of different memory access spaces are realized, so as to realize the access management of different cores and different modes of the same core to the on-chip cache.

[0011] 2) The comparison of the access address by the first memory management circuit of the memory access management module and the judgment in the machine mode of CPU core0 are implemented based on hardware circuits. Only CPU core0 can access this memory block in the machine mode, realizing the access protection of the memory block. Thus, based on the hardware circuit, other CPU cores cannot access the memory block, and CPU core0 cannot access the memory block in the non-machine mode, ensuring the control and security of memory access permissions.

[0012] 3) The comparison of the access address by the second memory management circuit of the memory access management module is implemented based on hardware circuits to achieve access protection for the memory block only within the address space range configured by this CPU core. Thus, based on the hardware circuit, other CPU cores cannot access the memory block, ensuring the control and security of memory access permissions. [[ID=??]]Description of the Drawings

[0013] Figure 1 It is a principle block diagram of a multi-core access memory management system; Figure 2 It is a schematic diagram of the first memory management circuit; Figure 3 It is a schematic diagram of the second memory management circuit. Specific Embodiments

[0014] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

[0015] Refer to Figures 1 - 3 , the present invention provides a technical solution: a multi-core access memory management system, including a memory access management module, the memory access management module is connected to a security configuration register module, multiple memory blocks and multiple CPU cores; the memory access management module is used to manage and map the memory access space, so that the target CPU core can only access the target memory block in a preset mode.

[0016] In this embodiment, as Figure 1 shown, a memory access management module is added between the CPU access to each cache block on the SoC chip. Through the memory access management module, the management and mapping of different memory access spaces are realized, so as to realize the access management of different cores and the same core in different modes to the on-chip cache.

[0017] It should be noted that there is an unclear "??" in the translation. It might be a mistake in the original text or an unclear tag. You can double-check and correct it if needed.In some embodiments, the memory access management module includes a plurality of first memory management circuits and / or second memory management circuits, and each CPU core is connected to a first memory management circuit or a second memory management circuit.

[0018] In this embodiment, since the CPU has multiple cores, the memory access management module also has a plurality of first memory management circuits and / or second memory management circuits.

[0019] In some embodiments, the first memory management circuit includes a first comparator, a second comparator, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first OR gate, and a first inverter; a first terminal of the first comparator is connected to a front-end input, a second terminal of the first comparator is connected to the front-end input and a first terminal of the second comparator, and an output terminal of the first comparator is connected to a first terminal of the first AND gate; a second terminal of the second comparator is connected to the front-end input, and an output terminal of the second comparator is connected to a second terminal of the first AND gate; an output terminal of the first AND gate is connected to a first terminal of the third AND gate; a first terminal of the second AND gate is connected to the front-end input and an input terminal of the first inverter, a second terminal of the second AND gate is connected to the front-end input, and an output terminal of the second AND gate is connected to a second terminal of the third AND gate; an output terminal of the third AND gate is connected to a first terminal of the first OR gate; an output terminal of the first inverter is connected to a second terminal of the first OR gate; an output terminal of the first OR gate is connected to a first terminal of the fourth AND gate; a second terminal of the fourth AND gate is connected to the front-end input, and an output terminal of the fourth AND gate is connected to a back-end output.

[0020] In this embodiment, as Figure 2 shown, the first memory management circuit manages the access to memory blocks in different modes of the same CPU core through two comparators, four two-input AND gates, one two-input OR gate, and one inverter, and only allows the CPU core to access this sram0 memory block in machine mode. This sram0 memory block cannot be accessed by this CPU core in other modes or by other CPU cores in different modes.

[0021] In some embodiments, when the memory access management mode is enabled, the security firmware in the ROM is initialized and the memory start address strt_addr and the memory end address end_addr are configured to the first end of the first comparator and the second end of the second comparator to form an address space range; then the register signal pmp_init_done is configured to 1 and input to the first end of the second AND gate. At this time, the memory start address strt_addr and the memory end address end_addr cannot be changed; when the target CPU core is in the preset mode, the input signal core0_mch_mod at the second end of the second AND gate is at a high level. At this time, the address signal addr_in is input to the second end of the first comparator and the first end of the second comparator for comparison. If the address signal addr_in is within the address space range, both the first comparator and the second comparator output a high level; at this time, the output signal sram0_acc_en of the first OR gate is at a high level, allowing reading and writing of the target memory block; when the target CPU core is in the preset mode, if the address signal addr_in is not within the address space range, the output signal sram0_acc_en of the first OR gate is at a low level and the input signal core0_sram0_re at the second end of the fourth AND gate are ANDed to be at a low level, thereby preventing illegal access; when the target CPU core is not in the preset mode, the input signal core0_mch_mod at the second end of the second AND gate is at a low level and the register signal pmp_init_done are ANDed to be at a low level, thereby making the output signal sram0_acc_en of the first OR gate at a low level, and sram0_acc_en and the input signal core0_sram0_re at the second end of the fourth AND gate are ANDed to be at a low level, thereby preventing illegal access.

[0022] In this embodiment, strt_addr and end_addr are the starting address and ending address of the memory configured by the secure firmware in the ROM during initialization. After the configuration is completed, the pmp_init_done register is configured to 1. This register cannot be rewritten after being written as 1 and can only be reset during a power-on hardware reset. At the same time, when pmp_init_done is 1, the strt_addr and end_addr registers cannot be written, thus realizing the locking of the address space after configuring the pmp_init_done register. When core0_mch_mod is at a high level, that is, when CPU core0 is in the machine mode, two comparators are used to compare the input addr_in. If addr_in is greater than or equal to strt_addr and end_addr is greater than or equal to addr_in, the outputs of both comparators are at a high level, within the allowed address space range. At this time, the sram0_acc_en signal is at a high level, allowing read and write access to sram0. In the core0 machine mode, if the input address is not within the address space range composed of the starting address and the ending address, the sram0_acc_en signal is at a low level, and after being ANDed with the core0_sram0_re signal, it is at a low level, thus preventing illegal access. When CPU core0 is not in the machine mode, core0_mch_mod is at a low level, and at this time, after being ANDed with the pmp_init_done signal, it is at a low level, so that the sram0_acc_en signal is at a low level, and after being ANDed with the core0_sram0_re signal, it is at a low level, thus preventing illegal access.

[0023] This embodiment is the situation after the pmp_init_done signal is initialized and configured to 1. Before the pmp_init_done signal is configured to 1, the memory access management mode function is not in effect, and each CPU core is allowed to access this sram0 in the address space mapped in different modes.

[0024] In some embodiments, the second memory management circuit includes a third comparator, a fourth comparator, a fifth AND gate, a sixth AND gate, a seventh AND gate, a second OR gate, and a second inverter; a first terminal of the third comparator is connected to a front-end input, a second terminal of the third comparator is connected to the front-end input and a first terminal of the fourth comparator, and an output terminal of the third comparator is connected to a first terminal of the fifth AND gate; a second terminal of the fourth comparator is connected to the front-end input, and an output terminal of the fourth comparator is connected to a second terminal of the fifth AND gate; an output terminal of the fifth AND gate is connected to a first terminal of the sixth AND gate; a second terminal of the sixth AND gate is connected to the front-end input, and an output terminal of the sixth AND gate is connected to a first terminal of the second OR gate; an input terminal of the second inverter is connected to the front-end input, and an output terminal of the second inverter is connected to a second terminal of the second OR gate; an output terminal of the second OR gate is connected to a first terminal of the seventh AND gate; a second terminal of the seventh AND gate is connected to the front-end input, and an output terminal of the seventh AND gate is connected to a back-end output.

[0025] In this embodiment, as Figure 3 shown, the second memory management circuit manages the access to memory blocks in different modes of the same CPU core through two comparators, three two-input AND gates, one two-input OR gate, and one inverter, and other CPU cores cannot access this sram1 memory block.

[0026] In some embodiments, when the memory access management mode is enabled, the secure firmware in the ROM is initialized and configures the memory start address strt_addr and the memory end address end_addr to the first terminal of the third comparator and the second terminal of the fourth comparator to form an address space range; then configures the register signal pmp_init_done to 1 and inputs it to the second terminal of the sixth AND gate and the input terminal of the second inverter. At this time, the memory start address strt_addr and the memory end address end_addr cannot be changed; at this time, the address signal addr_in is input to the second terminal of the third comparator and the first terminal of the fourth comparator for comparison. If the address signal addr_in is within the address space range, both the first comparator and the second comparator output a high level; at this time, the output signal sram1_acc_en of the second OR gate is a high level, allowing reading and writing of the target memory block; when the target CPU core is in a preset mode, if the address signal addr_in is not within the address space range, the output signal sram1_acc_en of the second OR gate is a low level and the input signal core1_sram1_re to the second terminal of the seventh AND gate is ANDed to be a low level, thereby preventing illegal access.

[0027] In this embodiment, strt_addr and end_addr are the starting address and ending address of the memory configured by the secure firmware in the ROM during initialization. After the configuration is completed, the pmp_init_done register is configured to 1. This register cannot be rewritten after being written to 1 and can only be reset during a power-on hardware reset. At the same time, when pmp_init_done is 1, the strt_addr and end_addr registers cannot be written, thus realizing the locking of the address space after configuring the pmp_init_done register. The input addr_in is compared by two comparators. If addr_in is greater than or equal to strt_addr and end_addr is greater than or equal to addr_in, the outputs of both comparators are high, within the allowed address space range. At this time, the sram0_acc_en signal is high, allowing reading and writing to sram1. In the core1 machine mode, if the input address is not within the address space range composed of the starting address and the ending address, the sram1_acc_en signal is low, and after being ANDed with the core1_sram1_re signal, it is low, thus preventing illegal access. This embodiment is the situation after the pmp_init_done signal is initialized and configured to 1. Before the pmp_init_done signal is configured to 1, the memory access management mode function is not effective at this time, and each CPU core is allowed to access this sram1 in the address space mapped in different modes.

[0028] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications, and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in related fields. And the changes and modifications made by those skilled in the art that do not depart from the spirit and scope of the present invention should all be within the protection scope of the appended claims of the present invention.

Claims

1. A multi-core access memory management system, characterized in that: It includes a memory access management module, and the memory access management module is connected to a security configuration register module, multiple memory blocks, and multiple CPU cores; The memory access management module is used to perform access management and mapping on the memory access space, so that the target CPU core can only access the target memory block in a preset mode.

2. The multi-core access memory management system according to claim 1, characterized in that: The memory access management module includes multiple first memory management circuits and / or second memory management circuits, and each CPU core is connected to a first memory management circuit or a second memory management circuit.

3. The multi-core access memory management system according to claim 2, wherein: The first memory management circuit includes a first comparator, a second comparator, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first OR gate, and a first inverter; the first end of the first comparator is connected to the front-end input, the second end of the first comparator is connected to the front-end input and the first end of the second comparator, and the output end of the first comparator is connected to the first end of the first AND gate; the second end of the second comparator is connected to the front-end input, and the output end of the second comparator is connected to the second end of the first AND gate; the output end of the first AND gate is connected to the first end of the third AND gate; the first end of the second AND gate is connected to the front-end input and the input end of the first inverter, the second end of the second AND gate is connected to the front-end input, and the output end of the second AND gate is connected to the second end of the third AND gate; the output end of the third AND gate is connected to the first end of the first OR gate; the output end of the first inverter is connected to the second end of the first OR gate; the output end of the first OR gate is connected to the first end of the fourth AND gate; the second end of the fourth AND gate is connected to the front-end input, and the output end of the fourth AND gate is connected to the back-end output.

4. The multi-core access memory management system according to claim 3, wherein: When the memory access management mode is enabled, the security firmware in the ROM is initialized and the memory start address strt_addr and the memory end address end_addr are configured to the first end of the first comparator and the second end of the second comparator to form an address space range; then the register signal pmp_init_done is configured to 1 and input to the first end of the second AND gate. At this time, the memory start address strt_addr and the memory end address end_addr cannot be changed; when the target CPU core is in the preset mode, the input signal core0_mch_mod at the second end of the second AND gate is at a high level. At this time, the address signal addr_in is input to the second end of the first comparator and the first end of the second comparator for comparison. If the address signal addr_in is within the address space range, both the first comparator and the second comparator output a high level; at this time, the output signal sram0_acc_en of the first OR gate is at a high level, allowing reading and writing of the target memory block; when the target CPU core is in the preset mode, if the address signal addr_in is not within the address space range, the output signal sram0_acc_en of the first OR gate is at a low level, and after being ANDed with the input signal core0_sram0_re at the second end of the fourth AND gate, it is at a low level, thus preventing illegal access; when the target CPU core is not in the preset mode, the input signal core0_mch_mod at the second end of the second AND gate is at a low level, and after being ANDed with the register signal pmp_init_done, it is at a low level, so that the output signal sram0_acc_en of the first OR gate is at a low level. After sram0_acc_en is ANDed with the input signal core0_sram0_re at the second end of the fourth AND gate, it is at a low level, thus preventing illegal access.

5. The multi-core access memory management system according to claim 2, characterized in that: The second memory management circuit described above includes a third comparator, a fourth comparator, a fifth AND gate, a sixth AND gate, a seventh AND gate, a second OR gate, and a second inverter; the first end of the third comparator is connected to the front-end input, the second end of the third comparator is connected to the front-end input and the first end of the fourth comparator, and the output end of the third comparator is connected to the first end of the fifth AND gate; the second end of the fourth comparator is connected to the front-end input, and the output end of the fourth comparator is connected to the second end of the fifth AND gate; the output end of the fifth AND gate is connected to the first end of the sixth AND gate; the second end of the sixth AND gate is connected to the front-end input, and the output end of the sixth AND gate is connected to the first end of the second OR gate; the input end of the second inverter is connected to the front-end input, and the output end of the second inverter is connected to the second end of the second OR gate; the output end of the second OR gate is connected to the first end of the seventh AND gate; the second end of the seventh AND gate is connected to the front-end input, and the output end of the seventh AND gate is connected to the back-end output.

6. The multi-core access memory management system according to claim 5, characterized in that: When the memory access management mode is enabled, the security firmware in the ROM is initialized and the memory start address strt_addr and the memory end address end_addr are configured to the first end of the third comparator and the second end of the fourth comparator to form an address space range; then the register signal pmp_init_done is configured to 1 and input to the second end of the sixth AND gate and the input end of the second inverter. At this time, the memory start address strt_addr and the memory end address end_addr cannot be changed; at this time, the address signal addr_in is input to the second end of the third comparator and the first end of the fourth comparator for comparison. If the address signal addr_in is within the address space range, both the first comparator and the second comparator output a high level; at this time, the output signal sram1_acc_en of the second OR gate is at a high level, allowing reading and writing of the target memory block; when the target CPU core is in the preset mode, if the address signal addr_in is not within the address space range, the output signal sram1_acc_en of the second OR gate is at a low level and the input signal core1_sram1_re of the second end of the seventh AND gate is ANDed to be at a low level, thereby preventing illegal access.

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