An apparatus and method for improving data recovery capability of a dual-port SSD persistent storage area

Abstract

The application relates to the storage field and specifically relates to a device and a method for improving the data recovery capability of a dual-port SSD persistent storage area. The device comprises a dual-path access monitoring unit, a data moving unit, a concurrent access control unit and a power supply monitoring unit. The dual-path access monitoring unit is used for monitoring the write access request of the persistent storage area issued from two PCIe interfaces in real time and recording relevant information. The concurrent access control unit solves the problem of cache atomicity through a hardware lock. The data moving unit is used for realizing data moving, and the power supply monitoring unit realizes the data saving of the persistent storage area under the power supply abnormal scene in cooperation with a backup power circuit. The application optimizes the data access management of the storage area and the data saving under the power supply failure condition, realizes the data management and recovery capability under the large-capacity PMR condition, and expands the application prospect of the PMR function.

Description

Technical Field

[0001] This invention relates to the field of storage, specifically to an apparatus and method for improving the data recovery capability of a dual-port SSD persistent storage area. Background Technology

[0002] Persistent Memory Region (PMR) is a persistent storage region feature of NVMe SSDs. SSDs supporting this feature have an internal memory space that provides the host with byte-by-byte access capabilities. The contents of this storage region are stored upon power-down and restored upon power-up by the SSD, laying the foundation for future CXL technology applications. In dual-port system designs, to ensure the atomicity of persistent storage region access, two independent memory space addresses are often created and associated with the persistent storage region. This puts pressure on data recovery in the event of a power failure. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides an apparatus and method for improving the data recovery capability of persistent storage areas (PMR) in dual-port SSDs. It optimizes both data access management and data preservation in the event of power failure, thereby achieving data management and recovery capabilities under large-capacity PMR conditions and expanding the application prospects of PMR functionality.

[0004] To solve the aforementioned technical problem, the technical solution adopted by the present invention is: a device for improving the data recovery capability of a dual-port SSD persistent storage area, comprising a dual-channel access monitoring unit, a concurrent access control unit, a data transfer unit, and a power monitoring unit;

[0005] The dual-access monitoring unit is connected to the PCIe interface to monitor access requests to the persistent storage area issued from the two PCIe interfaces in real time. It also uses an address mapping queue to record the starting address and length of the access request and notify the software that an access has occurred.

[0006] The concurrent access control unit is connected to the dual-path access monitoring unit and is used to lock the range of logical addresses recorded in the address mapping queue. When an access request is issued, the range of the locked logical addresses is recorded. When a subsequent access request comes in, it checks whether the logical address of the subsequent access request overlaps with the range of the locked logical addresses. If there is an overlap, data storage is not triggered; otherwise, data storage is triggered.

[0007] The data transfer unit is connected to the concurrent access control unit and is used to parse data addresses, convert the entry information in the address mapping queue into physical address information of the non-volatile medium, and transfer the data in the persistent storage area to the non-volatile medium.

[0008] The power monitoring unit is used to detect whether the power signal of the SSD is stable. When the power signal fails, it notifies the dual-access monitoring unit to trigger an interrupt and notifies the software to save the data in the address mapping queue.

[0009] Furthermore, when the host issues an access request to the persistent storage area, the dual-access monitoring unit records the starting address and length of the access request in a fixed format. The fixed format is to use the high 32 bits to represent the data logical address, which reflects the port information and the address offset of the access request in the persistent storage area, and the low 32 bits to represent the length of the data request and the lock handle. The high 32 bits and the low 32 bits are combined as an entry and added to the address mapping queue.

[0010] Furthermore, when two adjacent access requests have consecutive address ranges, they are merged into one access request.

[0011] Furthermore, the dual-access monitoring unit includes a bus monitoring module, an address mapping queue, and an interrupt triggering module. The bus monitoring module is used to monitor access requests to persistent storage areas issued from the two PCIe interfaces. The address mapping queue is used to record the starting address and length of the memory accessed by the access request. The interrupt triggering module is used to generate an interrupt notification to the software that an access has occurred.

[0012] Furthermore, the address management granularity in the address mapping queue is configured via registers, with a minimum address management granularity of 512B.

[0013] Furthermore, the interrupt triggering module notifies the software of an access event via a hardware interrupt. Upon receiving the interrupt, the software retrieves the corresponding entry from the address mapping queue, parses it, and triggers the saving of the Nand Flash.

[0014] Furthermore, the concurrent access control unit includes an address mapping queue, a pending queue, and a handle management module. When an access request is issued, the handle management module records the range of the locked logical address. When a subsequent access request comes in, the handle management module checks whether the logical address of the subsequent access request overlaps with the range of the locked logical address. If there is an overlap, data storage is not triggered, and the entry is taken from the address mapping queue of the dual-channel access monitoring unit and placed in the pending queue. Otherwise, the entry is taken from the address mapping queue of the dual-channel access monitoring unit and placed in the address mapping queue of the concurrent access control unit. This triggers the interrupt notification software to retrieve the corresponding entry from the address mapping queue of the concurrent access control unit, parse it, and trigger the Nand Flash storage. After the Nand Flash storage is completed, the handle is released. After a lock release is detected, the concurrent access control unit retrieves the entry from the pending queue, relocks it, and then puts it back into the address mapping queue.

[0015] This invention also discloses a method for improving the data recovery capability of a dual-port SSD persistent storage area. This method is based on the above-mentioned device and includes the following steps:

[0016] S01. The dual-channel access monitoring unit monitors access requests to the persistent storage area issued from the two PCIe interfaces in real time, and records the starting address and length of the access request using an address mapping queue, and triggers an interrupt to notify the software that an access has occurred.

[0017] S02. After receiving an interrupt, the software retrieves an entry from the address mapping queue and performs unlocking / unlocking based on the address. If unlocking is successful, the data transmission unit is configured. The data transmission unit includes the target NAND Flash stripe address and the entry content of the address mapping queue, and the data of the corresponding persistent storage area is written into the NAND Flash.

[0018] S03. If, during the process of updating persistent storage data to Nand Flash in the software, a host simultaneously updates the content of the corresponding address range, concurrent access control is triggered to prevent the host from transferring data to memory at this time. Only after the data transfer module completes a transfer can subsequent access requests for non-volatile storage operations continue.

[0019] S04. The power monitoring module monitors the power signal of the SSD in real time. When the power signal fails, it notifies the dual-access monitoring unit to trigger an interrupt and notifies the software to save the data in the address mapping queue.

[0020] Furthermore, in step S02, after the data in the persistent storage area is written to the Nand Flash, the completion status is written to the address specified by the software as a completion message returned to the software, and the software updates the corresponding mapping table according to the completion status.

[0021] Furthermore, step S03 is implemented through the concurrent access control unit. The implementation process is as follows: When an access request is issued, the lock management module records the range of the locked logical address. When a subsequent access request comes in, the lock management module checks whether the logical address of the subsequent access request overlaps with the range of the locked logical address. If there is an overlap, data storage is not triggered, and the entry is taken out from the address mapping queue of the dual-channel access monitoring unit and placed in the pending queue. Otherwise, the entry is taken out from the address mapping queue of the dual-channel access monitoring unit and placed in the address mapping queue of the concurrent access control unit. The interrupt notification software is triggered to retrieve the corresponding entry from the address mapping queue of the concurrent access control unit, parse it, and trigger the Nand Flash to be saved. When the Nand Flash is fully stored, the lock handle is released. After it is determined that a lock has been released, the concurrent access control unit retrieves the entry from the pending queue, relocks it, and then puts it into the address mapping queue.

[0022] The beneficial effects of this invention are as follows: This invention provides a device and method for improving the data recovery capability of a dual-port SSD persistent storage area controller. Through this invention, the dependence on supercapacitors in the event of power failure under the condition of large-capacity persistent storage area can be effectively reduced. By innovatively designing a monitoring module, updates to the storage area can be detected in a timely manner, and persistent storage can be performed in a timely manner, thus expanding the application scenarios of persistent storage areas. Attached Figure Description

[0023] Figure 1 This is a schematic block diagram of the device described in Example 1;

[0024] Figure 2 This is a flowchart of the system power-on process;

[0025] Figure 3 This is a flowchart of the system when it loses power. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0027] Example 1

[0028] This embodiment discloses an apparatus for improving the data recovery capability of the persistent storage area of ​​a dual-port SSD, such as... Figure 1 As shown, based on the existing SSD storage system, a dual-path access monitoring unit, a concurrent access control unit, a data migration unit, and a power monitoring unit have been added to realize the distributed nature of PMR storage, which greatly reduces the pressure of centralized data storage in power failure scenarios and enables support for caching of large-capacity persistent storage areas.

[0029] The dual-access monitoring unit is connected to the PCIe module, with both PCIe interfaces integrated within it. The unit monitors access requests for persistent memory (PMR) from the PCIe module (both PCIe interfaces) in real time, using an address mapping queue to record the starting address and length of each request. It then notifies the software of any access activity via an interrupt. This design avoids the centralized storage of large memory blocks, effectively supporting the preservation of large PMR data (such as 32MB or 64MB).

[0030] In this embodiment, the address management granularity of the address mapping queue in the dual-access monitoring unit can be configured via registers, with a minimum granularity of 512 bits. When the host issues a write access request, the dual-access monitoring unit records the starting address and length of the write request according to a specific format. The high 32 bits represent the data logical address, and the low 32 bits represent the length and handle of the data request. The high and low 32 bits are combined as an entry and added to the address mapping queue. The data logical address addressing rules should reflect two aspects: port information, used to distinguish which PCIe port the write request originated from, facilitating physical separation for future expansion; and the address offset in the PMR region, used to form a mapping relationship. In this embodiment, the address information recording function supports cumulative calculation of address ranges. When two adjacent access address ranges are consecutive, they can be merged into one record. The depth of the address mapping queue needs to be designed based on the supported bandwidth.

[0031] Specifically, the dual-access monitoring unit includes a bus monitoring module, an address mapping queue, and an interrupt triggering module. The bus monitoring module monitors access requests to persistent storage areas issued from both PCIe interfaces. The address mapping queue records the starting address and length of host memory accesses. The interrupt triggering module generates an interrupt to notify the software that an access has occurred. In this embodiment, the interrupt triggering module notifies the software via a hardware interrupt. The software retrieves the corresponding entry from the address mapping queue, parses it, and triggers the saving of the Nand Flash memory. The interrupt module supports masking and uses a polling approach.

[0032] The concurrent access control unit solves the cache atomicity problem through hardware locking. The concurrent access control unit is designed with an address mapping queue, a pending queue, and a lock management module. It locks the logical address range recorded in the address mapping queue. When an access request is issued, the lock management module records the range of locked logical addresses. When subsequent accesses arrive, the lock management module checks if the immediate address of the subsequent access overlaps with the locked range. If there is overlap, software storage is not triggered, and the entry is removed from the address mapping queue and placed in the pending queue. Otherwise, the entry is removed from the mapping queue of the dual-path access monitoring unit and placed in the address mapping queue of the concurrent access control unit. This triggers an interrupt to notify the software to retrieve the corresponding entry from the address mapping queue of the concurrent access control unit, parse it, and trigger the NAND flash storage. After NAND storage is complete, the lock is released by software configuration. When a lock release is detected, the concurrent access control unit retrieves the entry from the pending queue, re-locks it, and then puts it back into the address mapping queue. This ensures the atomicity of simultaneous access to a persistent storage area by the host write and data migration modules, guaranteeing atomicity during the storage of a single entry. Storage can only continue after the data migration module has finished reading.

[0033] The data migration unit comprises two functions: one is resolving data addresses, converting entry information in the address mapping queue into physical address information for non-volatile media; the other is the data migration engine, which migrates data from persistent storage to non-volatile media and returns a completion message to the software. The software relies on this module to automatically calculate the specific location where data needs to be stored in the Nand Flash chip, activates the internal data migration engine, and achieves the preservation of persistent memory while also implementing wear leveling for user data on the NVMe command path. The input variables for address resolution are the entry information in the address mapping queue and the superblock information filled in by the software when triggering the save operation. The output includes the physical path number, chip select number, physical block number of the Nand Flash chip, and the number of word lines to be operated on. The data migration engine then writes the data from persistent memory to the Nand Flash.

[0034] The power monitoring unit, in conjunction with the backup power circuit, ensures data preservation in the persistent storage area during power outages. It detects the stability of the 12V power signal at the SSD's gold fingers to determine if the external power supply has failed. If a power failure occurs, the dual-channel monitoring unit is promptly notified to trigger an interrupt, instructing the software to save the data in the address mapping queue.

[0035] Example 2

[0036] This embodiment discloses a method for improving the data recovery capability of a dual-port SSD persistent storage area. This method is based on the device described in Embodiment 1 and includes the following steps:

[0037] S01. The dual-channel access monitoring unit monitors access requests to the persistent storage area issued from the two PCIe interfaces in real time, and records the starting address and length of the access request using an address mapping queue, and triggers an interrupt to notify the software that an access has occurred.

[0038] In this embodiment, the address management granularity of the address mapping queue can be configured via registers, with a minimum granularity of 512 bits. When the host issues a write access request, the dual-channel access monitoring unit records the starting address and length of the write request according to a specific format. The high 32 bits represent the data logical address, and the low 32 bits represent the request length. These are combined and added as an entry to the address mapping queue. The addressing rules for the data logical address should reflect two aspects: port information to distinguish which PCIe port the write request originated from, facilitating physical separation for future expansion; and the address offset in the PMR region to form a mapping relationship. In this embodiment, the address information recording function supports cumulative calculation of address ranges. When two adjacent access address ranges are consecutive, they can be merged into one entry. The depth of the address mapping queue needs to be designed based on the supported bandwidth.

[0039] S02. Upon receiving an interrupt, the software retrieves an entry from the address mapping queue and performs locking / unlocking processing based on the address. If unlocking is successful, the data transmission unit is configured. The data transmission unit includes the target NAND Flash stripe address and the entry content in the address mapping queue. The data of the corresponding persistent storage area is then written into the NAND Flash. Data migration, which involves writing the data from the persistent storage area into the NAND Flash, completes the process by writing the completion status to the address specified by the software as a completion message. The software then updates the corresponding mapping table based on the completion status to facilitate data recovery in the next PMR (Persistent Memory Registry).

[0040] S03. If, during the software update of persistent storage data to Nand Flash, a host simultaneously updates the content of the corresponding address range, concurrent access control is triggered to prevent the host from transferring data to memory at this time. Only after the data migration module completes one migration can subsequent access requests for non-volatile storage operations continue, ensuring data atomicity. The atomicity value can be determined according to the data implementation scheme and can be a multiple of 16k.

[0041] In this embodiment, step S03 is implemented through the concurrent access control unit. The implementation process is as follows: When an access request is issued, the lock handle management module records the range of the locked logical address. When a subsequent access request comes in, the lock handle management module checks whether the logical address of the subsequent access request overlaps with the range of the locked logical address. If there is an overlap, data storage is not triggered, and the entry is taken out from the address mapping queue of the dual-channel access monitoring unit and placed in the pending queue. Otherwise, the entry is taken out from the address mapping queue of the dual-channel access monitoring unit and placed in the address mapping queue of the concurrent access control unit. The interrupt notification software is triggered to take out the corresponding entry from the address mapping queue of the concurrent access control unit, parse it, and trigger the Nand Flash to be saved. When the Nand Flash is fully stored, the lock handle is released. After it is determined that a lock has been released, the concurrent access control unit takes out the entry from the pending queue, relocks it, and puts it back into the address mapping queue.

[0042] S04. The power monitoring module monitors the power signal of the SSD in real time. When the power signal failure is detected (such as abnormal drop), it notifies the dual-access monitoring unit to trigger an interrupt and notifies the software to save the cached data recorded in the address mapping queue in a timely manner during the backup power capacitor time.

[0043] The method described in this embodiment is reflected in two processes: power-on and abnormal power-off. For example... Figure 2 As shown, upon power-up, the software initializes the address management granularity to 512 bytes, enables the persistent storage area controller, and sets the persistent storage area size to 32MB. This completes the power-up recovery of the persistent storage area memory, and the persistent storage area is enabled by the host. The host updates the persistent storage area memory (the dual-access monitoring unit detects access requests to the persistent storage area), triggering the dual-access monitoring unit function to add an entry to the address mapping queue. The software receives an interrupt, checks the linked list of the concurrent access control unit to determine if a NAND flash operation can be performed. If so, it obtains the current superblock information, triggers the data migration module, and after data migration is complete, updates the FTL mapping, stores the data in the NAND flash, and releases the concurrent access control handle.

[0044] During power-up, data is written from the persistent storage area to the NAND flash in multiple chunks. Since most of the data has already been written to the NAND flash, the pressure on data recovery during abnormal power outages is reduced. Furthermore, the data writing process uses hardware locking to solve the problem of cache atomicity.

[0045] like Figure 3As shown, the abnormal power-down process is as follows: an abnormal power failure is detected and a control signal is output. It is determined whether there are any unstored entries in the address mapping queue. If there are, the system switches to backup power mode and completes the data saving of the unstored entries, that is, the unstored entries in the address mapping queue of the persistent storage area are stored in the NAND FLASH.

[0046] In this embodiment, the software is embedded in the CPU core. This is reflected in the connection relationship of the modules, where the dual-path access monitoring unit, concurrent access control unit, data transfer unit, and power monitoring unit are all connected to the CPU core.

[0047] The above description is merely the basic principle and preferred embodiment of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.

Claims

1. An apparatus for improving the data recovery capability of a dual-port SSD persistent storage area, characterized in that: It includes a dual-path access monitoring unit, a concurrent access control unit, a data transfer unit, and a power monitoring unit; The dual-access monitoring unit is connected to the PCIe interface to monitor access requests to the persistent storage area issued from the two PCIe interfaces in real time. It also uses an address mapping queue to record the starting address and length of the access request and notify the software that an access has occurred. The concurrent access control unit is connected to the dual-path access monitoring unit and is used to lock the range of logical addresses recorded in the address mapping queue. When an access request is issued, the range of the locked logical addresses is recorded. When a subsequent access request comes in, it checks whether the logical address of the subsequent access request overlaps with the range of the locked logical addresses. If there is an overlap, data storage is not triggered; otherwise, data storage is triggered. The concurrent access control unit includes an address mapping queue, a pending queue, and a handle management module. When an access request is issued, the handle management module records the range of the locked logical address. When a subsequent access request comes in, the handle management module checks whether the logical address of the subsequent access request overlaps with the range of the locked logical address. If there is an overlap, data storage is not triggered, and the entry is taken from the address mapping queue of the dual-channel access monitoring unit and placed in the pending queue. Otherwise, the entry is taken from the address mapping queue of the dual-channel access monitoring unit and placed in the address mapping queue of the concurrent access control unit. This triggers the interrupt notification software to retrieve the corresponding entry from the address mapping queue of the concurrent access control unit, parse it, and trigger the saving of the Nand Flash. Once the Nand Flash storage is complete, the lock handle is released. After detecting that a lock has been released, the concurrent access control unit retrieves the entry from the pending queue, re-locks it, and then puts it into the address mapping queue. The data transfer unit is connected to the concurrent access control unit and is used to parse data addresses, convert the entry information in the address mapping queue into physical address information of the non-volatile medium, and transfer the data in the persistent storage area to the non-volatile medium. The power monitoring unit is used to detect whether the power signal of the SSD is stable. When the power signal fails, it notifies the dual-access monitoring unit to trigger an interrupt and notifies the software to save the data in the address mapping queue.

2. The apparatus for improving data recovery capability of persistent storage areas in dual-port SSDs according to claim 1, characterized in that: When the host issues an access request to the persistent storage area, the dual-access monitoring unit records the starting address and length of the access request in a fixed format. The fixed format is to use the high 32 bits to represent the data logical address, which reflects the port information and the address offset of the access request in the persistent storage area, and the low 32 bits to represent the length of the data request and the lock handle. The high 32 bits and the low 32 bits are combined as an entry and added to the address mapping queue.

3. The apparatus for improving data recovery capability of dual-port SSD persistent storage area according to claim 2, characterized in that: When two adjacent access requests have consecutive address ranges, they are merged into one access request.

4. The apparatus for improving data recovery capability of persistent storage areas in dual-port SSDs according to claim 1, characterized in that: The dual-access monitoring unit includes a bus monitoring module, an address mapping queue, and an interrupt triggering module; The bus monitoring module is used to monitor access requests to persistent storage areas issued from the two PCIe interfaces. The address mapping queue is used to record the starting address and length of the memory accessed by the access request. The interrupt triggering module is used to generate an interrupt to notify the software that an access has occurred.

5. The apparatus for improving data recovery capability of persistent storage area of ​​dual-port SSD according to claim 4, characterized in that: The address management granularity in the address mapping queue is configured via registers, with a minimum address management granularity of 512B.

6. The apparatus for improving data recovery capability of persistent storage area of ​​dual-port SSD according to claim 4, characterized in that: The interrupt triggering module notifies the software of an access event via a hardware interrupt. Upon receiving the interrupt, the software retrieves the corresponding entry from the address mapping queue, parses it, and triggers the saving of the Nand Flash.

7. A method for improving the data recovery capability of a dual-port SSD persistent storage area, characterized in that: This method is implemented based on the apparatus described in any one of claims 1-6, and includes the following steps: S01. The dual-channel access monitoring unit monitors access requests to the persistent storage area issued from the two PCIe interfaces in real time, and records the starting address and length of the access request using an address mapping queue, and triggers an interrupt to notify the software that an access has occurred. S02. After receiving an interrupt, the software retrieves an entry from the address mapping queue and performs unlocking / unlocking based on the address. If unlocking is successful, the data transmission unit is configured. The data transmission unit includes the target NAND Flash stripe address and the entry content of the address mapping queue, and the data of the corresponding persistent storage area is written into the NAND Flash. S03. If, during the process of updating persistent storage data to Nand Flash in the software, a host simultaneously updates the content of the corresponding address range, concurrent access control is triggered to prevent the host from transferring data to memory at this time. Only after the data transfer module completes one transfer can the subsequent access request for non-volatile storage operation continue. Step S03 is implemented through the concurrent access control unit. The implementation process is as follows: When an access request is issued, the lock management module records the range of the locked logical address. When a subsequent access request comes in, the lock management module checks whether the logical address of the subsequent access request overlaps with the range of the locked logical address. If there is an overlap, data storage is not triggered, and the entry is taken out from the address mapping queue of the dual-channel access monitoring unit and placed in the pending queue. Otherwise, the entry is taken out from the address mapping queue of the dual-channel access monitoring unit and placed in the address mapping queue of the concurrent access control unit. The interrupt notification software is triggered to retrieve the corresponding entry from the address mapping queue of the concurrent access control unit, parse it, and trigger the Nand Flash to be saved. When the Nand Flash is fully stored, the lock handle is released. After it is determined that a lock has been released, the concurrent access control unit retrieves the entry from the pending queue, relocks it, and then puts it into the address mapping queue. S04. The power monitoring module monitors the power signal of the SSD in real time. When the power signal fails, it notifies the dual-access monitoring unit to trigger an interrupt and notifies the software to save the data in the address mapping queue.

8. The method for improving the data recovery capability of a dual-port SSD persistent storage area according to claim 7, characterized in that: In step S02, after the data in the persistent storage area is written to the Nand Flash, the completion status is written to the address specified by the software as a completion message returned to the software. The software updates the corresponding mapping table according to the completion status.

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