An interrupt control device and method based on RISC-V architecture

Abstract

This application discloses an interrupt control device and method based on a RISC-V architecture, relating to the field of interrupt handling technology. The device includes a processor, an interrupt controller, and a data preparation module. The interrupt controller is used to acquire a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; and generates a first interrupt signal based on the acquired first interrupt request. The data preparation module is used to load the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information, and data load length information. The processor is used to suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handler, and acquire the target data corresponding to the interrupt handler from the data preparation module.

Description

Technical Field

[0001] This application relates to the field of interrupt handling technology, and in particular to an interrupt control device and method based on RISC-V architecture. Background Technology

[0002] With the development of RISC-V architecture-based CPUs, their application in high-real-time chips is increasing. However, traditional RISC-V architecture-based CPUs, when performing real-time tasks, especially interrupt handling tasks, need to wait for the current instructions of the general program to complete before responding to interrupts. This results in excessively long interrupt response times and a poor user experience. Summary of the Invention

[0003] In view of this, embodiments of this application provide an interrupt control device and method based on a RISC-V architecture.

[0004] According to a first aspect of this application, embodiments of this application provide an interrupt control device based on a RISC-V architecture, comprising:

[0005] Processor, interrupt controller, and data preparation module;

[0006] The interrupt controller is used to obtain the first interrupt request and enable information sent by the first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; it sends the enable information, data load address information and data load length information to the data preparation module; and it generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor.

[0007] The data preparation module is used to load the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information, and data load length information.

[0008] The processor is used to acquire the first interrupt signal, suspend the general program after executing the current instructions of the general program, and respond to the first interrupt signal to execute the interrupt handler and acquire the target data corresponding to the interrupt handler from the data preparation module.

[0009] Optionally, the interrupt controller is further configured to, based on the interrupt source ID, count the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generate enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

[0010] Optionally, the interrupt controller is further configured to generate a deletion signal if it fails to acquire the first interrupt request sent by the first interrupt source within the maximum time limit for the next interrupt request sent by the first interrupt source, and send the deletion signal to the data preparation module so that the data preparation module stops loading the target data corresponding to the interrupt handler from memory into the data preparation module, and deletes the target data corresponding to the interrupt handler that has been loaded in the data preparation module.

[0011] Optionally, the interrupt controller includes an interrupt validity determination and priority determination module and an interrupt pre-parsed address information table control module;

[0012] The interrupt validity and priority determination module is used to obtain the first interrupt request and enable information sent by the first interrupt source; send the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parse address information table control module; and generate a first interrupt signal based on the obtained first interrupt request and send the first interrupt signal to the processor.

[0013] The interrupt pre-parse address information table control module is used to query the data loading address information and data loading length information of the corresponding interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source; and send the enable information, data loading address information and data loading length information to the data preparation module.

[0014] Optionally, the interrupt controller may also include an interrupt prediction module;

[0015] The interrupt prediction module is used to count the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request, based on the interrupt source ID; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generate enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

[0016] Optionally, the data preparation module includes a control signal receiving and parsing module, a data loading module, a data caching module, and an interface module;

[0017] The control signal receiving and parsing module is used to receive enable information, data loading address information and data loading length information, and based on the enable information, send the data loading address information and data loading length information to the data loading module.

[0018] The data loading module is used to load the target data corresponding to the interrupt handler from memory into the data cache module based on the data loading address information and the data loading length information.

[0019] The data caching module is used to cache the target data corresponding to the interrupt handler;

[0020] The interface module is used to respond to the processor's read requests by outputting the target data corresponding to the interrupt handler from the data cache module to the processor.

[0021] Optionally, the interrupt control device based on the RISC-V architecture includes a synchronous execution module;

[0022] Before the processor finishes executing the current instruction of the general program, it is also used to send the current instruction to the synchronous execution module for execution if it determines that the current instruction is a load instruction or a first store instruction, and to respond to the first interrupt signal;

[0023] The synchronous execution module is used to execute the current instruction based on the source address information, target address information, and data length information corresponding to the current instruction.

[0024] Optionally, the interrupt controller is also configured to acquire the second interrupt request sent by the second interrupt source, generate a second interrupt signal based on the acquired second interrupt request, and send the second interrupt signal to the processor;

[0025] The processor is also configured to, in response to the acquisition of a second interrupt signal, send the second stored instruction of the interrupt handler to the synchronous execution module for execution when the second stored instruction of the interrupt handler is acquired, and respond to the second interrupt signal.

[0026] Optionally, the synchronous execution module includes:

[0027] The load splitting request processing module is used to receive the current instruction sent by the processor; and when it is determined that the current instruction is a load instruction, it sends the current instruction to the load splitting control module; and when it is determined that the current instruction is a first storage instruction, it sends the current instruction to the storage splitting control module.

[0028] Load the flow control module to parse the current instruction and obtain the source address information, target address information, and data length information corresponding to the current instruction;

[0029] The storage distribution control module is used to parse the current instruction and obtain the source address information, target address information, and data length information corresponding to the current instruction.

[0030] The address decoding module is used to obtain the physical address information corresponding to the current instruction sent by the processor, and convert the original address information and target address information corresponding to the current instruction into physical address information.

[0031] The bus interface control module is used to execute the current instruction based on the physical address information and data length information of the current instruction.

[0032] Optionally, the processor is also used to count the frequency of interrupt requests initiated by different interrupt sources, and store the address of the interrupt handler corresponding to the target interrupt source whose interrupt request frequency is greater than the threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signal corresponding to the target interrupt source to the processor, it can synchronously send the address of the interrupt handler corresponding to the target interrupt source.

[0033] According to a second aspect of this application, embodiments of this application provide an interrupt control method based on a RISC-V architecture, applied to an interrupt control device based on a RISC-V architecture. The device includes a processor, an interrupt controller, and a data preparation module. The method includes:

[0034] The interrupt controller obtains the first interrupt request and enable information sent by the first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; it sends the enable information, data load address information and data load length information to the data preparation module; and it generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor.

[0035] The data preparation module loads the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information, and data load length information.

[0036] Upon receiving the first interrupt signal, the processor suspends the general program after executing the current instruction of the general program; and responds to the first interrupt signal by executing the interrupt handler and obtaining the target data corresponding to the interrupt handler from the data preparation module.

[0037] Optionally, the interrupt control method based on the RISC-V architecture further includes: the interrupt controller, based on the interrupt source ID, counting the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request; predicting the time of the next interrupt request from the first interrupt source based on the time interval and the time of the most recent interrupt request; and generating enable information when the predicted time of the next interrupt request from the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

[0038] Optionally, the interrupt control method based on the RISC-V architecture also includes:

[0039] If the interrupt controller fails to receive the first interrupt request from the first interrupt source within the maximum time limit for the next interrupt request from the first interrupt source, it generates a deletion signal and sends the deletion signal to the data preparation module. This causes the data preparation module to stop loading the target data corresponding to the interrupt handler from memory into the data preparation module and delete the target data corresponding to the interrupt handler that has been loaded in the data preparation module.

[0040] Optionally, the interrupt controller includes an interrupt validity determination and priority determination module and an interrupt pre-parsed address information table control module;

[0041] The interrupt validity and priority determination module obtains the first interrupt request and enable information sent by the first interrupt source; sends the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parse address information table control module; and generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor.

[0042] The interrupt pre-parse address information table control module queries the data loading address information and data loading length information corresponding to the interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source; and sends the enable information, data loading address information and data loading length information to the data preparation module.

[0043] Optionally, the interrupt controller also includes an interrupt prediction module; the interrupt control method based on the RISC-V architecture also includes:

[0044] The interrupt prediction module calculates the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request based on the interrupt source ID; predicts the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generates enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

[0045] Optionally, the data preparation module includes a control signal receiving and parsing module, a data loading module, a data caching module, and an interface module;

[0046] The control signal receiving and parsing module receives enable information, data loading address information, and data loading length information, and sends the data loading address information and data loading length information to the data loading module based on the enable information;

[0047] The data loading module loads the target data corresponding to the interrupt handler from memory into the data cache module based on the data loading address information and the data loading length information;

[0048] The data caching module caches the target data corresponding to the interrupt handler;

[0049] In response to the processor's read request, the interface module retrieves the target data corresponding to the interrupt handler from the data cache module and outputs it to the processor.

[0050] Optionally, the device also includes a synchronous execution module; the interrupt control method based on the RISC-V architecture further includes:

[0051] Before the processor finishes executing the current instruction of the general program, if it determines that the current instruction is a load instruction or a first store instruction, it sends the current instruction to the synchronous execution module for execution and responds to the first interrupt signal.

[0052] The synchronous execution module executes the current instruction based on the source address information, target address information, and data length information corresponding to the current instruction.

[0053] Optionally, the interrupt control method based on the RISC-V architecture also includes:

[0054] The interrupt controller receives the second interrupt request sent by the second interrupt source, generates a second interrupt signal based on the received second interrupt request, and sends the second interrupt signal to the processor;

[0055] In response to receiving the second interrupt signal, the processor, upon receiving the second stored instruction of the interrupt handler, sends the second stored instruction to the synchronous execution module for execution and responds to the second interrupt signal.

[0056] Optionally, the synchronous execution module includes a traffic splitting request processing module, a loading traffic splitting control module, a storage traffic splitting control module, an address decoding module, and a bus interface control module;

[0057] The load splitting request processing module receives the current instruction sent by the processor; and when it determines that the current instruction is a load instruction, it sends the current instruction to the load splitting control module; and when it determines that the current instruction is a first storage instruction, it sends the current instruction to the storage splitting control module.

[0058] The load splitting control module parses the current instruction to obtain the source address information, target address information, and data length information corresponding to the current instruction;

[0059] The storage distribution control module parses the current instruction to obtain the source address information, target address information, and data length information corresponding to the current instruction;

[0060] The address decoding module obtains the physical address information corresponding to the current instruction sent by the processor, and converts the original address information and target address information corresponding to the current instruction into physical address information;

[0061] The bus interface control module executes the current instruction based on the physical address information and data length information of the current instruction.

[0062] Optionally, the interrupt control method based on the RISC-V architecture also includes:

[0063] The processor counts the frequency of interrupt requests from different interrupt sources and stores the address of the interrupt handler corresponding to the target interrupt source whose interrupt request frequency is greater than a threshold in the interrupt controller. This allows the interrupt controller to send the address of the interrupt handler corresponding to the target interrupt source to the processor at the same time as sending the interrupt signal corresponding to the target interrupt source.

[0064] The interrupt control device and method based on the RISC-V architecture provided in this application embodiment includes a processor, an interrupt controller, and a data preparation module. The interrupt controller acquires a first interrupt request and enable information sent by a first interrupt source. Based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler. It then sends the enable information, data load address information, and data load length information to the data preparation module. Based on the acquired first interrupt request, it generates a first interrupt signal and sends the first interrupt signal to the processor. The data preparation module loads the target data corresponding to the interrupt handler from memory to the data preparation module based on the enable information, data load address information, and data load length information. The preparation module is used by the processor to receive the first interrupt signal, suspend the general program after executing the current instruction of the general program, and respond to the first interrupt signal by executing the interrupt handler. It retrieves the target data corresponding to the interrupt handler from the data preparation module. Thus, while the processor is executing the current instruction of the general program, the data preparation module can synchronously load the target data required for the interrupt handler from memory. This eliminates the need for the processor to retrieve the target data from memory after executing the current instruction of the general program, significantly reducing the time required for the processor to obtain the target data. This greatly improves the execution speed of the interrupt handler, thereby accelerating the response speed to interrupt requests and enhancing the user experience.

[0065] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0066] Figure 1 This is a schematic diagram of the hardware structure of an interrupt control device based on the RISC-V architecture in an embodiment of this application;

[0067] Figure 2 This is a schematic diagram of the interrupt controller according to an embodiment of this application;

[0068] Figure 3 This is a schematic diagram of the data preparation module in an embodiment of this application;

[0069] Figure 4 This is a schematic diagram of the hardware structure of another interrupt control device based on the RISC-V architecture in the embodiments of this application;

[0070] Figure 5 This is a schematic diagram of the structure of the synchronous execution module in an embodiment of this application;

[0071] Figure 6 This is a flowchart illustrating an interrupt control method based on a RISC-V architecture in an embodiment of this application. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0073] This application provides an interrupt control device based on a RISC-V architecture, such as... Figure 1 As shown, it includes: processor 11, interrupt controller 12 and data preparation module 13.

[0074] The interrupt controller 12 is used to obtain the first interrupt request and enable information sent by the first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data loading address information and data loading length information corresponding to the interrupt handler; it sends the enable information, data loading address information and data loading length information to the data preparation module 13; and it generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor 11.

[0075] The data preparation module 13 is used to load the target data corresponding to the interrupt handler from memory into the data preparation module 13 based on the enable information, data load address information and data load length information.

[0076] The processor 11 is used to acquire the first interrupt signal, suspend the general program after executing the current instruction of the general program, and respond to the first interrupt signal to execute the interrupt handler and acquire the target data corresponding to the interrupt handler from the data preparation module.

[0077] In this embodiment, the interrupt control device based on the RISC-V architecture can be a CPU based on the RISC-V architecture, or it can be a chip, electronic device, etc. that includes a CPU based on the RISC-V architecture.

[0078] In this embodiment, as Figure 1 As shown, the processor 11 may include at least one processor core (RISC-V Core), a dedicated L1 cache unit for the processor core, and a shared L2 cache unit for the processor core.

[0079] In this embodiment, the address of the first instruction after the RISC-V Core powers on and resets points to the starting address of the interrupt vector table cached in memory, and pre-execution processing is performed on all interrupt handlers indicated in the interrupt vector table. Pre-execution refers to pre-executing the load instructions in the interrupt handlers; that is, only the starting address (Load_addr) and load length (Load_Length) of the load instructions in all interrupt handlers are monitored, and an interrupt pre-resolution address information table as shown in Table 1 is created based on the interrupt source ID (Inter_ID) corresponding to the interrupt handler. After completing the pre-processing of all interrupt handlers, the RISC-V Core jumps back to the starting address of the regular program for normal operation, and caches the interrupt pre-resolution address information table in the interrupt controller 12.

[0080] Table 1

[0081]

[0082] In some embodiments, such as Figure 2 As shown, the interrupt controller 12 may include an interrupt validity determination and priority determination module and an interrupt pre-parsed address information table control module. The interrupt validity determination and priority determination module is used to obtain the first interrupt request and enable information sent by the first interrupt source; send the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parsed address information table control module; and generate a first interrupt signal based on the obtained first interrupt request, and send the first interrupt signal to the processor; the interrupt pre-parsed address information table control module is used to query the data load address information and data load length information corresponding to the corresponding interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source; and send the enable information, data load address information, and data load length information to the data preparation module.

[0083] In specific implementation, after the interrupt validity judgment and priority judgment module of the interrupt controller 12 obtains the first interrupt request and enable information sent by the first interrupt source, it performs interrupt enable information judgment. If the first interrupt request is normally enabled, the first interrupt signal is generated to the RISC-V Core.

[0084] The interrupt controller 12's interrupt pre-parse address information table and control module, based on the enable information and according to the ID information of the first interrupt source, query the interrupt pre-parse address information table to find the data load address information and data load length information corresponding to the interrupt handler. Then, the enable information, data load address information, and data load length information are sent to the data preparation module 13.

[0085] In this embodiment, the data preparation module 13 initiates a direct memory access (DMA) operation based on the enable information. It preloads the target data (corresponding to the data load address and data load length information) from memory into the data preparation module 13. This allows the RISC-V Core to directly retrieve the data used by the Load instruction from the data preparation module when processing the first interrupt signal, eliminating the need for loading from memory. The Load instruction is very clock-intensive, requiring tens or even hundreds of clock cycles for a single memory operation, thus significantly accelerating the interrupt handler's processing speed.

[0086] The interrupt control device based on the RISC-V architecture provided in this application includes a processor, an interrupt controller, and a data preparation module. The interrupt controller receives a first interrupt request and enable information from a first interrupt source. Based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler. It then sends the enable information, data load address information, and data load length information to the data preparation module. Based on the received first interrupt request, it generates a first interrupt signal and sends the first interrupt signal to the processor. The data preparation module loads the target data corresponding to the interrupt handler from memory to the data preparation module based on the enable information, data load address information, and data load length information. The processor, upon receiving the first interrupt signal, suspends the general program after executing its current instructions. It then responds to the first interrupt signal by executing the interrupt handler and retrieves the target data corresponding to the interrupt handler from the data preparation module. Thus, while the processor executes the current instructions of the general program, the data preparation module can simultaneously load the target data required for the interrupt handler from memory. This eliminates the need for the processor to retrieve the target data from memory after executing the current instructions of the general program, significantly reducing the time required for the processor to obtain the interrupt handler's target data. This greatly improves the processor's execution speed of the interrupt handler, thereby accelerating the response speed to interrupt requests and enhancing the user experience.

[0087] In an optional embodiment, the interrupt controller 12 is further configured to, based on the interrupt source ID, count the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generate enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

[0088] In this embodiment, the interrupt controller 12 may also have an interrupt prediction and processing function.

[0089] In specific implementation, such as Figure 2As shown, the interrupt controller may further include an interrupt prediction module. The interrupt prediction module is used to count the time interval between the interrupt requests sent by the first interrupt source and the time of the most recent interrupt request based on the interrupt source ID; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generate enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request sent by the first interrupt source is obtained. For example, the interrupt prediction module may record the time interval between the interrupt requests initiated by the interrupt source according to the interrupt source ID, T_0---T_N-1 (record N times, N can be a default value or a register configuration), and perform a weighted average on the N intervals:

[0090] T_mid = T_0×PARAM_0 + T_1×PARAM_1……T_N-1×PARAM_N-1;

[0091] where it is required that PARAM_0<PARAM_1<PARAM_2……PARAM_N- , that is, the closer to the current moment, the greater its weight.

[0092] When N statistics are completed, T_mid is obtained, and the time T_Cur when the Nth interrupt request occurs is recorded. When the time (T_Cur + T_mid) of the next interrupt request arrives and the corresponding interrupt source has not initiated an interrupt request for the time, the interrupt prediction module will issue enable information, that is, pre_inter_en, and use this enable information as a query signal to input to the interrupt pre-parse address information table and the control module, and then perform the address and length query of the corresponding Load instruction. Then the enable information, the address and length of the corresponding Load instruction are passed to the data preparation module.

[0093] At the same time, the interrupt prediction module is also used to perform feedback adjustment on the interrupt prediction mechanism, and monitor in real time whether there is another interrupt occurrence in the predicted interrupt source:

[0094] The interrupt prediction module is further used to generate a deletion signal when no first interrupt request sent by the first interrupt source is obtained within the maximum time of the next interrupt request sent by the first interrupt source preset, and send the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handling program from the memory to the data preparation module, and deletes the target data corresponding to the interrupt handling program that has been loaded in the data preparation module.

[0095] In other words, if the corresponding interrupt source has not actually initiated an interrupt request within the maximum time (T_Cur + T_max) of the next interrupt request (T_max can be a default value or configured via a register), a deletion signal `pre_inter_detect` is generated, indicating a current interrupt prediction error. The `pre_inter_detect` signal is also passed to the interrupt pre-parse address information table and control module, and then to the data preparation module, pausing its ongoing Load operation and deleting the already loaded data. Simultaneously, feedback is provided to modify the prediction formula.

[0096] T_mid = T_0×PARAM_0 + T_1×PARAM_1……T_N-1×PARAM_N-1, which expands the relevant parameters and also expands T_max.

[0097] If the interrupt source has initiated an interrupt request before time T_Cur+T_max, and the data preparation module has already performed the loading operation normally, then the interrupt pre-resolution address information table and control module are fed back. Enable information, data loading address information, and data loading length information no longer need to be sent to the data preparation module, and the prediction formula is modified accordingly.

[0098] T_mid = T_0×PARAM_0 + T_1×PARAM_1……T_N-1×PARAM_N-1, which reduces the relevant parameters and also reduces T_max.

[0099] In this embodiment, the interrupt controller can anticipate interrupt requests in advance. When the predicted interrupt request time arrives, it can trigger the preparation of the target data for the corresponding interrupt handler, instead of waiting for the actual interrupt request to arrive. This can further improve the execution speed of the interrupt handler by the processor, thereby speeding up the response speed of interrupt requests.

[0100] In an optional embodiment, such as Figure 3 As shown, the data preparation module 13 includes a control signal receiving and parsing module 131, a data loading module 132, a data caching module 133, and an interface module 134.

[0101] The control signal receiving and parsing module 131 is used to receive enable information, data loading address information and data loading length information, and send the data loading address information and data loading length information to the data loading module based on the enable information.

[0102] The data loading module 132 is used to load the target data corresponding to the interrupt handler from memory to the data cache module based on the data loading address information and the data loading length information.

[0103] The data caching module 133 is used to cache the target data corresponding to the interrupt handler.

[0104] Interface module 134 is used to respond to the processor's read request by outputting the target data corresponding to the interrupt handler from the data cache module to the processor.

[0105] In this embodiment, the control signal receiving and parsing module 131 can also receive a deletion signal and send it to the data loading module 132. Based on the deletion signal, the data loading module 132 stops loading data from memory. The control signal receiving and parsing module 131 also sends the deletion signal to the data caching module 133. Based on the deletion signal, the data caching module 133 deletes the corresponding stored data.

[0106] In this embodiment, the data preparation module is configured to include multiple sub-modules, so that each sub-module can operate on each other or independently, thereby quickly realizing the function of the data preparation module.

[0107] In an optional embodiment, such as Figure 4 As shown, the interrupt control device based on the RISC-V architecture includes a synchronous execution module 14.

[0108] Before executing the current instruction of the general program, the processor 11 is also used to send the current instruction to the synchronous execution module 14 for execution if it is determined that the current instruction is a load instruction or a first store instruction, and to respond to the first interrupt signal.

[0109] The synchronous execution module 14 is used to execute the current instruction based on the source address information, target address information, and data length information corresponding to the current instruction.

[0110] In practical implementation, when the interrupt controller 12 receives the first interrupt request, the RISC-V Core needs to finish executing the current instructions of the general program before responding to the first interrupt request. However, if the RISC-V Core is currently executing the load or store instructions of the general program, the completion of these two instructions typically requires hundreds of clock cycles. To speed up the interrupt response, in this embodiment, if the RISC-V Core is not executing the load / store instructions of the general program, it can suspend the general program after executing the current instructions and respond to the first interrupt signal to execute the interrupt handler. If the RISC-V Core is executing the load / store instructions of the general program, the execution of the load / store instructions can be offloaded to the synchronous execution module 14, and the RISC-V Core can immediately respond to the first interrupt signal. In this way, the processor 11 does not need to wait for the current instructions of the general program to finish executing before responding to the first interrupt request, thus speeding up the response to the first interrupt signal.

[0111] In some implementations, the specific architecture of the synchronous execution module is as follows: Figure 5 As shown, it includes:

[0112] The load splitting request processing module 141 is used to receive the current instruction sent by the processor; and when it is determined that the current instruction is a load instruction, it sends the current instruction to the load splitting control module 142; and when it is determined that the current instruction is a first storage instruction, it sends the current instruction to the storage splitting control module 143.

[0113] Load the flow control module 142 to parse the current instruction and obtain the source address information, target address information and data length information corresponding to the current instruction.

[0114] The storage distribution control module 143 is used to parse the current instruction and obtain the source address information, target address information and data length information corresponding to the current instruction.

[0115] Address decoding module 144 is used to obtain the physical address information corresponding to the current instruction sent by the processor, and convert the original address information and target address information corresponding to the current instruction into physical address information;

[0116] The bus interface control module 145 is used to execute the current instruction based on the physical address information and data length information of the current instruction.

[0117] In this embodiment, the load shunting request processing module 141 receives load shunting requests from the RISC-V Core and monitors whether the load shunting control module 142 and the storage shunting control module 143 are idle. The load shunting control module 142 parses the relevant information of the Load instruction passed from the RISC-V Core, including the source address, destination address, and length of the Load instruction. The source address is a memory address, and the destination address is the internal buffer of the RISC-V Core. The storage shunting control module 143 parses the relevant information of the Store instruction passed from the RISC-V Core, including the source address, destination address, and length of the Store instruction. The source address is the RISC-V Core buffer space, and the destination address is a memory address. The address decoding module 144 performs the conversion between the virtual address and physical address of the Load / Store instruction because the RISC-V Core obtains a virtual address when executing Load or Store instructions, while physical addresses are required for memory operations. In this embodiment, the RISC-V Core also has a function: when a first interrupt handling request is received, within the same clock cycle, the current Load / Store instruction performs a physical address lookup in the Memory Management Unit (MMU) and synchronously sends the physical address to the address decoding module 144 of the synchronous execution module. The bus interface control module 145 generates the interface timing corresponding to the RISC-V Core interface or the memory bus interface. During the Load instruction, a read operation is initiated on the memory based on the translated physical address, and the read data is written back to the RISC-V Core's internal cache. During the Store instruction, data is read from the RISC-V Core's internal cache and written to the translated physical address to initiate a write operation on the memory.

[0118] In this embodiment, by setting the synchronous execution module to include multiple sub-modules, the multiple sub-modules can operate independently or jointly, which facilitates the faster implementation of the synchronous execution module's functions.

[0119] In some implementations, the interrupt controller 12 is further configured to acquire a second interrupt request sent by a second interrupt source, generate a second interrupt signal based on the acquired second interrupt request, and send the second interrupt signal to the processor 11.

[0120] The processor 11 is also configured to, in response to the acquisition of a second interrupt signal, send the second storage instruction of the interrupt handler to the synchronous execution module 14 for execution when the second storage instruction of the interrupt handler is acquired, and respond to the second interrupt signal.

[0121] In this embodiment, after the interrupt controller 12 transmits the first interrupt signal corresponding to the first interrupt source to the RISC-V Core, if the interrupt controller 12 receives the second interrupt request from the second interrupt source before the first interrupt signal has been processed, the interrupt controller 12 will still generate the second interrupt signal and transmit the second interrupt signal to the RISC-V Core.

[0122] In this embodiment, when the RISC-V Core receives the first interrupt signal from the interrupt controller 12 and executes the interrupt handler in response to the first interrupt signal, if it encounters a Store instruction (this instruction writes data from the RISC-V Core to memory, which is time-consuming, requiring hundreds of clock cycles for a single data transfer, while the Store instruction typically requires multiple data transfers), it will transfer the execution of the Store instruction in the interrupt handler to the synchronous execution module 14 for execution. This allows the RISC-V Core to continue responding to the second interrupt signal and executing the interrupt handler corresponding to the second interrupt signal (because the instruction fetching and decoding hardware units within the RISC-V Core are idle at this time). After the Load instruction corresponding to the first interrupt signal completes execution, the RISC-V Core saves the execution status of the instruction corresponding to the second interrupt signal and the values ​​of the relevant registers to the synchronous execution module 14, enabling the RISC-V Core to continue executing the interrupt handler corresponding to the first interrupt signal until the next Store instruction of the interrupt handler corresponding to the first interrupt signal is executed. Then, the RISC-V Core reloads the instruction status of the interrupt handler corresponding to the second interrupt signal and the values ​​of the relevant registers back into the RISC-V Core. The core then redirects the execution of the Store instruction corresponding to the first interrupt signal to the synchronous execution module 14 for processing.

[0123] In this implementation, the synchronous parallel execution of different interrupt handlers corresponding to different interrupt sources can be achieved, ensuring that high-priority interrupt requests and medium-priority interrupt requests can be responded to synchronously, both of which have high real-time performance, thereby further guaranteeing and improving the overall real-time performance of the RISC-V Core.

[0124] In an optional embodiment, the processor is further configured to count the frequency of interrupt requests initiated by different interrupt sources, and store the address of the interrupt handler corresponding to the target interrupt source whose interrupt request frequency is greater than a threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signal corresponding to the target interrupt source to the processor, it can synchronously send the address of the interrupt handler corresponding to the target interrupt source.

[0125] In this embodiment, to further accelerate the execution speed of interrupt handlers in the RISC-V Core, a new key function of the RISC-V Core is to monitor the frequency of interrupt requests from interrupt sources and copy the address of the interrupt handler with the most frequent interrupt requests (this address is in the interrupt vector table, in DDR memory) to the interrupt controller via L1 Cache. This allows the interrupt controller to simultaneously transmit the address of the corresponding interrupt handler to the RISC-V Core when transmitting the interrupt signal. This avoids the RISC-V Core having to query memory to obtain the interrupt handler address, a step that would take tens or even hundreds of clock cycles. This greatly speeds up the execution of interrupt handlers and further improves the real-time processing capabilities of the RISC-V CPU.

[0126] This application provides an interrupt control method based on a RISC-V architecture, applied to an interrupt control device based on a RISC-V architecture. The device includes a processor, an interrupt controller, and a data preparation module, such as... Figure 6 As shown, the interrupt control method based on the RISC-V architecture includes:

[0127] S601, the interrupt controller obtains the first interrupt request and enable information sent by the first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; it sends the enable information, data load address information and data load length information to the data preparation module; and generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor.

[0128] S602, the data preparation module loads the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information and data load length information.

[0129] S603: When the processor receives the first interrupt signal, after executing the current instruction of the general program, it suspends the general program; and responds to the first interrupt signal, executes the interrupt handler, and obtains the target data corresponding to the interrupt handler from the data preparation module.

[0130] For a detailed description of the embodiments of this application, please refer to the interrupt control device based on the RISC-V architecture in the above embodiments, which will not be repeated here.

[0131] The interrupt control method based on the RISC-V architecture provided in this application includes a processor, an interrupt controller, and a data preparation module. The interrupt controller receives a first interrupt request and enable information from a first interrupt source. Based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler. It then sends the enable information, data load address information, and data load length information to the data preparation module. Based on the received first interrupt request, it generates a first interrupt signal and sends the first interrupt signal to the processor. The data preparation module loads the target data corresponding to the interrupt handler from memory to the data preparation module based on the enable information, data load address information, and data load length information. The processor, upon receiving the first interrupt signal, suspends the general program after executing its current instructions. It then responds to the first interrupt signal by executing the interrupt handler and retrieves the target data corresponding to the interrupt handler from the data preparation module. Thus, while the processor executes the current instructions of the general program, the data preparation module can simultaneously load the target data required for the interrupt handler from memory. This eliminates the need for the processor to retrieve the target data from memory after executing the current instructions of the general program, significantly reducing the time required for the processor to obtain the interrupt handler's target data. This greatly improves the processor's execution speed of the interrupt handler, thereby accelerating the response speed to interrupt requests and enhancing the user experience.

[0132] In an optional embodiment, the interrupt controller, based on the interrupt source ID, counts the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request; based on the time interval and the time of the most recent interrupt request, predicts the time when the first interrupt source will send the next interrupt request; and if the predicted time for the first interrupt source to send the next interrupt request arrives and no first interrupt request is received from the first interrupt source, it generates enable information.

[0133] In an optional embodiment, the interrupt control method based on the RISC-V architecture further includes:

[0134] If the interrupt controller fails to receive the first interrupt request from the first interrupt source within the maximum time limit for the next interrupt request from the first interrupt source, it generates a deletion signal and sends the deletion signal to the data preparation module. This causes the data preparation module to stop loading the target data corresponding to the interrupt handler from memory into the data preparation module and delete the target data corresponding to the interrupt handler that has been loaded in the data preparation module.

[0135] In an optional embodiment, the interrupt controller includes an interrupt validity determination and priority determination module and an interrupt pre-parse address information table control module.

[0136] The interrupt validity and priority determination module obtains the first interrupt request and enable information sent by the first interrupt source; it sends the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parse address information table control module; and generates a first interrupt signal based on the obtained first interrupt request, and sends the first interrupt signal to the processor; the interrupt pre-parse address information table control module queries the data load address information and data load length information corresponding to the corresponding interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source; and sends the enable information, data load address information, and data load length information to the data preparation module.

[0137] In an optional embodiment, the interrupt controller further includes an interrupt prediction module; the interrupt control method based on the RISC-V architecture also includes:

[0138] The interrupt prediction module calculates the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request based on the interrupt source ID; predicts the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generates enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

[0139] In an optional embodiment, the data preparation module includes a control signal receiving and parsing module, a data loading module, a data caching module, and an interface module;

[0140] The control signal receiving and parsing module receives enable information, data load address information, and data load length information, and sends the data load address information and data load length information to the data loading module based on the enable information. The data loading module loads the target data corresponding to the interrupt handler from memory to the data cache module based on the data load address information and data load length information. The data cache module caches the target data corresponding to the interrupt handler. In response to the processor's read request, the interface module outputs the target data corresponding to the interrupt handler from the data cache module to the processor.

[0141] In an optional embodiment, the device further includes a synchronous execution module; the interrupt control method based on the RISC-V architecture further includes:

[0142] Before the processor finishes executing the current instruction of the general program, if it determines that the current instruction is a load instruction or a first store instruction, it sends the current instruction to the synchronous execution module for execution and responds to the first interrupt signal. The synchronous execution module executes the current instruction based on the source address information, target address information and data length information corresponding to the current instruction.

[0143] In an optional embodiment, the interrupt control method based on the RISC-V architecture further includes:

[0144] The interrupt controller receives the second interrupt request sent by the second interrupt source, generates a second interrupt signal based on the received second interrupt request, and sends the second interrupt signal to the processor. In response to receiving the second interrupt signal, the processor receives the second stored instruction of the interrupt handler, sends the second stored instruction to the synchronous execution module for execution, and responds to the second interrupt signal.

[0145] In an optional embodiment, the synchronous execution module includes a traffic splitting request processing module, a loading traffic splitting control module, a storage traffic splitting control module, an address decoding module, and a bus interface control module.

[0146] The load splitting request processing module receives the current instruction sent by the processor; and when it determines that the current instruction is a load instruction, it sends the current instruction to the load splitting control module; when it determines that the current instruction is a first storage instruction, it sends the current instruction to the storage splitting control module; the load splitting control module parses the current instruction to obtain the source address information, target address information, and data length information corresponding to the current instruction; the storage splitting control module parses the current instruction to obtain the source address information, target address information, and data length information corresponding to the current instruction; the address decoding module obtains the physical address information corresponding to the current instruction sent by the processor, and converts the source address information and target address information corresponding to the current instruction into physical address information; the bus interface control module executes the current instruction according to the physical address information and data length information of the current instruction.

[0147] In an optional embodiment, the interrupt control method based on the RISC-V architecture further includes:

[0148] The processor counts the frequency of interrupt requests from different interrupt sources and stores the address of the interrupt handler corresponding to the target interrupt source whose interrupt request frequency is greater than a threshold in the interrupt controller. This allows the interrupt controller to send the address of the interrupt handler corresponding to the target interrupt source to the processor at the same time as sending the interrupt signal corresponding to the target interrupt source.

[0149] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0150] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0151] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An interrupt control device based on a RISC-V architecture, characterized in that, include: Processor, interrupt controller, and data preparation module; The interrupt controller is used to acquire the first interrupt request and enable information sent by the first interrupt source; Based on the enable information and the interrupt source ID corresponding to the first interrupt source, the data loading address information and data loading length information of the corresponding interrupt handler are retrieved. The enable information, the data loading address information, and the data loading length information are sent to the data preparation module; and a first interrupt signal is generated based on the obtained first interrupt request and sent to the processor; The data preparation module is used to load the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, the data loading address information, and the data loading length information. The processor is used to receive the first interrupt signal and suspend the general program after executing the current instruction of the general program; In response to the first interrupt signal, the interrupt handler is executed to obtain the target data corresponding to the interrupt handler from the data preparation module; The interrupt controller is further configured to, based on the interrupt source ID, count the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request; based on the time interval and the time of the most recent interrupt request, predict the time of the next interrupt request sent by the first interrupt source; and generate the enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source. The interrupt controller is further configured to generate a deletion signal if it fails to receive the first interrupt request sent by the first interrupt source within the maximum time limit for the next interrupt request sent by the first interrupt source, and send the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handler from memory into the data preparation module, and deletes the target data corresponding to the interrupt handler that has been loaded in the data preparation module.

2. The interrupt control device based on RISC-V architecture according to claim 1, characterized in that, The interrupt controller includes an interrupt validity determination and priority determination module and an interrupt pre-parsed address information table control module; The interrupt validity determination and priority determination module is used to obtain the first interrupt request and enable information sent by the first interrupt source; send the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parse address information table control module; and generate a first interrupt signal based on the obtained first interrupt request and send the first interrupt signal to the processor. The interrupt pre-parse address information table control module is used to query the data loading address information and data loading length information of the corresponding interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source. The enable information, the data loading address information, and the data loading length information are sent to the data preparation module.

3. The interrupt control device based on RISC-V architecture according to claim 2, characterized in that, The interrupt controller also includes an interrupt prediction module; The interrupt prediction module is used to calculate the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request based on the interrupt source ID; predict the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generate the enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

4. The interrupt control device based on RISC-V architecture according to claim 1, characterized in that, The data preparation module includes a control signal receiving and parsing module, a data loading module, a data caching module, and an interface module; The control signal receiving and parsing module is used to receive the enable information, the data loading address information, and the data loading length information, and based on the enable information, send the data loading address information and the data loading length information to the data loading module. The data loading module is used to load the target data corresponding to the interrupt handler from memory to the data cache module based on the data loading address information and the data loading length information; The data caching module is used to cache the target data corresponding to the interrupt handler; The interface module is used to respond to the processor's read request by outputting the target data corresponding to the interrupt handler from the data cache module to the processor.

5. The interrupt control device based on RISC-V architecture according to claim 1, characterized in that, It also includes a synchronous execution module; Before executing the current instruction of the general program, the processor is further configured to, if it determines that the current instruction is a load instruction or a first store instruction, send the current instruction to the synchronous execution module for execution and respond to the first interrupt signal; The synchronous execution module is used to execute the current instruction based on the source address information, target address information, and data length information corresponding to the current instruction.

6. The interrupt control device based on RISC-V architecture according to claim 5, characterized in that, The interrupt controller is also configured to acquire a second interrupt request sent by a second interrupt source, generate a second interrupt signal based on the acquired second interrupt request, and send the second interrupt signal to the processor; The processor is further configured to, in response to receiving the second interrupt signal, send the second storage instruction to the synchronous execution module for execution when the second storage instruction of the interrupt handler is received, and respond to the second interrupt signal.

7. The interrupt control device based on RISC-V architecture according to claim 5, characterized in that, The synchronous execution module includes: The traffic splitting request processing module is used to receive the current instruction sent by the processor; and when it is determined that the current instruction is the load instruction, it sends the current instruction to the load traffic splitting control module; and when it is determined that the current instruction is the first storage instruction, it sends the current instruction to the storage traffic splitting control module. The load split control module is used to parse the current instruction to obtain the source address information, target address information and data length information corresponding to the current instruction; The storage splitting control module is used to parse the current instruction to obtain the source address information, target address information, and data length information corresponding to the current instruction; The address decoding module is used to obtain the physical address information corresponding to the current instruction sent by the processor, and convert the original address information and target address information corresponding to the current instruction into the physical address information; The bus interface control module is used to execute the current instruction based on the physical address information and the data length information of the current instruction.

8. The interrupt control device based on RISC-V architecture according to claim 1, characterized in that, The processor is also used to count the frequency of interrupt requests initiated by different interrupt sources, and store the address of the interrupt handler corresponding to the target interrupt source whose interrupt request frequency is greater than a threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signal corresponding to the target interrupt source to the processor, it can synchronously send the address of the interrupt handler corresponding to the target interrupt source.

9. An interrupt control method based on RISC-V architecture, characterized in that, An interrupt control device based on a RISC-V architecture, the device comprising a processor, an interrupt controller, and a data preparation module, wherein the method comprises: The interrupt controller obtains the first interrupt request and enable information sent by the first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data loading address information and data loading length information corresponding to the interrupt handler; it sends the enable information, the data loading address information and the data loading length information to the data preparation module; and it generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor. Based on the enable information, the data loading address information, and the data loading length information, the data preparation module loads the target data corresponding to the interrupt handler from memory into the data preparation module. Upon receiving the first interrupt signal, the processor suspends the general program after executing the current instruction of the general program; and in response to the first interrupt signal, executes the interrupt handler to obtain the target data corresponding to the interrupt handler from the data preparation module. The interrupt controller, based on the interrupt source ID, counts the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request; based on the time interval and the time of the most recent interrupt request, it predicts the time when the first interrupt source will send the next interrupt request; and if the predicted time for the next interrupt request from the first interrupt source arrives and no first interrupt request is received from the first interrupt source, it generates the enable information. If the interrupt controller does not receive the first interrupt request sent by the first interrupt source within the maximum time limit for the next interrupt request sent by the first interrupt source, it generates a deletion signal and sends the deletion signal to the data preparation module, so that the data preparation module stops loading the target data corresponding to the interrupt handler from memory into the data preparation module and deletes the target data corresponding to the interrupt handler that has been loaded in the data preparation module.

10. The interrupt control method based on RISC-V architecture according to claim 9, characterized in that, The interrupt controller includes an interrupt validity determination and priority determination module and an interrupt pre-parsed address information table control module; The interrupt validity determination and priority determination module obtains the first interrupt request and enable information sent by the first interrupt source; sends the enable information and the interrupt source ID corresponding to the first interrupt source to the interrupt pre-parse address information table control module; and generates a first interrupt signal based on the obtained first interrupt request and sends the first interrupt signal to the processor. The interrupt pre-parse address information table control module queries the data loading address information and data loading length information of the corresponding interrupt handler based on the enable information and the interrupt source ID corresponding to the first interrupt source. The enable information, the data loading address information, and the data loading length information are sent to the data preparation module.

11. The interrupt control method based on RISC-V architecture according to claim 10, characterized in that, The interrupt controller further includes an interrupt prediction module; the method further includes: The interrupt prediction module calculates the time interval between the first interrupt source sending interrupt requests and the time of the most recent interrupt request based on the interrupt source ID; predicts the time of the next interrupt request sent by the first interrupt source based on the time interval and the time of the most recent interrupt request; and generates the enable information when the predicted time of the next interrupt request sent by the first interrupt source arrives and no first interrupt request is received from the first interrupt source.

12. The interrupt control method based on RISC-V architecture according to claim 10, characterized in that, The data preparation module includes a control signal receiving and parsing module, a data loading module, a data caching module, and an interface module; The control signal receiving and parsing module receives the enable information, the data loading address information, and the data loading length information, and sends the data loading address information and the data loading length information to the data loading module based on the enable information; The data loading module loads the target data corresponding to the interrupt handler from memory to the data cache module based on the data loading address information and the data loading length information; The data caching module caches the target data corresponding to the interrupt handler; In response to a read request from the processor, the interface module outputs the target data corresponding to the interrupt handler from the data cache module to the processor.

13. The interrupt control method based on RISC-V architecture according to claim 9, characterized in that, The apparatus further includes a synchronization execution module; the method further includes: Before the processor finishes executing the current instruction of the general program, if it determines that the current instruction is a load instruction or a first store instruction, it sends the current instruction to the synchronous execution module for execution and responds to the first interrupt signal. The synchronous execution module executes the current instruction based on the source address information, target address information, and data length information corresponding to the current instruction.

14. The interrupt control method based on RISC-V architecture according to claim 13, characterized in that, Also includes: The interrupt controller receives a second interrupt request sent by a second interrupt source, generates a second interrupt signal based on the received second interrupt request, and sends the second interrupt signal to the processor; In response to receiving the second interrupt signal, the processor, upon receiving the second storage instruction of the interrupt handler, sends the second storage instruction to the synchronous execution module for execution and responds to the second interrupt signal.

15. The interrupt control method based on RISC-V architecture according to claim 13, characterized in that, The synchronous execution module includes a traffic splitting request processing module, a loading traffic splitting control module, a storage traffic splitting control module, an address decoding module, and a bus interface control module. The load splitting request processing module receives the current instruction sent by the processor; and when it determines that the current instruction is the load instruction, it sends the current instruction to the load splitting control module; and when it determines that the current instruction is the first storage instruction, it sends the current instruction to the storage splitting control module. The loading and routing control module parses the current instruction to obtain the source address information, target address information, and data length information corresponding to the current instruction; The storage splitting control module parses the current instruction to obtain the source address information, target address information, and data length information corresponding to the current instruction; The address decoding module obtains the physical address information corresponding to the current instruction sent by the processor, and converts the original address information and target address information corresponding to the current instruction into the physical address information; The bus interface control module executes the current instruction based on the physical address information and the data length information of the current instruction.

16. The interrupt control method based on RISC-V architecture according to claim 9, characterized in that, Also includes: The processor counts the frequency of interrupt requests initiated by different interrupt sources and stores the address of the interrupt handler corresponding to the target interrupt source whose interrupt request frequency is greater than a threshold in the interrupt controller, so that when the interrupt controller sends the interrupt signal corresponding to the target interrupt source to the processor, it can synchronously send the address of the interrupt handler corresponding to the target interrupt source.

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