Multi-core heterogeneous architecture chip operating system, inter-core communication method, system and device and medium

Abstract

The invention provides a multi-core heterogeneous architecture chip operating system, an inter-core communication method, system and device and a medium, and relates to the technical field of computers. The multi-core heterogeneous architecture chip operating system comprises a main control core and at least one heterogeneous core, a self-adaptive instruction conversion channel is arranged between the main control core and the heterogeneous core, the self-adaptive instruction conversion channel is constructed according to an instruction set of the main control core and an instruction set of the heterogeneous core, and the self-adaptive instruction conversion channel is used for performing instruction conversion in an inter-core communication process. A task allocation unit is arranged in the main control core, the task allocation unit is used for acquiring operation characteristic data of the heterogeneous cores to construct a resource allocation matrix, performing task allocation on the plurality of heterogeneous cores according to the resource allocation matrix, and issuing a task allocation instruction through a self-adaptive instruction conversion channel, and the operation characteristic data comprises load data. According to the invention, through instruction conversion of the adaptive instruction conversion channel, hybrid scheduling of different architectures can be realized, the utilization rate of heterogeneous cores is improved, and the load balancing deviation is reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a multi-core heterogeneous architecture chip operating system, an inter-core communication method, system, device, and medium. Background Art

[0002] In related technologies, the multi-core heterogeneous architecture chip operating system faces the following problems:

[0003] Insufficient cross-architecture instruction compatibility, the difference in instruction sets between the main control core and heterogeneous cores (such as NPU / DSP) leads to low task scheduling efficiency, and it is necessary to rely on a complex software layer conversion, increasing system latency; static resource allocation, the fixed resource allocation strategy cannot adapt to dynamic loads, resulting in energy efficiency waste. Summary of the Invention

[0004] The main purpose of the embodiments of the present disclosure is to propose a multi-core heterogeneous architecture chip operating system, an inter-core communication method, system, device, and medium, which can achieve hybrid scheduling of different architectures, reduce task migration latency, improve the utilization rate of heterogeneous cores, and reduce the load balancing deviation.

[0005] To achieve the above object, on the one hand, an embodiment of the present application proposes a multi-core heterogeneous architecture chip operating system, including a main control core and at least one heterogeneous core;

[0006] An adaptive instruction conversion channel is provided between the main control core and the heterogeneous core. The adaptive instruction conversion channel is constructed according to the instruction set of the main control core and the instruction set of the heterogeneous core, and the adaptive instruction conversion channel is used for instruction conversion during inter-core communication;

[0007] A task allocation unit is provided in the main control core. The task allocation unit is used to obtain the operation characteristic data of the heterogeneous core to construct a resource allocation matrix, allocate tasks to the plurality of heterogeneous cores according to the resource allocation matrix, and issue task allocation instructions through the adaptive instruction conversion channel. The operation characteristic data includes load data.

[0008] In some embodiments, the main control core includes a trusted computing unit, and the heterogeneous core includes an independent power supply domain;

[0009] The trusted computing unit is used to isolate key data by adjusting the configuration parameters of the independent power supply domain.

[0010] In some embodiments, the shared memory between the main control core and the heterogeneous core includes a real-time message area and a non-real-time message area;

[0011] The real-time message area is used to store the first type of data, and the real-time message area controls the transmission of the first type of data by using a two-level interrupt trigger mechanism;

[0012] The non-real-time message area is used to store the second type of data. The non-real-time message area uses the scattering writing technology to store the second type of data, where the first type of data is defined as transmission type data and the second type of data is defined as storage type data.

[0013] In some embodiments, the two-level interrupt triggering mechanism is used to trigger an interrupt for data transmission through a first-level interrupt signal and a second-level interrupt signal;

[0014] The first-level interrupt signal is used to control the transmission of emergency signals;

[0015] The second-level interrupt signal is used to control the transmission of batch data.

[0016] In some embodiments, the scattering writing technology is used to disperse a single data block and store it in multiple physical addresses, and exclusive-or check is used to check the data stored or transmitted.

[0017] On the other hand, an embodiment of the present invention proposes a method for inter-core communication of a multi-core heterogeneous architecture chip. The method for inter-core communication of the multi-core heterogeneous architecture chip is applied to the operating system of the multi-core heterogeneous architecture chip as described in the previous embodiments. The method for inter-core communication of the multi-core heterogeneous architecture chip includes the following steps:

[0018] Obtain the running characteristic data of the heterogeneous cores;

[0019] Use the running characteristic data of the heterogeneous cores to construct a resource allocation matrix;

[0020] Perform task allocation for multiple heterogeneous cores according to the resource allocation matrix, and issue a task allocation instruction through the adaptive instruction conversion channel.

[0021] In some embodiments, performing task allocation for multiple heterogeneous cores according to the resource allocation matrix includes the following steps:

[0022] Obtain a target task;

[0023] According to the load data in the resource allocation matrix, determine the heterogeneous core with lower load as the target core;

[0024] Allocate the target task to the target core and update the parameters of the resource allocation matrix.

[0025] In some embodiments, distinguish the type of the target task to determine whether the target task is a real-time task or a non-real-time task;

[0026] When the target task is a real-time task, according to the priority information of the target task, add the target task to the preemptive priority queue to wait for the preemptive priority queue to schedule the target task and allocate the target task to the target core;

[0027] When the target task is a non-real-time task, synchronize the memory mapping table through an atomic lock and allocate the target task to the target core.

[0028] On the other hand, an embodiment of the present invention provides an electronic device, including:

[0029] At least one processor;

[0030] At least one memory for storing at least one program;

[0031] When the at least one program is executed by the at least one processor, when the at least one program is executed by the at least one processor, at least one of the processors implements the inter-core communication method of the multi-core heterogeneous architecture chip as described in the previous embodiments.

[0032] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to make a computer execute the inter-core communication method of the multi-core heterogeneous architecture chip as described in the previous embodiments.

[0033] At least one of the above technical solutions of the present invention has at least the following advantages or beneficial effects:

[0034] Through the instruction conversion of the adaptive instruction conversion channel, it supports the mixed scheduling of different architectures and reduces the task migration delay. During the inter-core communication process, a resource allocation matrix is dynamically constructed, and tasks are allocated based on the computing power, bandwidth, etc. of heterogeneous cores, improving the utilization rate of heterogeneous cores. At the same time, the success rate of real-time task scheduling is increased, and the load balancing deviation is reduced. Description of the Drawings

[0035] Figure 1 It is a flowchart of an inter-core communication method of a multi-core heterogeneous architecture chip provided by an embodiment of the present application;

[0036] Figure 2 It is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present application. Detailed Embodiments

[0037] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] It should be noted that although the functional modules are divided in the device schematic diagram and the logical sequence is shown in the flowchart, in some cases, the steps shown or described may be executed in a different module division in the device or a different sequence in the flowchart. Terms such as "first" and "second" in the specification, claims and the above-mentioned drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0040] In the related multi-core heterogeneous architecture chip operating system, the differences in the instruction sets between the main control core and the heterogeneous cores (such as NPU / DSP) lead to low task scheduling efficiency, and it is necessary to rely on a complex software layer conversion, which increases the system latency; the inter-core communication efficiency is limited: the traditional shared memory mechanism does not distinguish between real-time and non-real-time tasks, and the data copy and synchronization lock competition result in a communication delay fluctuation exceeding 30%; the resource allocation is static: the fixed resource allocation strategy cannot adapt to dynamic loads, and the computing power, cache and bandwidth utilization rate of the heterogeneous cores are less than 50%, resulting in energy efficiency waste; the security isolation is weak: the key management and the power supply of the heterogeneous cores are not physically isolated, and side-channel attacks can steal sensitive data, and the system security is difficult to meet the requirements of high-security scenarios such as power grids.

[0041] Based on this, the embodiments of the present invention provide a multi-core heterogeneous architecture chip operating system, and the multi-core heterogeneous architecture chip operating system includes a main control core and at least one heterogeneous core;

[0042] An adaptive instruction conversion channel is provided between the main control core and the heterogeneous core. The adaptive instruction conversion channel is constructed according to the instruction set of the main control core and the instruction set of the heterogeneous core, and the adaptive instruction conversion channel is used to perform instruction conversion during the inter-core communication process;

[0043] A task allocation unit is provided in the main control core. The task allocation unit is used to obtain the operation characteristic data of the heterogeneous core to construct a resource allocation matrix, allocate tasks to multiple heterogeneous cores according to the resource allocation matrix, and issue task allocation instructions through the adaptive instruction conversion channel. The operation characteristic data includes load data.

[0044] The main control core and the heterogeneous core usually have different instruction set architectures. The instruction set is a set of instructions that a processor can execute, and it defines the types of operations that the processor can perform, such as arithmetic operations, logical operations, data transmission, etc.

[0045] Due to the different instruction sets of the main control core and heterogeneous cores, during inter-core communication, directly transmitting instructions may cause the heterogeneous cores to be unable to understand and execute them. Therefore, an adaptive instruction conversion channel is constructed according to the instruction sets of the two. This channel can convert the instructions of the main control core into an instruction format that the heterogeneous cores can recognize and execute when the main control core sends instructions to the heterogeneous cores.

[0046] The task allocation unit in the main control core, whose main function is to obtain the running characteristic data of the heterogeneous cores, such as load data. Based on these running characteristic data, a resource allocation matrix is constructed, which can describe the resource usage of the heterogeneous cores. The task allocation unit allocates tasks to multiple heterogeneous cores according to the resource allocation matrix, and reasonably distributes different tasks to each heterogeneous core for execution to fully utilize the performance of the heterogeneous cores. The task allocation instructions are sent through the adaptive instruction conversion channel, enabling the heterogeneous cores to correctly receive and execute the task allocation instructions.

[0047] The instruction conversion in the traditional software layer (such as compiler translation, virtual machine instruction conversion) is completely completed at the software level, while this embodiment is a hybrid solution of hardware and software co-design. An instruction channel is established through the hardware abstraction layer, making the instruction conversion faster and more efficient.

[0048] In some embodiments, the main control core establishes an adaptive instruction conversion channel with the heterogeneous cores through the hardware abstraction layer, generating a variable-length instruction set carrying dynamic operation codes and security identifiers.

[0049] The hardware abstraction layer provides basic support for the establishment and operation of the instruction conversion channel. The Hardware Abstraction Layer (HAL) is located between the hardware and software, and its role is to shield the specific details of the hardware and provide a unified interface for the upper-layer software. Through the hardware abstraction layer, the hardware characteristics of different cores can be abstracted, thus building a bridge for instruction conversion between different instruction sets, and achieving efficient cross-architecture collaboration.

[0050] The opcode conversion module is a part of the instruction conversion channel, mainly responsible for converting and optimizing the operation codes of the instructions. The opcode conversion module can perform adaptive code optimization according to the target core architecture characteristics.

[0051] The operation code can be dynamically adjusted according to different task requirements and the architecture characteristics of the target core; the security identifier can provide security guarantees for the transmission and execution of instructions, preventing the injection of illegal instructions and malicious attacks.

[0052] According to the task requirements, the real-time state of the target heterogeneous core, and the hardware resource situation, the adaptive instruction conversion channel generates a variable-length instruction set. The variable-length instruction set can achieve mixed scheduling for architectures such as ARM and RISC-V, reducing task migration latency.

[0053] In some embodiments, the instruction set conversion interface (adaptive instruction conversion channel) supports binary mutual conversion between RV32IMC extension instructions and Thumb-2 instruction sets, and the conversion latency is controlled within 5 clock cycles; a standardized API interface is provided to encapsulate inter-core communication, memory allocation, and interrupt control functions, supporting mixed programming calls in C / C++ and Python.

[0054] In some embodiments, the main control core includes a trusted computing unit, and the heterogeneous core includes an independent power supply domain. The trusted computing unit is used to isolate key data by adjusting the configuration parameters of the independent power supply domain.

[0055] Side-channel attack means an attack method that measures and analyzes physical information such as power consumption, electromagnetic radiation, and time consumption (i.e., side-channel information) generated during the operation of a cryptographic device, extracts information related to the key from it, and then obtains sensitive data.

[0056] The trusted computing unit can provide security services such as authentication and data encryption, building a trusted operating environment for the system. By adjusting the configuration parameters (such as voltage, current, etc.) of the independent power supply domain, the trusted computing unit can control the power state of the heterogeneous core. For example, when abnormal traffic is detected, a traffic shaping algorithm is enabled to limit the bandwidth of non-critical tasks, and the encryption computing power is enhanced by increasing the voltage of the NPU core.

[0057] The configuration of the independent power supply domain enables the system to achieve more refined resource isolation and security control, improving the overall security and reliability of the system. By independently controlling the power supply of each heterogeneous core, the system can flexibly adjust the power state of each core according to actual task requirements and security requirements, achieving more efficient power consumption management.

[0058] In some embodiments, a trusted execution environment (Trusted Execution Environment, TEE) is partitioned in the main control core. The trusted execution environment is used for key management, and an independent power supply domain is set in the heterogeneous core. The main control core dynamically adjusts the core voltage and clock frequency of the independent power supply domain of the heterogeneous core based on a dual-loop feedback mechanism, controlling the deviation of the system energy efficiency ratio within 5%.

[0059] A physical isolation bus is set between the trusted execution environment and the ordinary execution environment. The key synchronization uses a physically unclonable function to generate a dynamic fingerprint, which is updated every 30 seconds; the TEE environment and the physical isolation bus block more than 90% of side-channel attacks, and the dynamic key update mechanism reduces the key leakage risk by 70%.

[0060] The independent power supply domain of the heterogeneous core is configured with an overvoltage protection module. When the voltage fluctuation exceeds ±5%, dynamic frequency scaling is triggered and an abnormal log is recorded.

[0061] Deploy dynamic key management in a trusted execution environment (TEE), and combine a dual-loop feedback mechanism to regulate the core voltage and frequency, so that the system energy efficiency deviation ≤ 5%. The dual-loop feedback mechanism is combined with independent power supply domain control to achieve a 18% reduction in power consumption and a computing power density increase to 12 TOPS / W in the power grid monitoring scenario.

[0062] In some embodiments, the shared memory between the main control core and the heterogeneous cores includes a real-time message area and a non-real-time message area;

[0063] The real-time message area is used to store the first type of data, and the real-time message area adopts a two-level interrupt trigger mechanism to control the transmission of the first type of data;

[0064] The non-real-time message area is used to store the second type of data, and the non-real-time message area uses a scatter write technology to store the second type of data. Among them, the first type of data is defined as transmission type data, and the second type of data is defined as storage type data.

[0065] Transmission type data needs to be processed and transmitted in a timely and rapid manner. After this data is generated, it needs to be acquired and processed by the processor. Otherwise, it may lead to the loss of important information or the delay of system response, thus affecting the normal operation of the entire system. For example, in an autonomous driving system, the road conditions, obstacle information, etc. obtained in real time by sensors such as cameras and radars. These data all need to be quickly transmitted to the processing unit for analysis and decision-making to ensure the safe driving of the vehicle.

[0066] Storage type data has relatively low requirements for transmission real-time and does not need to be processed immediately, such as historical records, backup data, etc. Although these data also need to be recorded when they are generated, they do not need to be processed immediately, but will be used when subsequent data analysis and fault troubleshooting are required.

[0067] The main control core and the heterogeneous cores communicate and interact with each other through the shared memory. Dividing the shared memory into a real-time message area and a non-real-time message area is a distinction based on the different time sensitivities of the messages. The real-time message area stores messages that have strict time requirements and need to be processed immediately, such as control instructions, emergency status feedback, etc.; the non-real-time message area stores messages that are not so urgent in terms of time, such as system log records, data backup instructions, etc.

[0068] By dividing the shared memory into a real-time message area and a non-real-time message area, real-time messages can be quickly responded to and transmitted, and non-real-time messages can also be processed at an appropriate time, improving the system's processing efficiency and ability for different types of messages, reducing the number of data copies, and making the emergency task response delay less than 10 μs.

[0069] In some embodiments, a two - level interrupt triggering mechanism is used to trigger an interrupt for data transmission through a first - level interrupt signal and a second - level interrupt signal;

[0070] The first - level interrupt signal is used to control the transmission of emergency signals;

[0071] The second - level interrupt signal is used to control the transmission of bulk data.

[0072] The first - level interrupt signal is used for the transmission of emergency signals (such as hardware failures, real - time sensor data acquisition, etc.). It can achieve sub - microsecond - level delay through hardware register flag bits or dedicated interrupt channels, enabling the processor to immediately pause the current task and give priority to processing emergency signals.

[0073] The second - level interrupt signal is used for the transmission of bulk data (such as file reading and writing, bulk network data sending and receiving). Its priority is relatively low and can be implemented through software scheduling or DMA (Direct Memory Access) technology. It allows the system to centrally process a large amount of data when resources are idle, which can reduce the additional overhead caused by multiple small - data transmissions and avoid competing with emergency tasks for hardware resources.

[0074] In some embodiments, the data transmission in the real - time message area adopts a two - level interrupt triggering mechanism: the first level realizes the transmission of emergency signals with a <10μs delay through register flag bits, and the second level adopts a bulk data transmission interrupt, and the buffer filling threshold can be set to 80%.

[0075] In some embodiments, the scatter - write technology is used to disperse a single data block and store it in multiple physical addresses, and XOR checksum is used to verify the data during storage or transmission.

[0076] Rather than storing a data block completely in a continuous physical address space, it is dispersed for storage. By dispersing the storage of a single data block, the storage redundancy and security of the data are increased. In data verification, XOR (exclusive - or) checksum can generate a checksum value by performing a specific XOR operation on the stored data. When reading the data, the same XOR operation is performed again on the read data, and the generated checksum value is compared with the previously stored checksum value. If they are not equal, it indicates that the data may be damaged or tampered with.

[0077] In some embodiments, the scatter - write technology is deployed in the non - real - time message area to disperse a single data block and store it in 8 physical addresses, and XOR checksum is used to prevent buffer - overflow attacks.

[0078] A buffer overflow attack is an attack where an attacker takes advantage of a vulnerability in a program's lax buffer boundary checking to write data exceeding its capacity into the buffer, thereby overwriting adjacent memory areas, which may lead to consequences such as program crashes and execution of malicious code. After adopting XOR verification in the non-real-time message area, since the stored data is verified, if an attacker attempts to tamper with the data through a buffer overflow attack, a mismatch in the verification value will be found during XOR verification, thus promptly detecting the attack behavior and taking corresponding measures.

[0079] Please refer to Figure 1 , Figure 1 FIG. is an optional flowchart of an inter-core communication method for a multi-core heterogeneous architecture chip provided by some embodiments of the present application. The inter-core communication method for a multi-core heterogeneous architecture chip is applied to the multi-core heterogeneous architecture chip operating system as in the previous embodiments. An inter-core communication method for a multi-core heterogeneous architecture chip according to an embodiment of the present invention includes but is not limited to steps S100 to S300:

[0080] Step S100, obtaining operation characteristic data of heterogeneous cores;

[0081] Step S200, constructing a resource allocation matrix using the operation characteristic data of heterogeneous cores;

[0082] Step S300, performing task allocation on multiple heterogeneous cores according to the resource allocation matrix, and issuing a task allocation instruction through an adaptive instruction conversion channel.

[0083] In step S100 of some embodiments, the heterogeneous cores have different architectures and functions, and their operation characteristic data reflects their current working states and performance. Such data includes but is not limited to load data (such as CPU usage rate, memory occupancy rate, etc.), operating frequency, etc. Through specific monitoring mechanisms and sensors, the system can obtain this data in real time.

[0084] In step S200 of some embodiments, the resource allocation matrix is a multi-dimensional data structure used to quantify the resource states and task allocation strategies of heterogeneous cores. Based on real-time operation characteristics, usually including dimensions such as computing power, storage capacity, communication bandwidth, power consumption, etc., each dimension corresponds to a resource attribute of a heterogeneous core. The real-time collected operation characteristics are converted into values in the matrix.

[0085] In step S300 of some embodiments, based on the constructed resource allocation matrix, the system can evaluate the resource availability of each heterogeneous core and the types of tasks suitable for execution, and reasonably allocate multiple tasks to each heterogeneous core. The goal of task allocation is to make full use of the performance advantages of heterogeneous cores, achieve load balancing, and improve the overall efficiency of the system. After the allocation is completed, the task allocation instructions are sent to the corresponding heterogeneous cores through the adaptive instruction conversion channel. Since the instruction sets of the main control core and the heterogeneous cores may be different, the adaptive instruction conversion channel will convert the instructions of the main control core into an instruction format that the heterogeneous cores can understand and execute.

[0086] Reasonable task allocation can make full use of the performance advantages of heterogeneous cores, achieve load balancing, and improve the overall processing capacity and response speed of the system. Through the adaptive instruction conversion channel, the main control core and heterogeneous cores with different instruction set architectures can work together, enhancing the flexibility and scalability of the system. The construction of the resource allocation matrix enables the system to more accurately understand the resource usage of heterogeneous cores, thereby realizing the optimal configuration of resources and improving the resource utilization rate.

[0087] In some embodiments, the main control core constructs a three-dimensional resource allocation matrix based on the operation characteristic data of the heterogeneous cores, classifies and configures different types of resources through three dimensions (X, Y, and Z axes), where the X axis can represent the type of security core, the Y axis can represent the encrypted storage area, and the Z axis can represent the channel communication bandwidth.

[0088] In some embodiments, step S300 may include but is not limited to steps S310 to S330:

[0089] Step S310, obtain the target task;

[0090] Step S320, according to the load data in the resource allocation matrix, determine the heterogeneous core with lower load as the target core;

[0091] Step S330, allocate the target task to the target core and update the parameters of the resource allocation matrix.

[0092] In steps S310 to S330 of some embodiments, the load data of each heterogeneous core (such as information reflecting the current workload of the core, such as CPU usage rate, memory occupancy rate, etc.) is recorded in the resource allocation matrix. By analyzing this load data, the heterogeneous core with lower load is screened out and determined as the target core. For example, if the memory occupancy rate of a certain core is 20% while the memory occupancy rates of other cores are 70%, then this core will be determined as a low-load core. The target task is allocated to this target core to start executing the task, and at the same time, the relevant parameters of the resource allocation matrix are updated, so that the resource allocation matrix can reflect the changes in the system resource status in real time.

[0093] If the task allocation is unreasonable, it is easy to have a situation where some heterogeneous cores are overloaded while other cores are underloaded, resulting in a decline in the overall system performance. By selecting heterogeneous cores with lower loads according to the load data to allocate tasks, the utilization rate of system resources can be improved.

[0094] In some embodiments, the initial task weight is an important basis for task allocation. When allocating tasks according to the resource allocation matrix, the initial task weight will affect the final allocation decision. Tasks with higher weights will be preferentially allocated to suitable heterogeneous cores. For example, if the resource allocation matrix shows that a certain heterogeneous core has high computing power and low current load, then for compute-intensive tasks, the initial task weight corresponding to this heterogeneous core is higher.

[0095] The master core can calculate the initial weight of the task based on the task type. The expression of the initial weight is:

[0096] W i = α·C compute + β·B memory + γ·D latency

[0097] Where α, β, and γ are core type adaptation coefficients, dynamically adjusted through historical load data; Wi is the initial weight of the task, C computer is the host weight, B memory is the memory weight, D latency is the latency weight.

[0098] In some embodiments, when the master core detects that the CRC error rate of the communication channel between the master core and the heterogeneous core > 0.1%, the master core automatically reduces the Z-axis bandwidth weight to 0.8 and enables the backup channel.

[0099] In some embodiments, step S330 may include but is not limited to steps S331 to S333:

[0100] Step S331, distinguish the type of the target task to determine whether the target task is a real-time task or a non-real-time task;

[0101] Step S332, when the target task is a real-time task, according to the priority information of the target task, add the target task to the preemptive priority queue to wait for the preemptive priority queue to schedule the target task and allocate the target task to the target core;

[0102] Step S333, when the target task is a non-real-time task, synchronize the memory mapping table through an atomic lock and allocate the target task to the target core.

[0103] In steps S331 to S333 of some embodiments, according to the sensitivity of the target task to time, it is divided into real-time tasks and non-real-time tasks.

[0104] After determining that the target task is a real-time task, the system will add it to the preemptive priority queue according to the priority information of the task. The tasks are sorted according to their priorities, and the tasks with higher priorities will be executed first. If at a certain moment, a task with a higher priority appears in the queue, the currently executing low-priority task will be suspended, and the CPU resources will be allocated to the high-priority task.

[0105] For non-real-time tasks, the system synchronizes the memory mapping table through an atomic lock. The memory mapping table is a data structure used to record the mapping relationship between virtual addresses and physical addresses. In a multi-tasking environment, multiple tasks may access and modify the memory mapping table simultaneously, which may lead to data inconsistency problems. An atomic lock is a synchronization mechanism that can ensure that only one task can access and modify the memory mapping table at the same time, thus avoiding data competition and inconsistency. After synchronizing the memory mapping table through the atomic lock, the system allocates non-real-time tasks to the target core for execution.

[0106] The scheduling mechanism of the preemptive priority queue can ensure that it is executed in a timely manner when it has a high priority, improving the system's response ability to real-time events and enhancing the real-time performance of the system. By synchronizing the memory mapping table through an atomic lock, the data competition problem when non-real-time tasks access the memory mapping table in a multi-tasking environment is solved, ensuring data consistency and integrity, and improving the stability and reliability of the system. Different types of tasks can be processed under a scheduling mechanism suitable for them, avoiding waste of resources and backlog of tasks.

[0107] In some embodiments, a preemptive priority queue is allocated for real-time tasks, and the round-robin algorithm is adopted. The maximum occupation duration of a single task can be set to 2 ms.

[0108] When non-real-time tasks are migrated, the source core and the target core synchronize the memory mapping table through an atomic lock, and update the Y-axis cache capacity of the resource allocation matrix after the migration is completed.

[0109] In some embodiments, the task type is identified. Computation-intensive tasks are preferentially allocated to the NPU core and occupy 70% of the Z-axis bandwidth of the resource allocation matrix exclusively; IO-intensive tasks are processed cooperatively by the DSP core and the CPU core, and the data throughput rate is increased by more than 30% through the dynamic expansion mechanism of the Y-axis cache capacity of the resource allocation matrix.

[0110] The embodiments of the present application at least include the following beneficial effects:

[0111] Task scheduling efficiency improvement: Through the dynamic resource allocation matrix and atomic operation migration strategy, the success rate of real-time task scheduling is increased by 40%, and the load balancing deviation is controlled within ±10%;

[0112] Significant reduction in communication latency: By adopting a circular buffer and a two-level interrupt mechanism, the transmission latency of key control instructions is compressed to 1 / 5 of the original scheme, meeting the 2ms real-time requirement of industrial control scenarios;

[0113] Enhanced system security: The TEE environment and the physical isolation bus block more than 90% of side-channel attacks, and the dynamic key update mechanism reduces the key leakage risk by 70%;

[0114] Breakthrough in energy efficiency optimization: The dual-loop feedback mechanism combined with independent power supply domain control achieves a 18% reduction in power consumption and a 12TOPS / W increase in computing power density in the power grid monitoring scenario.

[0115] In some embodiments, in the scenario of power grid monitoring system security protection.

[0116] Task classification and heterogeneous core scheduling:

[0117] The main control core (ARM Cortex-A72) analyzes the power grid monitoring data stream, identifies encrypted communication (computing-intensive) and anomaly detection (real-time <5ms) tasks, and allocates them to the NPU core and the RISC-V coprocessor respectively;

[0118] Construct a three-dimensional resource allocation matrix: The X-axis divides the security core types (ARM / RISC-V), the Y-axis configures the encrypted storage area (128MB ECC memory), and the Z-axis allocates the dual-channel communication bandwidth (main channel 32Gbps, backup channel 16Gbps).

[0119] Real-time communication and security isolation:

[0120] Encrypted data is transmitted through the TXVring buffer, encrypted using the AES-256 algorithm, and each frame is appended with a CRC32 checksum. When the check fails, the backup channel is switched to retransmit;

[0121] A trusted execution environment (TEE) is partitioned in the NPU core, and the key management module communicates with the main control core through a physical isolation bus to block side-channel attacks.

[0122] Dynamic defense and energy efficiency optimization:

[0123] When abnormal traffic (packet rate >50% threshold) is detected, the traffic shaping algorithm is enabled to limit the bandwidth of non-critical tasks, and the voltage of the NPU core is adjusted through dual-loop feedback (1.0V → 1.2V) to increase the encryption computing power by 25%;

[0124] The main control core sends a heartbeat packet to the TEE every 30 seconds. If no response is received within the timeout period, it triggers an inter-core reset, reconstructs the resource matrix, and resets the communication channel.

[0125] In some embodiments, in the scenario of edge security protection for smart meters.

[0126] Lightweight security protocol design:

[0127] Run the LWC-SHA3 protocol on the Cortex-M4 core to generate a 128-bit hash fingerprint for the meter measurement data, store it in the secure Flash area, and dynamically update the SM4 algorithm key through the PUF every 15 minutes;

[0128] Adopt the scattering writing technology to disperse and store the key data in 8 physical addresses to prevent buffer overflow attacks.

[0129] Multi-level intrusion detection:

[0130] Hardware layer detection: The RISC-V core monitors the GPIO level jump, triggers port locking after identifying a short circuit attack, and the response time < 2ms;

[0131] Protocol layer filtering: The main control core deploys a Modbus protocol whitelist to intercept illegal function code requests, and encrypts and uploads the violation logs to the cloud.

[0132] Anti-attack and self-healing mechanism:

[0133] Dynamic clock jitter (48 - 72MHz) interferes with power consumption analysis attacks, and the power supply of idle cores is turned off through gated clocks to reduce the risk of side-channel leakage;

[0134] Dual-core mutual inspection mechanism: The main control core and the coprocessor exchange check codes every 10ms. After 3 consecutive failures, the firmware is loaded from the read-only secure area, and the recovery time < 500ms.

[0135] The following combines Figure 2 to introduce the electronic device of the embodiment of the present application in detail.

[0136] As Figure 2 , Figure 2 illustrates the hardware structure of the electronic device in another embodiment. The electronic device includes:

[0137] A processor 1100, which can be implemented in ways such as a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present disclosure;

[0138] The memory 1200 can be implemented in the form of a Read Only Memory (ROM), a static storage device, a dynamic storage device, or a Random Access Memory (RAM), etc. The memory 1200 can store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 1200 and are called by the processor 1100 to execute the inter-core communication method of the multi-core heterogeneous architecture chip in the embodiments of the present disclosure;

[0139] The input / output interface 1300 is used to implement information input and output;

[0140] The communication interface 1400 is used to implement communication and interaction between this device and other devices. It can communicate through a wired manner (such as USB, network cable, etc.) or through a wireless manner (such as mobile network, WIFI, Bluetooth, etc.);

[0141] The bus 1500 transmits information between the various components of the device (such as the processor 1100, the memory 1200, the input / output interface 1300, and the communication interface 1400);

[0142] Among them, the processor 1100, the memory 1200, the input / output interface 1300, and the communication interface 1400 are communicatively connected to each other inside the device through the bus 1500.

[0143] The embodiments of the present disclosure also provide a storage medium, which is a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute the above-mentioned inter-core communication method of the multi-core heterogeneous architecture chip.

[0144] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory can include memories remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0145] The embodiments described in the embodiments of the present disclosure are to more clearly illustrate the technical solutions of the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions provided by the embodiments of the present disclosure. Those skilled in the art will know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present disclosure are equally applicable to similar technical problems.

[0146] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present disclosure, and may include more or fewer steps than shown in the figures, or combine certain steps, or different steps.

[0147] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations.

[0149] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0150] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (one) of the following" or similar expressions refer to any combination of these items, including any combination of single items (ones) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0151] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0152] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0153] In addition, in each embodiment of this application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0154] When an integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing an electronic device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media that can store programs, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs.

[0155] The preferred embodiments of the present disclosure have been described above with reference to the accompanying drawings. This does not limit the scope of rights of the embodiments of the present disclosure. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present disclosure shall fall within the scope of rights of the embodiments of the present disclosure.

Claims

1. A multi-core heterogeneous architecture chip operating system, characterized in that, The multi-core heterogeneous architecture chip operating system includes a main control core and at least one heterogeneous core; An adaptive instruction conversion channel is provided between the main control core and the heterogeneous core. The adaptive instruction conversion channel is constructed according to the instruction set of the main control core and the instruction set of the heterogeneous core, and is used for instruction conversion during inter-core communication; A task allocation unit is provided in the main control core. The task allocation unit is used to obtain the operation characteristic data of the heterogeneous core to construct a resource allocation matrix, allocate tasks to multiple heterogeneous cores according to the resource allocation matrix, and issue task allocation instructions through the adaptive instruction conversion channel. The operation characteristic data includes load data.

2. The multi-core heterogeneous architecture chip operating system according to claim 1, wherein The main control core includes a trusted computing unit, and the heterogeneous core includes an independent power supply domain; The trusted computing unit is used to isolate key data by adjusting the configuration parameters of the independent power supply domain.

3. The multi-core heterogeneous architecture chip operating system according to claim 1, characterized in that The shared memory between the main control core and the heterogeneous core includes a real-time message area and a non-real-time message area; The real-time message area is used to store the first type of data, and the real-time message area uses a two-level interrupt trigger mechanism to control the transmission of the first type of data; The non-real-time message area is used to store the second type of data, and the non-real-time message area uses a scatter write technology to store the second type of data. Among them, the first type of data is defined as transmission type data, and the second type of data is defined as storage type data.

4. The multi-core heterogeneous architecture chip operating system according to claim 3, characterized in that, The two-level interrupt trigger mechanism is used to trigger an interrupt for data transmission through a first-level interrupt signal and a second-level interrupt signal; The first-level interrupt signal is used to control the transmission of emergency signals; The second-level interrupt signal is used to control the transmission of batch data.

5. The multi-core heterogeneous architecture chip operating system according to claim 3, wherein The scatter write technology is used to disperse a single data block and store it in multiple physical addresses, and uses exclusive-or checksum to check the data stored or transmitted.

6. A method for inter-core communication of a multi-core heterogeneous architecture chip, characterized in that, The multi-core heterogeneous architecture chip inter-core communication method is applied to the multi-core heterogeneous architecture chip operating system according to any one of claims 1-5. The multi-core heterogeneous architecture chip inter-core communication method includes the following steps: Obtain the operation characteristic data of the heterogeneous core; Use the operation characteristic data of the heterogeneous core to construct a resource allocation matrix; Allocate tasks to multiple heterogeneous cores according to the resource allocation matrix, and issue task allocation instructions through the adaptive instruction conversion channel.

7. The method for inter-core communication of a multi-core heterogeneous architecture chip according to claim 6, wherein The step of allocating tasks to multiple heterogeneous cores according to the resource allocation matrix includes the following steps: Obtain a target task; According to the load data in the resource allocation matrix, determine the heterogeneous core with lower load as the target core; Allocate the target task to the target core and update the parameters of the resource allocation matrix.

8. The method for inter-core communication of a multi-core heterogeneous architecture chip according to claim 7, wherein, The step of allocating the target task to the target core includes the following steps: Distinguish the type of the target task to determine whether the target task is a real-time task or a non-real-time task; When the target task is a real-time task, according to the priority information of the target task, add the target task to the preemptive priority queue to wait for the preemptive priority queue to schedule the target task and allocate the target task to the target core; When the target task is a non-real-time task, synchronize the memory mapping table through an atomic lock, and allocate the target task to the target core.

9. An electronic device, characterized in that, Comprising: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, enabling the at least one processor to implement the inter-core communication method of the multi-core heterogeneous architecture chip as described in any one of claims 6-8.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that, The program executable by the processor, when executed by the processor, is used to implement the inter-core communication method of the multi-core heterogeneous architecture chip as described in any one of claims 6-8.

Images