Data transfer system and image processing device
By introducing a public cache module and a reference counting mechanism, the problem of low data flow efficiency between image processing modules is solved, and one-to-many transmission between upstream modules and downstream modules is realized, which improves data flow efficiency and system stability.
Patent Information
- Application Number
- CN202510582136.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2025-08-01
AI Technical Summary
In the prior art, data flow between image processing modules is inefficient and control logic is complex, resulting in inefficient data flow.
The public cache module is introduced to manage the use of cache blocks through the reference counting mechanism, allowing one-to-many transmission between the upstream module and the downstream module, and managing the number of references of the cache blocks through preset identification and interrupt information to achieve efficient control of data flow.
It improves data flow efficiency, simplifies control logic, reduces the complexity of memory management, and improves cache utilization and data flow system stability.
Smart Images
Figure CN120407238A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of data processing technology, and in particular to a data flow system and an image processing device. Background Art
[0002] For example, when processing image data, image processing devices such as security equipment can collect image data of the target area through image sensors, and the internal image processing module optimizes the image data in a pipeline processing manner, and finally outputs the optimized image data to a module or device with real functions to display the image corresponding to the image data.
[0003] Adjacent modules within a security device can be considered upstream and downstream modules. When transmitting data to a downstream module, an upstream module can access a free buffer from its own free buffer queue and store the data there for easy access by the downstream module. The downstream module can then access the ready buffer from the upstream module's ready buffer queue to retrieve the target data. After the downstream module has finished using the ready buffer, the upstream module releases the ready buffer and returns it to the free buffer queue.
[0004] This approach enables data flow between image processing modules, but a single piece of data from an upstream module cannot be accessed by multiple downstream modules simultaneously. Furthermore, when downstream modules execute tasks based on data in the upstream module's ready queue, they must consider when the upstream module destroys the ready queue. This complicates control logic and can lead to inefficient data flow between image processing modules. Summary of the Invention
[0005] The present application provides a data flow system and an image processing device to solve the problem of low data flow efficiency between image processing modules.
[0006] In a first aspect, some embodiments of the present application provide a data flow system, comprising: an upstream module, at least one downstream module, and a public cache module;
[0007] The upstream module is configured to: call the target cache block from the public cache module, and generate first interrupt information; the first interrupt information is used to increase the number of references of the target cache block by 1;
[0008] Storing target data into the target cache block;
[0009] Sending a preset identifier for characterizing the target cache block to the downstream module, and generating second interrupt information when the sending is completed; the second interrupt information is used to reduce the number of references of the target cache block by 1;
[0010] The downstream module is configured to: when receiving the preset identifier, generate a first interrupt message to increment the reference count of the target cache block by 1;
[0011] Obtain the target data in the target cache block according to the preset identifier;
[0012] After the target task is completed according to the target data, generate a second interrupt message to decrement the reference count of the target cache block by 1;
[0013] The common cache module is configured to: when detecting that the reference count of the target cache block returns to zero from a non-zero number, release the target cache block.
[0014] In some feasible embodiments, the cache capacities of the cache blocks partitioned in different common cache modules are different. Before the upstream module executes to call a target cache block from the common cache module, it is further configured to:
[0015] Determine a target cache block for caching the target data according to the data volume of the target data; the cache capacity of the target cache block is greater than or equal to the data volume of the target data; the difference between the cache capacity of the target cache block and the data volume of the target data is less than the difference between the data volume of other cache blocks and the data volume of the target data;
[0016] Determine the common cache module according to the cache capacity of the target cache block.
[0017] In some feasible embodiments, when the upstream module executes to send a preset identifier for characterizing the target cache to the downstream module, it is further configured to:
[0018] Obtain a preset binding relationship from the common cache module; the preset binding relationship includes at least one downstream module bound to the upstream module;
[0019] Call a target function corresponding to at least one downstream module from the common cache module according to the preset binding relationship; wherein, different downstream modules correspond to different target functions;
[0020] Add the preset identifier to the target function;
[0021] Send the target function including the preset identifier to at least one downstream module.
[0022] In some feasible embodiments, the common cache module includes a preset array, and the array units in the preset array are used to record target function pointers; the target function pointers are used to characterize that there is a registered target function between the upstream module and the downstream module;
[0023] Before the upstream module executes the step of calling, from the common cache module, a target function corresponding to at least one downstream module according to the preset binding relationship, the upstream module is further configured to:
[0024] Check whether the array cell corresponding to the bound downstream module contains the target function pointer;
[0025] If the array cell corresponding to the downstream module contains the target function pointer, call the target function corresponding to the target function pointer;
[0026] If the array cell corresponding to the downstream module does not contain the target function pointer, register the target function with the common cache module; wherein, the target function pointer corresponding to the newly registered target function is stored in the array cell corresponding to the downstream module.
[0027] In some possible embodiments, when the upstream module generates second interrupt information upon completion of sending, the upstream module is further configured to:
[0028] Obtain the return value returned by the target function;
[0029] If the return value is used to indicate that the preset identifier has been successfully sent to the downstream module, generate second interrupt information.
[0030] In some possible embodiments, the common cache module is configured to:
[0031] When the first interrupt information is detected, increment the reference count of the target cache block by 1;
[0032] When the second interrupt information is detected, decrement the reference count of the target cache block by 1.
[0033] In some possible embodiments, when the upstream module executes the step of calling a target cache block from the common cache module, the upstream module is further configured to:
[0034] If the first call fails, continue to call the target cache block from the common cache module at a preset interval until the target cache block is successfully called.
[0035] In some possible embodiments, when the downstream module executes the step of obtaining target data in the target cache block according to the preset identifier, the downstream module is further configured to:
[0036] Find the target cache block from the common cache module according to the physical address or virtual address included in the preset identifier;
[0037] Read the target data in the target cache block.
[0038] In a second aspect, some embodiments of the present application provide another data flow system, including: an upstream module, at least one intermediate module, a downstream module, and a common cache module;
[0039] The upstream module is configured to: call a first cache block from the common cache module, and generate first interrupt information; the first interrupt information is used to increment the reference count of the first cache block by 1;
[0040] Store first target data in the first cache block;
[0041] Send a first preset identifier representing the first cache block to the downstream module, and generate second interrupt information when the sending is completed; the second interrupt information is used to decrement the reference count of the first cache block by 1;
[0042] The intermediate module is configured to: generate first interrupt information when receiving the first preset identifier, so as to increment the reference count of the first cache block by 1;
[0043] Obtain the first target data in the first cache block according to the first preset identifier;
[0044] Execute a first target task based on the first target data to obtain second target data, and generate second interrupt information; the second interrupt information is used to decrement the reference count of the first cache block by 1;
[0045] Call a second cache block from the common cache module, and generate third interrupt information; the third interrupt information is used to increment the reference count of the second cache block by 1;
[0046] Store the second target data in the second cache block;
[0047] Send a second preset identifier representing the second cache block to the downstream module, and generate fourth interrupt information when the sending is completed; the fourth interrupt information is used to decrement the reference count of the second cache block by 1;
[0048] The downstream module is configured to: generate the third interrupt information when receiving the second preset identifier, so as to increment the reference count of the second cache block by 1;
[0049] Obtain the second target data in the target cache block according to the preset identifier;
[0050] Execute a second target task based on the second target data, and generate fourth interrupt information after the target task is completed according to the second target data.
[0051] In a third aspect, the present application provides an image processing apparatus, including: an image sensor, a display, and the data flow system according to any one of the first aspects;
[0052] The image sensor is configured to: collect target data and transmit the target data to the data flow system;
[0053] The data flow system is configured to: perform an image processing task on the target data and transmit the target data after image processing to the display;
[0054] The display is configured to: display a target image based on the target data after image processing.
[0055] As can be seen from the above technical content, the embodiments of the present application provide a data flow system and an image processing apparatus. By setting a common cache module in the data flow system, the upstream module can call the pre-divided cache blocks from the common cache module to cache the target data. And the downstream module can find the cache block through the preset identifier issued by the upstream module to obtain the target data. By introducing a reference counting mechanism, write protection can be set for the retrieved cache block, and the common cache module will only release the cache block when the reference count of the cache block returns from a non-zero number to zero. In this way, one-to-many transmission between the upstream module and the downstream module can be realized, and the control logic in the process of obtaining the target data can be reduced, which is beneficial to improving the data flow efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0056] In order to more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.
[0057] Figure 1 It is a schematic diagram of data flow between image processing modules;
[0058] Figure 2 It is a schematic diagram of preset interfaces of the common cache module provided by some embodiments of the present application;
[0059] Figure 3 It is an interaction schematic diagram of each module in the data flow system provided by some embodiments of the present application;
[0060] Figure 4 It is a schematic diagram of a preset array provided by some embodiments of the present application;
[0061] Figure 5 It is an interaction schematic diagram of each part of the image processing apparatus provided by some embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0062] Embodiments will be described in detail below, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following embodiments do not represent all embodiments consistent with the present application. They are merely examples of systems and methods consistent with some aspects of the present application detailed in the claims.
[0063] For example, when an image processing device such as a security device processes image data, it depends on a pipeline processing link formed between each image processing module to process the image data collected by an image sensor. For example, after receiving the image data collected by the image sensor, a video input module can perform processing procedures such as dead pixel correction, lens shading correction, 2D / 3D denoising, and color enhancement on the image data. The video input (VIN, video input) module can further send the processed image data to an image video processing system, and the image video processing system (IVPS, Image Video ProcessSystem) performs processing procedures such as frame rate control, color space conversion, fixed angle rotation, and mosaicing on the image data. The image video processing system can further transmit the processed data to a video output (Video Out) module, and the video output module transmits the processed data to a display and playback device according to the output protocol.
[0064] It can be understood that the image processing modules in a security device include but are not limited to the above modules. For example, it may further include an encoding module and a decoding module. The image processing modules realize the data flow in the form of a pipeline.
[0065] Take the module that sends data to other modules in the image processing module as the upstream module, and the module that receives data sent by other modules as the downstream module. Among them, a module can be an upstream module or a downstream module during the data flow process. As Figure 1 shown, an upstream module can have two corresponding buffer queues, namely an idle buffer queue and a ready buffer queue. Among them, the idle buffer queue is a queue composed of buffer units that have not saved data, and the ready buffer queue is a queue composed of buffer units that have saved data. When the upstream module sends data to the downstream module, it needs to first select a buffer unit from its corresponding idle buffer queue, fill the data into the buffer unit, and then place the buffer unit filled with data into the ready buffer queue.
[0066] For example, the downstream module needs to access the ready cache queue of the upstream module through the preset interface BM_borrow. At this time, the upstream module can delete the cache unit from the ready queue. And after the downstream module finishes using the data in the ready cache queue, it can return the cache unit to the idle cache queue of the upstream module through the preset interface BM_giveback.
[0067] However, in this data transfer method, after the downstream module accesses one cache unit in the upstream module, since the upstream module will destroy the cache unit from the ready queue, other downstream modules cannot access the data in this cache unit anymore. That is, one-to-many transmission cannot be achieved between the upstream module and the downstream module.
[0068] In addition, the downstream module operates on the cache units in the queue of the upstream module. Therefore, when the downstream module operates on the cache unit, it needs to consider whether the upstream module is destroying the cache unit, resulting in complex control logic. And based on this data transfer method, the pointer used to indicate data transfer is not conducive to management, and the memory application and release logic are completed by each module separately, making it difficult to troubleshoot problems when they occur.
[0069] To solve the above problems, an embodiment of the present application provides a data transfer system, including: an upstream module, at least one downstream module, and a common cache module.
[0070] As Figure 2 shown, multiple interfaces can be preset in the common cache module for interacting with the upstream module and the downstream module during the data transfer process. For example, the cache block acquisition / release interface (GetBlock / ReleaseBlock), the upstream module or the downstream module can acquire or release a cache block from the common cache module by accessing the cache block acquisition / release interface. Another example is the binding relationship registration / unregistration interface (Link / Unlink), so the binding relationship between the upstream module and the downstream module can be registered / unregistered in the common cache module through the registration / unregistration interface. Among them, unregistration can be understood as deleting the binding relationship between the upstream module and the downstream module in the common cache module. Still another example is the callback function registration / unregistration interface, so a callback function for receiving a cache block handle can be registered through the callback function registration / unregistration interface, such as CallBackFunc(int ModID, int BlkID). Among them, ModID can refer to the module currently receiving / sending the cache block handle, and BlkID is the cache block handle used to indicate the cache block. In addition, the common cache module also has a dispatch interface (Dispatch), and the upstream module can call the callback function to send the cache block handle to the downstream module by accessing the dispatch interface.
[0071] Based on the interface design of the common cache module, the upstream module and the downstream module can call cache blocks from the common cache module and store data in the cache blocks, so as to realize data flow by means of the cache blocks, cache block management capabilities, binding relationship management capabilities, and callback function management capabilities provided by the common cache module.
[0072] Among them, as Figure 3 shown, the upstream module is configured during the data flow process as:
[0073] Call the target cache block from the common cache module and generate the first interrupt information; the first interrupt information is used to increment the reference count of the target cache block by 1.
[0074] Store the target data in the target cache block.
[0075] Send the preset identifier representing the target cache block to the downstream module and generate the second interrupt information when the sending is completed; the second interrupt information is used to decrement the reference count of the target cache block by 1.
[0076] In some embodiments, the common cache module manages the reference count of the target cache block. That is, when the common cache module monitors the first interrupt information, it increments the reference count of the target cache block by 1. When the common cache module monitors the second interrupt information, it decrements the reference count of the target cache block by 1.
[0077] In some embodiments, the upstream module can call the target cache block from the common cache module through the cache block acquisition interface of the common cache module. And, before writing the target data to the target buffer block, the upstream module needs to generate the first interrupt information. Taking the upstream module as a video input module as an example, the first interrupt information can be IncreaseRefCnt(VIN, BlkID). In this way, the common cache module can receive the first interrupt information and perform a record operation of incrementing the reference count of the target cache block according to the first interrupt information.
[0078] It can be understood that the common cache module can internally record the reference count of each pre-divided cache block. Among them, when the reference count of the cache block is not 0, it means that the cache block is being used. When the reference count of the cache block returns to zero from a non-zero number, it indicates that the cache block can be released. In this way, taking the first access of the target cache block by the upstream module as an example, the reference count of the target cache block should be 1 at this time.
[0079] After successfully calling the target cache block, the upstream module can store the target data in the target cache block. Moreover, the upstream module can send a preset identifier for indicating the target cache block to the downstream module. Here, the preset identifier can be the cache block handle BlkID. When the upstream module determines that the downstream module has received the preset identifier, that is, when the preset identifier has been sent successfully, it can generate a second interrupt message. The second interrupt message can be denoted as DecreaseRefCnt(VIN, BlkID). In this way, when the common cache module detects the second interrupt message, it can decrement the reference count of the target cache block by 1.
[0080] In some other embodiments, when the upstream module calls the target cache block in the common cache module through the dispatch interface, there may be a failure, which may be caused by the common cache module not finding the binding relationship, not finding the callback function corresponding to the downstream module, or the system being busy, etc. At this time, the upstream module is further configured as:
[0081] If the first call fails, continue to call the target cache block from the common cache module at a preset interval until the target cache block is successfully called.
[0082] In some embodiments, in the scenario where the upstream module fails to call the target cache block, it will continuously access the common cache module through the dispatch interface until the target cache block is successfully called. After the upstream module successfully calls the target cache block, it will generate a corresponding first interrupt message to increment the reference count of the target cache block by 1 in the common cache module.
[0083] Among them, when the upstream module continuously accesses the common cache module, it can access at a preset interval to prevent affecting the normal operation of the common cache module.
[0084] It can be understood that after the upstream module successfully obtains the target cache block and stores the data, it can also send a preset identifier to multiple downstream modules so that multiple downstream modules can all access and obtain the data in the target cache block. Therefore, even when the common cache module detects the second interrupt message generated by the upstream module, the reference count of the target cache block does not necessarily drop to 0. When multiple downstream modules receive the preset identifier, they will all generate a first interrupt message. In this way, when the common cache module detects multiple first interrupt messages generated by the downstream modules, it can increment the reference count of the target cache block. As Figure 3 shown, the downstream module is configured as follows during the data flow:
[0085] When receiving the preset identifier, generate a first interrupt message to increment the reference count of the target cache block by 1.
[0086] Obtain the target data in the target cache block according to the preset identifier.
[0087] After the target task is executed according to the target data, second interrupt information is generated to decrement the reference count of the target cache block by 1.
[0088] For example, when an upstream module sends a preset identifier to one downstream module, the downstream module can generate first interrupt information when it receives the preset identifier. Taking the downstream module as a video data processing system as an example, the first interrupt information can be IncreaseRefCnt(IVPS, BlkID).
[0089] It should be noted that the first interrupt information here all refers to the information used to increase the reference count of the target cache block, and the second interrupt information all refers to the information used to decrease the reference count of the target cache block. It does not specifically refer to the information generated by a certain module. The first interrupt information and the second interrupt information can include information for indicating a specific module.
[0090] It can be understood that when one downstream module receives the preset identifier and generates the first interrupt information, the common cache module can increment the reference count of the target cache block by 1. In this way, the reference count of the target cache block is still 1, so the target cache block will not be released.
[0091] In some embodiments, when the upstream module sends a preset identifier to three downstream modules and all three downstream modules receive the preset identifier, they can all generate the first interrupt information. In this way, when the common cache module detects three first interrupt information, it can increment the reference count of the target cache block by 3. In this way, the reference count of the target cache block is 3, so the target cache block will not be released. Even if a downstream module finishes using the data in the target cache block first, since the reference count of the target cache block has not reached zero, the target buffer block will still not be released.
[0092] Continuing with the above embodiment, the preset identifier, i.e., the cache block handle, can include the physical address or virtual address of the target cache block. In this way, the downstream module can find the target cache block according to the corresponding physical address or virtual address in the cache block handle and obtain the target data in the target cache block.
[0093] Moreover, when different downstream modules obtain the same cache block handle, they can all find and obtain the target data in the target cache block according to the physical address or virtual address corresponding to the cache block handle.
[0094] In some embodiments, the common cache module can record the reference count of the cache block by monitoring the interrupt information generated by the upstream module and the downstream module, so as to manage the cache block according to the reference count of the cache block. That is, the common cache module is configured to: release the target cache block when it detects that the reference count of the target cache block returns to zero from a non-zero number.
[0095] It can be understood that the common cache module will release the target cache block only when the reference count of the target cache block returns to zero from a non-zero number. Moreover, during the data flow process, the common cache module can increase or decrease the reference count of the target cache block in real time according to the monitored interruption information, so as to release the target cache block that is no longer in use in a timely manner and accurately retain the target cache block that is still in use.
[0096] It should be noted that multiple common cache modules can be set as needed in the data flow system, and the cache capacities of the cache blocks divided in each common cache module are different, which can improve the flexibility of the upstream module and the downstream module when using the cache blocks and improve the utilization rate of the cache. For example, the upstream module can select the cache block closest to the data volume of the current target data to store the target data, that is, before the upstream module executes to call the target cache block from the common cache module, it is further configured as:
[0097] Determine the target cache block for caching the target data according to the data volume of the target data.
[0098] Determine the common cache module according to the cache capacity of the target cache block.
[0099] In some embodiments, when the upstream module calls the target cache block, it can select the target cache block according to the data volume of the data generated by itself. And the partitioning methods of the cache blocks in different common cache modules can be different, which can just meet the flexible requirements of the upstream module when generating data with different data volumes.
[0100] It can be understood that the cache capacity of the target cache block needs to be greater than or equal to the data volume of the target data, that is, the difference between the cache capacity of the target cache block and the data volume of the target data is less than the difference between the data volume of other cache blocks and the target data.
[0101] Among them, the partitioning method of the cache blocks by the common cache module can be pre-agreed in the data flow system, so the upstream module can select the cache blocks. In this way, the upstream module can select the cache block that can just accommodate the data volume generated by itself, which is beneficial to improving the utilization rate of the cache.
[0102] In some embodiments, the upstream module can send a preset identifier to the downstream module through a callback function, that is, when the upstream module executes to send the preset identifier for representing the target cache to the downstream module, it is further configured as:
[0103] Obtain the preset binding relationship from the common cache module.
[0104] Call the target function corresponding to at least one downstream module from the public cache module according to the preset binding relationship; wherein, different downstream modules correspond to different target functions;
[0105] Add the preset identifier to the target function;
[0106] Send the target function containing the preset identifier to at least one downstream module.
[0107] It can be understood that the binding relationship between the upstream module and the downstream module is pre-registered through the registration interface provided by the public cache module and saved by the public cache module. In this way, the upstream module can find the downstream modules bound to itself through the dispatch interface provided by the public cache module, and the public cache module can further find the target functions corresponding to the downstream modules. Among them, the target function can be a callback function (CallBackFunc), and the callback function can be triggered when the upstream module sends the cache block handle to the downstream module, and then the cache block handle is sent to the downstream module.
[0108] When the upstream module finds multiple downstream modules bound to itself, it can call multiple callback functions to send the cache block handle to multiple downstream modules. Among them, the cache block handle corresponding to the target cache block needs to be added to the callback function, so that the downstream module can find the target cache block according to the cache block handle and read the data in the target cache block to perform subsequent data processing tasks.
[0109] Moreover, the public cache module can increase or decrease the reference count of the target cache block by monitoring the interrupt information generated during the process of the upstream module and the downstream module sending and receiving the callback function, so as to control the retention and release of the target cache block based on the reference count. Thus, a transmission method in which the upstream module can perform one-to-many transmission with the downstream module is formed.
[0110] As Figure 4 shown, the public cache module also contains a preset array, and the preset array contains multiple array elements for recording target function pointers. That is, the array element contains the target function pointer, indicating that there is a target function that has been pre-registered in the public cache module between the upstream module and the downstream module. Therefore, when the upstream module sends the cache block handle to the downstream module through the callback function, it also needs to check whether the callback function is pre-registered in the public cache module. That is, the upstream module is also configured to:
[0111] Check whether the array element corresponding to the bound downstream module contains the target function pointer.
[0112] If the array element corresponding to the downstream module contains the target function pointer, call the target function corresponding to the target function pointer.
[0113] If the target function pointer is not included in the array unit corresponding to the downstream module, register the target function with the common cache module.
[0114] In some embodiments, the common cache module can maintain an array internally, namely the preset array. Each cache unit in the preset array stores the callback function pointer corresponding to each downstream module. In this way, when the common cache module receives a data request sent by the upstream module, it can find the downstream module corresponding to the upstream module according to the binding relationship, and then find the corresponding callback function pointer according to the downstream module, so as to send the cache block handle to the downstream module through the callback function pointer.
[0115] In some embodiments, when the common cache module fails to find the callback function pointer corresponding to the downstream module in the preset array, it can receive a callback function registration request from an external module, such as an upstream module / downstream module / other control module, through the callback function registration interface, and then realize the transfer of the cache block handle through real-time registration. Moreover, the common cache module can store the callback function pointer corresponding to the newly registered callback function in the preset array for reuse in subsequent data processing tasks.
[0116] In some embodiments, if the common cache module finds the callback function pointer corresponding to the downstream module in the preset array, it can send the cache block handle to the downstream module based on the callback function corresponding to the callback function pointer.
[0117] As shown in the figure, the upstream module is specifically configured when the sending is completed as follows:
[0118] Obtain the return value returned by the target function.
[0119] If the return value is used to indicate that the preset identifier is successfully sent to the downstream module, generate second interrupt information.
[0120] It can be understood that when the target function is a callback function, after successfully sending the cache block handle, the callback function can return a return value to the upstream module to inform the upstream module of the successful sending through the return value. Then, the upstream module can generate second interrupt information, so that the common cache module can maintain the reference count of the target cache block according to the second interrupt information.
[0121] For example, when the upstream module receives the return value "0", it can determine that the cache block handle is successfully sent. The upstream module can generate second interrupt information. For another example, when the upstream module receives the return value "1", it can determine that the cache block handle is sent failed, and then can perform corresponding processing for the sending failure.
[0122] Among them, during a cache block handle dispatch of the callback function, the time for the downstream module to generate the first interrupt information is earlier than the time for the upstream module to generate the second interrupt information upon receiving the return value of the callback function. This can ensure that the common cache module does not have the problem that the reference count of the target cache block is reset to zero and released due to detecting the second interrupt information generated by the upstream module first.
[0123] In this way, through the target function pointer maintenance ability and the callback function registration ability provided by the common cache module, it can be greatly ensured that data flows smoothly from the upstream module to the downstream module. And the common cache module uniformly manages elements such as memory and callback functions, which is beneficial to improving the integrity of the data flow system.
[0124] Moreover, based on the management of the reference count of the target cache block by the common cache module, it can cooperate with the one-to-many data dispatch of the upstream module and the downstream module. Even when any downstream module finishes using the data in the target cache block first, the target cache block will still be maintained by the common cache module because the reference count has not been reset to zero, and then other downstream modules can continue to use the data in the target cache block.
[0125] Some embodiments of the present application further provide a data flow system, including: an upstream module, at least one intermediate module, a downstream module, and a common cache module;
[0126] The upstream module is configured to: call a first cache block from the common cache module, and generate a first interrupt information; the first interrupt information is used to increment the reference count of the first cache block by 1;
[0127] Store first target data into the first cache block;
[0128] Send a first preset identifier representing the first cache block to the downstream module, and generate a second interrupt information when the sending is completed; the second interrupt information is used to decrement the reference count of the first cache block by 1;
[0129] The intermediate module is configured to: generate a first interrupt information when receiving the first preset identifier, so as to increment the reference count of the first cache block by 1;
[0130] Obtain the first target data in the first cache block according to the first preset identifier;
[0131] Execute a first target task based on the first target data to obtain second target data, and generate a second interrupt information; the second interrupt information is used to decrement the reference count of the first cache block by 1;
[0132] Invoke the second cache block from the public cache module and generate third interrupt information; the third interrupt information is used to increment the reference count of the second cache block by 1;
[0133] Store the second target data in the second cache block;
[0134] Send a second preset identifier representing the second cache block to the downstream module and generate fourth interrupt information when the sending is completed; the fourth interrupt information is used to decrement the reference count of the second cache block by 1;
[0135] The downstream module is configured to: generate the third interrupt information when receiving the second preset identifier, so as to increment the reference count of the second cache block by 1;
[0136] Obtain the second target data in the target cache block according to the preset identifier;
[0137] Execute a second target task based on the second target data, and generate fourth interrupt information after the target task is completed according to the second target data.
[0138] In some embodiments, there are also multiple intermediate modules between the upstream module and the downstream module in the data flow system. For example, if the upstream module is a video input module and the downstream module is a video output module, an intermediate module such as a video processing system module may also be included between the video input module and the video output module.
[0139] Among them, the first cache block and the second cache block are used to distinguish the cache blocks used by the upstream module and the intermediate module, and the intermediate module and the downstream module, rather than limiting the number of cache blocks. In this way, when the intermediate module receives a callback function triggered by the upstream module, it will generate first interrupt information for increasing the reference count of the first cache block. And when the intermediate module finishes using the data in the first cache block, it will generate second interrupt information for decreasing the reference count of the first cache block.
[0140] In addition, after the intermediate module finishes executing a task according to the data in the first cache block, it needs to invoke the second cache block from the public cache module. At this time, it will also generate third interrupt information for increasing the reference count of the second cache block, and trigger a callback function to send the cache block handle to the downstream module. After it is determined that the cache block handle has been sent to the downstream module, fourth interrupt information for decreasing the reference count of the second cache block can be generated.
[0141] After obtaining the cache block handle, the downstream module first generates third interrupt information for increasing the reference count of the second cache block, and then obtains the second target data to execute the second target task. After the execution of the second target task is completed, fourth interrupt information for reducing the reference count of the second cache block is generated.
[0142] In the process of the above data flow, the common cache module provides multiple functions such as binding relationship management, callback function management, and cache block management for each module to enhance the integrity and stability of the data flow system. It is beneficial to simplify the control logic, as well as exception troubleshooting, and improve the data flow efficiency.
[0143] Such as Figure 5 shown, some embodiments of the present application provide an image processing apparatus, including: an image sensor, a display, and the data flow system described in the system type embodiments.
[0144] The image sensor is configured to: collect target data and transmit the target data to the data flow system;
[0145] The data flow system is configured to: perform an image processing task on the target data and transmit the target data after image processing to the display;
[0146] The display is configured to: display a target image based on the target data after image processing.
[0147] As can be seen from the above technical content, the present application provides a data flow system and an image processing apparatus. By setting a common cache module in the data flow system, the upstream module can call the pre-divided cache blocks from the common cache module to cache the target data. And the downstream module can find the cache block through the preset identifier sent by the upstream module to obtain the target data. By introducing a reference counting mechanism, write protection can be set for the retrieved cache block, and the common cache module will only release the cache block when the reference count of the cache block returns from a non-zero number to zero. In this way, one-to-many transmission between the upstream module and the downstream module can be realized, and the control logic in the process of obtaining the target data can be reduced, which is beneficial to improving the data flow efficiency.
[0148] For the similar parts between the embodiments provided in the present application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of the present application and do not constitute a limitation on the protection scope of the present application. For those skilled in the art, any other embodiments extended based on the solution of the present application without creative efforts belong to the protection scope of the present application.
Claims
1. A data flow system, characterized in that, It includes: an upstream module, at least one downstream module, and a common cache module; The upstream module is configured to: call a target cache block from the common cache module, and generate first interrupt information; The first interrupt information is used to increment the reference count of the target cache block by 1; Store target data in the target cache block; Send a preset identifier representing the target cache block to the downstream module, and generate second interrupt information when the sending is completed; The second interrupt information is used to decrement the reference count of the target cache block by 1; The downstream module is configured to: generate first interrupt information when receiving the preset identifier, so as to increment the reference count of the target cache block by 1; Obtain the target data in the target cache block according to the preset identifier; After completing the target task according to the target data, generate second interrupt information to decrement the reference count of the target cache block by 1; 2. The system according to claim 1, wherein The common cache module is configured to: release the target cache block when detecting that the reference count of the target cache block returns to zero from a non-zero number. The cache capacities of the cache blocks divided in different common cache modules are different. Before the upstream module executes calling the target cache block from the common cache module, it is further configured to: Determine a target cache block for caching the target data according to the data volume of the target data; the cache capacity of the target cache block is greater than or equal to the data volume of the target data; the difference between the cache capacity of the target cache block and the data volume of the target data is less than the difference between the data volume of other cache blocks and the data volume of the target data; 3. The system according to claim 1, characterized in that, Determine the common cache module according to the cache capacity of the target cache block. When the upstream module executes sending the preset identifier representing the target cache to the downstream module, it is further configured to: Obtain a preset binding relationship from the common cache module; the preset binding relationship includes at least one downstream module bound to the upstream module; Call target functions corresponding to at least one downstream module from the common cache module according to the preset binding relationship; among them, different downstream modules correspond to different target functions; Add the preset identifier to the target function; 4. The system according to claim 3, characterized in that, Send the target function containing the preset identifier to at least one downstream module. The common cache module contains a preset array, and the array elements in the preset array are used to record target function pointers; the target function pointers are used to represent that there are registered target functions between the upstream module and the downstream module; Before the upstream module executes calling the target functions corresponding to at least one downstream module from the common cache module according to the preset binding relationship, it is further configured to: Check whether the array element corresponding to the bound downstream module contains the target function pointer; If the array element corresponding to the downstream module contains the target function pointer, then call the target function corresponding to the target function pointer; If the array cell corresponding to the downstream module does not contain the target function pointer, register the target function with the common cache module; wherein, the target function pointer corresponding to the newly registered target function is stored in the array cell corresponding to the downstream module.
5. The system according to claim 3, wherein When the upstream module generates a second interrupt message upon completion of sending, it is further configured to: Obtain the return value returned by the target function; If the return value is used to indicate that the preset identifier has been successfully sent to the downstream module, generate a second interrupt message.
6. The system according to claim 1, wherein The common cache module is configured to: When detecting the first interrupt message, increment the reference count of the target cache block by 1; When detecting the second interrupt message, decrement the reference count of the target cache block by 1.
7. The system according to claim 1, wherein When the upstream module executes to call the target cache block from the common cache module, it is further configured to: If the first call fails, continue to call the target cache block from the common cache module according to a preset interval until the target cache block is successfully called.
8. The system according to claim 1, wherein When the downstream module executes to obtain the target data in the target cache block according to the preset identifier, it is further configured to: Locate the target cache block from the common cache module according to the physical address or virtual address included in the preset identifier; Read the target data in the target cache block.
9. A data flow system, characterized in that, It includes: An upstream module, at least one intermediate module, a downstream module, and a common cache module; The upstream module is configured to: call a first cache block from the common cache module, and generate a first interrupt message; The first interrupt message is used to increment the reference count of the first cache block by 1; Store first target data in the first cache block; Send a first preset identifier for characterizing the first cache block to the downstream module, and generate a second interrupt message upon completion of sending; The second interrupt message is used to decrement the reference count of the first cache block by 1; The intermediate module is configured to: when receiving the first preset identifier, generate a first interrupt message to increment the reference count of the first cache block by 1; Obtain the first target data in the first cache block according to the first preset identifier; Execute a first target task based on the first target data to obtain second target data, and generate a second interrupt message; The second interrupt message is used to decrement the reference count of the first cache block by 1; Call a second cache block from the common cache module, and generate a third interrupt message; The third interrupt message is used to increment the reference count of the second cache block by 1; Store the second target data in the second cache block; Send a second preset identifier for characterizing the second cache block to the downstream module, and generate a fourth interrupt message upon completion of sending; The fourth interrupt message is used to decrement the reference count of the second cache block by 1; The downstream module is configured to: when receiving the second preset identifier, generate the third interrupt message to increment the reference count of the second cache block by 1; Obtain the second target data in the target cache block according to the preset identifier; Execute a second target task based on the second target data, and generate a fourth interrupt message after the target task is executed according to the second target data.
10. An image processing apparatus, characterized in that, It includes an image sensor, a display, and the data flow system according to any one of claims 1-8; The image sensor is configured to: collect target data and transmit the target data to the data flow system; The data flow system is configured to: perform an image processing task on the target data and transmit the target data after image processing to the display; The display is configured to: display a target image based on the target data after image processing.