Controller reset method and device of NVMe accelerator card, equipment and medium

Abstract

The invention discloses a controller reset method and device of an NVMe accelerator card, equipment and a medium, relates to the technical field of computer storage, is applied to a preset reset test tool of a target host end, and comprises the following steps: sending a reset test command to the NVMe accelerator card; the reset test command carries a first / second memory ground used for storing a register state before / after reset; the NVMe accelerator card responds to the reset test command to execute a controller reset process, and obtains a first state of a target NVMe accelerator card written in the first memory address and a second state of the target NVMe accelerator card written in the second memory address; based on the first state, the second state and a target reset state specified by the NVMe protocol, whether a reset test result corresponding to the reset process of the controller meets a preset test success condition or not is judged, and if not, a reset repair command generated based on the reset test result is sent to the NVMe accelerator card so that the NVMe accelerator card can execute corresponding repair operation.

Description

Technical Field

[0001] The present invention relates to the technical field of computer storage, and particularly relates to a method, device, equipment and medium for resetting a controller of an NVMe acceleration card. Background Art

[0002] With the development of information technology, the storage bandwidth requirements of data center servers are constantly increasing. To improve the hard disk IO (Input / Output) performance, many devices for accelerating the hard disk IO process have been designed currently, such as an NVMe (Non-Volatile Memory express) acceleration card, which can accelerate the execution process of IO commands of the NVMe protocol, including the transmission and execution process of IO commands.

[0003] During the R & D stage of the NVMe acceleration card, the problem of NVMe controller reset often occurs. For example, when the NVMe acceleration card firmware receives the NVMe controller reset interrupt notification, it configures the controller reset register provided by the NVMe acceleration card hardware, but the controller reset interface implemented by the hardware does not correctly reset the NVMe standard register in the PCIe (Peripheral Component Interconnect Express) BAR (Base Address Register) space of the NVMe acceleration card; or the controller reset interface implemented by the hardware not only resets the NVMe standard register in the PCIe BAR space of the NVMe acceleration card, but also redundantly resets other device internal registers in the device BAR space, etc., resulting in the reset range exceeding the NVMe protocol regulations.

[0004] The currently commonly used NVMe acceleration card controller reset test method mainly includes resetting the controller, enabling the controller, and testing the controller availability. However, this method has many problems: first, the test is incomplete and it is impossible to observe whether the device-side register reset range is correct; second, the problem prompt is incomplete and it cannot comprehensively point out the problem points of the device-side NVMe controller reset; third, the problem cannot be fixed and there is no automated analysis and solution plan.

[0005] In summary, how to achieve a more complete controller reset test and perform automated repair when problems occur is an issue to be solved currently. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for resetting the controller of an NVMe acceleration card, which can achieve a more complete controller reset test and perform automatic repair when problems occur. The specific solution is as follows:

[0007] In the first aspect, the present application discloses a method for resetting the controller of an NVMe acceleration card, which is applied to a preset reset test tool on the target host side and includes:

[0008] Sending a preset reset test command to the target NVMe acceleration card; wherein, the reset test command carries a first memory address locally pre-created for storing the register state before reset and a second memory address for storing the register state after reset;

[0009] The target NVMe acceleration card responds to the reset test command to execute a preset controller reset process, and obtains a first state written by the target NVMe acceleration card in the first memory address and a second state written in the second memory address; the first state is the state of each register in the target NVMe acceleration card before the hardware reset operation in the execution of the controller reset process; the second state is the state of each register in the target NVMe acceleration card after the execution of the hardware reset operation;

[0010] Based on the first state, the second state and the target reset state specified by the NVMe protocol, it is judged whether the reset test result corresponding to the controller reset process meets the preset test success condition. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe acceleration card so that the target NVMe acceleration card can perform corresponding repair operations.

[0011] Optionally, sending a preset reset test command to the target NVMe acceleration card includes:

[0012] Determining a predefined test command format; the test command format includes an operation code for indicating the command type, a command identifier for distinguishing multiple different commands in the same management command queue, a field for recording the first memory address, and a field for recording the second memory address;

[0013] Based on the test command format and through the management command queue, a preset reset test command is sent to the target NVMe acceleration card.

[0014] Optionally, the execution process of the controller reset process includes:

[0015] The NVMe device driver software on the target host sends a target management command for deleting the input / output queue to the target NVMe acceleration card through the management command queue, so that the target NVMe acceleration card performs the deletion operation on the input / output queue based on the target management command;

[0016] The NVMe device driver software sends a control command to the target NVMe acceleration card, so that the target NVMe acceleration card generates a controller reset interrupt signal to perform a firmware reset operation and a hardware reset operation, writes the status of each local register to the first memory address before performing the hardware reset operation, and writes the status of each local register to the second memory address after performing the hardware reset operation, and then sends a message indicating the completion of the reset to the NVMe device driver software after the firmware reset operation and the hardware reset operation are completed.

[0017] Optionally, based on the first state, the second state, and the target reset state specified by the NVMe protocol, determine whether the reset test result corresponding to the controller reset process meets the preset test success condition, including:

[0018] Compare the first state and the second state corresponding to the same register to determine a number of target registers whose register status has changed;

[0019] Determine whether each target register is a standard register specified by the NVMe protocol;

[0020] If each target register is a standard register specified by the NVMe protocol, read the target reset state of the standard register specified by the NVMe protocol, and determine whether each second state is consistent with the corresponding target reset state. If each second state is consistent with the corresponding target reset state, it is determined that the standard register reset test is successful. If there is a target standard register whose second state is inconsistent with the corresponding target reset state, it is determined that the target standard register reset test fails;

[0021] If there are other registers in addition to the standard registers specified by the NVMe protocol among the target registers, it is determined that the current register reset range exceeds the target reset range specified by the NVMe protocol, and it is determined that the reset test of the other registers fails.

[0022] Optionally, generate a reset repair command based on the reset test result, including:

[0023] Determine the target standard registers and other registers for which the reset test fails;

[0024] Construct a first key-value pair based on the base address of the target standard register and the corresponding target reset state, and store the first key-value pair in a preset key-value pair repair list;

[0025] Construct a second key-value pair based on the base addresses of the remaining registers and the corresponding original register states, and store the second key-value pair in the key-value pair repair list;

[0026] Write the key-value pair repair list to a pre-constructed third memory address, and generate a reset repair command carrying the third memory address.

[0027] Optionally, send the reset repair command to the target NVMe accelerator card so that the target NVMe accelerator card performs corresponding repair operations, including:

[0028] Send the reset repair command to the target NVMe accelerator card through the management command queue, so that the target NVMe accelerator card parses the reset repair command to obtain the third memory address, and repairs the corresponding register states based on the key-value pair repair list obtained from the third memory address, and sends a target message indicating that the reset repair command has been executed to the target host after the repair is completed.

[0029] Optionally, the controller reset method of the NVMe accelerator card of the present application further includes:

[0030] After obtaining the target message sent by the target NVMe accelerator card, perform a clearing operation on the contents stored in the first memory address, the second memory address, and the third memory address.

[0031] In a second aspect, the present application discloses a controller reset device for an NVMe accelerator card, which is applied to a preset reset test tool on a target host. The device includes:

[0032] A test command sending module, configured to send a preset reset test command to the target NVMe accelerator card; wherein, the reset test command carries a first memory address locally pre-created for storing the register states before reset and a second memory address for storing the register states after reset;

[0033] A status acquisition module, configured to execute a preset controller reset process through the target NVMe accelerator card's response to the reset test command, and acquire a first status written by the target NVMe accelerator card in the first memory address and a second status written in the second memory address; the first status is the register states in the target NVMe accelerator card before the hardware reset operation during the execution of the controller reset process by the target NVMe accelerator card; the second status is the register states in the target NVMe accelerator card after the execution of the hardware reset operation.

[0034] A reset repair module, configured to determine whether a reset test result corresponding to a controller reset process meets a preset test success condition based on a first state, a second state, and a target reset state specified by the NVMe protocol. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe accelerator card, so that the target NVMe accelerator card performs corresponding repair operations.

[0035] In a third aspect, the present application discloses an electronic device, including:

[0036] A memory, configured to store a computer program;

[0037] A processor, configured to execute the computer program to implement the steps of the controller reset method for the foregoing disclosed NVMe accelerator card.

[0038] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the controller reset method for the foregoing disclosed NVMe accelerator card are implemented.

[0039] It can be seen that a preset reset test tool on the target host sends a preset reset test command to the target NVMe accelerator card; wherein, the reset test command carries a first memory address locally pre-created for storing the register state before reset and a second memory address for storing the register state after reset; the target NVMe accelerator card responds to the reset test command to execute a preset controller reset process, and obtains a first state written by the target NVMe accelerator card at the first memory address and a second state written at the second memory address; the first state is the register state in the target NVMe accelerator card before the hardware reset operation in the execution of the controller reset process by the target NVMe accelerator card; the second state is the register state in the target NVMe accelerator card after the execution of the hardware reset operation; it is determined whether the reset test result corresponding to the controller reset process meets a preset test success condition based on the first state, the second state, and the target reset state specified by the NVMe protocol. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe accelerator card, so that the target NVMe accelerator card performs corresponding repair operations.

[0040] Beneficial effects: This application discloses a preset reset test tool for the host side. Before performing the reset test, the preset reset test tool will first create a first memory address for saving the register state before reset and a second memory address for saving the register state after reset locally. When performing the reset test, a preset reset test command will be sent to the target NVMe accelerator card, and the first memory address and the second memory address are carried in the reset test command. Further, after receiving the reset test command, the target NVMe accelerator card responds to the reset test command to execute a preset controller reset process. During this process, the preset reset test tool can obtain a first state written by the target NVMe accelerator card in the first memory address and a second state written in the second memory address. The first state refers to the register states in the target NVMe accelerator card before the hardware reset operation in the controller reset process is executed by the target NVMe accelerator card; the second state refers to the register states in the target NVMe accelerator card after the hardware reset operation is executed. After obtaining the first state and the second state, the preset reset test tool combines the target reset state specified in the NVMe protocol to determine whether the reset test result corresponding to the controller reset process meets the preset test success condition. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe accelerator card so that the target NVMe accelerator card can perform corresponding repair operations. That is, according to the obtained first state, second state, and target reset state, this application can discover whether there are abnormal problems in the current reset process, and generate a reset repair command based on the reset test result when there are problems to control the target NVMe accelerator card to complete automatic repair. Through the above solution, the controller reset test is made more complete and comprehensive. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative efforts.

[0042] Figure 1 It is a flowchart of a traditional NVMe accelerator card controller reset test disclosed in this application;

[0043] Figure 2 It is a flowchart of a method for resetting a controller of an NVMe accelerator card disclosed in this application;

[0044] Figure 3 It is a flowchart of a specific NVMe accelerator card controller reset test disclosed in this application;

[0045] Figure 4 Schematic diagram of the system framework of a preset reset test tool disclosed in this application;

[0046] Figure 5 Schematic diagram of the format definition of a reset test command disclosed in this application;

[0047] Figure 6 Schematic diagram of the format definition of a reset repair command disclosed in this application;

[0048] Figure 7 Schematic diagram of the structure of a controller reset device for an NVMe acceleration card disclosed in this application;

[0049] Figure 8 Schematic diagram of the structure of an electronic device disclosed in this application. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0051] The currently commonly used method for resetting and testing the NVMe acceleration card controller mainly includes the following steps: (1) resetting the controller, (2) enabling the controller, and (3) testing the availability of the controller. The specific process is as Figure 1 shown below.

[0052] Among them, (1) resetting the controller includes the following sub-steps:

[0053] (a) The host NVMe driver sends an "admin command to delete the IO queue" to the NVMe acceleration card through the admin queue (management command queue). The command content includes the IO queue identifier, interrupt vector, etc. The NVMe acceleration card firmware obtains the base address of the admin queue through the "admin queue base address register" in the "device NVMe standard register", then takes out the admin command from the admin queue, and determines that it is an "admin command to delete the IO queue" by parsing the command opcode. Then, by configuring the "IO queue attribute register" inside the device, the hardware configuration attributes of the specified IO queue are deleted;

[0054] (b)The host NVMe driver triggers the device to generate a controller reset interrupt by writing the device NVMe standard register CC.EN = 0. The corresponding firmware interrupt handler then performs the following operations: reset the firmware data structures related to the controller, then configure the "reset register" of the controller hardware to reset the device NVMe standard register, and then write the NVMe standard register CSTS.RDY = 0 to notify the host that the reset is complete;

[0055] (c)The host NVMe driver continuously polls the value of the device NVMe standard register CSTS.RDY. When it detects that CSTS.RDY = 0, it considers that the controller reset is successful.

[0056] (2)Enable the controller, including the following sub-steps:

[0057] (a)The host NVMe driver configures the admin queue properties to the device NVMe standard register, and then writes the device NVMe standard register CC.EN = 1 to trigger the NVMe acceleration card hardware to generate a controller enable interrupt. The corresponding NVMe acceleration card firmware interrupt handler re-initializes the firmware data structures and device registers, and then writes the NVMe standard register CSTS.RDY = 1 to notify the host that the controller enable is complete;

[0058] (b)The host NVMe driver continuously polls the value of the device NVMe standard register CSTS.RDY. When it polls CSTS.RDY = 1, it considers that the controller enable is successful;

[0059] (c)The host NVMe driver sends a series of admin commands for enumerating NVMe devices to the NVMe acceleration card through the admin queue, including identify controller, identify namespace, set feature, etc. The NVMe acceleration card obtains the base address of the admin queue through the "admin queue base address register" in the "device NVMe standard register", and then fetches and parses a series of admin commands for enumerating NVMe devices from it and executes them.

[0060] (3)Test the controller availability, including the following sub-steps:

[0061] (a)The host NVMe driver sends an "IO queue creation" admin command to the NVMe acceleration card through the admin queue. The command content includes the IO queue identifier, interrupt vector, etc. The NVMe acceleration card obtains the admin queue base address through the "admin queue base address register" in the "device NVMe standard register", then extracts the admin command from it, determines that it is an "IO queue creation" admin command by parsing the command opcode, and then configures the "IO queue attribute register" inside the device to save the IO queue attributes;

[0062] (b)The host NVMe driver sends an "IO command for reading and writing device data" to the NVMe acceleration card through the IO queue. The command content includes the starting address of the data block, the number of data blocks, the sector address, etc. The NVMe acceleration card hardware obtains the IO queue base address through the "IO queue attribute register" inside the device, then extracts the IO command from it, determines that it is an "IO command for reading and writing device data" by parsing the command opcode, and then reads and writes the specified length of data to the specified device sector according to the IO command parameters;

[0063] (c)After the IO command execution is completed, the NVMe acceleration card hardware returns the IO command execution status to the host through the IO command response queue, including whether the command is successful, whether there is an error, and the reason for the error, etc. After the host NVMe driver detects the IO command response, it parses the command response to determine whether the IO command has been executed successfully. If successful, it is considered that the NVMe acceleration card controller reset is successful; otherwise, it is considered that the controller reset fails. On the premise of successful controller reset, observe whether other controller reset behaviors (such as the firmware receiving the IO queue deletion command, resetting the NVMe standard register of the device except for ASQ / ACQ, etc.) are correct.

[0064] Although the above method can test the controller reset, there are still many problems: First, the test is incomplete. Since traditional NVMe controller reset test tools can only observe whether admin and IO commands can be processed normally after the controller is reset from the host side, but cannot observe whether the reset range of device-side registers is correct; for example, internal registers outside the NVMe standard are reset, resulting in the device not conforming to the NVMe protocol. Second, the problem prompt is incomplete. Since traditional NVMe controller reset test tools have incomplete tests for the NVMe controller reset on the device side, the problem prompt is also incomplete and cannot comprehensively give the problem points of the NVMe controller reset on the device side, such as the reset range of registers being too small or too large, etc. Third, the problem cannot be fixed. Since traditional NVMe controller reset test tools can only give the problem points that do not conform to the NVMe controller reset, and there is no automated solution to analyze and solve the problem, it is impossible to automatically fix the controller reset problem in firmware when the controller reset problem is detected.

[0065] Therefore, the embodiments of the present application disclose a method, device, equipment and medium for resetting the controller of an NVMe acceleration card, which can achieve a more complete controller reset test and perform automated repair when problems occur.

[0066] See Figure 2 and Figure 3 As shown, the embodiments of the present application disclose a method for resetting the controller of an NVMe acceleration card, which is applied to a preset reset test tool on the target host side. The method includes:

[0067] Step S11: Send a preset reset test command to the target NVMe acceleration card; wherein, the reset test command carries the first memory address for locally pre-creating the register state before reset and the second memory address for saving the register state after reset.

[0068] The present embodiment discloses a preset reset test tool on the host side. Specifically, as Figure 4 shown, the preset reset test tool is implemented in two parts.

[0069] (1) Host NVMe controller reset test tool

[0070] It includes a "test memory management" module for managing the memory used in the controller reset test process, a "device reset test" module for executing the reset test process, and a "reset problem repair" module for fixing the discovered problem points.

[0071] (2)NVMe Accelerator Card controller Reset Processing

[0072] It includes a "Host Memory DMA" module for performing DMA (Direct Memory Access) on the memory configuration used in the host's test process, a "Device Reset Execution" module for performing the device controller reset process, and a "Register List Update" module for receiving a reset exception register list from the host through a serial port and then updating the reset exception register.

[0073] Specifically, before performing the reset test, the preset reset test tool will first call the test memory management module to create a first memory address for saving the register state before the reset and a second memory address for saving the register state after the reset locally. When performing the reset test, a preset reset test command will be sent to the target NVMe accelerator card, and the first memory address and the second memory address are carried in the reset test command.

[0074] In the specific implementation manner, sending the preset reset test command to the target NVMe accelerator card includes: determining a predefined test command format; the test command format includes an opcode for indicating the command type, a command identifier for distinguishing multiple different commands in the same management command queue, a field for recording the first memory address, and a field for recording the second memory address; and sending the preset reset test command to the target NVMe accelerator card based on the test command format through the management command queue.

[0075] That is, the preset reset test tool will construct a custom reset test command based on the predefined test command format and send the preset reset test command to the target NVMe accelerator card through the management command queue (i.e., the admin command queue). The format definition of the reset test command is as Figure 5As shown in the figure, the valid data fields in the test command format include an opcode, a reserved field, a command identifier, a first memory address, and a second memory address. Among them, the opcode = 0xda, which represents the command type and is used to distinguish other types of NVMe commands; the reserved field represents the fields not used by the NVMe protocol and is used for future protocol expansion; the command identifier represents the command sequence number in the same "admin command queue" and is used to distinguish different commands in the same "admin command queue", such as multiple commands of the same type; the first memory address represents the memory address used to save the state of the device registers before reset; the second memory address represents the memory address used to save the state of the device registers after reset. The meanings of the fields related to the command format are as follows: The T001 command contains 16 dwords (corresponding to DW0 - DW15 in the figure), each dword contains 4 bytes, the 1st byte represents the 1st byte from the low address to the high address in the dword, the 2nd byte represents the 2nd byte from the low address to the high address in the dword, and so on.

[0076] Step S12: The target NVMe accelerator card responds to the reset test command to execute a preset controller reset process, and obtains the first state written by the target NVMe accelerator card in the first memory address and the second state written in the second memory address. The first state is the state of each register in the target NVMe accelerator card before the hardware reset operation in the controller reset process; the second state is the state of each register in the target NVMe accelerator card after the hardware reset operation.

[0077] In this embodiment, after receiving the reset test command, the target NVMe accelerator card responds to the reset test command to execute a preset controller reset process. In this process, the preset reset test tool can obtain the first state written by the target NVMe accelerator card in the first memory address and the second state written in the second memory address. The first state refers to the state of each register in the target NVMe accelerator card before the hardware reset operation in the controller reset process; the second state refers to the state of each register in the target NVMe accelerator card after the hardware reset operation.

[0078] It should be noted that the preset reset test tool uses the same steps as Figure 1 the reset controller process in the traditional controller reset test method in to notify the NVMe accelerator card to reset the controller. Therefore, after receiving the reset test command, the target NVMe accelerator card extracts and saves the first memory address and the second memory address, and then enters the "reset test state". From Figure 1As can be seen, the controller reset process includes resetting the controller firmware and resetting the controller hardware. Here, the hardware reset operation in the controller reset process refers to resetting the controller hardware. Therefore, before performing the reset of the controller hardware in this application, it is necessary to write the states of all registers of the NVMe acceleration card device to the first memory address on the target host side through the DMA method, and after performing the reset of the controller hardware, write the states of all registers of the NVMe acceleration card device to the second memory address on the target host side through the DMA method.

[0079] In the specific implementation manner, the execution process of the controller reset process includes: using the NVMe device driver software on the target host side to send a target management command for deleting the input / output queue to the target NVMe acceleration card through the management command queue, so that the target NVMe acceleration card performs the deletion operation on the input / output queue based on the target management command; using the NVMe device driver software to send a control command to the target NVMe acceleration card, so that the target NVMe acceleration card generates a controller reset interrupt signal to perform the firmware reset operation and the hardware reset operation, and writes the states of each local register to the first memory address before performing the hardware reset operation, and writes the states of each local register to the second memory address after performing the hardware reset operation, and then sends a message indicating the completion of the reset to the NVMe device driver software after the firmware reset operation and the hardware reset operation are completed.

[0080] That is, first, use the NVMe device driver software on the target host side to send a target management command for deleting the input / output queue (IO queue) to the target NVMe acceleration card through the admin queue, so that the target NVMe acceleration card performs the deletion operation on the input / output queue based on the target management command. Further, use the NVMe device driver software to send a control command to the target NVMe acceleration card, specifically by writing the NVMe standard register CC.EN = 0 of the device to trigger the device to generate a controller reset interrupt, so that the target NVMe acceleration card generates a controller reset interrupt signal to perform the firmware reset operation and the hardware reset operation. Before performing the hardware reset operation, the target NVMe acceleration card will write the states of each local register to the first memory address on the host side, and after performing the hardware reset operation, write the states of each local register to the second memory address on the host side, and then send a message indicating the completion of the reset to the NVMe device driver software after the firmware reset operation and the hardware reset operation are completed.

[0081] Step S13: Based on the first state, the second state, and the target reset state specified by the NVMe protocol, determine whether the reset test result corresponding to the controller reset process meets the preset test success condition. If not, generate a reset repair command based on the reset test result and send the reset repair command to the target NVMe acceleration card so that the target NVMe acceleration card performs corresponding repair operations.

[0082] In this embodiment, the preset reset test tool reads the first state and the second state of the registers before and after the NVMe acceleration card controller is reset from the first memory address and the second memory address respectively. And import the target reset state of the NVMe standard register defined by the NVMe protocol specification from the outside, and then compare these three to determine whether the reset test result corresponding to the controller reset process meets the preset test success condition. That is, to determine whether there are abnormal problems in the current reset process, and generate a reset repair command based on the reset test result when there are problems, so as to control the target NVMe acceleration card to complete automatic repair. Through the above solution, the controller reset test is made more complete and comprehensive.

[0083] In the specific implementation manner, determining whether the reset test result corresponding to the controller reset process meets the preset test success condition based on the first state, the second state, and the target reset state specified by the NVMe protocol specifically includes: comparing the first state and the second state corresponding to the same register to determine a number of target registers whose register states have changed; determining whether each target register is a standard register specified by the NVMe protocol; if each target register is a standard register specified by the NVMe protocol, read the target reset state of the standard register specified by the NVMe protocol, and determine whether each second state is consistent with the corresponding target reset state. If each second state is consistent with the corresponding target reset state, it is determined that the standard register reset test is successful. If there is a target standard register whose second state is inconsistent with the corresponding target reset state, it is determined that the target standard register reset test fails; if there are other registers in addition to the standard registers specified by the NVMe protocol among the target registers, it is determined that the current register reset range exceeds the target reset range specified by the NVMe protocol, and it is determined that the reset test of the other registers fails.

[0084] That is, when comparing the first state, the second state, and the target reset state, first compare the first state and the second state corresponding to the same register to determine a certain number of target registers whose register states have changed, that is, first determine the registers whose states have changed before and after the hardware reset operation is executed. Further, it is determined whether each target register is a standard register specified by the NVMe protocol. The purpose of this determination step is to observe whether the register reset range at the device end is correct, such as whether there are internal registers of the device outside the NVMe standard that are reset, resulting in the device end not conforming to the NVMe protocol.

[0085] In a specific embodiment, if each target register is a standard register specified by the NVMe protocol, it indicates that the register reset range at the device end is correct, but it is still necessary to determine whether these standard registers are correctly reset. Therefore, the target reset state of the standard register specified by the NVMe protocol is read, and it is determined whether each second state is consistent with the corresponding target reset state. If each second state is consistent with the corresponding target reset state, it indicates that the standard register has been correctly reset, so it is determined that the standard register reset test is successful; in addition, if there is a target standard register whose second state is inconsistent with the corresponding target reset state, it indicates that the standard register has not been correctly reset, so it is determined that the target standard register reset test fails.

[0086] In another specific embodiment, if there are other registers in addition to the standard registers specified by the NVMe protocol among the target registers, it indicates that the current register reset range exceeds the target reset range specified by the NVMe protocol, and it is determined that the reset test of the other registers fails. That is, there are redundant non-standard registers that are reset, resulting in non-compliance with the NVMe protocol, so the reset fails.

[0087] It can be seen that this solution can not only observe whether the admin and IO commands can be normally processed after the controller is reset from the host side, but also observe whether the register reset range at the device end conforms to the NVMe controller reset. Therefore, the NVMe controller reset test is more complete; correspondingly, the controller reset problem prompt is also more complete, and it can give comprehensive NVMe controller reset problem points at the device end, such as the register reset range being too small or too large, etc.

[0088] Further, a reset repair command is generated based on the reset test result, including: determining target standard registers and the remaining registers for which the reset test fails; constructing a first key-value pair based on the base address of the target standard register and the corresponding target reset state, and storing the first key-value pair in a preset key-value pair repair list; constructing a second key-value pair based on the base address of the remaining registers and the corresponding original register state, and storing the second key-value pair in the key-value pair repair list; writing the key-value pair repair list to a pre-constructed third memory address, and generating a reset repair command carrying the third memory address.

[0089] That is, the present application constructs corresponding key-value pairs according to the target standard registers that are not correctly reset and the remaining registers that are redundantly reset. Specifically, a first key-value pair is constructed based on the base address of the target standard register and the corresponding target reset state, and the first key-value pair is stored in a preset key-value pair repair list, and a second key-value pair is constructed based on the base address of the remaining registers and the corresponding original register state, and the second key-value pair is stored in the key-value pair repair list. In addition, it should be noted that before performing the reset test, in addition to calling the test memory management module to create a first memory address and a second memory address locally, the preset reset test tool also creates a third memory address for repairing device reset problems. Therefore, the present application writes the key-value pair repair list to the third memory address and generates a reset repair command carrying the third memory address based on a predefined repair command format.

[0090] Among them, the format of the key-value pair is (register base address: register value). For example, the NVMe standard register AQA (Admin Queue Attributes) is not correctly reset. It should have been reset to 0x0 but remains 0x3F0000. Assuming its base address is 0x24, the corresponding key-value pair is expressed as (0x24: 0x0); another example is that the device custom register DEV_CTRL (0x1000) is wrongly reset, that is, its original register state value is 0xABCD1234. It should not have been reset but was cleared. Assuming its base address is 0x1000, then its corresponding key-value pair is expressed as (0x1000: 0xABCD1234).

[0091] In addition, it should be noted that if there are n register values, it means that n 32-bit registers starting from the register base address need to be updated. That is to say, the present application provides a batch update mechanism for a continuous register area:

[0092] Register base address: starting register address;

[0093] n register values: n 32-bit values to be written;

[0094] Update range: n consecutive 32-bit register spaces starting from the base address.

[0095] The format definition of the reset repair command is as Figure 6 shown. Its format definition is similar to that of the reset test command, except that its operation code = 0xdb, which is used to represent the reset repair command. In addition, the valid data field includes the third memory address, which represents the memory address used to save the key-value pair repair list.

[0096] Furthermore, sending the reset repair command to the target NVMe acceleration card so that the target NVMe acceleration card performs the corresponding repair operations includes: sending the reset repair command to the target NVMe acceleration card through the management command queue, so that the target NVMe acceleration card parses the reset repair command to obtain the third memory address, and repairs the corresponding register status based on the key-value pair repair list obtained from the third memory address, and sends a target message indicating that the reset repair command has been executed to the target host after the repair is completed. That is to say, this application still uses the management command queue to send the reset repair command to the target NVMe acceleration card, so that the target NVMe acceleration card parses the reset repair command to obtain the third memory address, and enters the "reset repair state", then obtains the key-value pair repair list from the third memory address and saves it inside the device firmware, so as to repair the corresponding register status using each key-value pair stored in the key-value pair repair list, and finally sends a target message to notify the host that the "reset repair command" has ended. It can be seen that this application can not only give the problem points that do not conform to the NVMe controller reset, but also automatically analyze the solution to the problem. Therefore, when the controller reset problem is detected, the problem can be automatically repaired in firmware mode.

[0097] Among them, in order to ensure the safe and stable operation of the target NVMe acceleration card, digital signatures can also be used to verify the legality of the key-value pair repair list, ensuring that only authorized key-value pair repair lists can be executed by the acceleration card device, fundamentally eliminating the risk of malicious tampering with register configurations. In the specific implementation, during the stage of creating the key-value pair repair list, the private key can be used to encrypt the key-value pair repair list to generate a digital signature. The generated digital signature will be embedded in the key-value pair repair list and stored and transmitted together with other data in the list, so that when the NVMe acceleration card firmware obtains the key-value pair repair list, it can also obtain the corresponding digital signature. When the NVMe acceleration card receives the key-value pair repair list, it needs to obtain the corresponding public key for signature verification. The public key and the private key used to generate the digital signature before are a pair of key pairs, and the public key can be obtained publicly. In system design, the public key is usually pre-stored in a specific area of the NVMe acceleration card or sent to the NVMe acceleration card from the host in a secure manner. The NVMe acceleration card uses the extracted public key to decrypt the digital signature in the repair list; at the same time, it uses the same hash algorithm to recalculate the hash value of the content of the repair list. If the decrypted digital signature is consistent with the recalculated hash value, it means that the key-value pair repair list has not been tampered with during transmission and its source is trustworthy, that is, the repair list is legal; otherwise, if the two are inconsistent, it indicates that the key-value pair repair list may have been tampered with or interfered with, and this repair list will be regarded as illegal and will not be applied to the register repair operation of the device.

[0098] In addition, the above method further includes: after obtaining the target message sent by the target NVMe acceleration card, performing a clearing operation on the content stored in the first memory address, the second memory address, and the third memory address. That is, after the host receives the target message, it clears the first memory address and the second memory address used to save the device register states before and after reset, and clears the third memory address used to repair the device reset problem, that is, to save the key-value pair repair list.

[0099] It should be noted that this application can add different processing according to the "device state" during the "reset controller hardware stage" of the traditional controller reset. When the "device state" is the "default state", only the controller hardware is reset; when the "device state" is the "reset test state", the controller hardware is reset, and the register states before and after the device reset are written into the first memory address and the second memory address through DMA; when the "device state" is the "reset repair state", after the controller hardware is reset, the registers are updated according to the key-value pair repair list.

[0100] It can be seen that the present application discloses a preset reset test tool for the host side. Before performing the reset test, the preset reset test tool will first create a first memory address for storing the register status before reset and a second memory address for storing the register status after reset locally. When performing the reset test, a preset reset test command will be sent to the target NVMe accelerator card, and the first memory address and the second memory address are carried in the reset test command. Further, after receiving the reset test command, the target NVMe accelerator card responds to the reset test command to execute the preset controller reset process. During this process, the preset reset test tool can obtain the first status written by the target NVMe accelerator card in the first memory address and the second status written in the second memory address. The first status refers to the register statuses in the target NVMe accelerator card before the hardware reset operation in the controller reset process; the second status refers to the register statuses in the target NVMe accelerator card after the hardware reset operation. After obtaining the first status and the second status, the preset reset test tool combines the target reset status specified by the NVMe protocol to determine whether the reset test result corresponding to the controller reset process meets the preset test success condition. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe accelerator card so that the target NVMe accelerator card can perform the corresponding repair operation. That is, the present application can discover whether there are abnormal problems in the current reset process based on the obtained first status, second status, and target reset status, and generate a reset repair command based on the reset test result when there are problems to control the target NVMe accelerator card to complete automatic repair. Through the above solution, the controller reset test is made more complete and comprehensive.

[0101] See Figure 7 As shown, an embodiment of the present application discloses a controller reset device for an NVMe accelerator card, which is applied to a preset reset test tool for a target host side. The device includes:

[0102] A test command sending module 11, configured to send a preset reset test command to the target NVMe accelerator card; wherein, the reset test command carries a first memory address locally created in advance for storing the register status before reset and a second memory address for storing the register status after reset;

[0103] A status acquisition module 12 is configured to respond to a reset test command through a target NVMe accelerator card to execute a preset controller reset process, and acquire a first status written by the target NVMe accelerator card at a first memory address and a second status written at a second memory address; the first status is the status of each register in the target NVMe accelerator card before the hardware reset operation in the controller reset process; the second status is the status of each register in the target NVMe accelerator card after the hardware reset operation.

[0104] A reset repair module 13 is configured to determine whether the reset test result corresponding to the controller reset process meets a preset test success condition based on the first status, the second status, and the target reset status specified by the NVMe protocol. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe accelerator card so that the target NVMe accelerator card performs corresponding repair operations.

[0105] It can be seen that the present application discloses a preset reset test tool on the host side. Before performing the reset test, the preset reset test tool will first create a first memory address for storing the register status before the reset and a second memory address for storing the register status after the reset locally, so that when performing the reset test, a preset reset test command will be sent to the target NVMe accelerator card, and the first memory address and the second memory address are carried in the reset test command. Further, after receiving the reset test command, the target NVMe accelerator card responds to the reset test command to execute a preset controller reset process. During this process, the preset reset test tool can acquire the first status written by the target NVMe accelerator card at the first memory address and the second status written at the second memory address. The first status refers to the status of each register in the target NVMe accelerator card before the hardware reset operation in the controller reset process; the second status refers to the status of each register in the target NVMe accelerator card after the hardware reset operation. After acquiring the first status and the second status, the preset reset test tool combines the target reset status specified by the NVMe protocol to determine whether the reset test result corresponding to the controller reset process meets the preset test success condition. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe accelerator card so that the target NVMe accelerator card performs corresponding repair operations. That is, the present application can discover whether there are abnormal problems in the current reset process according to the acquired first status, second status, and target reset status, and generate a reset repair command based on the reset test result when there are problems to control the target NVMe accelerator card to complete automatic repair. Through the above solution, the controller reset test is more complete and comprehensive.

[0106] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part are described with reference to the embodiments of the above method part and will not be elaborated herein.

[0107] Figure 8 FIG. is a schematic structural diagram of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the NVMe acceleration card controller reset method executed by the electronic device disclosed in any of the foregoing embodiments.

[0108] In this embodiment, the power supply 23 is used to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed thereon herein; the input / output interface 25 is used to obtain external input data or output data to the outside, and the specific interface type thereof can be selected according to specific application needs, and no specific limitation is made herein.

[0109] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one of the following hardware forms: DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0110] In addition, as a carrier for storing resources, the memory 22 can be a read-only memory, a random access memory, a magnetic disk, an optical disc, etc. The resources stored thereon include an operating system 221, a computer program 222, data 223, etc. The storage method can be transient storage or permanent storage.

[0111] Among them, the operating system 221 is used to manage and control each hardware device on the electronic device 20 and the computer program 222, so as to enable the processor 21 to perform operations and processing on the massive data 223 in the memory 22. It can be Windows, Unix, Linux, etc. In addition to the computer program that can be used to complete the controller reset method of the NVMe acceleration card executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks. The data 223 can include not only the data transmitted by external devices received by the electronic device, but also the data collected by its own input / output interface 25, etc.

[0112] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium. When a computer program stored in the storage medium is loaded and executed by a processor, the steps of the controller reset method of the NVMe acceleration card disclosed in any of the foregoing embodiments are implemented.

[0113] An embodiment of the present invention also discloses a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the controller reset method of the NVMe acceleration card disclosed in any of the foregoing embodiments are implemented.

[0114] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0115] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0116] The steps of the methods or algorithms described in combination with the embodiments disclosed in this document can be implemented directly by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any other form of storage medium well-known in the technical field.

[0117] Finally, it should also be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0118] The above has introduced in detail a method, device, equipment and storage medium for resetting the controller of an NVMe acceleration card provided by the present invention. Specific examples are used in this document to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for resetting a controller of an NVMe acceleration card, characterized in that, A preset reset test tool applied to the target host side, the method includes: Sending a preset reset test command to the target NVMe acceleration card; wherein, the reset test command carries a first memory address pre-created locally for storing the register state before reset and a second memory address for storing the register state after reset; Responding to the reset test command by the target NVMe acceleration card to execute a preset controller reset process, and obtaining a first state written by the target NVMe acceleration card in the first memory address and a second state written in the second memory address; the first state is the state of each register in the target NVMe acceleration card before the hardware reset operation in the execution of the controller reset process by the target NVMe acceleration card; the second state is the state of each register in the target NVMe acceleration card after the execution of the hardware reset operation; Based on the first state, the second state and the target reset state specified by the NVMe protocol, determining whether the reset test result corresponding to the controller reset process meets the preset test success condition; if not, generating a reset repair command based on the reset test result and sending the reset repair command to the target NVMe acceleration card so that the target NVMe acceleration card performs corresponding repair operations.

2. The controller reset method of the NVMe acceleration card according to claim 1, characterized in that The sending the preset reset test command to the target NVMe acceleration card includes: Determining a predefined test command format; the test command format includes an opcode for indicating the command type, a command identifier for distinguishing multiple different commands in the same management command queue, a field for recording the first memory address, and a field for recording the second memory address; Based on the test command format and through the management command queue, sending a preset reset test command to the target NVMe acceleration card.

3. The method for resetting the controller of the NVMe acceleration card according to claim 1, wherein The execution process of the controller reset process includes: Using the NVMe device driver software of the target host side to send a target management command for deleting the input / output queue to the target NVMe acceleration card through the management command queue, so that the target NVMe acceleration card performs the deletion operation on the input / output queue based on the target management command; Using the NVMe device driver software to send a control command to the target NVMe acceleration card, so that the target NVMe acceleration card generates a controller reset interrupt signal to perform a firmware reset operation and a hardware reset operation, and writes the state of each local register into the first memory address before the execution of the hardware reset operation, and writes the state of each local register into the second memory address after the execution of the hardware reset operation, and then sends a message indicating the completion of the reset to the NVMe device driver software after the execution of the firmware reset operation and the hardware reset operation.

4. The method for resetting the controller of the NVMe acceleration card according to any one of claims 1 to 3, characterized in that, The determining whether the reset test result corresponding to the controller reset process meets the preset test success condition based on the first state, the second state and the target reset state specified by the NVMe protocol includes: Compare the first state and the second state corresponding to the same register to determine a number of target registers whose register states have changed; Determine whether each of the target registers is a standard register specified by the NVMe protocol; If each of the target registers is a standard register specified by the NVMe protocol, read the target reset state of the standard register specified by the NVMe protocol, and determine whether each of the second states is consistent with the corresponding target reset state. If each of the second states is consistent with the corresponding target reset state, it is determined that the reset test of the standard register is successful. If there is a target standard register whose second state is inconsistent with the corresponding target reset state, it is determined that the reset test of the target standard register fails; If there are other registers in addition to the standard registers specified by the NVMe protocol among the target registers, it is determined that the current register reset range exceeds the target reset range specified by the NVMe protocol, and it is determined that the reset test of the other registers fails.

5. The controller reset method of the NVMe acceleration card according to claim 4, wherein, The generating a reset repair command based on the reset test result includes: Determine the target standard registers and the other registers for which the reset test fails; Construct a first key-value pair based on the base address of the target standard register and the corresponding target reset state, and store the first key-value pair in a preset key-value pair repair list; Construct a second key-value pair based on the base address of the other register and the corresponding original register state, and store the second key-value pair in the key-value pair repair list; Write the key-value pair repair list to a pre-constructed third memory address, and generate a reset repair command carrying the third memory address.

6. The controller reset method of the NVMe acceleration card according to claim 5, characterized in that, The sending the reset repair command to the target NVMe accelerator card so that the target NVMe accelerator card performs corresponding repair operations includes: Send the reset repair command to the target NVMe accelerator card through the management command queue, so that the target NVMe accelerator card parses the reset repair command to obtain the third memory address, and repairs the corresponding register state based on the key-value pair repair list obtained from the third memory address, and after the repair is completed, send a target message indicating that the reset repair command has been executed to the target host.

7. The controller reset method of the NVMe acceleration card according to claim 6, characterized in that It further includes: After obtaining the target message sent by the target NVMe accelerator card, perform a clearing operation on the content stored in the first memory address, the second memory address, and the third memory address.

8. A controller reset device for an NVMe acceleration card, characterized by A preset reset test tool applied to a target host, the device includes: A test command sending module, configured to send a preset reset test command to a target NVMe accelerator card; wherein, the reset test command carries a first memory address locally pre-created for saving the register state before reset and a second memory address for saving the register state after reset; A status acquisition module, configured to respond to the reset test command through the target NVMe accelerator card to execute a preset controller reset process, and acquire a first status written by the target NVMe accelerator card in the first memory address and a second status written by the target NVMe accelerator card in the second memory address; the first status is the status of each register in the target NVMe accelerator card before the hardware reset operation in the execution of the controller reset process by the target NVMe accelerator card; the second status is the status of each register in the target NVMe accelerator card after the execution of the hardware reset operation. A reset repair module, configured to determine whether a reset test result corresponding to the controller reset process meets a preset test success condition based on the first status, the second status, and a target reset status specified by the NVMe protocol. If not, a reset repair command is generated based on the reset test result and sent to the target NVMe accelerator card, so that the target NVMe accelerator card performs corresponding repair operations.

9. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the steps of the controller reset method for the NVMe accelerator card according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, For storing a computer program; wherein, when the computer program is executed by a processor, the steps of the controller reset method for the NVMe accelerator card according to any one of claims 1 to 7 are implemented.

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