Cache access method and device, equipment and storage medium

Abstract

The invention provides a cache access method and device, equipment and a storage medium, the method is applied to a QPC cache, and the method comprises the following steps: receiving a read request and a first update signal sent by an RDMA network card; the first update signal is used for indicating an operation type of an update operation performed on the target data by the QPC cache; the target data is the data requested by the read request; under the condition that the QPC cache is hit, sending target data to the RDMA network card in response to the read request, and determining a target field for updating in the target data based on preset arbitration logic; and updating the target data according to the operation type and the target field. According to the invention, the working efficiency of cache access can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a cache access method, apparatus, device, and storage medium. Background Art

[0002] Remote direct memory access (RDMA) is a network technology that allows one computer system to directly access the memory of another computer system. By bypassing the operating system's network protocol stack, it enables direct data transfer between application memories, significantly improving data transmission efficiency and reducing latency.

[0003] When the RDMA network card accesses the queue pair context cache (QPC cache) to read target information, two request operations are required, namely a read request and a write request, to prepare for the next access without affecting subsequent operations. This takes a long time and reduces the efficiency of cache access. Summary of the Invention

[0004] The present disclosure provides a cache access method, apparatus, device, and storage medium, which can improve the working efficiency of cache access.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] The present disclosure provides a cache access method, applied to a QPC cache, comprising: receiving a read request and a first update signal sent by a remote direct memory access (RDMA) network card; the first update signal being used to indicate an operation type of an update operation performed by the QPC cache on target data; the target data being the data requested by the read request; in the event of a hit in the QPC cache, sending the target data to the RDMA network card in response to the read request, determining a target field to be updated in the target data based on preset arbitration logic; and updating the target data based on the operation type and the target field.

[0007] In some possible implementations, the read request carries an address index pointing to target data; and in the case of a QPC cache hit, the target data is sent to the RDMA network card in response to the read request, including: in the case of a QPC cache hit, in response to the read request, obtaining the target data from the address pointed to by the address index; and sending the target data to the RDMA network card.

[0008] In some possible embodiments, a first address tag is carried in the read request; in the case of hitting the QPC cache, before sending the target data to the RDMA network card in response to the read request and determining the target field to be updated in the target data based on a preset arbitration logic, the above method further includes: obtaining a second address tag; the second address tag corresponds to the target data; in the case where the first address tag and the second address tag match, it is determined that the QPC cache is hit; in the case where the first address tag and the second address tag do not match, it is determined that the QPC cache is not hit.

[0009] In some possible embodiments, the above method further includes: in the case where the QPC cache is not hit, sending indication information to the RDMA network card; the indication information is used to instruct the RDMA network card to obtain the target data from the memory.

[0010] The present disclosure provides a cache access method, which is applied to an RDMA network card. The method includes: generating a read request; the read request is used to request to obtain target data from the QPC cache; based on the read request, generating a first update signal; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; sending the read request and the first update signal to the QPC cache; receiving the target data sent by the QPC cache in response to the read request.

[0011] In some possible embodiments, the read request carries an address index pointing to the target data; receiving the target data sent by the QPC cache in response to the read request includes: receiving the target data obtained at the address pointed to by the address index sent by the QPC cache.

[0012] In some possible embodiments, the method further includes: in the case where the QPC cache is not hit, receiving the indication information sent by the QPC cache; the indication information is used to instruct the RDMA network card to obtain the target data from the memory; in response to the indication information, obtaining the target data from the memory.

[0013] The present disclosure provides a cache access device, which is executed by the QPC cache. The device includes: a first receiving module, configured to receive the read request and the first update signal sent by the RDMA network card; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; the target data is the data requested by the read request; a first sending module, configured to, in the case of hitting the QPC cache, send the target data to the RDMA network card in response to the read request and determine the target field to be updated in the target data based on a preset arbitration logic; an update module, configured to update the target data according to the operation type and the target field.

[0014] In some possible embodiments, the read request carries an address index pointing to the target data; a first sending module, configured to, when hitting the QPC cache, in response to the read request, obtain the target data from the address pointed to by the address index; and send the target data to the RDMA network card.

[0015] In some possible embodiments, the read request carries a first address tag; the above device further includes: a judging module, configured to obtain a second address tag; the second address tag corresponds to the target data; when the first address tag and the second address tag match, it is determined that the QPC cache is hit; when the first address tag and the second address tag do not match, it is determined that the QPC cache is not hit.

[0016] In some possible embodiments, the first sending module is further configured to, when the QPC cache is not hit, send indication information to the RDMA network card; the indication information is used to instruct the RDMA network card to obtain the target data from the memory.

[0017] The present disclosure provides a cache access device, which is executed by an RDMA network card. The above device includes: a data generation module, configured to generate a read request; the read request is used to request to obtain target data from a queue pair context cache (QPC cache); the data generation module is further configured to, based on the read request, generate a first update signal; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; a second sending module, configured to send the read request and the first update signal to the QPC cache; a second receiving module, configured to receive the target data sent by the QPC cache in response to the read request.

[0018] In some possible embodiments, the read request carries an address index pointing to the target data; the second receiving module is configured to receive the target data obtained from the address pointed to by the address index and sent by the QPC cache.

[0019] In some possible embodiments, the second receiving module is further configured to, when the QPC cache is not hit, receive the indication information sent by the QPC cache; the indication information is used to instruct the RDMA network card to obtain the target data from the memory; the above device further includes: a data acquisition module, configured to, in response to the indication information, obtain the target data from the memory.

[0020] The present disclosure provides an electronic device, including: a memory, configured to store executable instructions; a processor, configured to, when executing the executable instructions stored in the memory, implement the method provided by the present disclosure.

[0021] The present disclosure provides a computer storage medium storing executable instructions, which, when executed by a processor, are used to implement the method provided by the present disclosure.

[0022] The present disclosure provides a computer program product including a computer program or instructions, which, when executed by a processor, are used to implement the method provided by the present disclosure.

[0023] In the present disclosure, after the QPC cache sends the target data to the RDMA network card, it can determine the target fields in the target data that need to be updated according to the preset arbitration logic, and then directly update the target data in the QPC cache without writing back the target data after the update. In this way, after updating the target data, the time for the RDMA network card to send a write request to access the QPC cache can be saved, and the working efficiency of cache access can be improved.

[0024] Furthermore, the cache access method described in the present disclosure only performs one request operation, which can avoid data conflicts (that is, after the request is completed, the data stored in the QPC cache is not the expected data) in the case where multiple hosts perform write operations on the same QP, which is beneficial to maintaining the consistency of the QPC cache.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0027] Figure 1 It is a schematic structural diagram of a queue pair in an embodiment of the present disclosure;

[0028] Figure 2 It is a schematic structural diagram of memory and RDMA in an embodiment of the present disclosure;

[0029] Figure 3 It is a schematic flowchart of a cache access method in an embodiment of the present disclosure;

[0030] Figure 4 It is a schematic flowchart of the first embodiment of the cache access method in an embodiment of the present disclosure;

[0031] Figure 5 It is a schematic flowchart of the second embodiment of the cache access method in an embodiment of the present disclosure;

[0032] Figure 6 It is a schematic flowchart of the third embodiment of the cache access method in an embodiment of the present disclosure;

[0033] Figure 7 It is a schematic flowchart of the fourth embodiment of the cache access method in the embodiments of the present disclosure;

[0034] Figure 8 It is the first signal flow diagram of the cache access method in the embodiments of the present disclosure;

[0035] Figure 9 It is the second signal flow diagram of the cache access method in the embodiments of the present disclosure;

[0036] Figure 10 It is the first structural diagram of the cache access device in the embodiments of the present disclosure;

[0037] Figure 11 It is the second structural diagram of the cache access device in the embodiments of the present disclosure. Detailed implementation manners

[0038] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present disclosure. On the contrary, they are only examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0039] To illustrate the technical solutions described in the present disclosure, the following will be described through specific examples.

[0040] Remote direct memory access (RDMA) is a new direct memory access technology that allows data to be directly transferred between computing nodes without occupying the resources of the central processing unit (CPU). It can provide extremely high network bandwidth and has the characteristics of low latency and low CPU overhead. RDMA network cards are widely used in various fields such as high-performance computing and big data analysis. During the implementation of RDMA, a queue pair (QP) is a virtual interface between hardware and software, and it can also be understood that QP is a data structure maintained by the driver. The hardware stores the relevant attributes of QP, that is, the queue pair context (QPC), to synchronize QP information between hardware and software.

[0041] In some embodiments, the QP includes a send queue (SQ), a receive queue (RQ), and a completion queue (CQ). Among them, the SQ stores the tasks sent from software to hardware in sequence, that is, work queue elements (WQEs). Figure 1 is a schematic structural diagram of the queue pair in the embodiments of the present disclosure. Refer to Figure 1 As shown, the QP is a storage space containing several WQEs.

[0042] In some embodiments, in order to avoid frequent access to memory to obtain QPC information, a queue pair context cache (QPC cache) is introduced. In the QPC cache implementation scheme, when a read request is received, it is judged whether there is a hit. If there is a hit, the content at the corresponding address is read out. If there is no hit, memory is accessed to obtain the data at the corresponding address. When a write request is received, it is judged whether there is a hit. If there is a hit, the data to be written is written to the corresponding address. If there is no hit, it is written to the corresponding address in memory.

[0043] In some embodiments, software can design a certain data structure as the attribute information of the QP (such as service type, the current WQE to be processed, etc.) data to apply for memory space for storage. However, what software sees are all virtual addresses, which are discrete in the physical space, and hardware cannot confirm the storage locations of these data. This requires software to apply for a large continuous space in advance, that is, QPC, to carry this information to hardware.

[0044] In some embodiments, in order to avoid frequent access to the memory and reduce the latency caused by accessing the memory through the bus, a part of the relevant information QPC of the QP can be stored in the Cache, that is, QPC Cache. Each QP corresponds to a QPC. When the RDMA network card needs to transmit the QPC content, it can first access the QPC Cache. If the information needed is stored in the QPC Cache, there is no need to access the memory through the bus. If the required information is not found in the QPC Cache, then access the memory through the bus.

[0045] In some embodiments, Figure 2 is a schematic structural diagram of the memory and RDMA in the embodiments of the present disclosure. Refer to Figure 2 as shown in (a) therein, the QP and the QPC are discrete. Refer to Figure 2 as shown in (b) therein, after introducing the QPC Cache technology, the relevant information QPC of the QP can be cached in the QPC Cache, and the QPC information can be quickly obtained by accessing the QPC Cache.

[0046] In some embodiments, Figure 3 is a schematic flowchart of a cache access method in an embodiment of the present disclosure. Refer to Figure 3 As shown, the process of the cache access method is as follows:

[0047] S301, the RDMA network card sends a read request, and the read request is used to request target data.

[0048] S302, the QPC Cache determines whether it is hit. If it is hit, S303 is executed; if not, S304 is executed.

[0049] S303, the QPC Cache reads out the target data and sends the data to the RDMA network card.

[0050] S304, the RDMA network card accesses the memory through the bus to read the target data and saves the target data to the QPC Cache.

[0051] S305, the RDMA network card updates the received target data.

[0052] S306, the RDMA network card sends a write request to the QPC Cache.

[0053] S307, the QPC Cache determines whether it is hit. If it is hit, S308 is executed; if not, S309 is executed.

[0054] S308, the RDMA network card writes the updated target data into the QPC Cache.

[0055] S309, the RDMA network card accesses the memory through the bus to obtain the target data and writes the updated target data into the QPC Cache.

[0056] S310, the QPC Cache enters the ready state.

[0057] When using the above solution in the QPC Cache, the efficiency is relatively low. When a read request is received and it is hit, the content at the corresponding address is read. However, after each time the content at the corresponding position in the QPC Cache is read, the content at the corresponding position needs to be updated according to the situation. Therefore, after each read request is executed, the updated data needs to be written back to the corresponding address. This makes it necessary to add the process of writing back data every time the QPC Cache executes a read request, increasing the latency. When multiple command messages need to access the same QPC Cache simultaneously, multiple read and write operations are required. The process of multiple read and write operations occupies a large bandwidth, reducing the working efficiency of the Cache and thus affecting the performance.

[0058] To solve the above problems, embodiments of the present disclosure provide a cache access method, apparatus, device, and storage medium to improve the working efficiency of cache access.

[0059] Figure 4 FIG. 4 is a schematic flowchart of a first embodiment of the cache access method in the embodiments of the present disclosure. This method is applied to the QPC cache. Refer to Figure 4 As shown, the method may include:

[0060] S401, receiving a read request and a first update signal sent by the RDMA network card. Among them, the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; the target data is the data requested by the read request.

[0061] It can be understood that before reading out the target data, the RDMA network card may send a read request and a first update signal to the QPC cache. The read request is used to request the target data cached in the QPC cache, and the first update signal is used to indicate how to update the target data in the QPC cache, that is, the operation type of the update.

[0062] In some embodiments, the RDMA network card sends a read request and a first update signal through a queue pair (QP). This read request can be encapsulated as a work queue element (WQE) and submitted to the send queue (SQ).

[0063] In some embodiments, the QPC cache needs to maintain a "ready" state to ensure correct processing when receiving a read request and a first update signal. The state management of the QPC Cache is a key part of the normal operation of the QPC Cache, ensuring timely data update and response.

[0064] S402, when the QPC cache is hit, in response to the read request, send the target data to the RDMA network card, and determine the target field to be updated in the target data based on a preset arbitration logic.

[0065] It can be understood that when the QPC cache is hit, it means that the target data requested by the RDMA request is cached in the QPC cache. In response to the read request, the QPC cache sends the target data to the RDMA network card.

[0066] In some embodiments, when the RDMA network card initiates a read request, an address index and an address tag can be used to check the QPC Cache to determine whether the requested data is already in the cache. If there is a cache hit, it indicates that the requested data can be directly retrieved from the QPC Cache.

[0067] In some embodiments, a preset arbitration logic is cached in the QPC cache. In the case of a QPC cache hit, the QPC cache can determine the fields to be updated for the target data based on the preset arbitration logic and the read request. For example, the target data A is {A, B, C, D}, and the first update signal can instruct the QPC cache to update fields B and D of the target data, and fields B and D are the target fields.

[0068] In some embodiments, the arbitration logic can be set based on various factors, such as the importance of the data, the update frequency, the data consistency requirements, etc. The embodiments of the present disclosure do not specifically limit the setting rules of the arbitration logic.

[0069] In one example, taking the importance of the data as the rule for setting the arbitration logic as an example, the target data B is {E, F, G, H}, and the target data includes four fields, namely E, F, G, and H. The importance ranking of the above four fields is as follows: G > E > H > F. The arbitration logic can be set to update the fields with the top 50% importance ranking. Then, the target fields of the target data B are G and E.

[0070] S403. Update the target data according to the operation type and the target fields.

[0071] It can be understood that the QPC cache can update the target data according to the operation type indicated by the first update signal and the target fields determined based on the arbitration logic.

[0072] In some possible implementation manners, the read request carries an address index pointing to the target data; in the case of a QPC cache hit, sending the target data to the RDMA network card in response to the read request may include: in the case of a QPC cache hit, in response to the read request, obtaining the target data at the address pointed to by the address index; sending the target data to the RDMA network card.

[0073] It can be understood that the QPC cache receives a read request carrying an address index, and the address index is used to locate a specific data block in the QPC cache. Then, the QPC cache can obtain the target data corresponding to the address index in the cache and send the target data to the RDMA network card.

[0074] In some embodiments, after receiving the target data, the RDMA network card may generate a completion queue element (CQE) to notify the application program that controls the RDMA network card. The application program may confirm whether the operations related to the read request are successful by checking the CQE.

[0075] In some possible implementation manners, a first address tag is carried in the read request; before the above S402, the method may further include: obtaining a second address tag; the second address tag corresponds to the target data; in a case where the first address tag and the second address tag match, it is determined that the QPC cache is hit; in a case where the first address tag and the second address tag do not match, it is determined that the QPC cache is not hit.

[0076] It can be understood that the read request may also carry a first address tag, which is an identifier used by the RDMA network card to represent the requested data. The QPC Cache stores a second address tag associated with the cached data block, which is used to identify the data block stored in the cache. After receiving the read request, the QPC Cache compares the first address tag and the second address tag. If the first address tag and the second address tag match, it means that the target data requested by the RDMA network card is already in the QPC Cache, that is, a cache hit occurs. If the first address tag and the second address tag do not match, the read request misses the QPC Cache.

[0077] In some possible implementation manners, the method may further include: in a case where the QPC cache is not hit, sending indication information to the RDMA network card; the indication information is used to instruct the RDMA network card to obtain the target data in the memory.

[0078] It can be understood that in a case where the QPC cache is not hit, the QPC cache may send indication information to the RDMA network card to instruct the RDMA network card to access the memory through the bus to obtain the target data.

[0079] In some embodiments, after the RDMA network card accesses the memory through the bus to obtain the target data, the target data may be cached in the QPC cache so that the target data can be obtained in the QPC cache through a read request later.

[0080] An embodiment of the present disclosure provides a cache access method, which is applied to an RDMA network card. Figure 5 For the second embodiment flowchart of the cache access method in the embodiments of the present disclosure, see Figure 5 As shown, the method may include:

[0081] S501, generate a read request. The read request is used to request to obtain target data from the QPC cache.

[0082] It can be understood that before the RDMA network card requests data, it can first generate a read request.

[0083] S502, based on the read request, generate a first update signal. The first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data.

[0084] It can be understood that the RDMA network card can generate a first update signal based on the read request, and the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data.

[0085] S503, send the read request and the first update signal to the QPC cache.

[0086] It can be understood that after the RDMA network card generates the read request and the first update signal, it simultaneously sends the read request and the first update signal to the QPC cache to request the target data and indicate the QPC cache to update the target data.

[0087] S504, receive the target data sent by the QPC cache in response to the read request.

[0088] It can be understood that the QPC cache sends the cached target data to the RDMA network card in response to the read request.

[0089] In some possible implementation manners, the read request carries an address index pointing to the target data; the above S504 may include: receiving the target data obtained at the address pointed to by the address index sent by the QPC cache.

[0090] It can be understood that the read request carries an address index, and the address index is used to locate a specific data block in the QPC cache. The QPC cache can obtain the target data corresponding to the address index in the cache based on the address index, send the target data to the RDMA network card, and the RDMA network card receives the target data sent by the QPC cache.

[0091] In some possible implementation manners, the above method further includes: in the case of a miss in the QPC cache, receiving the indication information sent by the QPC cache; the indication information is used to indicate the RDMA network card to obtain the target data in the memory; in response to the indication information, obtaining the target data in the memory.

[0092] It can be understood that in the case of hitting the QPC cache, the RDMA can receive the target data from the QPC cache; while in the case of missing the QPC cache, the QPC cache can send indication information to the RDMA network card; in response to the indication information, the RDMA network card accesses the memory through the bus to obtain the target data.

[0093] Figure 6 FIG. 3 is a schematic flowchart of a third embodiment of the cache access method in the embodiments of the present disclosure. The following will be combined with Figure 5 to describe the cache access method of the embodiments of the present disclosure.

[0094] S601, the RDMA network card sends a read request and a first update signal to the QPC cache.

[0095] S602, the QPC cache determines whether it is hit based on the read request. If it is hit, S603 is executed; if it is not hit, S604 is executed.

[0096] S603, the QPC cache reads out the target data from the cache based on the read request and sends the data to the RDMA network card.

[0097] S604, the RDMA network card accesses the memory through the bus to read out the target data and caches the target data in the QPC cache.

[0098] S605, the QPC cache determines the target field to be updated in the target data based on a preset arbitration logic, and calculates the updated target data according to the operation type indicated by the first update signal and the target field.

[0099] S606, the QPC cache caches the updated target data.

[0100] S607, the QPC cache enters the ready state and waits to receive the next read request.

[0101] Thus, the RDMA network card and the QPC cache complete the above cache access method.

[0102] In some embodiments, the storage sub-unit in the QPC cache may be a random access memory (RAM). The following takes the storage medium sub-unit in the QPC cache as RAM as an example to describe the above cache access method. Figure 7 FIG. 4 is a schematic flowchart of a fourth embodiment of the cache access method in the embodiments of the present disclosure. Refer to Figure 7 as shown, the above method includes:

[0103] S701. The QPC cache receives a read request or a write request, and the read request and the write request carry a first address tag; the RAM in the QPC cache receives the first address tag.

[0104] S702. The QPC cache determines whether there is a hit based on the first address tag. If there is a hit, it outputs the target data; if there is no hit, it instructs the RDMA network card to read the memory through the bus.

[0105] S703. In the case of a hit in the QPC cache, the QPC cache determines the target data to be updated in the target data based on the arbitration logic and writes the updated target data into the RAM; or, in the case of a hit in the QPC cache, the QPC cache obtains the target data to be written into the cache according to the write request and writes the target data into the RAM.

[0106] In some embodiments, in the cache access method, after reading the target data in the QPC cache, the stored target data needs to be updated. Figure 8 This is the first signal flow diagram of the cache access method in the embodiments of the present disclosure. Refer to Figure 8 As shown, after the read request operation is completed, a write request needs to be executed once to write the updated target data into the QPC cache; that is, for a complete cache access to read the target information process, two operations need to be performed on the QPC cache, one read request and one write request. Figure 9 This is the second signal flow diagram of the cache access method in the embodiments of the present disclosure. Refer to Figure 9 As shown, after reading out the target data, the target field is determined through the arbitration logic, and the target data is updated based on the target field to obtain the updated target data, without going through a complete write request process again.

[0107] In the embodiments of the present disclosure, after the QPC cache sends the target data to the RDMA network card, it can determine the target field to be updated in the target data according to the preset arbitration logic, and then directly update the target data in the QPC cache, without writing back the target data after the update. In this way, after updating the target data, the time for the RDMA network card to send a write request to access the QPC cache can be saved, and the working efficiency of cache access can be improved.

[0108] Furthermore, the cache access method described in the embodiments of the present disclosure only performs one request operation, which can avoid data conflicts (that is, after the request is completed, the data stored in the QPC cache is not the expected data) in the case where multiple hosts perform write operations on the same QP, which is beneficial to maintaining the consistency of the QPC cache.

[0109] Based on the same inventive concept, an embodiment of the present disclosure further provides a cache access device. This device can be a chip or a system-on-chip of a server, or can also be a functional module in the server for the method described in one or more of the above embodiments. This device is executed by the QPC cache. Figure 10 FIG. is a schematic diagram of the first structure of the cache access device in an embodiment of the present disclosure. Refer to Figure 10 As shown, the cache access device 1000 may include: a first receiving module 1001, configured to receive a read request and a first update signal sent by an RDMA network card; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; the target data is the data requested by the read request; a first sending module 1002, configured to, when the QPC cache is hit, in response to the read request, send the target data to the RDMA network card, and determine a target field to be updated in the target data based on a preset arbitration logic; an update module 1003, configured to update the target data according to the operation type and the target field.

[0110] In some possible implementation manners, the read request carries an address index pointing to the target data; the first sending module 1001 is configured to, when the QPC cache is hit, in response to the read request, obtain the target data at the address pointed to by the address index; and send the target data to the RDMA network card.

[0111] In some possible implementation manners, the read request carries a first address tag; the above device 1000 further includes: a judgment module, configured to obtain a second address tag; the second address tag corresponds to the target data; when the first address tag and the second address tag match, it is determined that the QPC cache is hit; when the first address tag and the second address tag do not match, it is determined that the QPC cache is not hit.

[0112] In some possible implementation manners, the first sending module 1001 is further configured to, when the QPC cache is not hit, send indication information to the RDMA network card; the indication information is used to indicate the RDMA network card to obtain the target data in the memory.

[0113] Based on the same inventive concept, an embodiment of the present disclosure further provides a cache access device. This device can be a chip or a system-on-chip of a server, or can also be a functional module in the server for the method described in one or more of the above embodiments. This device is executed by the RDMA network card. Figure 11 FIG. is a schematic diagram of the second structure of the cache access device in an embodiment of the present disclosure. Refer to Figure 11As shown, the cache access device 1100 may include: a data generation module 1101, configured to generate a read request; the read request is used to request to obtain target data from a queue pair context cache (QPC cache); the data generation module 1101 is further configured to generate a first update signal based on the read request; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; a second sending module 1102, configured to send the read request and the first update signal to the QPC cache; and a second receiving module 1103, configured to receive the target data sent by the QPC cache in response to the read request.

[0114] In some possible implementation manners, the read request carries an address index pointing to the target data; the second receiving module 1103 is configured to receive the target data obtained at the address pointed to by the address index and sent by the QPC cache.

[0115] In some possible implementation manners, the second receiving module 1103 is further configured to, when the QPC cache is not hit, receive indication information sent by the QPC cache; the indication information is used to indicate that an RDMA network card obtains the target data from a memory; the above device 1100 further includes: a data acquisition module, configured to obtain the target data from the memory in response to the indication information.

[0116] Embodiments of the present disclosure provide a computer program product or a computer program, which includes computer instructions stored in a computer storage medium. A processor of a computer device reads the computer instructions from the computer storage medium, and the processor executes the computer instructions, so that the computer device executes the cache access method described in the embodiments of the present disclosure.

[0117] Embodiments of the present disclosure provide a computer storage medium storing executable instructions, where the executable instructions, when executed by a processor, will cause the processor to execute the cache access method provided by the embodiments of the present disclosure, for example Figure 4 and Figure 5 the cache access method shown.

[0118] In some embodiments, the computer storage medium may be a memory such as a FRAM, a ROM, a PROM, an EPROM, an EEPROM, a flash memory, a magnetic surface memory, an optical disc, or a CD-ROM; or may be various devices including one or any combination of the above memories.

[0119] In some embodiments, the executable instructions may be in the form of a program, software, a software module, a script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as a stand-alone program or being deployed as a module, a component, a subroutine, or other unit suitable for use in a computing environment.

[0120] As an example, the executable instructions may or may not correspond to a file in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a hyper text markup language (HTML) document, stored in a single file dedicated to the program being discussed, or, stored in multiple cooperating files (such as files that store one or more modules, subroutines, or portions of code).

[0121] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one site, or, on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0122] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0123] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A cache access method, characterized in that, Applied to the queue pair context cache (QPC cache), the method includes: Receiving a read request and a first update signal sent by a remote direct memory access (RDMA) network card; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; the target data is the data requested by the read request; When the QPC cache is hit, sending the target data to the RDMA network card in response to the read request, and determining the target field to be updated in the target data based on a preset arbitration logic; Updating the target data according to the operation type and the target field.

2. The method according to claim 1, characterized in that, The read request carries an address index pointing to the target data; The step of, when the QPC cache is hit, sending the target data to the RDMA network card in response to the read request includes: When the QPC cache is hit, in response to the read request, obtaining the target data at the address pointed to by the address index; Sending the target data to the RDMA network card.

3. The method according to claim 1, characterized in that, The read request carries a first address tag; Before the step of, when the QPC cache is hit, sending the target data to the RDMA network card in response to the read request and determining the target field to be updated in the target data based on a preset arbitration logic, the method further includes: Obtaining a second address tag; the second address tag corresponds to the target data; When the first address tag and the second address tag match, determining that the QPC cache is hit; When the first address tag and the second address tag do not match, determining that the QPC cache is not hit.

4. The method according to claim 3, characterized in that, The method further includes: When the QPC cache is not hit, sending an indication message to the RDMA network card; the indication message is used to instruct the RDMA network card to obtain the target data in the memory.

5. A cache access method, characterized in that, Applied to a remote direct memory access (RDMA) network card, the method includes: Generating a read request; the read request is used to request to obtain target data in the queue pair context cache (QPC cache); Based on the read request, generating a first update signal; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; Sending the read request and the first update signal to the QPC cache; Receiving the target data sent by the QPC cache in response to the read request.

6. The method according to claim 5, characterized in that The read request carries an address index pointing to the target data; The step of receiving the target data sent by the QPC cache in response to the read request includes: Receiving the target data obtained by the QPC cache at the address pointed to by the address index.

7. The method according to claim 5, wherein The method further includes: In the case of a miss in the QPC cache, receive the indication information sent by the QPC cache; the indication information is used to instruct the RDMA network card to obtain the target data in the memory; In response to the indication information, obtain the target data in the memory.

8. A cache access device, characterized in that Executed by the queue pair context cache QPC cache, the device includes: A first receiving module, configured to receive a read request and a first update signal sent by a remote direct memory access RDMA network card; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; the target data is the data requested by the read request; A first sending module, configured to, in the case of a hit in the QPC cache, send the target data to the RDMA network card in response to the read request, and determine the target field to be updated in the target data based on a preset arbitration logic; An update module, configured to update the target data according to the operation type and the target field.

9. A cache access device, characterized in that, Executed by a remote direct memory access RDMA network card, the device includes: A data generation module, configured to generate a read request; the read request is used to request to obtain target data in the queue pair context cache QPC cache; The data generation module is further configured to generate a first update signal based on the read request; the first update signal is used to indicate the operation type of the update operation performed by the QPC cache on the target data; A second sending module, configured to send the read request and the first update signal to the QPC cache; A second receiving module, configured to receive the target data sent by the QPC cache in response to the read request.

10. An electronic device, characterized in that, The electronic device includes: A memory, configured to store executable instructions; A processor, configured to implement the method according to any one of claims 1 to 4 or claims 5 to 7 when executing the executable instructions or computer program stored in the memory.

11. A computer-readable storage medium storing executable instructions or a computer program, characterized in that, When the executable instructions are executed by the processor, the method according to any one of claims 1 to 4 or claims 5 to 7 is implemented.

12. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, the steps of the method according to any one of claims 1 to 4 or claims 5 to 7 are implemented.

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