Three-dimensional memory operation circuit

Abstract

The invention provides a three-dimensional memory operation circuit, the three-dimensional memory operation circuit comprises a peripheral circuit layer and a plurality of memory circuit layers which are sequentially stacked, the peripheral circuit layer comprises a computing circuit, the computing circuit comprises a plurality of computing units, each memory circuit layer comprises a memory matrix, the memory matrix comprises a plurality of memory units, and each memory unit comprises a plurality of memory cells. The plurality of calculation units are in one-to-one correspondence with the positions of target storage units in each layer of storage matrix in the stacking direction, and the target storage units comprise one row of storage units or one storage unit in the storage matrix to which the target storage units belong; and each calculation unit is used for acquiring target storage data in the corresponding target storage unit in the at least one layer of storage matrix, and performing calculation based on the target storage data to obtain a calculation result. Therefore, the upper limits of the storage capacity and the computing power in the in-memory operational circuit are greatly improved, and the influence on the storage density is reduced, so that the computing speed and the computing efficiency are improved, and the power consumption and the computing error are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a three-dimensional in-memory operation circuit. Background Art

[0002] With the rapid development of the digital age, storage and computing have become core requirements of modern information technology, giving rise to 3D stacked chips. 3D stacked chips are a technology that vertically stacks multiple chip layers. Compared to traditional 2D planar designs, 3D stacking significantly improves chip performance, reduces power consumption, and shrinks size. It offers the advantages of high-density integration, short interconnects, and heterogeneous integration.

[0003] In traditional 3D stacked chip design, a structure that adds computing circuits to the memory array is usually adopted to increase computing power. However, the storage capacity of 3D stacked chips with this structure is limited, and there is an upper limit to the ratio of storage capacity to computing capacity, which affects the efficiency of data calculation. If the upper limit is exceeded, there may also be losses in power consumption and reliability. Summary of the Invention

[0004] The embodiments of the present disclosure provide at least one three-dimensional in-memory computing circuit, which can significantly increase the upper limit of storage capacity and computing power in the in-memory computing circuit.

[0005] An embodiment of the present disclosure provides a three-dimensional in-memory arithmetic circuit, the three-dimensional in-memory arithmetic circuit comprising a peripheral circuit layer and a plurality of storage circuit layers stacked in sequence, the peripheral circuit layer comprising a computing circuit, the computing circuit comprising a plurality of computing units; each of the storage circuit layers comprising a storage matrix, the storage matrix comprising a plurality of storage units for storing data; the plurality of computing units corresponding one-to-one with the positions of target storage units in each layer of the storage matrix in a stacking direction, the target storage unit comprising a row of storage units or a single storage unit in the corresponding storage matrix;

[0006] Each of the calculation units is used to obtain target storage data in a corresponding target storage unit in at least one layer of the storage matrix, and perform calculation based on the target storage data to obtain a calculation result.

[0007] In an optional implementation, each of the computing units is configured to obtain target storage data in a corresponding target storage unit in at least one layer of the storage matrix, including:

[0008] Each of the computing units is used to receive a computing task, determine a target storage unit that matches the computing task from the corresponding target storage units in the storage matrix of each layer according to the computing task, and obtain target storage data in the target storage unit that matches the computing task.

[0009] In an alternative embodiment, when the target storage unit includes a row of storage units in the storage matrix, each of the storage circuit layers further includes a column address decoding module for determining, from the storage matrix, the storage units located in a first target column;

[0010] Each of the computing units is configured to obtain target storage data in corresponding target storage units in at least one layer of the storage matrix, including:

[0011] The computing unit is configured to obtain the target storage data in the storage units located in the first target column among the corresponding target storage units in at least one layer of the storage matrix.

[0012] In an alternative embodiment, the column address decoding module is located at the edge of the storage circuit layer.

[0013] In an alternative embodiment, the peripheral circuit layer further includes a read / write circuit and a row address decoding module for determining, from the storage matrix, the storage units located in a target row;

[0014] Each of the storage circuit layers further includes a column address decoding module for determining, from the storage matrix, the storage units located in a second target column;

[0015] The read / write circuit is configured to perform read / write processing on the storage data in the storage units located in the target row and in the second target column in the storage matrix.

[0016] In an alternative embodiment, the computing circuit, the row address decoding module, and the read / write circuit are arranged side by side in sequence.

[0017] In an alternative embodiment, the peripheral circuit layer further includes a control circuit for controlling the execution of the computing circuit, the column address decoding module, the row address decoding module, and the read / write circuit.

[0018] In an alternative embodiment, each of the storage units is further configured to store first check information; each of the computing units is further configured to store second check information;

[0019] Each of the computing units is configured to obtain target storage data in corresponding target storage units in at least one layer of the storage matrix and perform calculations based on the target storage data to obtain a calculation result, including:

[0020] Each of the computing units is configured to obtain target stored data and first check information in corresponding target storage units in at least one layer of the storage matrix, and perform a check on the corresponding target storage units in at least one layer of the storage matrix based on the obtained first check information and second check information of the computing unit. When the corresponding target storage units in at least one layer of the storage matrix pass the check, calculations are performed based on the target stored data to obtain a calculation result.

[0021] In an alternative embodiment, the types of the multiple storage circuit layers are the same;

[0022] The types of the multiple storage circuit layers include one of the following:

[0023] Static random access memory, dynamic random access memory, magnetoresistive random access memory, resistive random access memory.

[0024] In an alternative embodiment, the peripheral circuit layer and the storage circuit layer are chips, or the peripheral circuit layer and the storage circuit layer are bare die.

[0025] The three-dimensional in-memory computing circuit provided by the embodiments of the present disclosure includes a peripheral circuit layer and multiple storage circuit layers stacked in sequence. The peripheral circuit layer includes a computing circuit, and the computing circuit includes multiple computing units. Each storage circuit layer includes a storage matrix, and the storage matrix includes multiple storage units. The positions of the multiple computing units and the target storage units in each layer of the storage matrix correspond one-to-one in the stacking direction. The target storage unit includes a row of storage units or a storage unit in the storage matrix to which it belongs. Each computing unit is configured to obtain target stored data in the corresponding target storage units in at least one layer of the storage matrix, and perform calculations based on the target stored data to obtain a calculation result.

[0026] In this way, by stacking the peripheral circuit layer and the multiple storage circuit layers in sequence, the upper limits of the storage capacity and computing power in the in-memory computing circuit are greatly improved, effectively solving the problem of limited improvement in the storage capacity and computing capacity in traditional in-memory computing circuits, improving the reliability of the three-dimensional in-memory computing circuit, and reducing the influence of process errors; moreover, the positions of the multiple computing units in the peripheral circuit layer and the target storage units in each layer of the storage matrix correspond one-to-one in the stacking direction, effectively reducing the proportion of the computing units in the three-dimensional in-memory computing circuit, reducing the influence on the storage density, and greatly increasing the storage units corresponding to each computing unit without increasing the distance between the computing unit and the corresponding storage unit, thereby improving the computing speed and computing efficiency, and reducing the power consumption and computing error.

[0027] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the technical solutions of the present disclosure.

[0028] In order to make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for use in the embodiments. Here, the drawings are incorporated into the specification and constitute a part of this specification. These drawings show embodiments that conform to the present disclosure and, together with the specification, are used to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0030] Figure 1 shows a schematic structural diagram of an in-memory computing circuit in the related art;

[0031] Figure 2 shows a schematic structural diagram of a three-dimensional in-memory computing circuit provided by an embodiment of the present disclosure;

[0032] Figure 3 shows a schematic structural diagram of another three-dimensional in-memory computing circuit provided by an embodiment of the present disclosure;

[0033] Figure 4 shows a schematic structural diagram of another three-dimensional in-memory computing circuit provided by an embodiment of the present disclosure;

[0034] Figure 5 shows a schematic structural diagram of yet another three-dimensional in-memory computing circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Usually, the components of the embodiments of the present disclosure described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure to be protected, but only represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.

[0036] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further definition and explanation thereof is not required in subsequent figures.

[0037] As used herein, the term "and / or" merely describes an association relationship and means that three relationships may exist. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, or B exists alone. Additionally, the term "at least one" as used herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C may mean including any one or more elements selected from the set consisting of A, B, and C.

[0038] Furthermore, the terms "first", "second", etc. in the description, claims, and the above figures of the embodiments of the present disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0039] It has been found through research that in traditional 3D stacked chip designs, a structure of adding computing circuits in a memory array is usually adopted to increase computing power. To better understand the present invention, an exemplary introduction to the structure of in-memory computing circuits in related technologies is provided. Refer to Figure 1 , Figure 1 is a schematic diagram of the structure of an in-memory computing circuit in related technologies. As shown in Figure 1 , the in-memory computing circuit includes a read / write circuit layer, a plurality of computing circuit layers, and a plurality of memory matrix layers. Here, a computing circuit layer and a memory matrix layer are alternately stacked in one layer of the read / write circuit, that is, a computing circuit layer is added between each memory matrix layer, so that each memory matrix layer corresponds to a computing circuit layer. Among them, in order to more clearly show the computing path for in-memory computing and the read / write path for storage, they are distinguished by solid lines and dashed lines. As can be seen from Figure 1 , the solid line represents the computing path for in-memory computing, and the dashed line represents the read / write path for storage.

[0040] However, this type of in-memory arithmetic circuit has two major problems. First, the storage capacity of the in-memory arithmetic circuit is limited. Since the computing circuit layer is added between multiple storage matrix layers, the computing circuit occupies a large proportion of the entire in-memory arithmetic circuit, which greatly affects the storage density. Second, there is an upper limit to the ratio of storage capacity to computing capacity. If the ratio of storage capacity to computing capacity is much larger than the design of the in-memory arithmetic circuit, the low-cost in-memory arithmetic circuit will find it difficult to support the entire storage range. Therefore, the storage capacity of the in-memory arithmetic circuit is limited, and there is an upper limit to the ratio of storage capacity to computing capacity, which affects the efficiency of data calculation. If the upper limit is exceeded, there may be losses in power consumption, area, and reliability.

[0041] Based on the above research, the present disclosure provides a three-dimensional in-memory computing circuit, which greatly improves the upper limit of storage capacity and computing power in the in-memory computing circuit by stacking the peripheral circuit layer and multiple storage circuit layers in sequence, effectively solving the problem of limited storage and computing capacity in traditional in-memory computing circuits, and the positions of multiple computing units in the peripheral circuit layer correspond one-to-one to the target storage units in each layer of the storage matrix in the stacking direction, effectively reducing the proportion of computing units in the three-dimensional in-memory computing circuit, reducing the impact on storage density, thereby improving computing speed and efficiency, and reducing power consumption and computing errors.

[0042] The defects in the above solutions are the results obtained by the inventors after practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by this disclosure for the above problems below should be the contributions made by the inventors to this disclosure during the disclosure process.

[0043] The three-dimensional in-memory operation circuit provided by the embodiments of the present disclosure is described below with reference to the accompanying drawings.

[0044] See also Figure 2 The figure shows a schematic diagram of the structure of a three-dimensional in-memory arithmetic circuit provided by an embodiment of the present disclosure. The three-dimensional in-memory arithmetic circuit 100 provided by an embodiment of the present disclosure includes a peripheral circuit layer 10 and multiple storage circuit layers 20 stacked in sequence. The peripheral circuit layer 10 includes a computing circuit 11, and the computing circuit 11 includes multiple computing units. Each of the storage circuit layers 20 includes a storage matrix 21, and the storage matrix 21 includes multiple storage units for storing data. The multiple computing units correspond one-to-one with the positions of target storage units in each layer of the storage matrix 21 in the stacking direction. The target storage unit includes a row of storage units or a single storage unit in the corresponding storage matrix.

[0045] Optionally, the storage unit is used to store data including but not limited to matrix and address code.

[0046] As Figure 2 shown by solid lines, the compute-in-memory computing path is represented. Since the positions of the multiple computing units and the target storage units in each layer of the storage matrix 21 correspond one-to-one in the stacking direction, and the target storage units include a row of storage units or a single storage unit in the storage matrix to which they belong, each computing unit is used to obtain the target storage data in the corresponding target storage units in at least one layer of the storage matrix, and perform calculations based on the target storage data to obtain a calculation result.

[0047] To more clearly show the correspondence between the computing units and the target storage units, please refer to Figure 3 and Figure 4 , Figure 3 which is a schematic structural diagram of another three-dimensional in-memory computing circuit provided by an embodiment of the present disclosure. Figure 4 which is a schematic structural diagram of another three-dimensional in-memory computing circuit provided by an embodiment of the present disclosure. In this example, a three-dimensional in-memory computing circuit including 2 storage circuit layers is used as an example for illustration. It can be seen that in the 2 storage circuit layers, the storage circuit layer closer to the peripheral circuit layer is the storage circuit layer 1, and the storage circuit layer farther from the peripheral circuit layer is the storage circuit layer 2.

[0048] Refer to Figure 3 , in this example, the case where the target storage unit includes a single storage unit in the storage matrix to which it belongs is described. The peripheral circuit layer 10 includes a computing circuit 11. The computing circuit 11 includes n×m computing units. Specifically, A11 represents the computing unit located in the first row and the first column, A21 represents the computing unit located in the second row and the first column, An1 represents the computing unit located in the nth row and the first column, A12 represents the computing unit located in the first row and the second column, A22 represents the computing unit located in the second row and the second column, An2 represents the computing unit located in the nth row and the second column, A1m represents the computing unit located in the first row and the mth column, A2m represents the computing unit located in the second row and the mth column, and Anm represents the computing unit located in the nth row and the mth column.

[0049] For the storage circuit layer 1 (20) and the storage circuit layer 2 (20), both include an n×m storage matrix 21, and the n×m storage matrix 21 includes n×m storage units. Specifically, for the storage circuit layer 1 (20), B11 represents the storage unit located in the first row and the first column, B21 represents the storage unit located in the second row and the first column, Bn1 represents the storage unit located in the nth row and the first column, B12 represents the storage unit located in the first row and the second column, B22 represents the storage unit located in the second row and the second column, Bn2 represents the storage unit located in the nth row and the second column, B1m represents the storage unit located in the first row and the mth column, B2m represents the storage unit located in the second row and the mth column, and Bnm represents the storage unit located in the nth row and the mth column. For the storage circuit layer 2 (20), C11 represents the storage unit located in the first row and the first column, C21 represents the storage unit located in the second row and the first column, Cn1 represents the storage unit located in the nth row and the first column, C12 represents the storage unit located in the first row and the second column, C22 represents the storage unit located in the second row and the second column, Cn2 represents the storage unit located in the nth row and the second column, C1m represents the storage unit located in the first row and the mth column, C2m represents the storage unit located in the second row and the mth column, and Cnm represents the storage unit located in the nth row and the mth column.

[0050] Correspondingly, the computing unit A11 corresponds to the storage unit B11 in the storage circuit layer 1, and the computing unit A11 corresponds to the storage unit C11 in the storage circuit layer 2; the computing unit A21 corresponds to the storage unit B21 in the storage circuit layer 1, and the computing unit A21 corresponds to the storage unit C21 in the storage circuit layer 2; the computing unit An1 corresponds to the storage unit Bn1 in the storage circuit layer 1, and the computing unit An1 corresponds to the storage unit Cn1 in the storage circuit layer 2; and so on.

[0051] See Figure 4 , which is different from Figure 3 in that in this example, the case where the target storage unit includes a row of storage units in the storage matrix to which it belongs is described. As can be seen from Figure 4 , Figure 4 the storage circuit layer 1 and the storage circuit layer 2 in Figure 3 are the same as the storage circuit layer 1 and the storage circuit layer 2 in Figure 4 , except for the peripheral circuit layer. In the peripheral circuit layer 10 of Figure 4 , the computing circuit 11 includes n computing units. Specifically, A1 represents the computing unit located in the first row, A2 represents the computing unit located in the second row, and An represents the computing unit located in the nth row.

[0052] The computing unit A1 corresponds to the memory cells in the first row of each layer of the memory matrix 20. Specifically, the computing unit A1 corresponds to the memory cells B11, B12... B1m in the memory circuit layer 1, and the computing unit A11 corresponds to the memory cells C11, C12... C1m in the memory circuit layer 2. The computing unit A2 corresponds to the memory cells in the second row of each layer of the memory matrix 20. Specifically, the computing unit A2 corresponds to the memory cells B21, B22... B2m in the memory circuit layer 1, and the computing unit A2 corresponds to the memory cells C21, C22... C2m in the memory circuit layer 2. The computing unit An corresponds to the memory cells in the nth row of each layer of the memory matrix 20. Specifically, the computing unit An corresponds to the memory cells Bn1, Bn2... Bnm in the memory circuit layer 1, and the computing unit An corresponds to the memory cells Cn1, Cn2... Cnm in the memory circuit layer 2.

[0053] Here, each of the computing units is communicatively connected to the corresponding target memory cell in the adjacent memory circuit layer through a contact via hole, and the two target memory cells corresponding to the same computing unit in any two adjacent memory circuit layers are communicatively connected through a contact via hole. The contact via hole is, for example, a Through-Silicon Via (TSV).

[0054] To ensure the matching between the peripheral circuit layer and each memory circuit layer, the multiple memory circuit layers are of a single type.

[0055] Specifically, the multiple memory circuit layers 20 are of the same type; the types of the multiple memory circuit layers 20 include one of the following:

[0056] Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Magnetoresistive Random Access Memory (MRAM), Resistive Random Access Memory (RRAM).

[0057] In this way, by using memory circuit layers of the same type, the consistency of the memory circuit layers can be ensured, which helps to improve the reliability and stability of the three-dimensional in-memory computing circuit, reduce the failures caused by the compatibility issues between different types of memory circuit layers, and moreover, the memory circuit layers of the same type can adopt the same manufacturing process and production equipment, reducing the additional costs caused by producing different types of memory circuit layers.

[0058] Among them, the number of the multiple memory circuit layers is determined by the capacity upper limit information and computing power upper limit information of the three-dimensional in-memory computing circuit. It can be understood that the stacking of the multiple memory circuit layers cannot exceed the capacity upper limit and computing power upper limit of the three-dimensional in-memory computing circuit.

[0059] In some possible implementation manners, each of the computing units is configured to obtain target stored data in corresponding target storage units in at least one layer of the memory matrix, including:

[0060] Each of the computing units is configured to receive a computing task, determine, according to the computing task, target storage units in corresponding target storage units in each layer of the memory matrix that match the computing task, and obtain the target stored data in the target storage units that match the computing task.

[0061] In this way, the computing unit can dynamically select corresponding target storage units in each layer of the memory matrix according to the computing task to meet the requirements of different computing tasks, and realize dynamic and reconfigurable storage resource allocation.

[0062] Specifically, the computing unit can obtain the target stored data in the corresponding target storage units in a single layer of the memory matrix, or can obtain the target stored data in the corresponding target storage units in multiple layers of the memory matrix.

[0063] In some possible implementation manners, the computing unit performs a calculation based on the target stored data to obtain a calculation result, including:

[0064] When the computing unit obtains the target stored data in the corresponding target storage units in one layer of the memory matrix, the computing unit is configured to perform a calculation between vectors based on the target stored data to obtain a calculation result.

[0065] Here, only the data of the target storage unit needs to be obtained from a single layer of the memory matrix, and the calculation complexity is relatively low, which is suitable for relatively simple computing tasks. The access latency of a single layer of the memory matrix is relatively low, and the computing task can be completed quickly, which is suitable for scenarios with high real-time requirements.

[0066] In some other possible implementation manners, the computing unit performs a calculation based on the target stored data to obtain a calculation result, including:

[0067] When the computing unit obtains the target stored data in the corresponding target storage units in multiple layers of the memory matrix, the computing unit is configured to perform a calculation between a vector and a matrix based on the target stored data to obtain a calculation result.

[0068] Here, it supports calculations for multiple layers of the memory matrix, can handle relatively complex computing tasks, and is suitable for high-performance computing.

[0069] In some possible embodiments, each of the storage units is further configured to store first check information; each of the computing units is further configured to store second check information;

[0070] Each of the computing units is configured to obtain target storage data in corresponding target storage units in at least one layer of the storage matrix, and perform calculations based on the target storage data to obtain a calculation result, including:

[0071] Each of the computing units is configured to obtain target storage data and first check information in corresponding target storage units in at least one layer of the storage matrix, and perform a check on the corresponding target storage units in at least one layer of the storage matrix based on the obtained first check information and the second check information of the computing unit. When the corresponding target storage units in at least one layer of the storage matrix pass the check, calculations are performed based on the target storage data to obtain a calculation result.

[0072] Optionally, the first check information may be generated based on the position of the storage unit in the storage matrix to which it belongs, and the second check information may be generated based on the position of the computing unit in the computing circuit to which it belongs.

[0073] Alternatively, the first check information and the second check information may be a set of pre-set check information with a corresponding relationship.

[0074] In practical applications, errors may occur during data transmission or data storage. When the computing unit obtains target storage data from the target storage unit, it simultaneously reads the first check information and performs a joint check with the second check information stored in itself to determine whether the target storage unit is corresponding or whether the target storage data stored in the target storage unit is correct. After the check is error-free, it is considered that the target storage unit passes the check, and then calculations are performed.

[0075] In this way, through the check mechanism, errors that may occur during data transmission or data storage can be detected in a timely manner, ensuring that the data obtained by the computing unit is accurate, improving the accuracy of the calculation result, enhancing the reliability of the three-dimensional in-memory computing circuit at the same time, improving the fault tolerance of data storage, and reducing circuit failures caused by data errors.

[0076] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of another three-dimensional in-memory computing circuit provided by the embodiments of the present disclosure. As Figure 5As shown, when the target storage unit includes a row of storage units in the storage matrix, each storage circuit layer 20 further includes a column address decoding module 22, and the column address decoding module 22 is used to determine the storage units located in the first target column from the storage matrix 21.

[0077] Correspondingly, each of the computing units is used to obtain target storage data in the corresponding target storage units in at least one layer of the storage matrix, including:

[0078] The computing unit is used to obtain the target storage data in the storage units located in the first target column in the corresponding target storage units in at least one layer of the storage matrix.

[0079] Here, since each computing unit corresponds to a row of storage units, during calculation, there will inevitably be an output for each row. Therefore, there is no need to use a row decoding module to locate the row of storage units anymore. Only a column address decoding module needs to be set to locate the column of storage units. Compared with the related art where both a row address decoding module and a column address decoding module are set, since there is no need to reserve additional space and resources for the row decoding module in the storage circuit layer, the storage space utilization rate is improved. At the same time, the circuit design complexity is reduced, the number of hardware components required for the three-dimensional in-memory computing circuit is reduced, and the risk of data errors caused by hardware failures or signal interference is reduced, making the computing path more direct and concise.

[0080] Optionally, the storage matrix and the column address decoding module are arranged side by side in sequence.

[0081] In some possible implementation manners, the column address decoding module 22 is located at the edge of the storage circuit layer 20.

[0082] In this way, the column address decoding module is located at the edge of the storage circuit layer, so as to correspond to the first target column from the storage matrix more quickly, reduce the time for data searching, and improve the data access efficiency.

[0083] When the target storage unit includes a single storage unit in the storage matrix to which it belongs, since multiple computing units correspond one-to-one to multiple storage units in each layer of the storage matrix, the storage circuit layer does not need to be provided with a column address decoding module, and the computing unit can directly locate the corresponding target storage units in each layer of the storage matrix.

[0084] Refer to again Figure 5 , the peripheral circuit layer 10 further includes a read / write circuit 13 and a row address decoding module 12, and the row address decoding module 12 is used to determine the storage units located in the target row from the storage matrix;

[0085] Each of the storage circuit layers 20 further includes a column address decoding module 22, and the column address decoding module 22 is configured to determine the storage units located in the second target column from the storage matrix;

[0086] The read / write circuit 13 is configured to read and write the stored data in the storage units located in the target row and the second target column in the storage matrix.

[0087] As Figure 5 shown, the storage read / write path is represented by a dotted line. First, the column address decoding module 22 is used to determine the storage units located in the second target column, then the row address decoding module 12 is used to determine the storage units located in the target row, and then the read / write circuit 13 locates the storage units located in the target row and the second target column in the storage matrix and reads and writes the stored data therein.

[0088] In this way, the three-dimensional in-memory computing circuit can also implement data reading and writing. Through the row address decoding module and the column address decoding module, the storage units for data reading and writing can be located, improving the overall performance of the three-dimensional in-memory computing circuit.

[0089] Optionally, referring to Figure 5 , the computing circuit 11, the row address decoding module 12, and the read / write circuit 13 are arranged side by side in sequence.

[0090] In some possible implementation manners, the peripheral circuit layer 10 further includes a control circuit 14, and the control circuit 14 is configured to control the execution of the computing circuit 11, the column address decoding module 22, the row address decoding module 12, and the read / write circuit 13.

[0091] In this way, through the control circuit, the operation of each component can be uniformly managed and coordinated, ensuring the collaborative work among the computing circuit, the column address decoding module, the row address decoding module, and the read / write circuit, avoiding conflicts and incompatibility problems among different components, and enabling the entire three-dimensional in-memory computing circuit to efficiently execute diverse tasks.

[0092] Optionally, the computing circuit 11, the row address decoding module 12, the read / write circuit 13, and the control circuit 14 are arranged side by side in sequence.

[0093] In practical applications, specifically, the peripheral circuit layer 10 and the storage circuit layer 20 are chips, or the peripheral circuit layer 10 and the storage circuit layer 20 are bare dies.

[0094] In this way, both the peripheral circuit layer and the storage circuit layer in the embodiments of the present disclosure are small-scale units, with low cost and power consumption, effectively reducing power consumption and cost while ensuring the realization of functions.

[0095] Correspondingly, the three-dimensional in-memory computing circuit 100 is the package of the dies where the peripheral circuit layer 10 and the multiple memory circuit layers 20 are located respectively;

[0096] Alternatively, the three-dimensional in-memory computing circuit 100 is the package of the chips where the peripheral circuit layer 10 and the multiple memory circuit layers 20 are located respectively;

[0097] Alternatively, the three-dimensional in-memory computing circuit 100 is a functional structure block integrating the peripheral circuit layer 10 and the multiple memory circuit layers 20.

[0098] It can be understood that in the case of design changes in the peripheral circuit layer 10 and the multiple memory circuit layers 20, the form of the three-dimensional in-memory computing circuit 100 can be changed accordingly.

[0099] The three-dimensional in-memory computing circuit provided by the embodiments of the present disclosure, by sequentially stacking the peripheral circuit layer and the multiple memory circuit layers, greatly improves the upper limits of the storage capacity and computing power in the in-memory computing circuit, effectively solves the problem of limited improvement in storage and computing amounts in traditional in-memory computing circuits, improves the reliability of the three-dimensional in-memory computing circuit, and reduces the influence of process errors; and the positions of the multiple computing units in the peripheral circuit layer and the target storage units in each memory matrix correspond one by one in the stacking direction, effectively reducing the proportion of the computing units in the three-dimensional in-memory computing circuit, reducing the influence on the storage density, and greatly increasing the storage units corresponding to each computing unit without increasing the distance between the computing units and the corresponding storage units, thereby improving the computing speed and computing efficiency and reducing power consumption and computing errors.

[0100] In several embodiments provided by the present disclosure, it should be understood that the disclosed three-dimensional in-memory computing circuit can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0101] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] In addition, in each embodiment of the present disclosure, each functional unit may be integrated into one processing unit, may exist physically alone for each unit, or two or more units may be integrated into one unit.

[0103] If the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present disclosure. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0104] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise clearly defined and limited, the terms "set", "install", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0105] The above-described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts fall within the scope of protection of the embodiments of the present invention.

[0106] If the technical solution of this application involves personal information, before the product applying the technical solution of this application processes personal information, it has clearly informed the personal information processing rules and obtained the independent consent of the individual. If the technical solution of this application involves sensitive personal information, before the product applying the technical solution of this application processes sensitive personal information, it has obtained the individual's separate consent and at the same time meets the requirements of "express consent". For example, at personal information collection devices such as cameras, a clear and prominent sign is set to inform that the personal information collection scope has been entered and personal information will be collected. If an individual voluntarily enters the collection scope, it is regarded as consenting to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are informed by obvious signs / information, personal authorization is obtained through pop-up messages or by asking the individual to upload their personal information by themselves, etc.; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0107] Finally, it should be noted that: the above-mentioned embodiments are only specific implementation manners of the present disclosure, used to illustrate the technical solutions of the present disclosure, rather than limiting them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present disclosure can still modify the technical solutions recorded in the foregoing embodiments or can easily think of changes, or make equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A three-dimensional in-memory computing circuit, characterized in that The three-dimensional in-memory computing circuit includes a peripheral circuit layer and a plurality of memory circuit layers stacked in sequence. The peripheral circuit layer includes a computing circuit, and the computing circuit includes a plurality of computing units; each of the memory circuit layers includes a memory matrix, and the memory matrix includes a plurality of memory units for storing data; The positions of the plurality of computing units and the target memory units in each memory matrix correspond one-to-one in the stacking direction, and the target memory units include a row of memory units or a single memory unit in the corresponding memory matrix; Each computing unit is configured to obtain target memory data in the corresponding target memory units in at least one memory matrix, and perform calculations based on the target memory data to obtain a calculation result.

2. The circuit according to claim 1, wherein The step that each computing unit is configured to obtain target memory data in the corresponding target memory units in at least one memory matrix includes: Each computing unit is configured to receive a computing task, determine, according to the computing task, target memory units matching the computing task from the corresponding target memory units in each memory matrix, and obtain the target memory data in the target memory units matching the computing task.

3. The circuit according to claim 1, wherein When the target memory units include a row of memory units in the corresponding memory matrix, each memory circuit layer further includes a column address decoding module, and the column address decoding module is configured to determine the memory units located in a first target column from the memory matrix; The step that each computing unit is configured to obtain target memory data in the corresponding target memory units in at least one memory matrix includes: The computing unit is configured to obtain the target memory data in the memory units located in the first target column in the corresponding target memory units in at least one memory matrix.

4. The circuit according to claim 3, wherein The column address decoding module is located at the edge of the memory circuit layer.

5. The circuit according to claim 1, wherein The peripheral circuit layer further includes a read / write circuit and a row address decoding module, and the row address decoding module is configured to determine the memory units located in a target row from the memory matrix; Each memory circuit layer further includes a column address decoding module, and the column address decoding module is configured to determine the memory units located in a second target column from the memory matrix; The read / write circuit is configured to perform read / write processing on the memory data in the memory units located in the target row and in the second target column in the memory matrix.

6. The circuit according to claim 5, characterized in that, The computing circuit, the row address decoding module, and the read / write circuit are arranged side by side in sequence.

7. The circuit according to claim 5, characterized in that The peripheral circuit layer further includes a control circuit, and the control circuit is configured to control the execution of the computing circuit, the column address decoding module, the row address decoding module, and the read / write circuit.

8. The circuit according to claim 1, wherein Each memory unit is further configured to store first check information; each computing unit is further configured to store second check information; The step that each computing unit is configured to obtain target memory data in the corresponding target memory units in at least one memory matrix, and perform calculations based on the target memory data to obtain a calculation result includes: Each of the computing units is configured to obtain target storage data and first check information in corresponding target storage units in at least one layer of the storage matrix, and perform a check on the corresponding target storage units in at least one layer of the storage matrix based on the obtained first check information and second check information of the computing unit. When the corresponding target storage units in at least one layer of the storage matrix pass the check, a calculation result is obtained based on the target storage data.

9. The circuit according to any one of claims 1-8, characterized in that, The types of the multiple storage circuit layers are the same; The types of the multiple storage circuit layers include one of the following: Static random access memory, dynamic random access memory, magnetoresistive random access memory, resistive random access memory.

10. The circuit according to any one of claims 1-8, characterized in that, The peripheral circuit layer and the storage circuit layer are chips, or the peripheral circuit layer and the storage circuit layer are bare dies.

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