Data transmission method, apparatus, system, and storage medium

Abstract

The present disclosure relates to a data transmission method, device, system and storage medium. The method is used on the device side, connected with the host side through PCIe. The method comprises: a driver on the device side configures a first descriptor, sends the first descriptor to a DMA on the device side, and configures a second descriptor to send to the DMA in the case of determining that the preset condition is met according to the first descriptor; the DMA sends target data to PCIe according to the first descriptor; in the case that the target data has been sent to PCIe and the second descriptor is received, the DMA sends a read data request to PCIe according to the second descriptor, and in the case that the corresponding data of the returned read data request is received, sends an interrupt information to the CPU on the host side, so that the CPU reads the target data. According to the embodiment of the present disclosure, the integrity and correctness of data transmission can be ensured, and the data sent by the device side and the data read by the host side are consistent.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data processing, and particularly relates to a data transmission method, device, system and storage medium. BACKGROUND

[0002] In a computer system, data transmission between a device side and a host side is usually performed through direct memory access (DMA). In the data transmission process, data is communicated through a peripheral component interconnect express (PCIe). The use of DMA can significantly improve data transmission speed and system efficiency, and meanwhile, PCIe as an underlying transmission channel provides reliable high-speed data transmission capability. However, in a scenario where DMA writes data from the device side to the host side through PCIe, after receiving a completion reply sent by PCIe for a write data request, DMA considers that the data has been transmitted and reports an interrupt to a central process unit (CPU) of the host side, but at this time, the data may not have been written into a system memory of the host side, and thus there is a situation that DMA reports an interrupt to the host side in advance, resulting in that the CPU of the host side cannot read correct data from the system memory. SUMMARY

[0003] In view of this, the present disclosure provides a data transmission method, device, system and storage medium.

[0004] According to an aspect of the present disclosure, a data transmission method is provided. The method is used in a device side, the device side is connected with a host side through a high-speed serial bus PCIe, and the method comprises the following steps.

[0005] A driver of the device side configures a first descriptor, and sends the first descriptor to a direct memory access (DMA) of the device side;

[0006] In a case where it is determined according to the first descriptor that a preset condition is met, the driver configures a second descriptor, and sends the second descriptor to the DMA;

[0007] The DMA sends target data to the PCIe according to the first descriptor, and the PCIe is configured to send the target data to a first destination address;

[0008] In a case where the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor;

[0009] The DMA sends interrupt information to a central processing unit (CPU) on the host side when the returned data corresponding to the read data request is received, so that the CPU reads the target data from the first destination address.

[0010] In a possible implementation, the first descriptor includes a first source address and a first destination address, and the target data is data corresponding to the first source address.

[0011] The preset condition is that the first source address is an address of the memory on the device side and the first destination address is an address of a system memory on the host side.

[0012] In a possible implementation, the second descriptor includes a second source address and a second destination address, and the drive configures the second descriptor as follows.

[0013] The drive determines an arbitrary address in the system memory on the host side as the second source address.

[0014] The drive determines an arbitrary address in the memory on the device side as the second destination address.

[0015] In a possible implementation, the DMA sends, according to the second descriptor, a read data request to the PCIe to read data corresponding to the second source address, and writes the read data back to the second destination address.

[0016] In a possible implementation, the method further includes:

[0017] When the target data has been sent to the PCIe and the second descriptor is not received, the DMA sends interrupt information to the central processing unit (CPU) on the host side, so that the CPU reads the target data from the first destination address.

[0018] According to another aspect of the present disclosure, a data transmission device is provided. The device is used on a device side connected to a host side through a high-speed serial bus PCIe, and the device includes:

[0019] A first configuration module is configured to configure a first descriptor by a drive on the device side, and send the first descriptor to a direct memory access (DMA) on the device side.

[0020] A second configuration module is configured to configure a second descriptor by the drive when it is determined that a preset condition is met according to the first descriptor, and send the second descriptor to the DMA.

[0021] A first sending module is configured to send target data by the first descriptor to the PCIe, and the PCIe is configured to send the target data to a first destination address.

[0022] the second sending module is configured to send, by the DMA, a read data request to the PCIe according to the second descriptor when the target data has been sent to the PCIe and the second descriptor is received;

[0023] the third sending module is configured to send, by the DMA, interrupt information to a central processing unit (CPU) on the host side when the returned data corresponding to the read data request is received, so that the CPU reads the target data from the first destination address.

[0024] In a possible implementation, the first descriptor comprises a first source address and a first destination address, and the target data is data corresponding to the first source address.

[0025] The preset condition is that the first source address is an address of the memory on the device side and the first destination address is an address of a system memory on the host side.

[0026] In a possible implementation, the second descriptor comprises a second source address and a second destination address, and the second configuration module is configured to:

[0027] determine, by the driver, any address in the system memory on the host side as the second source address;

[0028] determine, by the driver, any address in the memory on the device side as the second destination address.

[0029] In a possible implementation, the read data request sent by the DMA to the PCIe according to the second descriptor is used to read data corresponding to the second source address, and the read data is written back to the second destination address.

[0030] In a possible implementation, the apparatus further comprises:

[0031] the fourth sending module is configured to send, by the DMA, interrupt information to a central processing unit (CPU) on the host side when the target data has been sent to the PCIe and the second descriptor is not received, so that the CPU reads the target data from the first destination address.

[0032] According to another aspect of the present disclosure, a data transmission system is provided. The system comprises a device side and a host side, and the device side and the host side are connected through a high-speed serial bus PCIe,

[0033] the driver on the device side is configured to:

[0034] configure a first descriptor and send the first descriptor to a direct memory access (DMA) on the device side;

[0035] configure a second descriptor and send the second descriptor to the DMA when it is determined that the preset condition is met according to the first descriptor;

[0036] the DMA is configured to:

[0037] sending target data to the PCIe according to the first descriptor;

[0038] in a case where the target data has been sent to the PCIe and the second descriptor is received, sending a read data request to the PCIe according to the second descriptor;

[0039] in a case where the returned data corresponding to the read data request is received, sending interrupt information to a central processing unit (CPU) on a host side;

[0040] the CPU is configured to:

[0041] in response to receiving the interrupt information, read the target data from the first destination address;

[0042] the PCIe is configured to:

[0043] send the target data to the first destination address.

[0044] In a possible implementation, the first descriptor includes a first source address and a first destination address, and the target data is data corresponding to the first source address.

[0045] The preset condition is that the first source address is an address of a memory on a device side and the first destination address is an address of a system memory on a host side.

[0046] In a possible implementation, the second descriptor includes a second source address and a second destination address, and the second descriptor is configured to include:

[0047] the driver determines any address in the system memory on the host side as the second source address;

[0048] the driver determines any address in the memory on the device side as the second destination address.

[0049] In a possible implementation, the read data request sent by the DMA to the PCIe according to the second descriptor is used to read data corresponding to the second source address, and the read data is written back to the second destination address.

[0050] In a possible implementation, the DMA is further configured to:

[0051] in a case where the target data has been sent to the PCIe and the second descriptor is not received, sending interrupt information to a central processing unit (CPU) on a host side, so that the CPU reads the target data from the first destination address.

[0052] According to another aspect of the present disclosure, a data transmission apparatus is provided, including a processor, a memory for storing processor-executable instructions, and wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0053] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the method described above.

[0054] According to another aspect of the present disclosure, there is provided a computer program product comprising computer readable code or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, the processor in the electronic device performs the method described above.

[0055] According to the embodiments of the present disclosure, by configuring the first descriptor by the driver of the device side, sending the first descriptor to the DMA of the device side, and in the case that it is determined according to the first descriptor that the preset condition is met, configuring the second descriptor and sending it to the DMA, the DMA sends the target data to the PCIe according to the first descriptor, and the PCIe is configured to send the target data to the first destination address, in the case that the target data has been sent to the PCIe and the second descriptor is received, the DMA sends the read data request to the PCIe according to the second descriptor, the characteristics of the PCIe can be utilized, by means of the software filling the descriptor in the case that the preset condition is met, it is ensured that the target data has been written into the first destination address when the read data request is completed. On this basis, by means of the DMA sending the interrupt information to the CPU of the host side in the case that the data corresponding to the returned read data request is received, the CPU reads the target data from the first destination address, the target data can be correctly and completely read from the first destination address by the CPU of the host side, the integrity and correctness of the data transmission are ensured, and the data sent by the device side and the data read by the CPU of the host side are consistent.

[0056] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0057] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0058] Figure 1 A schematic diagram showing the device side writing data to the host side in the prior art is shown.

[0059] Figure 2 A structural diagram of a data transmission system according to an embodiment of the present disclosure is shown.

[0060] Figure 3 A flowchart of a data transmission method according to an embodiment of the present disclosure is shown.

[0061] Figure 4A schematic diagram showing a descriptor according to an embodiment of the present disclosure.

[0062] Figure 5 A structural diagram of a data transmission apparatus according to an embodiment of the present disclosure is shown.

[0063] Figure 6 is a block diagram of an apparatus 1900 for data transmission according to an exemplary embodiment. DETAILED DESCRIPTION

[0064] Various exemplary embodiments, features and aspects of the present disclosure will be explained in detail below with reference to the drawings. The same reference numbers in different drawings denote the same or similar elements. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically noted.

[0065] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0066] In addition, for the purpose of better illustrating the present disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will appreciate that the present disclosure can be practiced without some or all of the specific details. In some instances, well-known methods, apparatuses, elements and circuits have not been described in detail in order to avoid obscuring the present disclosure.

[0067] In a computer system, data transmission between the device side and the host side is usually performed through direct memory access (DMA). During data transmission, data is communicated through a high-speed serial bus (peripheral component interconnect express, PCIe). The use of DMA can significantly improve data transmission speed and system efficiency, while PCIe as the underlying transmission channel provides reliable high-speed data transmission capability. However, referring to Figure 1, show a schematic diagram of writing data from device side to host side in prior art. In the scenario that DMA writes data from device side (Device side) to host side (Host side) through PCIe, the DMA from device side reads data from device memory Device Memory, and then sends the data to PCIe. After receiving the response (resp) sent by PCIe indicating that the data has been received, the DMA considers that the data has been transmitted and reports an interrupt (irq) to the central process unit (CPU) of the host side through PCIe. After receiving the interrupt, the CPU of the host side reads the data transmitted by the DMA through PCIe from the system memory. However, at this time, the data may not have been written into the system memory of the host side, and thus the DMA may report the interrupt to the host side in advance, resulting in that the CPU of the host side cannot read the correct data from the system memory.

[0068] Therefore, the present disclosure provides a data transmission method, device, system and storage medium. In the method of the present disclosure, a first descriptor is configured by a driver of the device side, the first descriptor is sent to a DMA of the device side, and a second descriptor is configured and sent to the DMA in a case where it is determined according to the first descriptor that a preset condition is met. The DMA sends target data to PCIe according to the first descriptor, and PCIe is configured to send the target data to a first destination address. In a case where the target data has been sent to PCIe and the second descriptor is received, the DMA sends a read data request to PCIe according to the second descriptor. In this way, by using the characteristics of PCIe and by means of software filling more descriptors in a case where the preset condition is met, it can be ensured that the target data has been written into the first destination address when the read data request is completed. On this basis, in a case where the DMA receives the data corresponding to the returned read data request, the DMA sends interrupt information to the CPU of the host side, so that the CPU reads the target data from the first destination address. In this way, the target data can be correctly and completely read from the first destination address by the CPU of the host side, the integrity and correctness of data transmission are ensured, and the data sent by the device side and the data read by the CPU of the host side are consistent.

[0069] Figure 2 A structural diagram of a data transmission system according to an embodiment of the present disclosure is shown. The data transmission system of the present disclosure can include a device side (Device side) and a host side (Host side). As shown in the structural diagram, the data transmission system of the present disclosure can include a device side (Device side) and a host side (Host side). As shown in the structural diagram, Figure 2As shown, the device side can include a DMA and a device-side memory (Device Memory), which is a memory or buffer of the device side; the host side can include a CPU and a system memory (System Memory), which can be used to store data and programs of the computer system. The host side and the device side can transmit data and communicate through PCIe.

[0070] The host side can be a terminal device or a server. The terminal device can be any one or more of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), and a vehicle-mounted device; and the server can be a physical device.

[0071] The device side can be an external device or an expansion card connected to the host, such as an image acquisition card, a network adapter, a graphics card, a storage controller, etc.

[0072] The data transmission method of the embodiments of the present disclosure can be applied to Figure 2 The data transmission system is shown to achieve data transmission between the device side and the host side. The data transmission method of the embodiments of the present disclosure is introduced below. Figure 3 The data transmission method of the embodiments of the present disclosure is introduced below.

[0073] Figure 3 A flowchart of the data transmission method according to the embodiments of the present disclosure is shown. The method can be used in the device side, which is connected to the host side through PCIe, such as Figure 3 As shown, the method can include:

[0074] In step S301, the driver of the device side configures a first descriptor and sends the first descriptor to the DMA of the device side.

[0075] The first descriptor can be configured by the driver after the upper layer (for example, an application layer or a protocol stack) issues a data transmission request to the driver. That is, when the upper layer instructs the device side to start a data transmission, the driver of the device side can configure the first descriptor according to the data transmission parameters sent by the upper layer, and then send the first descriptor to the DMA, so as to start the data transmission process. The data transmission request can be a write data request (for example, writing data from the device side to the host side).

[0076] Figure 4 A schematic diagram of the descriptor according to the embodiments of the present disclosure is shown. As Figure 4As shown, the descriptor can include a source address (such as src_address in the figure), a destination address (such as dst_address in the figure), and a size of the data transmitted (such as trans_size in the figure).

[0077] Based on Figure 4 The illustrated descriptor, the first descriptor can include a first source address (corresponding to Figure 4 src_address in the figure) and a first destination address (corresponding to Figure 4 dst_address in the figure). The first descriptor can also include a size of the target data (corresponding to Figure 4 trans_size in the figure). The first descriptor can represent writing the target data from the first source address to the first destination address.

[0078] At step S302, in a case where it is determined according to the first descriptor that the preset condition is met, the driver configures a second descriptor and sends the second descriptor to the DMA.

[0079] In the embodiments of the present disclosure, by the way of configuring one descriptor (i.e., the second descriptor) by the software (i.e., the driver) multiple times in a case where it is determined according to the first descriptor that the preset condition is met, it can be ensured that the target data corresponding to the first descriptor can be correctly and completely read by the host-side CPU subsequently.

[0080] The driver can determine whether to configure the second descriptor when configuring the first descriptor, and the preset condition can be that the first source address is an address of the device-side memory and the first destination address is an address of the system memory of the host side, indicating that the data is to be written from the device side to the host side.

[0081] The driver can configure the second descriptor after configuring the first descriptor, and in a case where it is determined according to the first descriptor that the preset condition is not met (i.e., the first source address is not an address of the device-side memory, or the first destination address is not an address of the system memory of the host side), the second descriptor can not be configured. In the embodiments of the present disclosure, by judging whether to configure the second descriptor by the driver, the data transmission resources can be further saved.

[0082] The second descriptor can be used for reading data by the device side, and the second descriptor can include a second source address (corresponding to Figure 4 src_address in the figure) and a second destination address (corresponding to Figure 4 dst_address in the figure), and the second descriptor can also include a size of the data read (corresponding to Figure 4The size of the target data can be any size. In the process of driving the second descriptor, any address in the system memory on the host side can be determined as the second source address, and any address in the device side memory can be determined as the second destination address. The size of the read data can also be any size.

[0083] For example, the target data of 1G described above can be read from the system memory on the host side and stored in the address in the device side memory by filling in the second descriptor. At this time, the second source address can be the address of the system memory on the host side for storing the target data, the second destination address can be the address of the device side for receiving and storing the target data, and the size of the data is 1G.

[0084] In step S303, the DMA sends the target data to the PCIe according to the first descriptor.

[0085] In step S303, the DMA sends the target data to the PCIe according to the first descriptor.

[0086] The PCIe can send the target data to the first destination address after receiving the target data sent by the DMA.

[0087] The PCIe can send the target data to the first destination address after receiving the target data sent by the DMA.

[0088] In step S304, the DMA sends a read data request to the PCIe according to the second descriptor in the case that the target data has been sent to the PCIe and the second descriptor has been received.

[0089] In step S304, the DMA sends a read data request to the PCIe according to the second descriptor in the case that the target data has been sent to the PCIe and the second descriptor has been received.

[0090] In step S305, the DMA sends an interrupt information to the CPU on the host side in the case that the returned data corresponding to the read data request has been received, so that the CPU reads the target data from the first destination address.

[0091] According to the embodiment of the present disclosure, by configuring a first descriptor by a device side, sending the first descriptor to a DMA, and in the case that it is determined according to the first descriptor that a preset condition is met, configuring a second descriptor and sending the second descriptor to the DMA, the DMA sends target data to a PCIe according to the first descriptor, the PCIe is configured to send the target data to a first destination address, in the case that the target data has been sent to the PCIe and the second descriptor is received, the DMA sends a read data request to the PCIe according to the second descriptor, the characteristics of the PCIe can be utilized, by means of the software filling the descriptor in the case that the preset condition is met, it is ensured that the target data has been written to the first destination address when the read data request is completed. On this basis, in the case that the DMA receives the data corresponding to the returned read data request, the interrupt information is sent to the CPU of the host side, so that the CPU reads the target data from the first destination address, the target data can be correctly and completely read from the first destination address by the CPU of the host side, the integrity and correctness of data transmission are ensured, and the data sent by the device side and the data read by the CPU of the host side are consistent.

[0092] In the present disclosure, the characteristics of the PCIe are utilized, that is, the read data request of the PCIe will wait until all write data requests before the read data request are completed. Therefore, in the present disclosure, by sending a read data request to the PCIe, when the DMA receives the data corresponding to the returned read data request, it indicates that all write data requests before the read data request have been completed, so that it can be ensured that the target data has been written to the system memory of the host side.

[0093] At this time, the CPU can read the target data from the first destination address after receiving the interrupt information. The interrupt information can be used to request the attention of the CPU and cause the CPU to pause the task currently being executed, and turn to process the task of the interrupt event. In the present disclosure, the task of the interrupt event can be implemented based on the target data, and in response to the interrupt information, the CPU can read the written target data from the system memory and execute the corresponding task. The generation mode of the interrupt information can be implemented based on the prior art, and the present disclosure is not limited thereto in the embodiment.

[0094] The method can further include:

[0095] In the case that the target data has been sent to the PCIe and the second descriptor is not received, the DMA sends interrupt information to the CPU of the host side, so that the CPU reads the target data from the first destination address.

[0096] The case can correspond to a case where it is determined according to the first descriptor that the preset condition is not met, that is, a case where the driver does not configure the second descriptor, and in this case, the first source address is not an address of the device-side memory, or the first destination address is not an address of the system memory on the host side.

[0097] Figure 5 A structural diagram of a data transmission apparatus according to an embodiment of the present disclosure is shown. The apparatus can be used on a device side, which can be connected with a host side through PCIe, as shown in the figure, the apparatus comprises: Figure 5

[0098] A first configuration module 501 is configured to configure a first descriptor by a driver on the device side, and send the first descriptor to a direct memory access (DMA) on the device side;

[0099] A second configuration module 502 is configured to configure a second descriptor by the driver in a case where it is determined according to the first descriptor that a preset condition is met, and send the second descriptor to the DMA;

[0100] A first sending module 503 is configured to send target data by the first descriptor to PCIe, and PCIe is configured to send the target data to a first destination address;

[0101] A second sending module 504 is configured to send a read data request by the DMA to PCIe according to the second descriptor in a case where the target data has been sent to PCIe and the second descriptor is received;

[0102] A third sending module 505 is configured to send an interrupt information by the DMA to a central processing unit (CPU) on the host side in a case where the read data request corresponding to the returned data is received, so that the CPU reads the target data from the first destination address.

[0103] In a possible implementation, the first descriptor comprises a first source address and a first destination address, and the target data is data corresponding to the first source address;

[0104] The preset condition is that the first source address is an address of a device-side memory and the first destination address is an address of a system memory on the host side.

[0105] In a possible implementation, the second descriptor comprises a second source address and a second destination address, and the second configuration module 502 is configured to:

[0106] determine, by the driver, any address in the system memory on the host side as the second source address;

[0107] determine, by the driver, any address in the device-side memory as the second destination address.

[0108] ​In a possible implementation, the DMA sends, according to the second descriptor, a read data request to the PCIe for reading data corresponding to the second source address, and writes the read data back to the second destination address.

[0109] In a possible implementation, the apparatus further includes:

[0110] The fourth sending module is configured to, in a case where the target data has been sent to the PCIe and the second descriptor is not received, send, by the DMA, an interrupt information to a central processing unit (CPU) on a host side, so that the CPU reads the target data from the first destination address. In some embodiments, the apparatus provided by the embodiments of the present disclosure has functions or includes modules that can be used to perform the methods described in the above method embodiments, and the specific implementation can refer to the description of the above method embodiments. For brevity, details are not described here.

[0111] The embodiments of the present disclosure also provide a computer-readable storage medium having computer program instructions stored therein, and the computer program instructions are executed by a processor to implement the above method. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0112] The embodiments of the present disclosure also provide a data transmission apparatus, including a processor, and a memory for storing processor-executable instructions, wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0113] The embodiments of the present disclosure also provide a computer program product, including computer readable code or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is run in a processor of an electronic device, the processor in the electronic device executes the above method.

[0114] Figure 6 is a block diagram of an apparatus 1900 for data transmission according to an exemplary embodiment. For example, the apparatus 1900 can be provided as a server or a terminal device. Referring to Figure 6 , the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932, for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0115] The apparatus 1900 can also include a power supply component 1926 configured to supply power to the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input / output interface 1958 (I / O interface). The apparatus 1900 can operate based on an operating system stored in the memory 1932, such as Windows Server TM , MacOS X TM , Unix TM , Linux TM , FreeBSD TM , or the like.

[0116] In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 1932 including computer program instructions, is also provided, which can be executed by the processing component 1922 of the apparatus 1900 to implement the above method.

[0117] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0118] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or punched tape, a

[0119] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0120] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing device, partly on the user's computing device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, for example, through the Internet using an Internet Service Provider. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0121] The computer readable program instructions can also be loaded onto a computing / processing device, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computing / processing device, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computing / processing device, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0122] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage cycles that change state. The instructions can be executed by one or more processors of a computer, to cause a series of operational steps to be performed on the computer to produce a computer-implemented process. The instructions can also cause one or more processors of a computer or other programmable data processing apparatus to

[0123] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0124] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0125] Embodiments of the present disclosure have been described above, and the description is intended to be illustrative of the embodiments and not restrictive of the disclosure. Many modifications and variations of the described embodiments are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto. The use of the terms "may" and "can" in the description is intended to convey that various embodiments of the present disclosure include, among other things, these and other possible features.

Claims

1. A data transmission method, characterized by, The method is used on the device side, which is connected to the host side via a high-speed serial bus PCIe. The method includes: The device-side driver configures a first descriptor and sends the first descriptor to the device-side direct memory access DMA. If a preset condition is determined to be met based on the first descriptor, the driver configures a second descriptor and sends the second descriptor to the DMA; The DMA sends target data to the PCIe according to the first descriptor, and the PCIe is used to send the target data to the first destination address; If the target data has been sent to the PCIe and the second descriptor has been received, the DMA sends a read data request to the PCIe based on the second descriptor; When the DMA receives the data corresponding to the returned read data request, it sends an interrupt message to the CPU on the host side, so that the CPU reads the target data from the first destination address.

2. The method of claim 1, wherein, The first descriptor includes a first source address and a first destination address, and the target data is the data corresponding to the first source address; The preset condition is that the first source address is the address of the device-side memory and the first destination address is the address of the host-side system memory.

3. The method according to claim 1, characterized in that, The second descriptor includes a second source address and a second destination address. The driver configures the second descriptor, including: The driver determines any address in the system memory on the host side as the second source address; The driver determines any address in the device-side memory as the second destination address.

4. The method according to claim 3, characterized in that, The DMA sends a read data request to the PCIe based on the second descriptor to read the data corresponding to the second source address and writes the read data back to the second destination address.

5. The method according to claim 1, characterized in that, The method further includes: If the target data has been sent to the PCIe and the second descriptor has not been received, the DMA sends the interrupt information to the central processing unit (CPU) on the host side, causing the CPU to read the target data from the first destination address.

6. A data transmission device, characterized in that, The device is used on the device side, which is connected to the host side via a high-speed serial bus PCIe. The device includes: The first configuration module is used to configure the first descriptor of the driver on the device side and send the first descriptor to the direct memory access DMA on the device side. The second configuration module is used to configure the second descriptor and send the second descriptor to the DMA when it is determined that the preset conditions are met according to the first descriptor; A first sending module is used to send target data from the first descriptor to the PCIe, wherein the PCIe is used to send the target data to a first destination address; The second sending module is configured to, when the target data has been sent to the PCIe and the second descriptor has been received, have the DMA send a read data request to the PCIe according to the second descriptor; The third sending module is used to send an interrupt message to the central processing unit (CPU) on the host side when the DMA receives the data corresponding to the returned read data request, so that the CPU reads the target data from the first destination address.

7. A data transmission system, characterized in that, The system includes a device side and a host side, which are connected via a high-speed serial bus PCIe. The device-side drive is used for: Configure a first descriptor and send the first descriptor to the device-side direct memory access DMA; If a preset condition is determined to be met based on the first descriptor, a second descriptor is configured and sent to the DMA; The DMA is used for: Send target data to the PCIe according to the first descriptor; If the target data has been sent to the PCIe and the second descriptor has been received, a read data request is sent to the PCIe according to the second descriptor; Upon receiving the data corresponding to the returned read data request, an interrupt message is sent to the central processing unit (CPU) on the host side. The CPU is used for: In response to receiving the interrupt information, the target data is read from the first destination address; The PCIe is used for: The target data is sent to the first destination address.

8. The system according to claim 7, characterized in that, The first descriptor includes a first source address and a first destination address, and the target data is the data corresponding to the first source address; The preset condition is that the first source address is the address of the device-side memory and the first destination address is the address of the host-side system memory.

9. A data transmission device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to implement the method of any one of claims 1 to 5 when executing instructions stored in the memory.

10. A non-volatile computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 5.

11. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 5.

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