Terminal correction circuit

Abstract

The invention provides a terminal correction circuit. The terminal correction circuit comprises a first terminal copy model, a terminal voltage offset correction circuit, a second terminal copy model and a terminal resistance offset correction circuit. The first terminal copy model is used for setting the resistance proportion of the first adjustable resistor and the second adjustable resistor according to the voltage correction code so as to adjust the terminal voltage. The terminal voltage offset correction circuit is used for comparing the terminal voltage with a third power supply voltage and providing a voltage correction code according to a comparison result. The second terminal copy model is used for setting the resistance ratio of the third adjustable resistor and the fourth adjustable resistor according to the voltage correction code, and reducing the equivalent resistance value between the half-voltage end and the grounding voltage according to the resistance correction code. The terminal resistance offset correction circuit is used for comparing the comparison voltage with a second power supply voltage and providing a resistance correction code according to a comparison result.

Description

Technical Field

[0001] The present invention relates to a calibration technology, and particularly to a terminal calibration circuit for calibrating a high-speed transmission interface. Background Art

[0002] In a high-speed transmission interface, the termination resistor (Rtt) of a transmitter or a receiver is very important for impedance matching during signal transmission, especially in a high-speed system. Generally, the resistance value of the termination resistor is prone to shift due to process, voltage, and temperature variations (PVT variation), resulting in the terminal voltage (common-mode voltage) not being able to maintain at a predetermined voltage value. Although there is currently a calibration mechanism for offset calibration of the termination resistor, if the two transmission resistors included in the termination resistor are mismatched, the voltage value of the terminal voltage will still shift from the predetermined voltage value. Summary of the Invention

[0003] The present invention provides a terminal calibration circuit that can perform a two-stage offset calibration to effectively eliminate the influence of process, voltage, and temperature variations on the termination resistor and the terminal voltage.

[0004] The terminal calibration circuit of the present invention includes a first terminal replica model, a terminal voltage offset calibration circuit, a second terminal replica model, and a termination resistor offset calibration circuit. The first terminal replica model has a first adjustable resistor and a second adjustable resistor. The first adjustable resistor is coupled between a second power supply voltage and a first node, and the second adjustable resistor is coupled between the first node and a ground voltage. The first terminal replica model is used to set the resistance ratio of the first adjustable resistor and the second adjustable resistor according to a voltage calibration code to adjust the terminal voltage generated at the first node. The terminal voltage offset calibration circuit is coupled to the first terminal replica model and is used to compare the terminal voltage with a third power supply voltage and provide a voltage calibration code according to the comparison result. The second terminal replica model is coupled to the terminal voltage offset calibration circuit and has a third adjustable resistor and a fourth adjustable resistor. The third adjustable resistor is coupled between a half-voltage terminal and a second node, and the fourth adjustable resistor is coupled between the second node and the ground voltage. The second terminal replica model is used to set the resistance ratio of the third adjustable resistor and the fourth adjustable resistor according to the voltage calibration code and reduce the equivalent resistance value between the half-voltage terminal and the ground voltage according to a resistance calibration code. The termination resistor offset calibration circuit is coupled to the second terminal replica model and is used to compare the comparison voltage generated at the half-voltage terminal with the second power supply voltage and provide a resistance calibration code according to the comparison result.

[0005] Based on the above, the terminal calibration circuit of the present invention can perform two-stage offset calibration to find accurate voltage calibration codes and resistance calibration codes. In addition to preventing the resistance value of the terminal resistor from shifting, it can also prevent the voltage of the terminal voltage from shifting. In this way, it is possible to effectively eliminate the influence of process, voltage, and temperature variations on the terminal resistor and terminal voltage, making the transmitted signal less likely to be distorted. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a circuit schematic diagram of a terminal calibration circuit according to an embodiment of the present invention;

[0007] Figure 2 is a circuit schematic diagram of a first terminal replication model according to an embodiment of the present invention;

[0008] Figure 3 is a circuit schematic diagram of a second terminal replication model according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0009] Please refer to Figure 1 , the terminal calibration circuit 100 is applicable to calibrate the terminal resistor and terminal voltage (common-mode voltage) of a transmitter or receiver in a high-speed transmission interface. The terminal calibration circuit 100 includes a reference voltage generation circuit 110, a first terminal replication model 120, a terminal voltage offset calibration circuit 130, a second terminal replication model 140, and a terminal resistor offset calibration circuit 150.

[0010] The reference voltage generation circuit 110 is coupled to the terminal voltage offset calibration circuit 130 and the terminal resistor offset calibration circuit 150. The reference voltage generation circuit 110 can be used to receive a first power supply voltage VDD1, and convert the first power supply voltage VDD1 into a third power supply voltage VDD3 and a second power supply voltage VDD2 and output them to the terminal voltage offset calibration circuit 130 and the terminal resistor offset calibration circuit 150 respectively. The reference voltage generation circuit 110 can be pre-adjusted and calibrated so that the voltage value of the second power supply voltage VDD2 is equal to one-half of the voltage value of the first power supply voltage VDD1, and the voltage value of the third power supply voltage VDD3 is equal to one-fourth of the voltage value of the first power supply voltage VDD1. The first power supply voltage VDD1 is, for example, 1.2 volts.

[0011] The first terminal replication model 120 has a first adjustable resistor RA1 and a second adjustable resistor RA2. Figure 2 Illustrates the implementation details of the first terminal replication model 120. Please also refer to Figure 1 and Figure 2 , the first adjustable resistor RA1 is coupled between the second power supply voltage VDD2 and the first node ND1. The second adjustable resistor RA2 is coupled between the first node ND1 and the ground voltage GND.

[0012] In addition, the first terminal replication model 120 further includes a first switching circuit SW1 and a second switching circuit SW2. The first switching circuit SW1 is connected in series with a first adjustable resistor RA1 on the circuit path between the second power supply voltage VDD2 and the first node ND1, and is controlled by a first control signal Sct1 to conduct or disconnect. The second switching circuit SW2 is connected in series with a second adjustable resistor RA2 on the circuit path between the first node ND1 and the ground voltage GND, and is also controlled by the first control signal Sct1 to conduct or disconnect. The first switching circuit SW1 and the second switching circuit SW2 can be constituted by, for example, one transistor or two transistors connected in parallel to each other. The first control signal Sct1, for example, comes from an external control circuit. When the first terminal replication model 120 is enabled for offset correction operation, the first switching circuit SW1 and the second switching circuit SW2 can conduct according to the first control signal Sct1 of a specific logic level. It should be noted that the above specific logic level can be logic 1 or logic 0 depending on actual requirements, and there is no fixed limit.

[0013] The first terminal replication model 120 is coupled to the terminal voltage offset correction circuit 130. The first terminal replication model 120 can receive a voltage correction code code1 from the terminal voltage offset correction circuit 130, and set the resistance ratio of the first adjustable resistor RA1 and the second adjustable resistor RA2 according to the voltage correction code code1 to adjust the terminal voltage Vcm1 generated at the first node Nd1. Specifically, the first adjustable resistor RA1 and the second adjustable resistor RA2 can respectively receive the voltage correction code code1, and change the length of the internal resistor connected to the circuit or the number of resistors connected in parallel according to the multiple bit values included in the voltage correction code code1 to adjust their respective resistance values.

[0014] In this embodiment, with respect to the voltage correction code code1, the change trend of the first adjustable resistor RA1 is opposite to that of the second adjustable resistor RA2. For example, when the voltage correction code code1 is incremented, the resistance value of the first adjustable resistor RA1 becomes larger, and the resistance value of the second adjustable resistor RA2 becomes smaller. When the voltage correction code code1 is decremented, the resistance value of the first adjustable resistor RA1 becomes smaller, and the resistance value of the second adjustable resistor RA2 becomes larger. The present invention is not limited thereto. Accordingly, the resistance ratio of the first adjustable resistor RA1 and the second adjustable resistor RA2 can be appropriately set, and the terminal voltage Vcm1 generated at the first node ND1 between the first adjustable resistor RA1 and the second adjustable resistor RA2 will also change accordingly.

[0015] The terminal voltage offset correction circuit 130 can be used to compare the terminal voltage Vcm1 with the third power supply voltage VDD3, and provide the voltage correction code code1 according to the comparison result. Specifically, Figure 1Among them, the terminal voltage offset correction circuit 130 includes a first comparator 132 and a first counting latch circuit 134. The non-inverting input terminal of the first comparator 132 is coupled to the first node ND1, the inverting input terminal of the first comparator 132 receives the third power supply voltage VDD3, and the output terminal of the first comparator 132 outputs a first comparison signal Scmp1. When the terminal voltage Vcm1 generated by the first node ND1 is greater than the third power supply voltage VDD3, the output terminal of the first comparator 132 outputs a first comparison signal Scmp1 with a high logic level. When the terminal voltage Vcm1 is less than the third power supply voltage VDD3, the output terminal of the first comparator 132 outputs a first comparison signal Scmp1 with a low logic level.

[0016] The first counting latch circuit 134 is coupled to the output terminal of the first comparator 132. The first counting latch circuit 134 can adjust the output voltage correction code code1 according to the first comparison signal Scmp1. Specifically, the first counting latch circuit 134 can initially provide a voltage correction code code1 with a default initial value, and then increment or decrement the voltage correction code code1 from the initial value in response to the logic level of the first comparison signal Scmp1.

[0017] The second terminal replication model 140 has a third adjustable resistor RA3 and a fourth adjustable resistor RA4. Figure 3 The implementation details of the second terminal replication model 140 are illustrated by way of example. Please also refer to Figure 1 and Figure 3 The second terminal replication model 140 includes a terminal replication circuit 142 and a resistor correction circuit 144.

[0018] The terminal replication circuit 142 includes a third adjustable resistor RA3, a fourth adjustable resistor RA4, a third switch circuit SW3, and a fourth switch circuit SW4. The third adjustable resistor RA3 is coupled between the half-voltage terminal HVT and the second node ND2, and the fourth adjustable resistor RA4 is coupled between the second node ND2 and the ground voltage GND. In the terminal correction circuit 100, the pull-up resistor Ru is coupled between the first power supply voltage VDD1 and the half-voltage terminal HVT, and the pull-up resistor Ru is, for example, 100 ohms.

[0019] The third switch circuit SW3 is connected in series with the third adjustable resistor RA3 on the circuit path between the half-voltage terminal HVT and the second node ND2, and is turned on or off under the control of the second control signal Sct2. The fourth switch circuit SW4 is connected in series with the fourth adjustable resistor RA4 on the circuit path between the second node ND2 and the ground voltage GND, and is also turned on or off under the control of the second control signal Sct2. The third switch circuit SW3 and the fourth switch circuit SW4 can be constituted by, for example, one transistor or two transistors connected in parallel with each other. The second control signal Sct2, for example, comes from an external control circuit. When the second terminal replication model 140 is enabled for the offset correction operation, the third switch circuit SW3 and the fourth switch circuit SW4 can be turned on according to the second control signal Sct2 of a specific logic level.

[0020] The second terminal replication model 140 is coupled to the terminal voltage offset correction circuit 130 and the terminal resistance offset correction circuit 150. The terminal replication circuit 142 in the second terminal replication model 140 can receive the voltage correction code code1 from the terminal voltage offset correction circuit 130, and set the resistance ratio of the third adjustable resistor RA3 and the fourth adjustable resistor RA4 according to the voltage correction code code1. Specifically, the third adjustable resistor RA3 and the fourth adjustable resistor RA4 can respectively receive the voltage correction code code1, and change the length of the internal resistor connected to the circuit or the number of resistors connected in parallel according to the multiple bit values included in the voltage correction code code1 to adjust their respective resistance values.

[0021] In this embodiment, the internal detailed structure of the terminal replication circuit 142 is the same as the internal detailed structure of the first terminal replication model 120. The first adjustable resistor RA1, the second adjustable resistor RA2, the first switch circuit SW1, and the second switch circuit SW2 are substantially the same as the third adjustable resistor RA3, the fourth adjustable resistor RA4, the third switch circuit SW3, and the fourth switch circuit SW4 respectively, and have the same circuit characteristics. Therefore, when receiving the same voltage correction code code1, the terminal voltage Vcm2 generated at the second node ND2 of the terminal replication circuit 142 is the same as the terminal voltage Vcm1 generated at the first node ND1 of the first terminal replication model 120.

[0022] On the other hand, as Figure 3 shown, the resistance correction circuit 144 includes four resistor circuits 146_1 to 146_4 connected in parallel with the terminal replication circuit 142 between the half-voltage terminal HVT and the ground voltage GND. In Figure 3In this case, the resistance circuit 146_1 includes a resistor R1_1, a selection switch SSW1, and a resistor R2_1. The resistance circuit 146_2 includes a resistor R1_2, a selection switch SSW2, and a resistor R2_2. The resistance circuit 146_3 includes a resistor R1_3, a selection switch SSW3, and a resistor R2_3. The resistance circuit 146_4 includes a resistor R1_4, a selection switch SSW4, and a resistor R2_4.

[0023] The structures and connection manners of the four resistance circuits 146_1 to 146_4 are similar. Taking the resistance circuit 146_1 as an example, the first end of the resistor R1_1 is coupled to the half-voltage terminal HVT. The first end of the selection switch SSW1 is coupled to the second end of the resistor R1_1, and the control end of the selection switch SSW1 receives the corresponding coding signal Str1. The first end of the resistor R2_1 is coupled to the second end of the selection switch SSW1, and the second end of the resistor R2_1 is coupled to the ground voltage GND. The resistance value of the resistance circuit 146_1 is equal to the sum of the resistance values of the resistor R1_1 and the resistor R2_1.

[0024] The resistance values of the resistors R1_1 to R1_4 are respectively the same as the resistance values of the resistors R2_1 to R2_4. The resistance values of the resistance circuits 146_1 to 146_4 are respectively formed by adding two internal resistors, and the resistance values of the resistance circuits 146_1 to 146_4 are different from each other. For example, the resistance values of the resistance circuits 146_1 to 146_4 can be incremented in a binary weighted manner from low to high, but the present invention is not limited thereto. Those skilled in the art can replace the resistors in the resistance circuits 146_1 to 146_4 as needed and with reference to the teachings of this embodiment to adjust the resistance values of the resistance circuits 146_1 to 146_4.

[0025] The resistance correction circuit 144 in the second terminal replication model 140 can receive the resistance correction code code2 from the terminal resistance offset correction circuit 150, and according to the resistance correction code code2, reduce the equivalent resistance value between the half-voltage terminal HVT and the ground voltage GND. Specifically, the four bit values included in the resistance correction code code2 can be respectively provided as the corresponding coding signals Str1 to Str4 to the selection switches SSW1 to SSW4 of each of the resistance circuits 146_1 to 146_4.

[0026] The resistor calibration circuit 144 can select to turn on one or more of the resistor circuits 146_1 to 146_4 according to the resistor calibration code code2. For example, if the four bit values included in the resistor calibration code code2 are 1010, the coding signals Str1 and Str3 are logic 1, and the coding signals Str2 and Str4 are logic 0. At this time, the resistor circuits 146_1 and 146_3 are turned on, and the resistor circuits 146_2 and 146_4 are turned off. Therefore, the resistors on the resistor circuits 146_1 and 146_3 are connected in parallel with the terminal replication circuit 142 between the half voltage terminal HVT and the ground voltage GND to reduce the equivalent resistance value between the half voltage terminal HVT and the ground voltage GND.

[0027] In one embodiment, the resistance value of one of the resistor circuits 146_1 to 146_4 can be designed to be a high resistance value (for example, 50 ohms), which is greater than the other resistor circuits and is configured to be turned on during the entire period of the offset correction operation. For example, when the resistor calibration code code2 is the preset initial value, only the resistor circuit with the high resistance value is turned on, and the other resistor circuits are turned off. After the resistor calibration code code2 is incremented or decremented from the preset initial value, in addition to the resistor circuit with the high resistance value being turned on, other resistor circuits are also turned on, thereby reducing the equivalent resistance value between the half voltage terminal HVT and the ground voltage GND.

[0028] The terminal resistor offset correction circuit 150 can be used to compare the comparison voltage Vcmp generated by the half voltage terminal HVT with the second power supply voltage VDD2 and provide the resistor calibration code code2 according to the comparison result. Specifically, in Figure 1 The terminal resistor offset correction circuit 150 includes a second comparator 152 and a second counting latch circuit 154. The non-inverting input terminal of the second comparator 152 receives the second power supply voltage VDD2, the inverting input terminal of the second comparator 152 is coupled to the half voltage terminal HVT, and the output terminal of the second comparator 152 outputs a second comparison signal Scmp2. When the second power supply voltage VDD2 is greater than the comparison voltage Vcmp generated by the half voltage terminal HVT, the output terminal of the second comparator 152 generates a second comparison signal Scmp2 with a high logic level. When the second power supply voltage VDD2 is less than the comparison voltage Vcmp, the output terminal of the second comparator 152 generates a second comparison signal Scmp2 with a low logic level.

[0029] The second counting latch circuit 154 is coupled to the output terminal of the second comparator 152. The second counting latch circuit 154 can adjust the output resistance correction code code2 according to the second comparison signal Scmp2. Specifically, the second counting latch circuit 154 can initially provide a resistance correction code code2 with a preset initial value, and then increment or decrement the resistance correction code code2 from the initial value in response to the logic level of the second comparison signal Scmp2.

[0030] Based on the above, the offset correction operation performed by the terminal correction circuit 100 can find the accurate voltage correction code code1 and resistance correction code code2, so that the transmission terminal or receiving terminal of the corresponding transmitter or receiver can obtain the accurate terminal voltage (common-mode voltage) and terminal resistance. It should be noted that the transmission terminals or receiving terminals of these corresponding transmitters or receivers need to be configured to be the same as or similar to the second terminal replication model 140, and can adjust the terminal voltage (common-mode voltage) and terminal resistance according to the voltage correction code code1 and resistance correction code code2.

[0031] Specifically, the offset correction operation can be divided into two stages: the first stage and the second stage. In the first stage, the terminal correction circuit 100 will first perform offset correction on the terminal voltage Vcm1 generated by the first node ND1 of the first terminal replication model 120 to make it equal to the third power supply voltage VDD3. First, the first counting latch circuit 134 in the terminal voltage offset correction circuit 130 provides a voltage correction code code1 with a default initial value to the first terminal replication model 120. Then, the first terminal replication model 120 will change the resistance values of the first adjustable resistor RA1 and the second adjustable resistor RA2 according to the voltage correction code code1 to set the resistance ratio of the first adjustable resistor RA1 and the second adjustable resistor RA2, thereby adjusting the terminal voltage Vcm1 generated by the first node ND1. Next, the first comparator 132 in the terminal voltage offset correction circuit 130 will compare the current terminal voltage Vcm1 with the third power supply voltage VDD3, and output a first comparison signal Scmp1 to the first counting latch circuit 134 according to the comparison result.

[0032] The first counting latch circuit 134 can continuously accumulate or decrement the voltage correction code code1 from its initial value in response to the logic level of the first comparison signal Scmp1 until the logic level of the first comparison signal Scmp1 changes state. For example, when the terminal voltage Vcm1 generated by the initial value of the voltage correction code code1 (e.g., 16) is greater than the third power supply voltage VDD3, the first counting latch circuit 134 will continuously accumulate the voltage correction code code1 from its initial value in response to the first comparison signal Scmp1 with a high logic level. In this case, the continuously accumulated voltage correction code code1 will cause the resistance value of the first adjustable resistor RA1 to continuously increase, and the resistance value of the second adjustable resistor RA2 to continuously decrease, thereby causing the voltage value of the terminal voltage Vcm1 to continuously decrease. When the terminal voltage Vcm1 decreases to the third power supply voltage VDD3, the first comparison signal Scmp1 will change state to a low logic level, so the first counting latch circuit 134 will stop accumulating the voltage correction code code1. Finally, the terminal voltage Vcm1 is fixed at the third power supply voltage VDD3 to complete the correction of the terminal voltage, and the corrected voltage correction code code1 can be stored.

[0033] In addition, in an embodiment, the terminal voltage Vcm1 generated by the initial value of the voltage correction code code1 may also be less than the third power supply voltage VDD3. At this time, the first counting latch circuit 134 can also continuously decrement the voltage correction code code1 from its initial value in response to the first comparison signal Scmp1 with a low logic level. The continuously decremented voltage correction code code1 will cause the resistance value of the first adjustable resistor RA1 to continuously decrease, and the resistance value of the second adjustable resistor RA2 to continuously increase, thereby causing the voltage value of the terminal voltage Vcm1 to continuously increase. When the terminal voltage Vcm1 increases to the third power supply voltage VDD3, the first comparison signal Scmp1 will change state to a high logic level, so the first counting latch circuit 134 will stop decrementing the voltage correction code code1. Finally, the terminal voltage Vcm1 is fixed at the third power supply voltage VDD3 to complete the correction of the terminal voltage, and the corrected voltage correction code code1 can be stored.

[0034] After the first stage is completed, the voltage correction code code1 provided by the first counting latch circuit 134 has been fixed. At the same time, the voltage correction code code1 will also be sent to the terminal replication circuit 142 in the second terminal replication model 140.

[0035] Next, in the second stage, the terminal calibration circuit 100 performs an offset calibration on the equivalent resistance value between the half-voltage terminal HVT and the ground voltage GND (equivalent to the terminal resistance formed by the second terminal replication model 140) to make it equal to the resistance value of the pull-up resistor Ru. First, the second counting latch circuit 154 in the terminal resistance offset calibration circuit 150 provides a resistance calibration code code2 with a default initial value to the second terminal replication model 140. Next, the resistance calibration circuit 144 in the second terminal replication model 140 selects one or more of the resistance circuits 146_1 to 146_4 to be switched on according to the resistance calibration code code2, so that the turned-on resistance circuits are connected in parallel between the half-voltage terminal HVT and the ground voltage GND to reduce the equivalent resistance value between the half-voltage terminal HVT and the ground voltage GND. Additionally, since the resistance ratio of the third adjustable resistor RA3 and the fourth adjustable resistor RA4 is still fixed, the switched-on resistance circuits will not affect the already calibrated terminal voltage Vcm2, which is half of the voltage of the half-voltage terminal HVT.

[0036] Next, the second comparator 152 in the terminal resistance offset calibration circuit 150 compares the second power supply voltage VDD2 with the comparison voltage Vcmp generated by the current half-voltage terminal HVT, and outputs a second comparison signal Scmp2 to the second counting latch circuit 154 according to the comparison result.

[0037] The second counting latch circuit 154 can continuously accumulate or decrement the resistance correction code code2 from the initial value in response to the logic level of the second comparison signal Scmp2 until the logic level of the second comparison signal Scmp2 changes state. For example, when the comparison voltage Vcmp generated at the half-voltage terminal HVT through the initial value of the resistance correction code code2 is greater than the second power supply voltage VDD2, the second counting latch circuit 154 will continuously accumulate the resistance correction code code2 from the initial value in response to the second comparison signal Scmp2 with a low logic level. In this case, the continuously accumulated resistance correction code code2 will continuously change the resistance circuits switched to the conducting state in the resistance circuits 146_1 to 146_4, so that the comparison voltage Vcmp generated at the half-voltage terminal HVT continuously decreases. When the comparison voltage Vcmp decreases to the second power supply voltage VDD2, the equivalent resistance value between the half-voltage terminal HVT and the ground voltage GND will be equal to the resistance value of the pull-up resistor Ru. At this time, the second comparison signal Scmp2 will change state to a high logic level, so the second counting latch circuit 154 will stop accumulating the resistance correction code code2. Finally, the comparison voltage Vcmp generated at the half-voltage terminal HVT is fixed at the second power supply voltage VDD2, the equivalent resistance value between the half-voltage terminal HVT and the ground voltage GND is equal to the resistance value of the pull-up resistor Ru, and the resistance value between the second node ND2 and the half-voltage terminal HVT and the resistance value between the second node ND2 and the ground voltage GND are maintained to match each other (both are equal to half of the resistance value of the pull-up resistor Ru) to complete the correction of the termination resistor, and the corrected resistance correction code code2 can be stored.

[0038] In this way, as long as the corrected voltage correction code code1 and resistance correction code code2 are applied to the transmission terminal or receiving terminal of the corresponding transmitter or receiver, an accurate terminal voltage (common-mode voltage) and terminal resistance can be obtained.

[0039] It should be noted that, depending on different design and decoding methods, in an embodiment, the second counting latch circuit 154 can also continuously decrement the resistance correction code code2 from the initial value in response to the second comparison signal Scmp2 with a low logic level, so that the comparison voltage Vcmp generated at the half-voltage terminal HVT continuously decreases to complete the correction of the termination resistor. The present invention is not limited thereto.

[0040] In addition, although the internal structures of the first terminal replication model 120 and the second terminal replication model 140 in this embodiment are different, the present invention is not limited thereto. In an embodiment, the internal structure of the first terminal replication model 120 can also be the same as that of the second terminal replication model 140 and include a terminal replication circuit and a resistance correction circuit, and the same effect as this embodiment can also be achieved.

[0041] Furthermore, although this embodiment is described by using a resistance correction circuit 144 including four resistance circuits 146_1 to 146_4, the number of the above components is not used to limit the present invention. Those skilled in the art can, according to their actual needs and with reference to the teachings of this embodiment, extrapolate the number of resistance circuits in the resistance correction circuit 144 to a greater number, thereby improving the accuracy of correction.

[0042] In summary, the terminal correction circuit of the present invention can perform two-stage offset correction to find accurate voltage correction codes and resistance correction codes. In addition to preventing the resistance value of the terminal resistor from shifting, it can also prevent the voltage of the terminal voltage from shifting. In this way, it can effectively eliminate the influence of process, voltage, and temperature changes on the terminal resistor and terminal voltage, and can effectively reduce signal disturbance during high-speed signal transmission and is not easily distorted. At the same time, compared with the current correction mechanism, the circuit area and capacitance value will also decrease, achieving the effect of cost reduction.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A terminal correction circuit, characterized in that, Including: A first terminal replication model having a first adjustable resistor and a second adjustable resistor. The first adjustable resistor is coupled between a second power supply voltage and a first node, and the second adjustable resistor is coupled between the first node and a ground voltage. The first terminal replication model is configured to set a resistance ratio of the first adjustable resistor and the second adjustable resistor according to a voltage correction code to adjust a terminal voltage generated at the first node; A terminal voltage offset correction circuit coupled to the first terminal replication model, configured to compare the terminal voltage with a third power supply voltage and provide the voltage correction code according to a comparison result; A second terminal replication model coupled to the terminal voltage offset correction circuit, having a third adjustable resistor and a fourth adjustable resistor. The third adjustable resistor is coupled between a half voltage terminal and a second node, and the fourth adjustable resistor is coupled between the second node and the ground voltage. The second terminal replication model is configured to set a resistance ratio of the third adjustable resistor and the fourth adjustable resistor according to the voltage correction code, and reduce an equivalent resistance value between the half voltage terminal and the ground voltage according to a resistance correction code; And A terminal resistance offset correction circuit coupled to the second terminal replication model, configured to compare a comparison voltage generated at the half voltage terminal with the second power supply voltage and provide the resistance correction code according to a comparison result.

2. The terminal calibration circuit according to claim 1, wherein Further including: A reference voltage generation circuit configured to receive a first power supply voltage and convert and output the first power supply voltage into the second power supply voltage and the third power supply voltage. A voltage value of the second power supply voltage is equal to one half of a voltage value of the first power supply voltage, and a voltage value of the third power supply voltage is equal to one quarter of the voltage value of the first power supply voltage.

3. The terminal calibration circuit according to claim 1, wherein The terminal voltage offset correction circuit includes: A first comparator having a non-inverting input terminal coupled to the first node, a inverting input terminal receiving the third power supply voltage, and an output terminal outputting a first comparison signal; and A first counting and latching circuit coupled to an output terminal of the first comparator, configured to adjust the output voltage correction code according to the first comparison signal.

4. The terminal calibration circuit according to claim 3, wherein The terminal resistance offset correction circuit includes: A second comparator having a non-inverting input terminal receiving the second power supply voltage, an inverting input terminal coupled to the half voltage terminal, and an output terminal outputting a second comparison signal; and A second counting and latching circuit coupled to an output terminal of the second comparator, configured to adjust the output resistance correction code according to the second comparison signal.

5. The terminal calibration circuit according to claim 4, characterized in that, Further including: A pull-up resistor coupled between the first power supply voltage and the half voltage terminal.

6. The terminal calibration circuit according to claim 5, wherein The offset correction operation performed by the terminal correction circuit can be divided into a first stage and a second stage. The first stage is configured to make the terminal voltage equal to the third power supply voltage, and the second stage is configured to make an equivalent resistance value between the half voltage terminal and the ground voltage equal to a resistance value of the pull-up resistor.

7. The terminal calibration circuit according to claim 6, wherein In the first stage, the first counting and latching circuit provides the voltage correction code of the initial value to the first terminal replication model. Then, the first comparator compares the current terminal voltage with the third power supply voltage, and outputs the first comparison signal to the first counting and latching circuit according to the comparison result.

8. The terminal calibration circuit according to claim 7, wherein In the first stage, the first counting and latching circuit continuously accumulates or decrements the voltage correction code from the initial value in response to the logic level of the first comparison signal until the logic level of the first comparison signal changes state.

9. The terminal calibration circuit according to claim 6, characterized in that, In the second stage, the second counting and latching circuit provides the resistance correction code of the initial value to the second terminal replication model. Then, the second comparator compares the current second power supply voltage with the comparison voltage, and outputs the second comparison signal to the second counting and latching circuit according to the comparison result.

10. The terminal calibration circuit according to claim 9, wherein In the second stage, the second counting and latching circuit continuously accumulates or decrements the resistance correction code from the initial value in response to the logic level of the second comparison signal until the logic level of the second comparison signal changes state.

11. The terminal calibration circuit according to claim 1, wherein The first terminal replication model includes: The first adjustable resistor and the second adjustable resistor respectively receive the voltage correction code, and adjust their respective resistance values according to the voltage correction code to set the resistance ratio of the first adjustable resistor to the second adjustable resistor; The first switch circuit is connected in series with the first adjustable resistor on the circuit path between the second power supply voltage and the first node, and is controlled by the first control signal to conduct or disconnect; and The second switch circuit is connected in series with the second adjustable resistor on the circuit path between the first node and the ground voltage, and is controlled by the first control signal to conduct or disconnect.

12. The terminal calibration circuit according to claim 1, characterized in that The second terminal replication model includes a terminal replication circuit, and the terminal replication circuit includes: The third adjustable resistor and the fourth adjustable resistor respectively receive the voltage correction code, and adjust their respective resistance values according to the voltage correction code to set the resistance ratio of the third adjustable resistor to the fourth adjustable resistor; The third switch circuit is connected in series with the third adjustable resistor on the circuit path between the half-voltage terminal and the second node, and is controlled by the second control signal to conduct or disconnect; and The fourth switch circuit is connected in series with the fourth adjustable resistor on the circuit path between the second node and the ground voltage, and is controlled by the second control signal to conduct or disconnect.

13. The terminal calibration circuit according to claim 12, wherein The second terminal replication model further includes a resistance correction circuit, and the resistance correction circuit includes a plurality of resistance circuits connected in parallel with the terminal replication circuit between the half-voltage terminal and the ground voltage. Each of the plurality of resistance circuits includes: A first resistor, whose first end is coupled to the half-voltage terminal; A selection switch, whose first end is coupled to the second end of the first resistor, and whose control end receives the corresponding coding signal; and A second resistor, whose first end is coupled to the second end of the selection switch, and whose second end is coupled to the ground voltage.

14. The terminal calibration circuit according to claim 13, wherein The resistance values of the plurality of resistance circuits increase in a binary weighted manner from low to high.

15. The terminal calibration circuit according to claim 13, characterized in that, A plurality of bit values included in the resistance correction code are respectively provided as corresponding encoding signals to the selection switches of the respective plurality of resistance circuits. The resistance correction circuit selects to switch on one or more of the plurality of resistance circuits according to the resistance correction code, so as to reduce the equivalent resistance value between the half-voltage terminal and the ground voltage.

16. The terminal calibration circuit according to claim 13, wherein The resistance value of one of the plurality of resistance circuits is greater than that of the other resistance circuits, and is configured to be turned on during the entire period of the offset correction operation.

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