Connection configuration method of computing equipment, computing equipment, system and device

Abstract

The invention discloses a connection configuration method of computing equipment, the computing equipment, a system and a device, and relates to the technical field of equipment management, after a user changes the line connection mode of the computing equipment, the line connection mode of the computing equipment is automatically identified through an exchange processor and is automatically switched into firmware adaptive to the line connection mode, and the user experience is improved. Therefore, the connection configuration difficulty of the computing device is reduced, and the universality of the computing device is improved.

Description

Technical Field

[0001] This application relates to the technical field of device management, and particularly to a connection configuration method for computing devices, computing devices, systems, and apparatuses. Background Art

[0002] With the rapid development of computationally intensive application scenarios, users have put forward high requirements for the hardware devices that perform computations. By using accelerators, computing efficiency can be improved. By interconnecting multiple accelerators to achieve collaborative work of multiple accelerators, computing efficiency can be further improved.

[0003] In the related art, multiple accelerators are connected in a fixed connection manner, and the fixed connection manner is adapted to the corresponding application scenario. When the application scenario is changed, the original connection manner is no longer applicable and needs to be adjusted. However, there are complex problems in adjusting the connection manner, resulting in the problem of low versatility of the device. Summary of the Invention

[0004] This application provides a connection configuration method for computing devices, computing devices, systems, and apparatuses to at least solve the problem of low versatility of computing devices in the related art.

[0005] This application provides a connection configuration method for a computing device, which is applied to a computing device. The computing device includes at least one switching processor, a first controller, and at least one connection port; for any one connection port, the method includes: obtaining, by the first controller, a first level state of an identification pin of the connection port and sending the first level state to the switching processor; determining, by the switching processor according to the first level state, a line connection manner corresponding to the connection port; and matching, by the switching processor, a firmware corresponding to the line connection manner so that the connection port performs data transmission according to the line connection manner.

[0006] This application also provides a computing device, including: at least one switching board, at least one switching processor, a first controller, and at least one connection port, wherein the switching processor, the first controller, and multiple connection ports are installed on the switching board; the first controller is connected to the multiple connection ports and the switching processor through internal lines of the switching board, and the first controller is configured to obtain a first level state of an identification pin of the connection port and send the first level state to the switching processor; the switching processor is configured to determine a line connection manner corresponding to the connection port according to the first level state; and the switching processor is further configured to match a firmware corresponding to the line connection manner so that the connection port performs data transmission according to the line connection manner.

[0007] The present application also provides a computing system, including: a host, a power supply, and a computing device. Among them, the host is connected to a second connector of the computing device, and the host is used to manage the computing system; the power supply is connected to a power supply connector of the computing device and the host, and the power supply is used to supply power to the computing system.

[0008] The present application also provides a connection configuration device for a computing device, which is applied to the computing device. The computing device includes at least one switching processor, a first controller, and at least one connection port; for any one connection port, the device includes: an acquisition module, configured to acquire a first level state of an identification pin of the connection port through the first controller and send the first level state to the switching processor; a determination module, configured to determine a line connection mode corresponding to the connection port through the switching processor according to the first level state; a matching module, configured to match a firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

[0009] The present application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above connection configuration methods of the computing device when executing the computer program.

[0010] The present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored. Wherein, when the computer program is executed by a processor, it implements the steps of any one of the above connection configuration methods of the computing device.

[0011] The present application also provides a computer program product, including a computer program, which implements the steps of any one of the above connection configuration methods of the computing device when executed by a processor.

[0012] Through the present application, after the user changes the line connection mode of the computing device, the switching processor automatically identifies the line connection mode of the computing device and automatically switches to the firmware adapted to the line connection mode, thereby reducing the difficulty of connection configuration of the computing device and improving the versatility of the computing device. Description of the Drawings

[0013] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 It is a schematic diagram of an application scenario of a computing device provided by an embodiment of the present application;

[0015] Figure 2Schematic flowchart of a connection configuration method for a computing device provided by an embodiment of the present application;

[0016] Figure 3 Schematic flowchart of a connection configuration method for a computing device provided by an embodiment of the present application;

[0017] Figure 4 Schematic diagram of the structure of a computing device provided by an embodiment of the present application;

[0018] Figure 5 Schematic diagram of the structure of a first connector provided by an embodiment of the present application;

[0019] Figure 6 Schematic diagram of the structure of a circuit board provided by an embodiment of the present application;

[0020] Figure 7 Schematic diagram of the structure of an inter-board connection provided by an embodiment of the present application;

[0021] Figure 8a Schematic diagram of a full-interconnection provided by an embodiment of the present application;

[0022] Figure 8b Schematic diagram of a non-full-interconnection provided by an embodiment of the present application;

[0023] Figure 9 Schematic diagram of the structure of a computing device provided by an embodiment of the present application;

[0024] Figure 10 Schematic diagram of the structure of a power supply board provided by an embodiment of the present application;

[0025] Figure 11 Schematic diagram of the structure of a computing system provided by an embodiment of the present application;

[0026] Figure 12 Schematic diagram of the structure of a connection configuration device for a computing device provided by an embodiment of the present application;

[0027] Figure 13 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0029] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0030] It should be noted that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. The terms "mounted", "connected", "joined" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. The terms "parallel", "perpendicular", "equal" include the described situations and situations similar to the described situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal values is less than or equal to 5% of either one of them. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

[0031] Exemplarily, a computing device is used to manage multiple devices to achieve data computing. For server application scenarios, the computing device may include a switching processor and at least one accelerator. The computing device can be used to manage multiple accelerators through the switching processor to achieve data computing. Among them, the accelerator is used to perform calculations. The accelerator has a large-scale parallel architecture and a deeply optimized data throughput design. The accelerator contains a large number of computing cores, and each core focuses on executing corresponding instructions, thereby effectively achieving parallel computing. The accelerator mounts dozens of task threads on each computing core through hardware-level thread scheduling. When a thread pauses due to unready data, the hardware instantly and seamlessly switches to the next thread, avoiding long waits and thus improving computing efficiency. The accelerator adopts on-board high-bandwidth video memory, which is directly connected to the computing core through chip stacking technology, expanding the memory bandwidth to several times that of the processor's main memory, thereby improving computing efficiency. The accelerator removes general-purpose logics necessary for processors such as complex branch prediction or out-of-order execution, so as to focus on computing and improve computing efficiency. The switching processor is used to manage multiple accelerators so that computing data can be correctly transmitted, enabling the accelerators to operate normally.

[0032] Combined with scenario examples, in computing-intensive application scenarios such as deep learning, scientific computing, big data processing, or graphics rendering, the computing efficiency is improved by interconnecting multiple accelerators. The switching processor of the computing device can effectively manage between multiple accelerators to achieve effective collaborative work between multiple accelerators.

[0033] In related technologies, in a computing device, the switching processor and multiple accelerators are connected in a fixed connection manner, and the fixed connection manner corresponds to one application scenario. When the application scenario is changed, the original application scenario is no longer applicable, and the connection manner between the switching processor and multiple accelerators needs to be adjusted. However, adjusting the connection manner has complex problems, resulting in poor versatility of the computing device.

[0034] Combined with scenario examples, different application scenarios have different requirements. For example, some scenarios have high requirements for computing efficiency, and the computing device has a larger number of accelerators. Some scenarios have high requirements for communication bandwidth, and the computing device should reduce the number of accelerators and increase network controllers. The fixed connection manner makes it difficult to make adjustments.

[0035] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the connection configuration method of the computing device depends, the specific application environment architecture or specific hardware architecture is described herein. Refer to Figure 1 ,Figure 1 The figure is a schematic diagram of the application scenario of a computing device. The user terminal generates data to be calculated and sends the data to be calculated to the computing device. The computing device performs calculation processing on the data to be calculated to obtain a calculation result, and the computing device sends the calculation result to the user terminal.

[0037] Figure 2 This is a schematic flowchart of the connection configuration method of the computing device provided by the embodiment of the present application. As Figure 2 shown, the embodiment of the present application provides a connection configuration method for a computing device. The method will be described in detail as follows:

[0038] S201. Obtain the first level state of the identification pin of the connection port through the first controller and send the first level state to the switching processor.

[0039] Among them, the connection configuration method of the computing device is applied to the computing device. The computing device includes at least one switching processor, a first controller, and at least one connection port; for any one connection port.

[0040] Exemplarily, the switching processor is used to manage the devices installed on the computing device. The connection port is used to connect an accelerator and / or a network controller to enable the accelerator and / or the network controller to access the computing device. The identification pin of the connection port is used to display the corresponding first level state according to the line connection mode between the connection port and the connected device. The first controller is used to monitor the first level state of the identification pin in real time. The first controller sends the first level state to the switching processor so that the switching processor determines the real-time line connection mode according to the first level state.

[0041] Optionally, when the connection port is connected to different types of devices, the corresponding line connection modes are different. For the same type of device, one connection port can be connected to one or more.

[0042] S202. Determine the line connection mode corresponding to the connection port through the switching processor according to the first level state.

[0043] Optionally, for different application scenarios, the line connection modes of the connection ports are different. The corresponding relationship between the line connection mode and the first level state is preset to associate the line connection mode with the first level state.

[0044] Combined with the scenario example, on this basis, when the user switches the line connection mode, the identification pin will switch to the corresponding first level state according to the preset corresponding relationship. Therefore, the real-time first level state can reflect the real-time line connection mode, so that the switching processor determines the real-time line connection mode.

[0045] S203. Match the firmware corresponding to the line connection method through the switching processor, so that the connection port performs data transmission according to the line connection method.

[0046] Exemplarily, the line connection method is a structure at the hardware level. After the user switches the line connection method, the firmware at the software level is required to implement data transmission. The switching processor loads the corresponding firmware according to the identified line connection method to implement data transmission using the corresponding firmware.

[0047] Combined with the scenario example, after switching the line connection method according to the application scenario, the switching processor automatically identifies the line connection method and loads the corresponding firmware, so that the line connection method can operate normally to implement data transmission, so that the computing device can adapt to the switched application scenario.

[0048] The connection configuration method of the computing device provided by the embodiment of the present application obtains the first level state of the identification pin of the connection port through the first controller and sends the first level state to the switching processor; according to the first level state, determines the line connection method corresponding to the connection port through the switching processor; matches the firmware corresponding to the line connection method through the switching processor, so that the connection port performs data transmission according to the line connection method. The above solution automatically identifies the line connection method of the computing device through the switching processor and automatically switches to the firmware adapted to the line connection method after the user changes the line connection method of the computing device, thereby reducing the difficulty of the connection configuration of the computing device and improving the versatility of the computing device.

[0049] Based on any of the above embodiments, below, combined with Figure 3 , the detailed process of the connection configuration of the computing device will be described.

[0050] Figure 3 It is a schematic flowchart of a connection configuration method of a computing device provided by an embodiment of the present application. As Figure 3 shown, the method includes:

[0051] S301. Determine a plurality of identification pins connected by a plurality of first connectors.

[0052] Among them, the connection port includes a plurality of first connectors.

[0053] Exemplarily, a plurality of first connectors are used to split the data transmission channels of the connection port to expand the number or type of devices connected to the connection port.

[0054] Illustrated with a scenario example, taking the connection port of 16 channels (X16) as an example, the connection port may include 2 first connectors. Each first connector includes 8 channels (X8), and the 2 first connectors constitute the 16 channels of the connection port. The 2 first connectors can jointly connect to one device to achieve data transmission of 16 channels. The 2 first connectors can also be respectively connected to one device to achieve data transmission of 2 eight-channel. Under different line connection methods, different firmware is required to achieve data transmission.

[0055] Exemplarily, each first connector is respectively connected to at least one identification pin, so that the identification pin can respectively identify each first connector.

[0056] S302. Obtain the first level states corresponding to multiple identification pins.

[0057] Exemplarily, each first connector is respectively connected to at least one identification pin. Therefore, the line connection method of each first connector can be represented by the first level state of at least one identification pin.

[0058] Illustrated with a scenario example, for the same type of device, when multiple first connectors of a connection port are all connected to the same device, the first level states of the identification pins of each first connector are different. When multiple first connectors of a connection port are respectively connected to different devices, the first level states of the identification pins of each first connector are the same. Thus, different line connection methods are distinguished by the first level state.

[0059] S303. If the connection port is a dual-function port, then according to the first level state, the line connection method corresponding to the connection port is determined by the switching processor. The line connection method is a full-interconnection connection or a non-full-interconnection connection. The dual-function port is used to connect to a network controller or to connect to other switching processors through other dual-function ports.

[0060] Exemplarily, the dual-function port is a connection port that supports connecting 2 types of devices. The user can switch the devices connected to the dual-function port according to the actual requirements of the application scenario.

[0061] Exemplarily, the interconnection connection is the connection between multiple computing devices to achieve the collaborative work of multiple computing devices, thereby improving the computing efficiency. Taking the interconnection connection of 2 computing devices as an example, any one switching processor of one computing device is connected to each switching processor of the other switching processor as a full-interconnection connection. Any one switching processor of one computing device is connected to one of the switching processors of the other switching processor as a non-full-interconnection connection. The switching processors between the 2 computing devices are connected through the dual-function ports of the 2 computing devices respectively.

[0062] Exemplarily, compared with non-full-interconnection connections, full-interconnection connections require more lines to implement. Correspondingly, there are more dual-functional ports participating in full-interconnection connections. In non-full-interconnection connections, there are fewer dual-functional ports participating in non-full-interconnection connections. Some of the dual-functional ports can be connected to the network controller to improve the network bandwidth of the computing device.

[0063] Exemplarily, the dual-functional port corresponds to different first-level states when it is used for interconnecting computing devices or not used for interconnecting computing devices.

[0064] Based on the above embodiments, the first-level state can automatically identify the line connection mode of the dual-functional port, and thus perform corresponding configurations to improve the versatility of the computing device.

[0065] S304. If the connection port is a single-functional port, then according to the first-level state, the switching processor determines the line connection mode corresponding to the connection port. The line connection mode is that the connection port is connected to one device, or the connection port is connected to multiple devices. The single-functional port is used to connect an accelerator or a network controller.

[0066] Exemplarily, the single-functional port is used to connect to an accelerator or a network controller. The difference between the single-functional port and the dual-functional port is that the single-functional port is not used to establish an interconnection connection.

[0067] Exemplarily, when the single-functional port is connected to different devices or connected to devices through different line connection modes, they respectively correspond to different first-level states.

[0068] It should be noted that the execution order of S303 and S304 in this application is not limited.

[0069] S305. The switching processor matches the firmware corresponding to the line connection mode so that the connection port performs data transmission according to the line connection mode.

[0070] It should be noted that for the execution process of S305, refer to S203, which will not be elaborated here.

[0071] Figure 4 This is the structural schematic diagram of the computing device provided by the embodiment of the present application, as Figure 4As shown in the figure, an embodiment of the present application provides a computing device. A detailed description of the structure of the computing device is as follows. The computing device includes: at least one switching board, at least one switching processor, a first controller, and at least one connection port. Among them, the switching processor, the first controller, and multiple connection ports are installed on the switching board; the first controller is connected to the multiple connection ports and the switching processor through the internal circuit of the switching board. The first controller is used to obtain the first level state of the identification pin of the connection port and send the first level state to the switching processor; the switching processor is used to determine the line connection mode corresponding to the connection port according to the first level state; the switching processor is also used to match the firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

[0072] Exemplarily, an internal circuit, connection ports, and a processor slot are integrated on the switching board. The processor slot is connected to the internal circuit, and the switching processor is installed in the processor slot to connect the switching processor to the internal circuit. The internal circuit is connected to the connection port. The switching processor is used to manage the devices on the switching board and the devices connected to the switching board.

[0073] Exemplarily, the switching processor is directly connected to the connection port through the internal circuit of the switching board to control the connection port. In addition, the switching processor is also connected to the first controller, and the first controller is connected to the connection port, so that the switching processor obtains the first level state of the connection port through the first controller.

[0074] Combined with the scenario example, through the real-time monitoring of the first controller, after the user switches the line connection mode of the computing device, the latest line connection mode can be obtained in real time, so that the switching processor performs corresponding configuration according to the latest line connection mode.

[0075] Optionally, the first controller can be a Complex Programmable Logic Device (CPLD for short).

[0076] A feasible implementation method Figure 5 is the structural schematic diagram of the first connector provided by the embodiment of the present application. As Figure 5 shown, the connection port includes multiple first connectors; among them, the multiple first connectors are connected to multiple identification pins, and the identification pins are used to indicate the first level state of the first connector; the first controller is connected to the multiple identification pins, and the first controller is used to obtain the first level state corresponding to the multiple identification pins.

[0077] Exemplarily, the multiple first connectors are used to split the data transmission channel of the connection port to expand the number or type of devices connected to the connection port.

[0078] Exemplarily, multiple first connectors of the same connection port can be respectively connected to devices, or multiple first connectors of the same connection port can jointly connect to one device. The above solutions correspond to different line connection methods, and in each line connection method, the corresponding channels are different.

[0079] Exemplarily, by setting identification pins on each first connector and respectively monitoring each identification pin, multiple line connection methods can be identified.

[0080] In this feasible implementation method, by setting multiple first connectors at the connection port, the types of line connection methods that can be identified can be expanded, so as to accurately identify for multiple application scenarios.

[0081] A feasible implementation method is that the switching processor is used to perform firmware matching to switch the line connection method for data transmission. The line connection method includes at least one of the following: full interconnection between switching processors, non-full interconnection between switching processors, one connection port connecting to one device, or one connection port connecting to multiple devices, and the device is an accelerator or a network controller.

[0082] Optionally, the connection ports can be divided into upstream ports, interconnection ports, and downstream ports according to their functions. The upstream port is connected to the host to realize data transmission between the switching device and the host. The interconnection port is used for connection between switching processors to realize collaborative work between switching processors, and the interconnection port is a dual-function port. The downstream port is connected to an accelerator or a network controller.

[0083] Combined with the scenario example, for application scenarios with high requirements for communication bandwidth, some dual-function ports are used to connect to network controllers to improve the network bandwidth of the computing device.

[0084] Optionally, the connection method of the connection port is set to a pluggable structure. When the application scenario of the switching device changes and it is necessary to adjust the device connected to the connection port, quick adjustment can be achieved through the pluggable structure.

[0085] Exemplarily, the interconnection port is set as a Fabric mode port. The Fabric mode port is a port whose function can be dynamically reset. The Fabric mode port is a protocol-independent signal channel. The Fabric mode port does not parse the upper-layer data content and focuses on realizing device direct connection and signal relay. Therefore, the Fabric mode port can be compatible with different types of devices, can switch to connect different devices according to the application scenario, and thus improve the versatility of the switching device. The dual-function mode of the interconnection port is realized through the Fabric mode.

[0086] Exemplarily, by adjusting the devices connected through the connection ports, different application scenarios can be adapted, thereby enhancing the versatility of the switching device.

[0087] Exemplarily, the accelerator is used to perform data calculations. The switching processor sends the data to be calculated to the accelerator, and the accelerator processes the calculation to obtain the calculation result, and then the accelerator sends the calculation result to the switching processor.

[0088] Optionally, the accelerator can be a Graphics Processing Unit (GPU for short).

[0089] Exemplarily, the network controller is used to implement the network connection of the switching device.

[0090] Combined with the scenario example, for the application scenario of large model training, networking is performed through the network controller to enable multiple computing devices to work together. If the application scenario has high requirements for communication bandwidth, it can be achieved by increasing the number of network controllers.

[0091] For computing-intensive and parallelizable application scenarios, such as large model training expansion and multi-task concurrent processing, connecting more accelerators can increase the parallelism, thereby improving the computing efficiency.

[0092] In this feasible implementation method, corresponding firmware is respectively matched for various line connection methods, so that the computing device can be flexibly configured in multiple application scenarios, thereby enhancing the versatility of the computing device.

[0093] A feasible implementation method Figure 6 is the structural schematic diagram of the circuit board provided by the embodiment of the present application. As Figure 6 shown, the computing device further includes at least one circuit board. Among them, the switching processor is connected to a circuit board through multiple first connectors of a connection port, and a circuit board is connected to a device to realize that one connection port is connected to one device; the switching processor is connected to multiple circuit boards through multiple first connectors of a connection port, and a circuit board is connected to a device to realize that one connection port is connected to multiple devices.

[0094] Exemplarily, the circuit board can be connected to one first connector or multiple first connectors. The circuit board precisely, reliably and permanently connects components such as resistors, capacitors and interfaces together through pre-designed and manufactured precision conductive lines to ensure the correct electrical path.

[0095] Optionally, the circuit board can be a Printed Circuit Board (PCB for short).

[0096] Exemplarily, each connector includes a fixed number of channels. The more channels there are, the greater the data transmission bandwidth. When the switching processor is connected to multiple accelerators through multiple first connectors of a connection port, the number of connected accelerators can be effectively expanded, thereby increasing the parallelism of the accelerators. When the switching processor is connected to one accelerator through multiple first connectors of a connection port, since the number of channels connected to the accelerator is relatively large, the transmission bandwidth of the accelerator can be effectively increased.

[0097] Illustrated with a scenario example, take the case where the connection port connects two first connectors, and each first connector corresponds to 8 channels. When both of the two first connectors are connected to one accelerator, one accelerator is connected to the switching processor through 16 channels. Compared with 8 channels, 16 channels can provide a larger bandwidth, thereby reducing communication latency. For data movement-intensive application scenarios, for example, in distributed training, gradients need to be synchronized frequently, and in high-resolution data processing, the processes of transmitting the data to be calculated to the accelerator video memory and outputting the calculation results to the switching processor have relatively high requirements for bandwidth. Providing a larger bandwidth can effectively improve the calculation efficiency.

[0098] For calculation-intensive parallelizable application scenarios, such as large model training expansion and multi-task concurrent processing, connecting more accelerators can increase the parallelism, thereby improving the calculation efficiency.

[0099] In this feasible implementation, by setting first connectors that can be flexibly switched, adaptive switching can be performed according to the application scenario of the switching device, thereby improving the versatility of the switching device.

[0100] A feasible implementation Figure 7 is a schematic structural diagram of the inter-board connection provided by the embodiment of the present application. As Figure 7 shown, the number of switching boards is multiple. Among them, the multiple switching boards are connected through connection ports to perform inter-board connection on the first connectors respectively corresponding to the multiple switching boards. The number of connection ports of any one switching board for inter-board connection is at least one.

[0101] Exemplarily, a computing device may include multiple switching boards. The inter-board connection is an interconnection between multiple switching boards to enable the collaborative work of multiple switching boards and establish connections between the devices respectively connected by the multiple switching boards. ]>

[0102] Exemplarily, the connection port for realizing the inter-board connection is a dual-functional port, that is, the dual-functional port is used to connect the switching board.

[0103] Exemplarily, by connecting ports for inter-board connection, direct connection between multiple switching boards can be achieved. When transmitting data and / or signals among multiple switching boards, the transmission is carried out through the inter-board connection lines. The data and / or signals do not need to be forwarded by other devices (such as a host, a backplane), and protocol conversion is not required, thereby improving the transmission efficiency.

[0104] In this feasible implementation, by accurately identifying the inter-board connection between multiple switching boards, accurate configuration can be carried out, thereby improving the transmission efficiency between multiple switching boards.

[0105] In a feasible implementation, any one of the first connectors of any one switching board among multiple switching boards is connected to multiple first connectors of other switching boards to achieve full-interconnection; any one of the first connectors of any one switching board among multiple switching boards is connected to one first connector of other switching boards to achieve non-full-interconnection.

[0106] Next, Figure 8a a description of full-interconnection will be given.

[0107] Figure 8a FIG. is a schematic diagram of the full-interconnection provided by an embodiment of the present application. As Figure 8a shown, in the full-interconnection, any one switching processor of any one switching board is respectively connected to multiple switching processors of another switching board.

[0108] Next, Figure 8b a description of non-full-interconnection will be given.

[0109] Figure 8b FIG. is a schematic diagram of the non-full-interconnection provided by an embodiment of the present application. As Figure 8b shown, in the non-full-interconnection, any one switching processor of any one switching board is only connected to one of the switching processors of another switching board.

[0110] Exemplarily, compared with non-full-interconnection, the full-interconnection has more inter-board lines, so more dual-function ports are required.

[0111] Optionally, the connection manner between switching processors further includes intra-board connection. By connecting the two first connectors corresponding to one of the connection ports on the switching board to each other, the two switching processors on one switching board can be interconnected. In the switching board, any one switching processor manages some devices. Through intra-board connection, multiple devices in the switching board can be interconnected to achieve direct transmission, thereby improving the computing efficiency of the computing device.

[0112] Illustrate specific scenarios for recognition based on the first level state with scenario examples. For example, the switchboard includes 2 switch processors, each connection port includes 2 first connectors, and the connection port is 16-channel. A first level state of 10 for a single-function port indicates that the single-function port is connected to one device in 16 channels. A first level state of 00 for a single-function port indicates that the single-function port is connected to 2 devices in 2 8-channel configurations. A first level state of 11 for a dual-function port indicates that the interconnection mode of the dual-function port is full interconnection. A first level state of 10 for a dual-function port indicates that the interconnection mode of the dual-function port is full interconnection.

[0113] In this feasible implementation, corresponding application scenarios are adapted for various interconnection methods respectively, the interconnection method is automatically recognized, and corresponding configurations can be made to improve the versatility of the switchboard.

[0114] A feasible implementation Figure 9 is the structural schematic diagram of the computing device provided by the embodiment of the present application, as Figure 9 shown, the computing device further includes a second controller, a configuration connector, and jumper pins. Among them, the jumper pins are connected to the configuration connector, and the jumper pins are used to control the second level state of the configuration connector; the first controller is connected to the configuration connector and the second controller, and the first controller is used to obtain the second level state and send the second level state to the second controller; the second controller is used to determine whether to manage the computing device according to the second level state.

[0115] Exemplarily, the second controller can be a Baseboard Management Controller (BMC for short). The second controller is used to manage the devices inside the computing device so that the computing device can operate normally.

[0116] Optionally, the management work of the second controller includes but is not limited to power supply, heat dissipation, etc.

[0117] Exemplarily, different management methods can be adapted in different application scenarios, and the computing device can be managed by the second controller inside the computing device or an external controller.

[0118] Illustrate with scenario examples that in the whole cabinet solution, the whole cabinet includes multiple computing devices, each computing device is independent, and the whole cabinet solution adapts the second controller inside the computing device to manage the computing device. In the whole cabinet solution, the failure of any one computing device does not affect global management (for example, when a computing device is short-circuited, the entire cabinet does not power off). When hot-swapping and replacing the switchboard of the computing device, the second controller can maintain local logs and configuration persistence. The whole cabinet solution can complete firmware upgrade without relying on the host outside the computing device.

[0119] In a rack-mounted server solution, the server includes multiple computing devices, which are uniformly managed by the host of the server. The host's unified management can unify the power supply timing, which may include power-on, initialization, and fan startup timings. The host's unified management can uniformly manage the topology mapping tables of multiple computing devices. The host's unified management can accurately control the server's heat dissipation devices based on the temperature inside the server.

[0120] Combined with a scenario example, after the user switches to an all-in-one cabinet solution or a rack-mounted server solution, manually adjust the jumper pins so that the computing device can automatically identify the current application scenario, and thus automatically determine the control scheme of the computing device.

[0121] In this feasible implementation, by setting the jumper pins and configuring the connectors, the first controller can obtain the second-level state in real time, so that the second controller can determine whether to manage the computing device according to the application scenario of the computing device, so that the management of the computing device adapts to different business scenarios, and thus improves the versatility of the computing device.

[0122] A feasible implementation, the computing device further includes a power supply board, wherein the power supply board is connected to the switching board, the accelerator, and the network controller, and the power supply board is used to supply power to the switching board, the accelerator, and the network controller.

[0123] Exemplarily, the computing device may include multiple switching boards, and the multiple switching boards are arranged in multiple layers to form the computing device. A power supply board is respectively connected to the switching boards of each layer of the computing device, and the multiple switching boards are powered by the power supply board to realize power supply to the devices on the multiple switching boards.

[0124] Next, in combination with Figure 10 the power supply board will be described.

[0125] Figure 10 It is a schematic structural diagram of the power supply board provided by the embodiment of the present application. As Figure 10 shown, the computing device includes multiple layers of switching boards, the power supply board includes multiple connectors, and the multiple connectors are arranged in multiple rows. The positions of the multiple connectors on the power supply board correspond to the connection ports of the multiple switching boards of the computing device to supply power to the computing device through the connectors.

[0126] Combined with a scenario example, through the multiple connectors of the power supply board, a detachable connection between the power supply board and the computing device can be realized. Compared with an integrated power supply board, in case of a single-point failure, only the faulty part can be removed and replaced, thus reducing the maintenance cost.

[0127] Optionally, multiple connectors of the power supply board can be used for power supply or data transmission. The connectors for power supply can transmit current, and the connectors for data transmission can transmit data, enabling the host to uniformly perform data transmission with multiple switching boards.

[0128] Exemplarily, power supply can be achieved through a power supply board including multiple connectors, enabling unified power supply to multiple devices in a computing device.

[0129] In this feasible implementation, the power supply board is used to uniformly power multiple devices in the computing device to reduce the complexity of power supply.

[0130] In a feasible implementation, the power supply board further includes a power supply connector. The power supply connector is connected to a power source outside the power supply board and the computing device, and is used to introduce the power source to supply power to the computing device.

[0131] Exemplarily, the power supply board is connected to a power source outside the computing device through a power supply device, thereby introducing external power supply. The power supply board is connected to multi-layer switching boards of the computing device through multiple connectors, thereby uniformly supplying power to devices on multiple switching boards simultaneously.

[0132] Combined with a scenario example, a power supply line between the power source and the computing device is realized through the power supply connector and multiple connectors of the power supply board to uniformly supply power to multiple switching boards of the computing device. There is no need to reserve independent power spaces for each switching board inside the computing device.

[0133] In this feasible implementation, current is uniformly introduced through the power supply connector of the power supply board to uniformly supply power to multiple switching boards of the computing device, which can effectively save the space of the computing device and thus improve the computing power density of the computing device.

[0134] Figure 11 The following is a schematic structural diagram of the computing system provided by the embodiment of the present application, as Figure 11 As shown, the embodiment of the present application provides a computing system, and the structure of the computing system is described in detail. The computing system includes a host, a power source, and multiple computing devices. Among them, the host is connected to a second connector of the computing device, and the host is used to manage the computing system; the power source is connected to the power supply connector of the computing device and the host, and the power source is used to supply power to the computing system.

[0135] Exemplarily, the computing system includes multiple computing devices, and the overall relatively large computing power of the computing system is achieved through the multiple computing devices. The power source is used to supply power to devices in the computing system. The host is used to uniformly manage the computing system, including managing the power source and multiple computing devices.

[0136] Exemplarily, the second connector of the computing device is used for connecting the computing device to the host, and the second connector is used for data transmission between the computing device and the host.

[0137] Exemplarily, by setting up the host, multiple computing devices of the computing system can be effectively managed, thereby improving the reliability of the collaborative work of multiple computing devices.

[0138] A feasible implementation is that the computing system further includes a backplane. Among them, the backplane is connected to the second connector and the power supply connector of the computing device; the host is connected to the backplane to connect the host to the computing device; the power supply is connected to the backplane to connect the power supply to the computing device and the host.

[0139] Exemplarily, the backplane connects multiple computing devices, and the integration degree of the host can be improved through the backplane. The backplane replaces discrete lines so that data between the host and the computing device can pass through directly. After the power supply is connected to the backplane, it supplies power to multiple computing devices through intelligent power distribution.

[0140] Exemplarily, the backplane is provided with high-current connectors to achieve board-to-board connection, and transmit 54V direct current on the backplane to the power supply board of the computing device. After the 54V direct current passes through the DC-DC buck module, 12V is output, and is transmitted to the switching board through the computing device power supply board. The 12V direct current entering the switching board powers the devices on the switching board.

[0141] Optionally, the backplane is internally wired in layers according to functions to separate data lines and power supply lines and avoid interference between lines.

[0142] In this feasible implementation, the integration degree of the computing system is improved through the backplane, thereby effectively improving the computing power density of the computing system.

[0143] A feasible implementation is that the backplane includes multiple high-density connectors. Among them, the high-density connectors are connected through the lines of the backplane; the high-density connectors are connected to the second connector of the computing device and the host.

[0144] Exemplarily, an interconnection channel is implemented through the high-density connector: the channel between the host and the computing device, and the channel between the computing devices. The channel between the host and the computing device can realize data transmission between the host and the computing device, and the channel between the computing devices can realize the collaborative work between the computing devices.

[0145] Exemplarily, the high-density connector adopts a micro-pitch pin structure, which can improve the bandwidth and stability of data transmission.

[0146] Exemplarily, as the core interconnection carrier in a computing system, a backplane has multiple high-density connectors integrally deployed on its surface. These high-density connectors achieve electrical interconnection through multi-layer precision circuits pre-laid inside the backplane, constructing a crisscross signal and power transmission network. Specifically, each high-density connector adopts a micro-pitch pin header structure, enabling the contacts to be densely arranged in a staggered layout within a compact space, and a grounding isolation strip is embedded between the contacts to block electromagnetic crosstalk. High-speed signal lines can be laid inside the backplane to ensure that the impedance of the signal path is maintained within the target threshold range throughout the process. The high-density connectors achieve the two-way connection function through a physical docking mechanism. The high-density connectors are interconnected through cascading wiring embedded in the backplane to form an interconnection channel, allowing a direct path to be established between any two computing devices without passing through the host for transit, forming a distributed device interconnection architecture.

[0147] In this feasible implementation, through unified connection by high-density connectors, the space of the lines can be effectively saved, thereby improving the computing power density of the computing system.

[0148] In a feasible implementation, the computing device further includes a heat dissipation device. The heat dissipation device is connected to the host and is used for dissipating heat from the computing system. The backplane includes multiple holes, and the opening directions of the multiple holes are parallel to the heat dissipation channels of the heat dissipation device; at least part of the heat dissipation channels of the heat dissipation device overlap with the heat dissipation channels of the computing device.

[0149] Exemplarily, as the active heat dissipation core unit, the heat dissipation device establishes a direct electrical connection with the host system and receives the heat dissipation strategy instructions sent by the host temperature monitoring processor in real time. At the same time, the main air duct or liquid cooling pipeline of the heat dissipation device forms a physical coupling path with the backplane opening matrix. The multiple groups of openings precisely arranged on the backplane surface strictly follow the principle of optimizing the aerodynamic cross-section. The axial extension directions of all the openings overlap with the axis of the main heat dissipation channel of the heat dissipation device at least partially, forming a vector-oriented flow field penetrating the interior of the system. After the high-speed air flow or coolant flow of the heat dissipation device passes through the backplane openings, its flow trajectory partially overlaps with the guiding structure of the built-in radiator of the computing device. Specifically, the jet flow at the outlet of the backplane holes directly impacts the air inlet edge area of the computing device radiator, causing the externally forced cooling air flow and the device's self-cooling air flow to form a cooperative vortex on the surface of the computing module.

[0150] Optionally, the heat dissipation device can be a cooling fan or a liquid cooling heat dissipation device.

[0151] In this feasible implementation, by setting the heat dissipation device and at least partially overlapping the heat dissipation channels of the heat dissipation device with the heat dissipation channels of the computing device, the computing system can effectively dissipate heat uniformly, avoiding the conflict of the heat dissipation channels of multiple computing devices and reducing the heat dissipation effect.

[0152] A feasible implementation manner, where the host includes a third controller. The third controller is connected to the first controller of the computing device, and the third controller is configured to determine whether to manage the computing device according to the second level state sent by the first controller.

[0153] Exemplarily, both the second controller and the third controller are configured to manage the computing device. The second controller is configured to manage one of the computing devices separately, and the third controller is configured to manage multiple computing devices uniformly. The second controller and the third controller are respectively adapted to different application scenarios. The current application scenario of the computing device is automatically determined through the second level state, so as to automatically determine the adapted controller to manage the computing device according to the current application scenario of the computing device.

[0154] In this feasible implementation manner, by setting jumper pins and configuring connectors, the first controller can obtain the second level state in real time, so that the third controller determines whether to manage the computing device according to the application scenario of the computing device, so that the management of the computing device adapts to different service scenarios, thereby improving the versatility of the computing device.

[0155] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation manner.

[0156] Figure 12 It is a schematic structural diagram of a connection configuration device for a computing device provided by an embodiment of the present application. As Figure 12 shown, an embodiment of the present application further provides a connection configuration device for a computing device. The connection configuration device 120 of the computing device may include: an acquisition module 121, a determination module 122, a matching module 123, and a connection module 124, where

[0157] The connection configuration device of the computing device is applied to the computing device. The computing device includes at least one switching processor, a first controller, and at least one connection port; for any one connection port.

[0158] The acquisition module 121 is configured to obtain the first level state of the identification pin of the connection port through the first controller and send the first level state to the switching processor.

[0159] The determination module 122 is configured to determine the line connection mode corresponding to the connection port through the switching processor according to the first level state.

[0160] The matching module 123 is configured to match the firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

[0161] Optionally, the obtaining module 121 may execute Figure 2 S201 in the embodiment.

[0162] Optionally, the determining module 122 may execute Figure 2 S202 in the embodiment.

[0163] Optionally, the matching module 123 may execute Figure 2 S203 in the embodiment.

[0164] It should be noted that the connection configuration device of the computing device shown in the embodiments of the present application may execute the technical solutions shown in the above method embodiments, and their implementation principles and beneficial effects are similar, so they will not be elaborated here.

[0165] In a possible implementation manner, the connection port includes a plurality of first connectors; the obtaining module 121 is specifically configured to:

[0166] Determine a plurality of identification pins connected by the plurality of first connectors;

[0167] Obtain the first level states corresponding to the plurality of identification pins.

[0168] The connection module 124 is configured to:

[0169] If the connection port is a dual-functional port, then according to the first level state, the switching processor determines the line connection mode corresponding to the connection port, and the line connection mode is a full-interconnection connection or a non-full-interconnection connection. The dual-functional port is used to connect a network controller or to connect to other switching processors through other dual-functional ports;

[0170] If the connection port is a single-functional port, then according to the first level state, the switching processor determines the line connection mode corresponding to the connection port, and the line connection mode is that the connection port connects to one device or the connection port connects to multiple devices. The single-functional port is used to connect an accelerator or a network controller.

[0171] For the description of the features in the corresponding embodiments of the connection configuration device of the computing device, reference may be made to the relevant descriptions in the corresponding embodiments of the connection configuration method of the computing device, which will not be elaborated here one by one.

[0172] Figure 13 It is a schematic structural diagram of the electronic device provided by the present application. As Figure 13 shown, the electronic device 130 provided in this embodiment includes: at least one processor 1301 and a memory 1302. Optionally, the electronic device 130 further includes a communication component 1303. Among them, the processor 1301, the memory 1302, and the communication component 1303 are connected through a bus.

[0173] In the specific implementation process, at least one processor 1301 executes the computer-executable instructions stored in the memory 1302, so that at least one processor 1301 executes the connection configuration method embodiment of the above computing device.

[0174] For the specific implementation process of the processor 1301, reference can be made to the above method embodiment, and its implementation principle and technical effects are similar, so they will not be elaborated here in this embodiment.

[0175] In the above embodiment, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0176] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0177] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0178] The embodiment of the present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored, and the computer program is set to execute the steps in any one of the connection configuration method embodiments of the above computing device when running.

[0179] In an exemplary embodiment, the above non-volatile computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0180] Embodiments of the present application also provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the connection configuration method for a computing device.

[0181] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the connection configuration method for a computing device.

[0182] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0183] The above has introduced in detail a connection configuration method, a computing device, a system, and a device provided by the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A connection configuration method for a computing device, characterized in that Applied to a computing device, the computing device includes at least one switching processor, a first controller, and at least one connection port; For any one of the connection ports, the method includes: Obtain the first level state of the identification pin of the connection port through the first controller, and send the first level state to the switching processor; According to the first level state, determine the line connection mode corresponding to the connection port through the switching processor; Match the firmware corresponding to the line connection mode through the switching processor, so that the connection port performs data transmission according to the line connection mode.

2. The method according to claim 1, wherein The connection port includes a plurality of first connectors; Obtaining the first level state of the identification pin of the connection port includes: Determine the plurality of identification pins connected by the plurality of first connectors; Obtain the first level state corresponding to the plurality of identification pins.

3. The method according to claim 2, wherein According to the first level state, determining the line connection mode corresponding to the connection port through the switching processor includes: If the connection port is a dual-function port, then according to the first level state, determine the line connection mode corresponding to the connection port through the switching processor, and the line connection mode is a full-interconnection connection or a non-full-interconnection connection. The dual-function port is used to connect a network controller or to connect to other switching processors through other dual-function ports; If the connection port is a single-function port, then according to the first level state, determine the line connection mode corresponding to the connection port through the switching processor, and the line connection mode is that the connection port connects to one device or the connection port connects to multiple devices. The single-function port is used to connect an accelerator or a network controller.

4. A computing device, characterized in that, Applied to the method according to any one of claims 1-3; including: at least one switching board, at least one switching processor, a first controller, and at least one connection port, wherein, The switching processor, the first controller, and the plurality of connection ports are installed on the switching board; The first controller is connected to the plurality of connection ports and the switching processor through the internal line of the switching board. The first controller is used to obtain the first level state of the identification pin of the connection port and send the first level state to the switching processor; The switching processor is used to determine the line connection mode corresponding to the connection port according to the first level state; The switching processor is further used to match the firmware corresponding to the line connection mode, so that the connection port performs data transmission according to the line connection mode.

5. The computing device according to claim 4, wherein The connection port includes a plurality of first connectors; wherein, The plurality of first connectors are connected to a plurality of identification pins, and the identification pins are used to indicate the first level state of the first connectors; The first controller is connected to the plurality of identification pins, and the first controller is used to obtain the first level state corresponding to the plurality of identification pins.

6. The computing device according to claim 5, wherein, The switching processor is used to match the firmware to switch the line connection mode for data transmission. The line connection mode includes at least one of the following: full - interconnection connection between switching processors, non - full - interconnection connection between switching processors, one connection port connecting one device, or one connection port connecting multiple devices. The device is an accelerator or a network controller.

7. The computing device according to claim 6, wherein The computing device further includes at least one circuit board. Among them, The switching processor is connected to a circuit board through multiple first connectors of one connection port. The circuit board is connected to a device to implement one connection port connecting one device. The switching processor is connected to multiple circuit boards through multiple first connectors of one connection port. The circuit board is connected to a device to implement one connection port connecting multiple devices.

8. The computing device according to claim 6, wherein The number of switching boards is multiple. Among them, Multiple switching boards are connected through connection ports to perform inter - board connection of the first connectors corresponding to the multiple switching boards respectively. The number of connection ports for inter - board connection of any one switching board is at least one.

9. The computing device according to claim 8, wherein Any one first connector of any one switching board among the multiple switching boards is connected to multiple first connectors of other switching boards to implement the full - interconnection connection. Any one first connector of any one switching board among the multiple switching boards is connected to one first connector of other switching boards to implement the non - full - interconnection connection.

10. The computing device according to claim 4, wherein The computing device further includes a second controller, a configuration connector, and jumper pins. Among them, The jumper pins are connected to the configuration connector. The jumper pins are used to control the second - level state of the configuration connector. The first controller is connected to the configuration connector and the second controller. The first controller is used to obtain the second - level state and send the second - level state to the second controller. The second controller is used to determine whether to manage the computing device according to the second - level state.

11. The computing device according to claim 4, wherein The computing device further includes a power supply board. Among them, The power supply board is connected to the switching board, the accelerator, and the network controller. The power supply board is used to supply power to the switching board, the accelerator, and the network controller.

12. The computing device according to claim 11, wherein: The power supply board further includes a power supply connector. Among them, The power supply connector is connected to the power supply board and a power source outside the computing device. The power supply connector is used to introduce a power source to supply power to the computing device.

13. A computing system, characterized in that, Including a host, a power source, and the computing device according to any one of claims 4 - 12. Among them, The host is connected to a second connector of the computing device. The host is used to manage the computing system. The power source is connected to the power supply connector of the computing device and the host. The power source is used to supply power to the computing system.

14. The computing system according to claim 13, wherein The computing system further includes a backplane. Among them, The backplane is connected to the second connector and the power supply connector of the computing device. The host is connected to the backplane to connect the host to the computing device. The power supply is connected to the backplane to connect the power supply to the computing device and the host.

15. The computing system according to claim 14, wherein The backplane includes a plurality of high-density connectors, wherein: The high-density connector is connected via the circuit of the backplane; The high-density connector is connected to the second connector of the computing device and the host.

16. The computing system according to claim 15, wherein The computing device further includes a heat dissipation device, wherein: The heat dissipation device is connected to the host, and is used to dissipate heat from the computing system; The back plate includes a plurality of holes, and the opening directions of the plurality of holes are parallel to the heat dissipation channels of the heat dissipation device; The heat dissipation channel of the heat dissipation device at least partially overlaps with the heat dissipation channel of the computing device.

17. The computing system according to claim 13, wherein The host includes a third controller, wherein The third controller is connected to the first controller of the computing device, and the third controller is used to determine whether to manage the computing device according to the second level status sent by the first controller.

18. An electronic device, characterized in that, include: memory for storing computer programs; A processor, configured to implement the steps of the connection configuration method for a computing device according to any one of claims 1 to 3 when executing the computer program.

19. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the connection configuration method of the computing device according to any one of claims 1 to 3 are implemented.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the connection configuration method of the computing device according to any one of claims 1 to 3 are implemented.

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