A dedicated high-frequency low-level control system

Abstract

The application discloses a special high-frequency low-level control system, characterized by comprising a digital signal processing board and a radio frequency front-end board; the digital signal processing board mainly comprises a clock distribution unit, an ADC digital-analog conversion unit, a DAC analog-digital conversion unit, an FPGA and a cavity frequency tuning driving unit; the ADC digital-analog conversion unit is used for converting intermediate frequency collection analog signals output by the radio frequency front-end board into digital intermediate frequency signals and sending the digital intermediate frequency signals into the FPGA; the DAC analog-digital conversion unit is used for converting DDS excitation signals output by the FPGA into intermediate frequency excitation analog signals and sending the intermediate frequency excitation analog signals into the radio frequency front-end board; the radio frequency front-end board performs frequency up-conversion on the intermediate frequency excitation analog signals to obtain RF excitation signals and sends the RF excitation signals into a high-frequency cavity to build a field, and performs frequency down-conversion on cavity field back collection signals to obtain intermediate frequency collection analog signals; the cavity frequency tuning driving unit comprises a motor slow tuning driving and a piezoelectric ceramic fast tuning driving; and the FPGA is used for data collection and loop control.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of accelerators, and particularly relates to a special high-frequency low-level control system, which is used for low-level control of a high-frequency system of a Beijing Electron Positron Collider II (BEPCII) in a second phase and can be widely applied to related projects involving high-frequency signal data acquisition and control. BACKGROUND

[0002] The high-frequency system is crucial in an accelerator device and is a “motor” of the entire accelerator system. A radio frequency electric field is established in a high-frequency resonant cavity, and a particle is moved along a longitudinal orbit, and when the particle passes through the radio frequency electric field, the particle obtains energy and is accelerated in an acceleration phase or is longitudinally bunched.

[0003] The high-frequency system mainly includes a high-frequency cavity, a power source and a low-level control.

[0004] The main functions of the high-frequency low-level control system include cavity field amplitude control and cavity field phase control, high-frequency cavity frequency tuning control, safety interlock protection and the like, so as to guarantee stable operation of the high-frequency system and even the accelerator system.

[0005] No matter for acceleration or bunching, the radio frequency electric field established by the high-frequency system must have good stability, so that the beam can obtain stable radio frequency electric field amplitude and phase when passing through the radio frequency electric field, and high-quality beam is ensured. Thus, the low-level control technology and the corresponding system are developed. Due to factors such as micro-vibration, Lorentz force, unevenness of beam bunch charge, temperature and nonlinearity of the klystron, the high-frequency cavity will be detuned, and a high-frequency system frequency control loop needs to be established to compensate for the detuning of the cavity. Due to changes in beam load and other factors, the amplitude and phase of the radio frequency field in the cavity will change, and a high-frequency system amplitude and phase control loop needs to be established to compensate for the fluctuation of the cavity field amplitude and phase in the cavity, so as to stabilize the amplitude and phase of the cavity field.

[0006] The low-level control technology has experienced three stages: all-analog control, digital plus analog control and all-digital control. The low-level control of high frequency system in the 1960s and 1970s was all-analog control, and the core component was micro-control device. In the 1980s and early 1990s, the mixed analog-digital high frequency low-level controller was developed, and the main reason was the appearance of high-precision and high-stability digital controlled oscillator (NCO). In the 21st century, the all-digital high frequency low-level control system was developed, and the digital signal processor (DSP) and field programmable gate array (FPGA) were widely used.

[0007] The analog low-level control system was used in the high frequency system of Beijing Electron-Positron Collider (BEPC-II) since 2005, which was imported from the High Energy Accelerator Research Organization (KEK) in Japan. The imported equipment has high cost, simple function and backward technology. The digitalization of low-level control system is the trend.

[0008] The low-level control systems based on Micro Advanced Telecom Computing Architecture (MTCA) and Compact Peripheral Component Interconnect (CPCI) are popular in the world. For example, the low-level control system of APS-U in the United States, PETRA-IV in Germany and MAX-IV in Sweden are based on MTCA, and the low-level control systems of the high frequency system of Shanghai Synchrotron Radiation Facility (SSRF) and China Spallation Neutron Source (CNSN) are based on CPCI. The low-level control systems based on MTCA and CPCI use commercial control chassis and bus technology, which can meet the basic requirements of low-level control. However, different projects require different control functions, which requires the low-level system to have flexible expansion function. The commercial board is not convenient to expand, and the cost is relatively high. The development of special digital low-level control system can meet the core requirements of low-level control. SUMMARY

[0009] In view of the development trend of digital low-level control system and the shortcomings of the digital low-level system based on commercial board, the application provides a new special high-frequency low-level control system. The application designs and manufactures a special digital signal processing (DSP) board card based on Altera FPGA, a radio frequency front-end board card and a low-level control case. The design of hardware board circuit principle diagram and the drawing of PCB are completed by using Altium Designer; an input and output control (IOC) application system based on experimental physics and industrial control system (EPICS) is developed, and the control interface of the upper layer is completed based on control system studio (CS-Studio). The cavity field amplitude and phase loop control and cavity frequency loop control are developed based on Quartus II development software.

[0010] The newly developed low-level hardware and control algorithm of the application includes:

[0011] 1) The digital signal processing board card takes FPGA as the core, is externally configured with SRAM, DRAM, EPCS, FLASH and other memories, is configured with high-speed parallel ADC and DAC, serial ADC and DAC, clock distribution chip AD9520 and configuration chip CPLD, optical coupling isolator, analog phase discriminator and the like.

[0012] 2) The radio frequency front-end board card realizes the frequency conversion of RF signal and IF signal. The main devices involved in the radio frequency front-end board card include power divider, amplifier, frequency mixer, filter and voltage stabilizer and the like. The high-frequency system of the high energy photon source (HEPS) project has two RF frequencies of 166.6 MHz and 499.8 MHz. In order to be compatible with the two RF frequencies, the working bandwidth of the radio frequency device can cover the two working frequencies.

[0013] 3) The control algorithm is realized based on the FPGA of the DSP board card, and mainly includes the amplitude and phase feedback loop control of the cavity field and the tuning control of the cavity frequency.

[0014] The technical scheme of the application is:

[0015] The hardware mainly includes digital signal processing board and radio frequency front-end board. The design of circuit schematic and PCB drawing are completed by Altium Designer. The digital signal processing board takes FPGA of Altera as the core chip to complete various digital algorithms and control functions of LLRF. The radio frequency front-end board includes the generation function of LO local oscillator and the up and down conversion function of RF signal. The control software is completed based on EPICS control system, and the control interface of upper layer is completed based on CS-Studio.

[0016] The digital signal processing board mainly includes:

[0017] 1) Clock distribution unit: high-performance clock distribution and synchronization chip AD9520-3 is adopted, the input is RF high-frequency signal, and the multi-output includes ADC and DAC clock, FPGA working clock, IF intermediate frequency reference signal, etc. The frequency of ADC clock and DAC clock is M division of RF frequency, and the frequency of IF intermediate frequency reference signal is N division of RF frequency.

[0018] CPLD chip is equipped to realize the configuration of clock distribution parameters of AD9520 through SPI serial interface.

[0019] 2) High-speed ADC and DAC analog-digital conversion unit: including 3 pieces of ADC chip AD9268-125 and 1 piece of DAC chip AD9788. AD9268-125 is a kind of high-performance analog-digital converter with 16 bits, double channels, maximum sampling rate of 125 MSPS, high SNR and SFDR, which is responsible for converting the IF intermediate frequency collection analog signal output by the radio frequency front-end board into digital intermediate frequency signal, and then sending it into the FPGA of the digital signal processing board for further processing. AD9788 is a kind of high-performance digital-analog converter with 16 bits, double channels and maximum sampling rate of 800 MSPS, which is responsible for converting the DDS excitation digital signal of FPGA into IF intermediate frequency excitation analog signal, and then sending it into the radio frequency front-end board to get low-level RF excitation signal after up-conversion.

[0020] 3) Cavity frequency tuning drive unit: The tuning drive unit includes two parts of motor slow tuning drive and piezo ceramic fast tuning drive. The motor slow tuning drive uses an optocoupler circuit to output the pulse signal, direction signal and enable signal of the FPGA driving motor to the motor driver, and then drive the motor to run to tune the cavity frequency. At the same time, the upper and lower limit switch signals of the motor are transmitted to the FPGA through the optocoupler circuit to realize the mechanical limit of the motor. The optocoupler circuit isolates the external signals of the non-low-level digital signal processing board card to prevent noise from being introduced into the low-level digital signal processing board card. In addition, a low-speed ADC is used to collect the position voltage signal of the motor tuning and send it to the FPGA, and the electrical limit of the motor is realized through the algorithm. The piezo ceramic fast tuning drive uses a slow DAC to convert the piezo drive digital signal generated by the FPGA control algorithm into a piezo drive analog signal, and then sends it to the ceramic driver. The ceramic driver amplifies the piezo drive analog signal and loads it on the piezoelectric ceramic body on the cavity to realize the frequency tuning of the high-frequency cavity.

[0021] 4) FPGA logic processing unit: The FPGA uses the EP3SL150F1152C2 chip of the Stratix III series produced by ALTERA company, and is externally configured with SRAM, DRAM, EPCS, FLASH and other memories. The FPGA is the core of the low-level control system, and the data acquisition, loop control algorithm and data communication functions of the low-level system are realized through the FPGA.

[0022] a) The main RF signals collected by the low-level system include reference signal REF, cavity field back sampling signal Pt, cavity forward power signal Pf, cavity reflected power signal Pr, etc. These signals are down-converted to obtain corresponding IF intermediate frequency sampling analog signals, and then sent to the ADC for data acquisition. The data acquisition function uses Non-IQ algorithm to convert the digital intermediate frequency signal converted by the ADC into I / Q domain orthogonal quantities, and further filters out high-frequency signals through a cascaded integrator-comb filter (CIC) to obtain the final I / Q quantities of the sampling signal.

[0023] b) The loop control algorithm mainly includes the amplitude and phase control loop algorithm of cavity field, the cavity frequency tuning control loop algorithm, etc. The amplitude and phase loop control of cavity field adopts the vector control method in I / Q domain. FPGA collects the cavity field back sampling signal Pt to obtain its quadrature quantities fdb_i and fdb_q, and obtains the quadrature quantities fdb_rot_i and fdb_rot_q of the cavity field back sampling rotated signal after vector rotation. The amplitude and phase set values of cavity field are ref_set_i and ref_set_q. After the difference between ref_set_i and fdb_rot_i is sent to the proportional-integral (PI) controller of the cavity field amplitude and phase loop, the in-phase component output signal pi_out_i of the PI controller is obtained, and after the difference between ref_set_q and fdb_rot_q is sent to the PI controller of the cavity field amplitude and phase loop, the quadrature component output signal pi_out_q of the PI controller is obtained. pi_out_i and pi_out_q are modulated to obtain the DDS excitation output signal of intermediate frequency through the NCO controller in FPGA, the DDS excitation digital signal is converted into IF intermediate frequency excitation analog signal of low level system through DAC digital-to-analog conversion, and then the signal is up-converted to RF high frequency signal through the up-conversion channel of the radio frequency front-end board card, the signal is sent to the subsequent power source as the low-level RF excitation signal for power amplification, and then the signal is sent to the high-frequency cavity for field building through the microwave transmission channel. The cavity frequency tuning control loop algorithm includes two algorithms of motor tuning and piezo tuning.The orthogonal I / Q quantity obtained by the FPGA collecting cavity field back signal Pt is firstly subjected to vector rotation and then cordic algorithm (Coordinate Rotation Digital Computer Algorithm) to obtain cavity field phase cav_pha; the orthogonal I / Q quantity obtained by the FPGA collecting cavity front power signal Pf is firstly subjected to vector rotation module and then cordic algorithm to obtain cavity front phase forw_pha, and the difference between the two is cavity detuning angle detun_angle, and the difference between detun_angle and set detuning angle load_angle is dif_angle; dif_angle is sent to the PI controller of the motor tuning loop, when dif_angle is less than motor start angle start_angle or greater than negative start_angle, the PI controller of the motor tuning loop outputs 0, and the motor is controlled to stop, otherwise the output of the PI controller of the motor tuning loop is not 0, and the motor starts to rotate; when dif_angle is greater than motor stop angle stop_angle or less than negative stop_angle, the PI controller of the motor tuning loop works normally, the motor enable signal is set to high level, the motor drive pulse signal pulse is assigned to the pulse signal of the motor set rate, and according to the positive and negative value of the output of the PI controller of the motor tuning loop and the motor rotation rate, the motor drive pulse signal pulse and the motor rotation direction signal dir are output to the motor driver, and the motor driver drives the motor to run according to the input pulse signal and dir signal. When dif_angle is less than motor stop angle stop_angle and greater than negative stop_angle, the output of the PI controller of the motor tuning loop is reset to 0, the motor enable signal enable and the pulse signal pulse are set to low level, and the rotation of the motor is stopped. dif_angle is also sent to the PI controller of the piezo tuning loop, and the output of the PI controller is filtered to remove high-frequency signals to obtain piezo_out, which is converted into a piezo drive analog signal by a slow-speed DAC and then output to a ceramic driver. The signal is amplified and output to the piezo ceramic of the high-frequency cavity to realize the tuning of the high-frequency cavity.

[0024] c) The data communication function is mainly realized by the embedded Nios-II soft core processor based on the Reduced Instruction Set Computer (RISC) architecture in the FPGA. The Nios-II processor is configured with SRAM, DRAM, EPCS, FLASH and other memories, a three-speed Ethernet module,

[0025] The FPGA's internal register modules use the Avalon bus for interconnected data communication. The Nios-II soft-core algorithm is based on a simple socket server routine. The soft-core system packages read and write data from the low-level system into network packets. Using the NicheStack TCP / IP protocol, the LWIP socket API enables Ethernet data transmission between the soft-core system and the database server.

[0026] Furthermore, the DSP board is equipped with a 2-way reset switch to implement hardware reset of the low-level control system.

[0027] Furthermore, the DSP board is equipped with two trigger interfaces, which can be used as low-level timing trigger inputs or as low-level TTL output ports.

[0028] Furthermore, the DSP board is equipped with 10-way I / O expansion interfaces, providing external interfaces to facilitate low-level function expansion.

[0029] Furthermore, the M and N frequency division coefficients of the clock distribution unit can be flexibly configured according to the requirements of the Non-IQ algorithm.

[0030] Furthermore, low-level control algorithms have also been developed to include maximum power protection, cavity quench protection, feedforward control and other functional algorithms.

[0031] The RF front-end board mainly includes:

[0032] 1) Power division of RF reference signal: After passing through 4 power dividers, 4 RF reference signals are output. The first RF output is sent to the clock distribution unit of the DSP board for clock distribution, which will generate an IF intermediate frequency reference signal and return it to the RF front-end board; the second RF output is mixed with the IF intermediate frequency reference signal output by the clock distribution unit of the DSP board and obtained after bandpass filtering to obtain the LO local oscillator signal; the third RF output is sent to the down-conversion channel for down-conversion and then output to the DSP board for ADC acquisition; the last RF output is output as the RF backup signal to the front panel of the low-level control chassis.

[0033] 2) LO signal generation: the IF intermediate frequency reference signal output by the DSP clock distribution unit is mixed with the low pass filtered RF reference signal. The mixed signal contains RF ± IF frequencies, the signal is first amplified by an amplifier, and then a LO local oscillator frequency band pass filter is obtained, the LO frequency is equal to the RF frequency minus the IF frequency, and then 2 power division is obtained 8 LO frequency signals, two of which are directly output as standby or used for signal monitoring, and the other 6 are amplified to about 7dBm, and are sent to the mixer of the 1 up-conversion and 5 down-conversion channels as LO local oscillator signals.

[0034] 3) 5 down-conversion channels: the RF acquisition signals such as cavity forward power signal Pf, cavity reflected power signal Pr, cavity field back acquisition signal Pt, etc. and LO local oscillator frequency signals are mixed by a mixer and amplified by an amplifier, and then filtered by a low pass filter to obtain the corresponding RF acquisition signal IF intermediate frequency acquisition analog signal, and the output IF intermediate frequency acquisition analog signal is connected to the ADC sampling channel of the DSP board card.

[0035] 4) 1 up-conversion channel: the IF intermediate frequency excitation analog signal output by the DSP board card and the LO local oscillator frequency signal are mixed by a mixer and amplified by an amplifier, and then filtered by a RF frequency band pass filter to obtain a low level RF excitation signal output. The RF output signal is sent to the power source as a low level excitation for power amplification, and then sent to the high frequency cavity for field building.

[0036] Further, each up-conversion and down-conversion channel of the radio frequency front-end board card is configured with a low-noise voltage stabilizing circuit.

[0037] Further, microwave shielding walls are arranged between each channel and between different functional circuits.

[0038] Further, the interface position of the radio frequency front-end board card is designed according to the position of the ADC and DAC channels of the digital signal processing board card.

[0039] Compared with the prior art, the present application has the following advantages:

[0040] 1) The development cost is reduced

[0041] Since it is a self-developed board card, all circuits on the board card are designed according to functional requirements, which is not like many commercial boards that are useless for low-level systems, and the selected chips are designed according to functional requirements, not the more expensive the better, saving costs.

[0042] 2) High functional integration

[0043] According to the functional requirements of low level, the system integrates the algorithm control circuit with FPGA as the core, clock distribution circuit, ADC / DAC analog-digital conversion circuit, motor driving circuit, ceramic piezo driving circuit, analog phase discrimination circuit, etc. For commercial board card, usually multiple board cards are needed to realize the control function of low level, and part of the functions cannot be used by commercial board and still need to develop special function board card, which increases the complexity of the control system.

[0044] 3) Easy function expansion

[0045] The low level control algorithm is mainly realized based on FPGA firmware algorithm, and the algorithm is easy to expand. The ADC / DAC analog-digital conversion circuit is an important part to ensure the control precision of low level, which is located in the periphery of the board card. If there is a better performance ADC / DAC chip, the PCB card can also be slightly modified to complete the upgrade of the board card. In addition, the board card also reserves more than 10 extension I / Os, which is convenient for subsequent function expansion of the board card. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 The hardware architecture diagram of the low level control system is shown in

[0047] Figure 2 The principle diagram of the digital signal processing board card is shown in

[0048] Figure 3 The principle diagram of the radio frequency front-end board card is shown in

[0049] Figure 4 The principle diagram of the cavity field amplitude and phase feedback loop control algorithm is shown in

[0050] Figure 5 The principle diagram of the cavity frequency tuning loop control algorithm is shown in

[0051] Figure 6 The software architecture diagram of the low level control system is shown in

[0052] Figure 7 The overall framework diagram of the high frequency system is shown in DETAILED DESCRIPTION

[0053] The application will be further described in detail below with reference to the accompanying drawings, and the examples are only used to explain the application, and not to limit the scope of the application.

[0054] 1. Top-level design

[0055] The composition framework diagram of the low level control system is shown in Figure 1As shown, the system mainly includes digital signal processing board, radio frequency front-end board, low-level chassis, etc. The digital signal processing board completes the conversion of analog and digital signals, the collection of digital signals and the control algorithm function, clock distribution function, etc. The radio frequency front-end board completes the up-conversion of IF signals and the down-conversion of RF signals. The low-level control chassis provides the board power supply, the interface with external devices, etc.

[0056] 2. Hardware design

[0057] The Altium designer is used for the design of the circuit schematic and the drawing of the PCB.

[0058] The hardware design of the DSP board is as follows:

[0059] The principle diagram of the digital signal processing board is as shown in the figure. The FPGA chip is selected from the EP3SL150F1152C2 chip of the Stratix III series produced by the ALTERA company, and its main performance parameters are shown in Table 1. The ALM and LE reach 56.8k and 142.5k respectively, and the pin I / O has 744, which is sufficient for the logic unit and the pin number for the LLRF low-level system, and meets the design requirements. Figure 2

[0060] Table 1 Main performance parameters of EP3SL150F1152C2

[0061]

[0062] According to the functional requirements, in order to realize the data communication function, the Nios-II soft core of the ALTERA FPGA embedded processor is used, and the SRAM, DRAM, EPCS, FLASH and other memories are configured in the periphery of the FPGA; in order to meet the high-precision control and high-speed data acquisition, the high-speed parallel ADC and DAC are configured; in addition, in order to collect the motor position signal, the serial ADC is configured, and in order to realize the driving control of the piezo ceramic, the slow serial DAC is configured; in order to provide the clock of the digital signal processing board and the clock of the ADC and DAC chips, the clock distribution chip AD9520 and the parameter configuration control chip CPLD are configured; the optocoupler isolator is configured between the motor driving circuit and the low-level control circuit to prevent the noise interference of the motor driving end from affecting the low-level control circuit; the analog phase discriminator is configured to realize the phase recovery function under the power-off condition of the low-level system. Through the integration of these hardware circuits, the low-level multi-functional hardware requirements can be met.

[0063] ​According to the chip selection and functional requirements to carry out the schematic design, and complete the PCB drawing, because the digital signal processing board card involves complex circuit, signal quantity, PCB design adopts 16 layers design, to ensure the integrity of the signal and good EMC electromagnetic shielding performance.

[0064] RF front-end board card hardware design:

[0065] High frequency RF acquisition signal includes reference signal REF, cavity forward power signal Pf, cavity reflected power signal Pr, cavity field back sampling signal Pt, beam signal Pb, etc., high frequency RF output signal is power source RF excitation signal. Therefore, the RF front-end board card includes 5 down-conversion channels and 1 up-conversion channel, which realizes 5 RF acquisition signal down-conversion to IF intermediate frequency acquisition analog signal, and 1 IF intermediate frequency excitation analog signal up-conversion to RF excitation signal. The main devices involved in the RF front-end board card include power divider, amplifier, mixer, filter and voltage stabilizer, etc. HEPS project includes 166.6MHz and 499.8MHz two RF frequencies, the selection of these RF devices first considers that the working bandwidth of the RF device needs to cover the two working frequencies. Secondly, according to the other main characteristics of each RF device, the schematic diagram is finally designed, and the PCB printed board is drawn. The PCB board drawing mainly considers the isolation between channels, and cooperates with the digital signal processing board card to complete the layout design of the channels. The schematic diagram of the RF front-end board card is shown in Figure 3 .

[0066] 3. Development of control algorithm

[0067] The main algorithm of the low-level control system includes cavity field amplitude and phase feedback loop control and cavity frequency tuning loop control.

[0068] a) Cavity field amplitude and phase feedback loop control:

[0069] The schematic diagram of the cavity field amplitude and phase feedback loop control algorithm is shown in Figure 4 .

[0070] ● Acquisition of two-way RF high frequency signal: the reference signal REF and the cavity field back sampling signal Pt are first down-converted to obtain their IF intermediate frequency sampling signals, and then sent to the high-speed ADC for analog-digital conversion. The digital signal obtained in the FPGA uses Non-IQ algorithm to obtain the orthogonal I / Q quantities of the reference signal and the cavity field back sampling signal.

[0071] ● Amplitude and phase acquisition: the orthogonal I / Q quantities of the reference signal and the cavity field back sampling signal can obtain the amplitude and phase of the corresponding signal through Cordic algorithm.

[0072] • PI feedback control: the quadrature I / Q quantity of the reference signal is first normalized, the I / Q setting quantity obtained by setting the reference amplitude and phase is used to vector rotate the normalized quadrature I / Q quantity of the reference signal to obtain the I / Q setting value ref_set_i / ref_set_q of the reference signal; the I / Q adjustment quantity obtained by adjusting the amplitude and phase is used to vector rotate the I / Q quadrature quantity of the cavity field back sampling signal to obtain the adjusted I / Q quantity fdb_rot_i / fdb_rot_q of the back sampling signal. The difference del_i between ref_set_i and fdb_rot_i is input into a PI controller to obtain the in-phase component output signal pi_out_i; the difference del_q between ref_set_q and fdb_rot_q is input into a PI controller to obtain the quadrature component output signal pi_out_q; pi_out_i and pi_out_q are input into a DDS to obtain the intermediate frequency excitation digital signal, and then the intermediate frequency excitation analog signal can be obtained through a DAC digital-to-analog converter. The intermediate frequency excitation analog signal is converted to an RF excitation signal through frequency up-conversion, and then the RF excitation signal is input into a high-frequency cavity through a radio frequency switch, a power source, and a circulator to build a field, thereby completing the entire loop feedback control.

[0073] b) Cavity frequency tuning loop control:

[0074] The principle diagram of the cavity frequency tuning loop control algorithm is shown in Figure 5 The cavity frequency tuning loop control includes motor tuning feedback control and piezo tuning feedback control.

[0075] • Acquisition of two-way rf high-frequency signals: the forward power signal Pf and the cavity field back sampling signal Pt are first converted to IF intermediate frequency signals through frequency down-conversion, and then input into a high-speed ADC for analog-to-digital conversion. The obtained digital signals are used to obtain the quadrature I / Q quantity of the forward power signal and the cavity field back sampling signal through Non-IQ algorithm in the FPGA.

[0076] • Acquisition of cavity detuning angle: the I / Q adjustment quantity obtained by adjusting the amplitude and phase of the forward power signal is used to vector rotate the quadrature I / Q quantity of the forward power signal to obtain the adjusted I / Q quantity forw_rot_i / forw_rot_q of the forward power signal, and the phase forw_angle of the forward power signal at the cavity port is obtained after cordic algorithm; the I / Q adjustment quantity obtained by adjusting the amplitude and phase of the cavity field back sampling signal is used to vector rotate the quadrature I / Q quantity of the cavity field back sampling signal to obtain the adjusted I / Q quantity cav_rot_i / cav_rot_q of the cavity field back sampling signal, and the phase cav_angle of the cavity field back sampling signal is obtained after cordic algorithm; the cavity detuning angle detun_angle is obtained by subtracting forw_angle from cav_angle.

[0077] Piezo tuning loop: 1. Set the difference between the detuning angle load_angle and the cavity detuning angle detun_angle as dif_angle, and send dif_angle to the PI controller of the piezo tuning loop, and the output is low-pass filtered to obtain the piezo drive digital signal; 2. The piezo drive digital signal is converted into a piezo drive analog signal by a slow DAC; 3. The piezo drive analog signal is amplified by a piezo ceramic driver to obtain a piezo tuning high-voltage signal; 4. The piezo tuning high-voltage signal is sent to the piezoelectric ceramic on the cavity side to realize frequency adjustment of the high-frequency cavity.

[0078] Motor tuning loop: Set the difference between the detuning angle load_angle and the cavity detuning angle detun_angle as dif_angle, when the absolute value of dif_angle is greater than the motor start angle start_angle, dif_angle is sent to the PI controller, the output of the PI controller is not 0, and the motor pulse signal and the direction signal are output to the motor driver to drive the motor to run and drive the cavity side tuning arm to adjust the frequency of the cavity. When the absolute value of dif_angle is less than the motor stop angle stop_angle, it means that the cavity frequency adjustment is in place, the PI controller is reset, so that the output of the PI controller is 0, and then the pulse signal is stopped to the motor, and the motor stops running, completing the tuning of the cavity frequency.

[0079] 4. Software development

[0080] The software architecture diagram of the low-level control system is shown in Figure 6 The software system is based on the EPICS control system to develop the Input / Output Controller (IOC) application. The record of the IOC supports RecordSupport to access the Linux kernel through the low-level device driver, and the linux kernel obtains the socket data packet through the network driver; the low-level device driver mainly completes the read-write function of the socket data packet based on the TCP / IP protocol, realizes the access of the IOC database application layer to the linux kernel, and thus realizes the data interaction with the digital signal processing board card, realizes the read-write of the FPGA internal register, and then realizes the algorithm control of the low level. The database of the IOC publishes the Process Variable (PV) on the network through channel access (CA). The upper control interface of the client OPI is realized based on CS-Studio to monitor and control the PV.

[0081] 4. System integration and debugging

[0082] After the digital signal processing board and the radio frequency front-end board are manufactured and the chips are soldered, a low-level cabinet needs to be designed and integrated into a complete low-level control system. The front panel of the cabinet mainly includes a power switch, LED status lights, a radio frequency signal input interface, a radio frequency signal excitation output interface, a ceramic excitation output interface, etc., and the back panel mainly includes motor-driven input and output interfaces, a reset switch, a trigger interface, a network interface, and a 220V power input, etc.

[0083] The overall integration and debugging of the high-frequency system is as shown in Figure 7 The reference line provides a low-level RF reference signal, the low-level control system collects cavity field return signals Pt, cavity forward power signals Pf and cavity reflected power signals Pr; the low-level RF excitation output signal is sent to the power source through the RF switch, the power source amplifies the RF excitation signal and then sends it to the high-frequency cavity through the circulator to build the field; the low-level system simultaneously tunes the frequency of the high-frequency cavity through the tuning driver, including the motor driver and the piezo ceramic driver, to realize frequency control. The low-level system performs network data interaction with the client OPI and the database server through the network.

[0084] Although specific embodiments of the present application are disclosed herein for illustrative purposes, and to aid in the understanding of the present application, it will be understood by those skilled in the art that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed best mode, and the scope of the present application is defined by the scope of the claims.

Claims

1. A special high-frequency low-level control system, characterized in that: It includes a digital signal processing board and a radio frequency front-end board; the digital signal processing board mainly includes a clock distribution unit, an ADC digital-to-analog conversion unit, a DAC analog-to-digital conversion unit, an FPGA logic processing unit, and a cavity frequency tuning drive unit; The clock distribution unit is used to generate an ADC clock signal, a DAC clock signal, an FPGA working clock, and an IF intermediate frequency reference signal according to the input RF signal, and send them to the ADC digital-to-analog conversion unit, the DAC analog-to-digital conversion unit, the FPGA logic processing unit, and the RF front-end board respectively; The clock distribution unit mainly includes a clock distribution chip and a CPLD chip, and the CPLD chip is used to configure clock distribution parameters for the clock distribution chip; The ADC digital-to-analog conversion unit is used to convert the intermediate frequency acquisition analog signal output by the RF front-end board into a digital intermediate frequency signal and send it to the FPGA logic processing unit; The DAC analog-to-digital conversion unit is used to convert the DDS excitation signal output by the FPGA logic processing unit into an intermediate frequency excitation analog signal and send it to the RF front-end board; The RF front-end board is used to up-convert the intermediate frequency excitation analog signal to obtain a low-level RF excitation signal, amplify the power of the signal, and then send it to the high-frequency cavity for field building, and attenuate the cavity field recovery signal and send it to the down-conversion channel for down-conversion to obtain the intermediate frequency acquisition analog signal and input it into the ADC digital-to-analog conversion unit; The cavity frequency tuning drive unit includes a motor slow tuning drive and a piezo ceramic fast tuning drive; The motor slow tuning driver drives the motor to operate according to the control signal of the FPGA logic processing unit to tune the frequency of the high-frequency cavity, and collects the position voltage signal of the motor tuning and sends it to the FPGA logic processing unit to control the electric limit of the motor; the piezo ceramic fast tuning driver converts the digital signal of the FPGA logic processing unit driving the high-frequency cavity piezo ceramic into an analog signal and sends it to the ceramic driver to tune the frequency of the high-frequency cavity; The FPGA logic processing unit is used for data acquisition and loop control; wherein, a) during data acquisition, converting the digital intermediate frequency signal into an orthogonal quantity in the I / Q domain and filtering out the high-frequency signal therein to obtain an orthogonal I / Q quantity of the sampling signal; the sampling signal includes an RF reference signal, a cavity field recovery signal, a cavity reflection power signal, and a cavity forward power signal; b) The loop control includes cavity field amplitude and phase loop control and cavity frequency tuning loop control; wherein, the cavity field amplitude and phase loop control adopts the I / Q domain vector control method to rotate the I component of the cavity field recovery signal to obtain fdb_rot_i, and rotate the Q component of the cavity field recovery signal to obtain fdb_rot_q; the cavity field amplitude and phase setting value ref_set_i of the I component is subtracted from fdb_rot_i and then sent to the PI controller of the cavity field amplitude and phase loop to obtain the in-phase component output signal pi_out_i, and the cavity field amplitude and phase setting value ref_set_q of the Q component is subtracted from fdb_rot_q and then sent to the PI controller to obtain the orthogonal component output signal pi_out_q; pi_out_i and pi_out_q are modulated by the NCO controller inside the FPGA logic processing unit to obtain the intermediate frequency DDS excitation signal; The cavity frequency tuning loop control includes a motor tuning loop and a piezo tuning loop; the motor tuning loop obtains the forward phase forw_pha and the cavity field phase cav_pha of the cavity according to the orthogonal I / Q quantities of the cavity forward power signal and the cavity recovery signal, and calculates the difference between forw_pha and cav_pha to obtain the cavity detuning angle detun_angle, and subtracts the cavity detuning angle detun_angle from the set detuning angle load_angle to obtain the phase difference dif_angle; dif_angle is sent to the PI controller of the motor tuning loop, and when dif_angle is less than the motor starting angle start_angle or greater than the negative start_angle, the PI controller output of the motor tuning loop is 0, and the motor is controlled to stop rotating; otherwise, the PI controller output of the motor tuning loop is not 0, and the motor is controlled to start rotating; when dif_angle is less than the motor starting angle start_angle or greater than the negative start_angle, the PI controller output of the motor tuning loop is 0, and the motor is controlled to stop rotating; otherwise, the PI controller output of the motor tuning loop is not 0, and the motor is controlled to start rotating; when dif_angle is less than the motor starting angle start_angle or greater than the negative start_angle, the PI controller output of the motor tuning loop is 0, and the motor is controlled to stop rotating. When f_angle is greater than the motor stop angle stop_angle or less than the negative stop_angle, the PI controller of the motor tuning loop works normally, and generates a motor drive pulse signal pulse and a motor rotation direction signal dir according to the positive and negative values ​​of the PI controller output of the motor tuning loop and sends them to the motor driver, driving the motor to operate and adjust the frequency of the high-frequency cavity; when dif_angle is less than the motor stop angle stop_angle and greater than the negative stop_angle, the PI controller output of the motor tuning loop is reset to stop the rotation of the motor; and dif_angle is sent to the PI controller of the piezo tuning loop to generate a driving digital signal for the piezo ceramic and convert it into a piezo driving analog signal and send it to the ceramic driver to amplify and obtain a piezo tuning high-voltage signal to act on the piezo ceramic on the high-frequency cavity, thereby realizing frequency tuning of the high-frequency cavity.

2. The dedicated high-frequency low-level control system according to claim 1, characterized in that: The RF front-end board divides the input RF reference signal into four RF signals through a 4-way power divider, one of which is mixed with the IF intermediate frequency reference signal output by the clock distribution unit to obtain an LO local oscillator signal, one of which is input into the clock distribution unit for clock distribution, one of which is sent to the down-conversion channel as a reference signal for down-conversion, and one of which is used as a backup.

3. The dedicated high-frequency low-level control system according to claim 1, characterized in that: The RF front-end board mixes the IF reference signal output by the clock distribution unit with the input RF reference signal after low-pass filtering; then the mixed signal is amplified by an amplifier and then passed through a band-pass filter of the LO local oscillator frequency to obtain an LO local oscillator signal and is divided into 8 LO signals, two of which are directly output for standby or monitoring, and the other 6 are amplified as LO local oscillator signals and respectively sent to a mixer including 1 up-conversion channel and 5 down-conversion channels; the down-conversion channel is used to mix the collected RF signal and LO signal through the mixer and amplify the amplifier, and then filter through a low-pass filter to obtain an intermediate frequency collection analog signal and input it into the ADC digital-to-analog conversion unit; the up-conversion channel mixes the intermediate frequency excitation analog signal and LO signal through the mixer and amplifies the amplifier, and then passes through a band-pass filter of the RF frequency to obtain a low-level RF excitation signal, which is power-amplified and sent to the high-frequency cavity for field building.

4. The dedicated high-frequency low-level control system according to claim 3, characterized in that: The collected RF signals include the reference signal REF, the cavity field recovery signal Pt, the cavity forward power signal Pf, the cavity reflected power signal Pr, and the beam signal Pb.

5. The dedicated high-frequency low-level control system according to claim 3, characterized in that: Each up- and down-conversion channel of the radio frequency front-end card is respectively equipped with a low-noise voltage stabilizing circuit.

6. The dedicated high-frequency low-level control system according to claim 1, 2 or 3, characterized in that: A Non-IQ algorithm is used to convert the digital intermediate frequency signal into an orthogonal quantity in the I / Q domain.

7. The dedicated high-frequency low-level control system according to claim 1, 2 or 3, characterized in that: The motor tuning loop rotates the orthogonal I / Q quantities of the cavity forward power signal and the cavity field recovery signal through a vector rotation module and then obtains the cavity forward phase forw_pha and the cavity field phase cav_pha respectively through a cordic algorithm.

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