FPGA-based one-dimensional radar radiation source identification method and system

Abstract

The invention discloses a one-dimensional radar radiation source identification method based on an FPGA. The method comprises the following steps: constructing a radar radiation source signal data set; converting a radar signal in the radar radiation source signal data set from a time domain to a time-frequency domain to obtain a two-dimensional signal; inputting the two-dimensional signal into a preset deep neural network for pre-training to obtain a pre-training model; optimizing the pre-training model by adopting a preset optimization strategy to obtain a radar radiation source identification model; and deploying and operating the radar radiation source identification model through a preset FPGA platform, and then receiving a radar radiation source signal in real time through the FPGA platform and identifying the radar radiation source signal to obtain an identification result. According to the invention, efficient and accurate radar radiation source signal identification is realized.

Description

Technical Field

[0001] The present invention relates to the field of radar emitter signal recognition. Specifically, it relates to a one-dimensional radar emitter recognition method and system based on FPGA Background Art

[0002] Electronic reconnaissance is an important part of electronic countermeasures, and radar emitter recognition is one of the most important links in electronic reconnaissance, which plays an important supporting role in threat warning, interference decision-making, etc.

[0003] Early radar emitter recognition methods mainly relied on template matching or expert systems, and the systems were relatively simple. With the increasing complexity of the electromagnetic environment, traditional radar emitter methods gradually could not meet the needs. At this time, with the development of machine learning, various artificial intelligence methods were introduced into this field, mainly including three aspects: feature selection, feature extraction, and classifier design. Among them, the selection and extraction of features were generally carried out manually. In recent years, the rise of the deep learning branch has led to remarkable developments in computer vision and natural language processing, and the trend still continues. Due to its strong generalization ability and performance no less than that of humans in computer vision, it has been introduced into the field of radar emitter recognition, further improving the recognition accuracy. Since deep learning has strong feature extraction capabilities, it can directly complete the output from the signal to the result without manual extraction of parameters. However, sometimes it may not be able to extract the features we expect, so manual extraction of parameters is still a feasible solution.

[0004] Degree. Because deep learning has strong feature extraction capabilities, it can directly complete the output from the signal to the result without manual extraction of parameters. However, sometimes it may not be able to extract the features we expect, so manual extraction of parameters is still a feasible solution.

[0005] Patent "CN107220606A" conducts emitter recognition based on one-dimensional convolutional neural network recognition. The network mainly extracts the features of the input signal through one-dimensional convolution, and the structure is relatively simple. Patent

[0006] "CN112115924A" conducts radar emitter recognition based on one-dimensional CNN and LSTM. In view of the low one-dimensional processing accuracy, the CNN network is used to extract local features, and the LSTM network is used to extract global features, which improves the recognition accuracy while ensuring low computational complexity. Patent "CN110147812A" conducts radar emitter recognition based on dilated residual network. Different from the above two methods that directly use the network for feature extraction, this method first selects time-frequency analysis for manual feature extraction, converts the signal into a two-dimensional time-frequency image and performs preprocessing, and then conducts emitter recognition through the dilated residual network. The time-frequency map extracted by this method can effectively reflect the features of the signal and improve the recognition accuracy. However, the computational complexity of time-frequency analysis is high, and the real-time performance of the method is poor.

[0007] With the development and application of deep learning, there is currently a situation of a hundred schools of thought contending in the design framework and deployment framework of neural networks. Due to the characteristics of neural networks, GPUs and FPGAs stand out due to their parallel computing capabilities and become the two main platforms for deploying neural network edge devices. Since it is very convenient to deploy networks through Nvidia's cuda library, GPUs are currently the main platforms for deploying neural networks. FPGAs still have not been eliminated due to their low power consumption and computing speed comparable to that of GPUs. Their biggest weakness lies in the lack of a general method to implement network deployment. Customized network deployment makes the development cycle long, so there is little research on the deployment of radar emitter recognition models. Summary of the Invention

[0008] To solve the technical problems of low accuracy and poor real-time performance in one-dimensional signal recognition in existing radar emitter recognition, the present invention provides a method and system for one-dimensional radar emitter recognition based on FPGA. The technical solution adopted by the present invention is:

[0009] The first aspect of the present invention provides a method for one-dimensional radar emitter recognition based on FPGA, the method comprising:

[0010] Construct a radar emitter signal data set;

[0011] Convert the radar signals in the radar emitter signal data set from the time domain to the time-frequency domain to obtain two-dimensional signals;

[0012] Input the two-dimensional signals into a preset deep neural network for pre-training to obtain a pre-trained model;

[0013] Optimize the pre-trained model using a preset optimization strategy to obtain a radar emitter recognition model;

[0014] Deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive radar emitter signals in real time through the FPGA platform and perform recognition to obtain recognition results.

[0015] As a preferred solution, the method for constructing a radar emitter signal data set includes:

[0016] Generate a radar emitter signal data set through MATLAB simulation. The radar emitter signal data set includes signals with twelve different modulation methods, and equal numbers of samples are generated for each signal at signal-to-noise ratios from -10 dB to 8 dB at intervals of 2 dB.

[0017] As a preferred solution, convert the radar signals in the radar emitter signal data set from the time domain to the time-frequency domain to obtain two-dimensional signals:

[0018] Sample the radar signal according to a preset data processing clock to obtain AD data;

[0019] Perform windowing processing on the AD data through a preset window function;

[0020] In the FPGA, perform time-frequency analysis on the AD data through STFT calculation. The specific formula is:

[0021]

[0022] where x(n) is the input sequence, ω(n) is the window function, and R is the step value.

[0023] As a preferred solution, the preset optimization strategy includes:

[0024] Parameter quantization processing and parameter fusion processing.

[0025] As a preferred solution, the method of the parameter quantization processing includes:

[0026] According to the characteristics of the FPGA, that is, the quantization bit width of the ADC is 16 bits, so the weight value is quantized to 8 bits and the bias value is quantized to 16 bits;

[0027] Assume that r represents a floating-point real number and q represents the quantized fixed-point integer. Then the conversion formula is as follows:

[0028] r = S(q - Z)

[0029]

[0030] where S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. The calculation method is:

[0031]

[0032] As a preferred solution, the method of the parameter fusion processing includes:

[0033] Fuse the convolutional layer and the BN layer;

[0034] For the operation of the convolutional layer:

[0035] y conv = ωx + b

[0036] where ω is the weight, x is the input matrix, b is the bias, and y is the output matrix;

[0037] For the operation of the BN layer:

[0038]

[0039]

[0040] where μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer;

[0041] According to the characteristics of the operation, there is:

[0042]

[0043] where is the fused weight, is the fused bias.

[0044] As a preferred solution, the method for deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving and identifying the radar emitter signal in real time through the FPGA platform to obtain the recognition result includes:

[0045] Sampling the radar emitter signal according to a preset data processing clock to obtain real-time AD data;

[0046] Windowing the real-time AD data through a preset window function;

[0047] Performing time-frequency analysis on the real-time AD data through STFT calculation in the FPGA to obtain a real-time two-dimensional signal;

[0048] Performing three convolution operations on the real-time two-dimensional signal through a preset Shallow Block module, then passing through the BN layer, and finally fusing the data and passing through the ReLu activation layer for output;

[0049] Next, further extracting temporal features from the fused data through a two-layer gated recurrent unit;

[0050] Finally, further refining and extracting the features of the data through a deep module composed of fully connected layers;

[0051] Finally, passing the data through a linear layer to obtain the classification result.

[0052] As a preferred solution, the method for further extracting temporal features from the fused data through a two-layer gated recurrent unit includes:

[0053] First, the input fusion data and hidden state are loaded through the cache module, and after passing through the reset gate and update gate together, the calculation result is obtained, and the output result of the update gate is cached in the register;

[0054] The reset gate operates on the hidden state of the previous step and passes through the candidate hidden state gate together with the current input to obtain the candidate hidden state;

[0055] The cached update gate and result, the hidden state of the previous step, and the candidate hidden state are calculated in parallel to obtain the hidden state of the current step.

[0056] As a preferred solution, the calculation formulas for the reset gate and update gate are:

[0057] R t = σ(X t W xr + H t-1 W hr + b r )

[0058] Z t = σ(X t W xr + H t-1 W hz + b z )

[0059] where X t ∈ R nxd is the input vector, n is the number of samples, d is the dimension of the input vector, and t is the time step; H t-1 ∈ R nxh is the hidden state, R t ∈ R nxh is the reset gate and Z t ∈ R nxh is the update gate;

[0060] W xr ,W xz ∈ R dxh ,W hr ,W hz ∈ R hxh are the weight parameters, b r ,b z ∈ R 1xh are the bias parameters;

[0061] The calculation formula for the hidden state is:

[0062]

[0063] where is the candidate hidden state W xh ∈ R dxh ,Whh ∈Rh xh and are weight parameters, b h ∈R 1xh is the bias term, and the ⊙ symbol is the Hadamard product (element-wise product) operator; the tanh non-linear activation function is used to ensure that the values in the candidate hidden state remain in the interval (-1, 1);

[0064] The final update formula of the gated recurrent unit is:

[0065]

[0066] The second aspect of the present invention provides a one-dimensional radar emitter recognition system based on FPGA, and the system includes a data set construction module, a time-frequency analysis module, a training module, an optimization module, and a signal real-time recognition module;

[0067] The data set construction module is used to construct a radar emitter signal data set;

[0068] The time-frequency analysis module is used to convert the radar signals in the radar emitter signal data set from the time domain to the time-frequency domain to obtain two-dimensional signals;

[0069] The training module is used to input the two-dimensional signals into a preset deep neural network for pre-training to obtain a pre-trained model;

[0070] The optimization module is used to optimize the pre-trained model by using a preset optimization strategy to obtain a radar emitter recognition model;

[0071] The signal real-time recognition module is used to deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive radar emitter signals in real time through the FPGA platform and perform recognition to obtain recognition results. [[ID=XXX]] [[ID=XXX]]

[0072] Compared with the prior art, the beneficial effects of the present invention are:

[0073] The present invention designs a recognition method based on a recurrent convolutional network, effectively extracts the timing features of signals to improve the recognition probability, and improves the real-time performance of time-frequency analysis and network inference through the FPGA platform. Description of the Drawings

[0074] Figure 1 is a flowchart of a one-dimensional radar emitter recognition method provided in this embodiment;

[0075] Figure 2 is a structural diagram of a radar emitter recognition network provided in this embodiment;

[0076] Figure 3Schematic diagram of one-dimensional pipeline linear operation provided by this embodiment;

[0077] Figure 4 Schematic diagram of the operation of conventional convolution provided by this embodiment;

[0078] Figure 5 Schematic diagram of the operation of depthwise separable convolution provided by this embodiment;

[0079] Figure 6 Schematic diagram of the operation of single-channel depth convolution provided by this embodiment;

[0080] Figure 7 Schematic diagram of the operation of point convolution provided by this embodiment;

[0081] Figure 8 Schematic diagram of the operation of the linear layer provided by this embodiment;

[0082] Figure 9 Schematic diagram of the calculation of the gated recurrent unit model provided by this embodiment;

[0083] Figure 10 Schematic diagram of GRU deployment provided by this embodiment;

[0084] Figure 11 Schematic diagram of the deployment of the FPGA model provided by this embodiment. Detailed implementation manners

[0085] The accompanying drawings are only for illustrative purposes and should not be construed as limiting the present invention;

[0086] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope protected by the embodiments of the present application.

[0087] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The singular forms of "a", "the" and "this" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0088] When the following description refers to the accompanying drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects and do not have to be used to describe a specific order or sequence, nor can they be construed as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0089] In addition, in the description of the present application, unless otherwise specified, "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0090] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0091] Embodiment 1

[0092] Please refer to Figure 1 , this embodiment provides a one-dimensional radar emitter recognition method based on FPGA, and the method includes:

[0093] S1: Construct a radar emitter signal data set;

[0094] In a specific embodiment, the method for constructing a radar emitter signal data set includes:

[0095] Generate a radar emitter signal data set through MATLAB simulation. The radar emitter signal data set includes signals of twelve different modulation methods, and an equal number of samples are generated for each signal at a signal-to-noise ratio interval of 2 dB from -10 dB to 8 dB.

[0096] In a specific embodiment, the signals of the twelve different modulation methods include:

[0097] cw, lfm, nlfm, bpsk, bfsk, qpsk, qfsk, p1, p2, p3, p4, msk.

[0098] S2: Convert the radar signals in the radar emitter signal data set from the time domain to the time-frequency domain to obtain two-dimensional signals;

[0099] In a specific embodiment, the radar signals in the radar radiation source signal dataset are converted from the time domain to the time-frequency domain to obtain two-dimensional signals:

[0100] Sample the radar signals according to a preset data processing clock to obtain AD data;

[0101] Perform windowing processing on the AD data through a preset window function;

[0102] In the FPGA, perform time-frequency analysis on the AD data through STFT calculation. The specific formula is:

[0103]

[0104] where x(n) is the input sequence, ω(n) is the window function, and R is the step value.

[0105] S3: Input the two-dimensional signal into a preset deep neural network for pre-training to obtain a pre-trained model;

[0106] S4: Optimize the pre-trained model using a preset optimization strategy to obtain a radar radiation source recognition model;

[0107] In a specific embodiment, the preset optimization strategy includes:

[0108] Parameter quantization processing and parameter fusion processing.

[0109] In a specific embodiment, the method of parameter quantization processing includes:

[0110] According to the characteristics of the FPGA, that is, the quantization bit width of the ADC is 16 bits, so the weight value is quantized to 8 bits and the bias value is quantized to 16 bits;

[0111] Assume that r represents a floating-point real number and q represents a quantized fixed-point integer. Then the conversion formula is as follows:

[0112] r = S(q - Z)

[0113]

[0114] where S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. The calculation method is:

[0115]

[0116] In a specific embodiment, the method of parameter fusion processing includes:

[0117] Fuse the convolutional layer and the BN layer;

[0118] For the convolution layer operation, we have:

[0119] y conv = ωx + b

[0120] where ω is the weight, x is the input matrix, b is the bias, and y is the output matrix;

[0121] For the operation of the BN layer, we have:

[0122]

[0123]

[0124] where μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer;

[0125] According to the characteristics of the operation, we have:

[0126]

[0127] where is the fused weight, is the fused bias.

[0128] S5: Deploy and run the radar emitter recognition model through a preset FPGA platform, then receive the radar emitter signal in real time through the FPGA platform and perform recognition to obtain the recognition result;

[0129] In a specific embodiment, the method of deploying and running the radar emitter recognition model through a preset FPGA platform, then receiving the radar emitter signal in real time through the FPGA platform and performing recognition to obtain the recognition result includes:

[0130] Sample the radar emitter signal according to a preset data processing clock to obtain real-time AD data;

[0131] Perform windowing processing on the real-time AD data through a preset window function;

[0132] In the FPGA, perform time-frequency analysis on the real-time AD data through STFT calculation to obtain a real-time two-dimensional signal;

[0133] Perform three convolution operations on the real-time two-dimensional signal through a preset Shallow Block module, then pass through the BN layer, and finally output the data after fusion through the ReLu activation layer;

[0134] Next, the gated recurrent unit with two layers is used to further extract the temporal features from the fused data;

[0135] Finally, the data is further refined and extracted through a deep module composed of fully connected layers;

[0136] Finally, the data passes through a linear layer to obtain the classification result.

[0137] In a specific embodiment, the method for further extracting the temporal features from the fused data through the gated recurrent unit with two layers includes:

[0138] First, the input fused data and the hidden state are loaded through a cache module, and after passing through the reset gate and the update gate together, the calculation result is obtained, and the output result of the update gate is cached in a register;

[0139] The reset gate operates on the previous hidden state and then passes through the candidate hidden state gate together with the current input to obtain the candidate hidden state;

[0140] The cached update gate and result, the previous hidden state, and the candidate hidden state are calculated in parallel to obtain the current hidden state.

[0141] In a specific embodiment, the calculation formulas for the reset gate and the update gate are:

[0142] R t =σ(X t W xr +H t-1 W hr +b r )

[0143] Z t =σ(X t W xr +H t-1 W hz +b z )

[0144] where X t ∈R nxd is the input vector, n is the number of samples, d is the dimension of the input vector, and t is the time step; H t-1 ∈R nxh is the hidden state, R t ∈R nxh is the reset gate and Z t ∈R nxh is the update gate;

[0145] W xr ,W xz ∈R dxh, W hr , W hz ∈R hxh is the weight parameter, b r , b z ∈R 1xh is the bias parameter;

[0146] The calculation formula for the hidden state is:

[0147]

[0148] where is the candidate hidden state W xh ∈R dxh , W hh ∈Rh xh and are weight parameters, b h ∈R 1xh is the bias term, and the ⊙ symbol is the Hadamard product (element-wise product) operator; the tanh non-linear activation function is used to ensure that the values in the candidate hidden state are kept in the interval (-1, 1);

[0149] The final update formula for the gated recurrent unit is:

[0150]

[0151] Example 2

[0152] This example can be regarded as an improvement or extended example based on Example 1. Specifically, it is a method for identifying radar radiation sources based on FPGA, and the method includes:.

[0153] Construct a radar radiation source signal dataset;

[0154] Specifically, first construct a simulation dataset in Matlab R2023a software. The simulation of the data uses real signal parameters and the characteristics of the signal passing through the FPGA hardware platform. The specific parameters are shown in Table 1:

[0155] Table 1

[0156]

[0157] Considering the influence of different window functions on time-frequency analysis, mainly the sidelobe effect and signal leakage, the Hamming window is comprehensively selected as the window function, and the formula of the window function is as follows:

[0158]

[0159] Convert the radar signals in the radar radiation source signal dataset from the time domain to the time-frequency domain to obtain two-dimensional signals;

[0160] Input the two-dimensional signal into a preset deep neural network for pre-training to obtain a pre-trained model;

[0161] Optimize the pre-trained model using a preset optimization strategy to obtain a radar emitter recognition model;

[0162] It should be noted that the calculation of the pre-trained model uses the tensor data type, that is, the calculation of floating-point number float-64. However, in the actual hardware platform, the calculation cost of floating-point numbers is very high. Therefore, the parameters need to be quantized at the end of model construction.

[0163] According to the characteristics of FPGA, that is, the quantization bit width of ADC is 16bit, so the weight value is quantized to 8bit and the bias value is quantized to 16bit.

[0164] Assume that r represents the floating-point real number and q represents the quantized fixed-point integer. Then the conversion formula is as follows:

[0165] r = S(q - Z)

[0166]

[0167] Where S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. Their calculation methods are:

[0168]

[0169] It should be noted that in the actual deployment of the neural network, due to the characteristics of the operators, different operators can be fused. In this case, the convolutional layer and the BN layer are fused.

[0170] For the convolutional layer operation:

[0171] y conv = ωx + b

[0172] Where ω is the weight, x is the input matrix, b is the bias, and y is the output matrix.

[0173] For the operation of the BN layer:

[0174]

[0175] Where μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer.

[0176] According to the characteristics of the operation, there are:

[0177]

[0178] where is the fused weight, is the fused bias.

[0179] Deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive and identify the radar emitter signal in real time through the FPGA platform to obtain the recognition result;

[0180] In a specific embodiment, the method of deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving and identifying the radar emitter signal in real time through the FPGA platform to obtain the recognition result includes:

[0181] Deploy the radar emitter recognition model;

[0182] Sample the radar emitter signal according to a preset data processing clock to obtain real-time AD data;

[0183] It should be noted that the sampling rate of the ADC on the FPGA side is set to 5 GHz, 40x decimation, IQ sampling, the quantization bit width is 16 bits, the data processing clock is 125 MHz, and the data rate is 125 MSps. The settings of this part in Matlab are consistent with the settings of the ADC.

[0184] Perform windowing processing on the real-time AD data through a preset window function;

[0185] In the FPGA, perform time-frequency analysis on the real-time AD data through STFT calculation to obtain a real-time two-dimensional signal;

[0186] Please refer to Figure 2 , perform three convolution operations on the real-time two-dimensional signal through a preset Shallow Block module, then pass through the BN layer, and finally output after data fusion through the ReLu activation layer;

[0187] Then, further extract the timing features from the fused data through a two-layer gated recurrent unit;

[0188] Finally, further refine and extract the features of the data through a depth module composed of fully connected layers;

[0189] Finally, pass the data through a linear layer to obtain the classification result.

[0190] Specifically, the method of deploying the radar emitter recognition model includes:

[0191] The deployment of the model is to describe the information of the network in the language of hardware. In the FPGA platform, the model receives time-frequency information and outputs labels of corresponding categories.

[0192] According to the characteristics of the model and the features of the FPGA platform, the deployment of the model can be divided into several steps: convolution operation, linear layer operation, and weight reading.

[0193] Convolution operation:

[0194] Convolution operation is the most important operation in this network, and its essence is multiply-accumulate operation.

[0195] As Figure 3 shown, it is a schematic diagram of one-dimensional pipelined linear operation. Each basic operator is a multiply-accumulate operation, and this is encapsulated in the FPGA as a multiplication accelerator (Multiply-accumulate, MAC), and further encapsulating the MAC forms a module. During the use process, the pipeline receives one input signal each time, and controls the switch of the MAC through valid. If the pipeline is fully utilized, the calculation results of the MAC layer quantity can be obtained for each clock.

[0196] The above module can be directly applied to one-dimensional convolution operation. weight represents the weight of the convolution kernel. As the pipeline progresses, it is equivalent to the movement of data on each convolution kernel. For example, at a certain moment, if each MAC is valid, then the data is in the first position in the convolution sum represented by the first MAC and in the last position in the convolution kernel represented by the last MAC. Therefore, at this moment, the output result of the last MAC is the convolution sum represented by this convolution kernel.

[0197] Please refer to Figure 4 , Figure 4 which is a schematic diagram of the operation of a conventional convolution. To simplify the difficulty of hardware deployment and reduce the number of parameters, please refer to Figure 5 , and this invention uses depthwise separable convolution to replace Figure 4 the conventional convolution. Research shows that the depthwise separable convolution has almost the same calculation accuracy while reducing the number of parameters. Therefore, the FPGA implementation of the convolution operation is transformed into the implementation of two parts: depthwise convolution (Depthwise, DW) and pointwise convolution (Pointwise, PW). The following will be analyzed one by one.

[0198] Figure 6 is a schematic diagram of the operation of depthwise separable convolution. Suppose the size of the convolution kernel is C in·KH·KW, then the convolution of each channel can be implemented using KH·KW MAC layers. In this case, the data in the KW dimension can also be viewed as a one-dimensional sequence, and the input now becomes the input sequence of KH. The difference is that the final output of each one-dimensional sequence must pass through an adder.

[0199] When in use, KW-1 MACs can be combined into a convolutional computing unit (Processing Unit, PE), so a total of C in KH PE.

[0200] like Figure 7 As shown, in point convolution, the size of the convolution kernel is C out ·C in ·1·1, each row in the figure above has a convolution kernel of one output channel, with a size of 1·C in ·1·1, the convolution result of each channel position can be obtained by splicing the calculation results of each row. When using, each row is instantiated as a PE, then a total of C out -1 PE.

[0201] Linear layer operation: The linear layer operation is as follows Figure 8 As shown, this operation can also be used Figure 7 To express.

[0203] Reading parameters:

[0204] In actual FPGA deployments, convolutional and linear layers have weight and bias parameters. Since these parameters do not change during computation, they can be stored in advance. On FPGAs, the BRAM IP core is used to store these parameters.

[0205] In PW, the size of the convolution kernel is C in ·KH·KW, a corresponding number of MACs are required. To encapsulate KW MACs, a total of C out KH PEs. In each PE, the weight is 16 KW bits and the bias is 8 KH bits.

[0206] In DW, the size of the convolution kernel is C out ·Cin·1·1, a corresponding number of MACs are required. in MACs are encapsulated, and a total of C out PE. In each PE, the weight is 16·C out bit, and the offset is 8·Cout bit.

[0207] In the linear layer, the size of the parameter is C out ·C in , and the corresponding number of MACs is required. Encapsulating C in MACs requires a total of C out PEs. In each PE, the size of the weight is 16·C out bit, and the bias is 8·C out bit.

[0208] Operations of the GRU module:

[0209] Please refer to Figure 9 , Figure 9 which is the calculation schematic diagram of the gated recurrent unit model. The calculation formulas for the reset gate and the update gate are:

[0210] R t =σ(X t W xr +H t-1 W hr +b r )

[0211] Z t =σ(X t W xr +H t-1 W hz +b z )

[0212] where X t ∈R nxd is the input vector, n is the number of samples, d is the dimension of the input vector, and t is the time step. H t-1 ∈R nxh is the hidden state, R t ∈R nxh is the reset gate, and Z t ∈R nxh is the update gate.

[0213] W xr , W xz ∈R dxh , W hr , W hz ∈R hxh are the weight parameters, and b r , b z ∈R 1xh are the bias parameters.

[0214] The calculation formula for the hidden state is:

[0215]

[0216] where is the candidate hidden state Wxh ∈R dxh ,W hh ∈Rh xh and are weight parameters, b h ∈R 1xh is the bias term, and the ⊙ symbol is the Hadamard product (element-wise product) operator. Here we use the tanh non-linear activation function to ensure that the values in the candidate hidden state remain in the interval (-1, 1).

[0217] The final update formula for the gated recurrent unit is as follows:

[0218]

[0219] Analysis of GRU calculations reveals that the module outputs the hidden state of the current step by receiving the hidden state of the previous time step and the input of the current step. The main internal calculations are element-wise operations on the sequence and operations of the linear layer. The specific steps can be decomposed as follows:

[0220] First, the input and the hidden state are loaded through the buffer module, and after passing through the reset gate and the update gate together, the calculation result is obtained, and the output result of the update gate is cached in the register.

[0221] After the reset gate operates on the hidden state of the previous step and together with the current input, it passes through the candidate hidden state gate to obtain the candidate hidden state.

[0222] The cached update gate and result, the hidden state of the previous step, and the candidate hidden state are calculated in parallel to obtain the hidden state of the current step.

[0223] Please refer to Figure 10 , Figure 10 for the GRU deployment schematic diagram, where the DSP mainly performs multiplication operations. The input / output buffer module and the weight and bias value loading module are omitted in the figure.

[0224] The model deployment is as shown in Figure 11As shown, the overall control is implemented by a state machine. When the convolution module is called, first the weights are called through the Weight_loader module, and then they are operated on with the data. The result of the operation is written into the Ping-pong buffer module. On the other hand, the data passes through the Conv_pw module to obtain the convolution result, and after adding the bias through the Bias_loader module, the final convolution structure is obtained and written into the Ping-pong buffer for the next step of processing. When performing the Squeeze-Excitation operation, the weights are first configured to the linear layer. The data enters the global average pooling from the buffer to obtain the importance metrics of each layer, and then a linear operation is performed with the weights. After that, the output of the linear layer is obtained through the Bias_loader. Finally, the output of the linear layer passes through a 12-way selector to output the corresponding label value.

[0225] Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A method for identifying one-dimensional radar radiation sources based on FPGA, characterized in that, The method includes: Constructing a radar emitter signal dataset; Converting the radar signals in the radar emitter signal dataset from the time domain to the time-frequency domain to obtain two-dimensional signals; Inputting the two-dimensional signals into a preset deep neural network for pre-training to obtain a pre-trained model; Optimizing the pre-trained model using a preset optimization strategy to obtain a radar emitter recognition model; Deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving radar emitter signals in real time through the FPGA platform and performing recognition to obtain recognition results.

2. The one-dimensional radar radiation source recognition method based on FPGA according to claim 1, characterized in that The method for constructing a radar emitter signal dataset includes: Generating a radar emitter signal dataset through MATLAB simulation. The radar emitter signal dataset includes signals of twelve different modulation methods, and for each signal, an equal number of samples are generated at signal-to-noise ratios from -10 dB to 8 dB with an interval of 2 dB.

3. A method for identifying one-dimensional radar radiation sources based on FPGA according to claim 1, characterized in that Converting the radar signals in the radar emitter signal dataset from the time domain to the time-frequency domain to obtain two-dimensional signals: Sampling the radar signals according to a preset data processing clock to obtain AD data; Performing windowing processing on the AD data through a preset window function; In the FPGA, performing time-frequency analysis on the AD data through STFT calculation. The specific formula is: where x(n) is the input sequence, ω(n) is the window function, and R is the step value.

4. A method for identifying one-dimensional radar radiation sources based on FPGA according to claim 1, characterized in that The preset optimization strategy includes: Parameter quantization processing and parameter fusion processing.

5. The one-dimensional radar radiation source recognition method based on FPGA according to claim 4, characterized in that, The method for parameter quantization processing includes: According to the characteristics of the FPGA, that is, the quantization bit width of the ADC is 16 bits, so the weight value is quantized to 8 bits and the bias value is quantized to 16 bits; Assuming that r represents a floating-point real number and q represents a quantized fixed-point integer, the conversion formula is as follows: r = S(q - Z) where S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. The calculation method is:

6. The one-dimensional radar radiation source identification method based on FPGA according to claim 4, wherein The method for parameter fusion processing includes: Fusing the convolutional layer and the BN layer; For the operation of the convolutional layer: y conv = ωx + b where ω is the weight, x is the input matrix, b is the bias, and y is the output matrix; For the operation of the BN layer: where μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer; According to the characteristics of the operation: Among them is the fused weight, is the fused bias.

7. A method for identifying one-dimensional radar radiation sources based on FPGA according to claim 1, characterized in that, The method for deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving radar emitter signals in real time through the FPGA platform and performing recognition to obtain recognition results includes: Sampling the radar emitter signals according to a preset data processing clock to obtain real-time AD data; Performing windowing processing on the real-time AD data through a preset window function; In the FPGA, performing time-frequency analysis on the real-time AD data through STFT calculation to obtain real-time two-dimensional signals; Performing three convolutional operations on the real-time two-dimensional signals through a preset Shallow Block module, then passing through the BN layer, and finally fusing the data and passing through the ReLu activation layer for output; Next, further extracting temporal features from the fused data through a two-layer gated recurrent unit; Finally, the data is further refined and extracted for features through a depth module composed of fully connected layers; Finally, the data passes through a linear layer to obtain the classification result.

8. A method for identifying one-dimensional radar radiation sources based on FPGA according to claim 7, characterized in that, The method for further extracting temporal features from the fused data through a two-layer gated recurrent unit includes: First, the input fused data and hidden state are loaded through a cache module, and the fused data and hidden state are calculated through a reset gate and an update gate to obtain a calculation result, and the output result of the update gate is cached in a register; The reset gate operates with the hidden state of the previous step and passes through the candidate hidden state gate together with the current input to obtain the candidate hidden state; The cached update gate and result, the hidden state of the previous step, and the candidate hidden state are calculated in parallel to obtain the hidden state of the current step.

9. The one-dimensional radar emitter recognition method based on FPGA according to claim 8, characterized in that The calculation formulas for the reset gate and the update gate are: R t = σ(X t W xr + H t-1 W hr + b r ) Z t = σ(X t W xr + H t-1 W hz + b z ) where X t ∈R nxd is the input vector, n is the number of samples, d is the dimension of the input vector, and t is the time step; H t-1 ∈R nxh is the hidden state, R t ∈R nxh is the reset gate and Z t ∈R nxh is the update gate; W xr ,W xz ∈R dxh ,W hr ,W hz ∈R hxh is a weight parameter, b r ,b z ∈R 1xh is a bias parameter; The calculation formula for the hidden state is: where is the candidate hidden state W xh ∈R dxh , W hh ∈Rh xh and are weight parameters, b h ∈R 1xh is the bias term, and the ⊙ symbol is the Hadamard product (element-wise product) operator; the tanh non-linear activation function is used to ensure that the values in the candidate hidden state remain in the interval (-1, 1); The final update formula for the gated recurrent unit is:

10. A one-dimensional radar radiation source recognition system based on FPGA, characterized in that, The system includes a dataset construction module, a time-frequency analysis module, a training module, an optimization module, and a signal real-time recognition module; The dataset construction module is used to construct a radar emitter signal dataset; The time-frequency analysis module is used to convert the radar signals in the radar emitter signal dataset from the time domain to the time-frequency domain to obtain two-dimensional signals; The training module is used to input the two-dimensional signals into a preset deep neural network for pre-training to obtain a pre-trained model; The optimization module is used to optimize the pre-trained model by using a preset optimization strategy to obtain a radar emitter recognition model; The signal real-time recognition module is used to deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive radar emitter signals in real time through the FPGA platform and perform recognition to obtain a recognition result.

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