Heterogeneous calculation and dynamic model updating method and device for brain-like chip and medium

Abstract

The invention provides a brain-like chip heterogeneous calculation and dynamic model updating method, which comprises the following steps: constructing a neuron pulse coding and video feature parallel calculation model, carrying out heterogeneous integration on a brain-like chip supporting an SNN pulse neural network and a multi-core processor, and constructing a spatial-temporal feature dual-channel processing unit; developing a task load balancing algorithm based on synaptic weight dynamic allocation, including constructing a resource state matrix, designing a task allocator based on reinforcement learning, and performing decision optimization in a dynamic environment; a direct memory access channel is established between a brain-like chip and a video codec, a dedicated instruction set is expanded, and motion vector data of a video encoder is read through instruction level collaboration; carrying out binary differential coding on the key layer by adopting hierarchical parameter importance sorting, and compressing the update quantity of the key layer by combining a compression algorithm; and migrating a full-amount model to a lightweight model through dynamic knowledge distillation, and dynamically generating an adaptive model in combination with an attention migration loss function.

Description

Technical Field

[0001] The present invention belongs to the technical field of industrial edge computing and artificial intelligence, and particularly relates to a heterogeneous computing and dynamic model updating method, device, and medium for a brain-inspired chip. Background Art

[0002] In the prior art, security monitoring systems generally adopt an "in-cloud training + edge inference" architecture, which has the following defects:

[0003] 1. Computing power bottleneck: Traditional edge devices (such as ARM CPUs / GPUs) are difficult to efficiently process spatio-temporal features of video streams, resulting in high response latencies (>300 ms) in industrial scenarios (such as mine safety monitoring and traffic flow analysis);

[0004] 2. Inefficient model updating: Industrial devices need to frequently update models to cope with dynamic environments (such as changes in manufacturing line processes and sudden risks at construction sites), but full-parameter updates (about 200 MB for ResNet-50) consume a large amount of bandwidth and the update cycle is as long as several hours;

[0005] 3. Poor dynamic adaptability: Industrial devices have strong heterogeneity (such as hardware differences between mine sensors and construction machinery), and manual tuning is required for model deployment, making it impossible to respond in real time to complex environments such as sudden changes in lighting and dust interference;

[0006] 4. Insufficient energy efficiency ratio: GPU acceleration solutions have too high power consumption (>50 W), making it difficult to meet the low-power requirements of scenarios such as mines and transportation.

[0007] Existing improvement solutions such as federated learning, although reducing the amount of data transmission, significantly reduce model accuracy (about 12% - 18%) in non-independent and identically distributed data scenarios, and industrial devices are difficult to support high-frequency updates due to poor network conditions (such as underground mines). In addition, for new security threats (such as adversarial attacks), traditional systems take more than 6 hours to complete model iteration, unable to meet the real-time protection requirements of critical scenarios. Summary of the Invention

[0008] The purpose of the present invention is to solve the problems in the prior art, and proposes a heterogeneous computing and dynamic model updating method, device, and medium for a brain-inspired chip, which integrates a heterogeneous computing system of a brain-inspired chip (KA200) and an ARM multi-core architecture, as well as a three-level dynamic model updating method for cloud-edge-end, and is applicable to real-time video analysis and intelligent decision-making in industrial scenarios such as manufacturing, construction, transportation, mines, and security.

[0009] To achieve the above purpose, the present invention adopts the following technical solutions.

[0010] The heterogeneous computing and dynamic model updating method for a brain-inspired chip,

[0011] Build a parallel computing model for neuron spike coding and video features, heterogeneously integrate a brain-inspired chip supporting the SNN spiking neural network with a multi-core processor, and build a spatio-temporal feature dual-channel processing unit;

[0012] Develop a task load balancing algorithm based on dynamic allocation of synaptic weights, including constructing a resource status matrix, designing a task allocator based on reinforcement learning, and optimizing decisions in a dynamic environment;

[0013] Establish a direct memory access channel between the brain-inspired chip and the video codec, expand the special instruction set, and read the motion vector data of the video encoder through instruction-level cooperation;

[0014] Adopt hierarchical parameter importance sorting to perform binary differential coding on the key layers, and combine with a compression algorithm to compress the key layer update amount;

[0015] Migrate the full model to a lightweight model through dynamic knowledge distillation, and dynamically generate an adapted model in combination with an attention transfer loss function.

[0016] Furthermore, the construction of the parallel computing model for neuron spike coding and video features, the heterogeneous integration of the brain-inspired chip supporting the SNN spiking neural network with the multi-core processor, and the construction of the spatio-temporal feature dual-channel processing unit include:

[0017] The brain-inspired chip supporting the SNN spiking neural network processes the time features in the video stream, and the parallel computing of the multi-core processor processes the space features;

[0018] The extraction of space features includes using the decoded video frames to extract the static features of the object contour by means of a lightweight convolutional network;

[0019] The extraction of time features includes that the brain-inspired chip encodes the dynamic features of the motion trajectory based on the spike-timing-dependent plasticity rule, and the spike-timing-dependent plasticity rule captures the causal relationship in the time series.

[0020] Furthermore, the development of the task load balancing algorithm based on dynamic allocation of synaptic weights, including constructing a resource status matrix, designing a task allocator based on reinforcement learning, and optimizing decisions in a dynamic environment includes:

[0021] By updating the Q-value table, the task allocator is made to execute the optimal allocation strategy under different load conditions. When the CPU load in the resource status matrix exceeds the set threshold, the LSTM time series prediction task is migrated to the neuromorphic computing unit of the brain-inspired chip.

[0022] Furthermore, the establishment of a direct memory access channel between the brain-inspired chip and the video codec, the expansion of the special instruction set, and the reading of the motion vector data of the video encoder through instruction-level cooperation include:

[0023] Instruction - level cooperation between the brain - like chip computing and video hardware, and the dedicated instruction set includes instructions that allow background difference operations to directly read the motion vector data of the encoder.

[0024] Furthermore, the method of using hierarchical parameter importance sorting to binarize the difference coding of the key layer and combining with a compression algorithm to compress the key layer update amount includes:

[0025] Perform binarization processing on the parameter changes of the key layer, and retain the flag bits where changes occur;

[0026] Use a compression algorithm to perform secondary compression on the binarized difference data.

[0027] Furthermore, the method of migrating the full - scale model to a lightweight model through dynamic knowledge distillation and dynamically generating an adapted model in combination with an attention transfer loss function includes:

[0028] Attention transfer loss function L AT = ∑||Q T - Q S ||², where Q T and Q S respectively represent the attention distributions of the teacher model and the student model;

[0029] By minimizing the difference between the attention distributions, ensure that the lightweight model inherits the key feature extraction ability of the teacher model.

[0030] Furthermore, it also includes setting a thermal switching mechanism for the edge - side model, including real - time monitoring of multi - dimensional indicators of the edge - side device, constructing an anomaly detection model, using the isolation forest algorithm for anomaly detection, and identifying anomaly patterns.

[0031] Even further, it also includes that when an anomaly is detected, the system will trigger the thermal switching mechanism. The switching process includes switching to the backup model within a specified time, and at the same time triggering an incremental rollback to restore to the previous state.

[0032] To achieve the above - mentioned purpose, the present invention also provides an electronic device, including a memory and a processor. The memory stores a program that runs on the processor, and when the processor runs the program, it executes the steps of the heterogeneous computing and dynamic model updating method of the brain - like chip as described above.

[0033] To achieve the above - mentioned purpose, the present invention also provides a computer - readable storage medium, on which computer instructions are stored. When the computer instructions run, they execute the steps of the heterogeneous computing and dynamic model updating method of the brain - like chip as described above.

[0034] The present invention proposes a heterogeneous computing and dynamic model updating method, device, and medium for a brain - like chip, having the following beneficial effects:

[0035] 1. Performance improvement: In the actual measurement of the intelligent park, the intrusion detection response time is reduced from 350 ms to 210 ms (a 40% improvement), and the energy efficiency ratio of video stream processing reaches 8.4 TOPS / W (5.3 times higher than that of GPU).

[0036] 2. Bandwidth optimization: The amount of data updated for the construction site model is reduced by 70% (from 1.2 GB to 360 MB for a single update), and concurrent updates of thousands of devices are supported.

[0037] 3. Enhanced industrial reliability: The false alarm rate of traffic tunnel monitoring equipment is greatly reduced under dust interference; at the same time, the success rate of model switching in high-temperature and high-humidity factory environments is improved.

[0038] Other features and advantages of the present invention will be described in the following specification, and part of them will be obvious from the specification or understood by implementing the present invention. Brief Description of the Drawings

[0039] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0040] Figure 1 is a flowchart of a heterogeneous computing and dynamic model updating method for a brain-inspired chip of the present invention;

[0041] Figure 2 is a schematic structural diagram of an electronic device 300 for implementing the embodiments of the present application. Detailed Embodiments

[0042] The following describes the preferred embodiments of the present invention with reference to the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0043] Embodiment 1

[0044] Figure 1 is a flowchart of a heterogeneous computing and dynamic model updating method for a brain-inspired chip according to the present invention. The following will refer to Figure 1 , and describe the heterogeneous computing and dynamic model updating method for a brain-inspired chip of the present invention in detail.

[0045] In step 101, a parallel computing model of neuron pulse coding and video features is constructed. A brain-inspired chip supporting the SNN pulse neural network is heterogeneously integrated with a multi-core processor to construct a spatio-temporal feature dual-channel processing unit.

[0046] Optionally, a parallel computing model for neuron spike coding and video features is constructed. This includes heterogeneous integration of a brain-inspired chip (such as KA200) supporting SNN (Spiking Neural Network) and an ARM multi-core processor (such as Cortex-A78) to build a spatio-temporal feature dual-channel processing unit. The brain-inspired chip supports SNN (Spiking Neural Network), and its high energy efficiency ratio and time dimension sensitivity make it very suitable for processing time features in video streams, while the multi-core parallel computing ability of ARM Cortex-A78 is suitable for processing spatial features.

[0047] In this embodiment, spatial feature extraction includes: for video frames decoded by H.265, using a lightweight convolutional network (such as Depthwise Conv2D) to extract static features such as object contours. This lightweight design can significantly reduce computational complexity while ensuring sufficient accuracy.

[0048] In this embodiment, static features include edge geometric features, key point distribution features, texture structure features, and topological relationship features, etc.

[0049] Time feature extraction includes: the brain-inspired chip encodes dynamic features such as motion trajectories based on the STDP (Spike-Timing-Dependent Plasticity) rule. The STDP rule can effectively capture causal relationships in time series and is particularly suitable for processing motion information in video streams.

[0050] In this embodiment, the time channel (SNN) in the dual-channel processing logic includes:

[0051] Spike coding strategy: Adopt an event-driven dynamic vision sensor (DVS) model to convert the video stream into a spike sequence, and divide the time window into 10ms granularity.

[0052] Time feature extraction includes: the input spike sequence undergoes synaptic weight adaptive adjustment through the STDP (Spike-Timing-Dependent Plasticity) rule; use the LIF (Leaky Integrate-and-Fire) neuron model to extract the motion pattern in the time dimension; the output layer generates a time feature tensor with dimensions [Batch, Time_step, Feature_dim]

[0053] The spatial channel (CPU / GPU) includes:

[0054] Spatial feature extraction network: Construct an improved 3D-CNN, integrating a channel attention mechanism: perform spatio-temporal slicing on the input video frame sequence to generate a three-dimensional input block; extract spatial-short-term features through a 3D convolutional kernel; the attention module dynamically adjusts the feature channel weights; output a spatial feature tensor with dimensions aligned with the time channel.

[0055] In this embodiment, the construction of the spatio-temporal feature dual-channel processing unit includes a hardware heterogeneous integration architecture. For the physical layer design: The 3D heterogeneous packaging technology is adopted to vertically stack the SNN brain-like chip (time feature processing unit) and the multi-core CPU / GPU (space feature processing unit), and high-bandwidth interconnection is achieved through through-silicon vias (TSVs). A shared memory pool is constructed, and a dual-port access controller is designed to support the SNN chip and the CPU / GPU to access the same storage area simultaneously, and a priority arbitration mechanism is adopted to solve access conflicts.

[0056] In this embodiment, by separately allocating spatial features and temporal features to different hardware units for parallel computing, the latency is reduced by 42%. This indicates that the architecture design has significant potential in performance optimization, especially in real-time video processing scenarios.

[0057] In this embodiment, a spatio-temporal feature synchronization protocol is designed to ensure the alignment of the output timestamps of the dual channels, and a gated fusion unit (GFU) is adopted to dynamically calculate the spatio-temporal feature weights.

[0058] In step 102, a task load balancing algorithm based on dynamic allocation of synaptic weights is developed, including constructing a resource status matrix, designing a task allocator based on reinforcement learning, and performing decision optimization in a dynamic environment.

[0059] Optionally, the dynamic allocation of synaptic weights load balancing algorithm includes constructing a resource status matrix and designing a task allocator based on reinforcement learning (Q-Learning). When the CPU utilization rate is greater than 80%, the LSTM time series prediction task is migrated to the neuromorphic computing unit of the brain-like chip, and the load balancing error <5%.

[0060] In this embodiment, the dynamic resource status modeling includes state matrix construction: Define an 8-dimensional state vector: S = [U cpu , R snn , M used , D task , B width , T emp , P ower , Q priority , which respectively represent CPU utilization rate, SNN pulse rate, memory occupancy, task latency, bandwidth occupancy, temperature, power consumption, and task priority.

[0061] Construct a dynamic update matrix N is the number of computing nodes, and the update period is 100 ms.

[0062] In this embodiment, the design of the task allocator based on reinforcement learning includes:

[0063] (1) Define the environmental state (State) to describe the real-time resource state of the system.

[0064] Construct a resource state matrix, including key metrics: S = [U cpu , R snn , M mem , D task , T emp , where U cpu : CPU utilization rate (0 - 100%); R snn : Pulse frequency of the brain-like chip (number of pulses per second); M mem : Memory usage rate (0 - 100%); D task : Average task processing delay (milliseconds); T emp : Chip temperature (°C). Update rule: Collect data every 100 ms and calculate the average value using a sliding window (window size 60 seconds).

[0065] (2) Define the action space (Action) to determine which devices tasks can be assigned to.

[0066] Design a discrete action set: A = {CPU, SNN, GPU, Offload}, where CPU: Assign the task to the multi-core CPU; SNN: Assign the task to the brain-like chip; GPU: Assign the task to the graphics processor; Offload: Offload the task to the edge server. Support task splitting (e.g., 70% to the CPU and 30% to the SNN).

[0067] (3) Design a reward function (Reward) to quantify the quality of each decision and guide model optimization.

[0068] Comprehensive reward formula: R = 0.5 × R balance + 0.3 × R delay + 0.2 × R safety

[0069] Among them, the load balancing reward:

[0070]

[0071] For example: CPU utilization rate is 80%, SNN utilization rate is 60%, then R balance = 1 - 80 / (80 + 60) = 0.43

[0072] The delay penalty term:

[0073]

[0074] The lower the delay, the larger the value (when D task = 10 ms, R delay = 0.37)

[0075] Safety constraint items:

[0076]

[0077] When the temperature exceeds 85 °C, the reward is negative and forced cooling is carried out.

[0078] (4) Construct a Policy Network to let the model learn which action to choose under what state.

[0079] The network structure includes:

[0080] Input layer: 5 nodes (corresponding to the state vector dimension);

[0081] Hidden layer: 64 nodes (using the ReLU activation function);

[0082] Output layer: 4 nodes (corresponding to the probabilities of 4 actions, Softmax normalization);

[0083] Training algorithm: Adopt PPO (Proximal Policy Optimization) to balance exploration and exploitation.

[0084] Update rule: New policy = old policy + learning rate × (new reward - old prediction). The initial value of the learning rate is set to 0.001 and decays gradually. Among them, the learning rate is used to control the model update speed, and the typical value is 0.001.

[0085] (5) Dynamic training and optimization to make the model adapt to the real-time changing environment.

[0086] Offline pre-training: Use historical data to simulate different load scenarios (such as peak periods, sudden tasks). Train for 100,000 iterations until the reward is stable.

[0087] Online fine-tuning: Continuously collect new data after deployment and store it in the experience pool (capacity of 10,000 entries). Update the model with the latest data every 30 minutes.

[0088] Exception handling: If three consecutive decisions result in temperature overlimit or delay doubling, roll back to the previous stable version.

[0089] (6) Decision execution process:

[0090] Observed state: Collect resource data every 100 ms.

[0091] State normalization: Scale the original data to the range of [0, 1].

[0092] For example: CPU utilization rate of 80% → 0.8.

[0093] Policy inference: Input the state into the policy network to obtain the probabilities of 4 actions.

[0094] Example output: [CPU: 0.6, SNN: 0.3, GPU: 0.1, Offload: 0.0]

[0095] Action selection: Random selection by probability (exploration), or select the action with the highest probability (exploitation). Safety filtering: If the selected action may cause the temperature to exceed the limit, automatically select the sub-optimal action.

[0096] Feedback learning: Record the reward of this decision for updating the model.

[0097] In this embodiment, the resource status matrix and task migration are used. Constructing the resource status matrix can reflect the resource usage of different hardware units in real time. On this basis, designing a task allocator (Q-Learning) based on reinforcement learning can achieve intelligent load balancing.

[0098] When the CPU load exceeds 80%, migrate the LSTM (Long Short-Term Memory) time series prediction task to the neuromorphic computing unit of the brain-inspired chip. The neuromorphic computing unit of the brain-inspired chip has low energy consumption and high parallel processing capabilities, and is suitable for processing time series modeling tasks such as LSTM.

[0099] Load balancing error < 5%, this indicator shows that the design of the task allocator is very efficient and can achieve near-optimal load distribution among hardware resources.

[0100] Q-Learning, as a model-free reinforcement learning method, is suitable for decision optimization in dynamic environments. By continuously updating the Q-value table, the task allocator can gradually learn the best allocation strategy under different load conditions, thus achieving the long-term load balancing goal.

[0101] In step 103, establish a direct memory access channel between the brain-inspired chip and the video codec, expand the dedicated instruction set, and read the motion vector data of the video encoder through instruction-level cooperation.

[0102] Optionally, instruction-level cooperation between brain-inspired computing and video hardware. This includes establishing a DMA direct connection channel between the brain-inspired chip and the video codec (such as H.264 ASIC), expanding the dedicated instruction set (such as the MOV_VECTOR instruction), enabling the background difference operation to directly read the motion vector data of the encoder, and reducing the instruction cycle by 65%.

[0103] In this embodiment, the hardware optimization design includes establishing a direct connection channel of DMA (Direct Memory Access) between the brain-inspired chip and the video codec (such as H.264 ASIC), and extending the dedicated instruction set (such as the MOV_VECTOR instruction), which is the key innovation to improve the overall performance of the system.

[0104] The DMA direct connection channel, through DMA technology, avoids the frequent copying of data between the main memory and external devices, thus significantly reducing the data transmission delay.

[0105] Dedicated instruction set: The MOV_VECTOR instruction allows the background difference operation to directly read the motion vector data of the encoder. This kind of instruction-level optimization can greatly reduce the instruction cycle and reduce the execution time by 65%.

[0106] The hardware optimization not only improves the efficiency of video processing, but also provides new ideas for the collaborative work between the brain-inspired chip and traditional hardware. Through instruction-level collaboration, the advantages of different hardware units can be fully utilized to avoid resource waste.

[0107] In this embodiment, the data transmission channel designs a zero-copy mechanism, establishes a physical direct connection channel between the SNN chip and the video codec; adopts a chained DMA controller to support automatic address increment and continuous data block transmission; designs a ring buffer management strategy with double buffers working alternately.

[0108] Optionally, for the instruction set extension, dedicated instructions are designed:

[0109] MV_LOAD: Load the motion vector data block into the specified register group in a single cycle;

[0110] SIMD_MVPROC: A macro instruction for parallel processing of motion vectors, supporting 8-way parallel computing.

[0111] The collaborative processing flow includes: After the video encoder generates the motion vector, it triggers a DMA interrupt; the SNN chip directly reads the preprocessed data through dedicated instructions; the data stream is deeply bound to the computing pipeline to achieve instruction-level parallelism.

[0112] In this embodiment, at the architecture level: Through the design of the spatio-temporal feature dual-channel processing unit, efficient parallel computing of spatial and temporal features is achieved. At the algorithm level: The load balancing algorithm based on reinforcement learning can dynamically adjust the task allocation to ensure the efficient utilization of resources. At the hardware level: The introduction of the DMA direct connection channel and the dedicated instruction set further improves the performance and energy efficiency of the system.

[0113] In step 104, hierarchical parameter importance sorting is used to perform binary differential encoding on the key layer, and the key layer update amount is compressed in combination with the compression algorithm.

[0114] Optionally, for the cloud differential compression transmission protocol, the algorithm design adopts hierarchical parameter importance ranking (HPC-Rank), and only binarizes and differentially encodes the top 30% of the critical layers (such as the Stage4 convolutional layer of ResNet), combined with LZ4 compression, reducing the ResNet-18 update volume from 189MB to 56MB.

[0115] In this embodiment, the cloud differential compression transmission protocol improves efficiency by reducing the data transmission volume during model updates, especially in cases where the bandwidth is limited or the device resources are restricted. The main innovation lies in the combination of hierarchical parameter importance ranking (HPC-Rank) and binarized differential encoding.

[0116] The steps of hierarchical parameter importance ranking can be specifically executed as follows:

[0117] Evaluate the importance of different layers of the deep learning model. For example, in ResNet, the Stage4 convolutional layer is usually a critical layer, undertaking most of the feature extraction tasks;

[0118] In this embodiment, perform amplitude sorting on the weights W of the critical layers, retaining the top-30% of the high-importance parameters; perform ternarization on the remaining parameters: where τ = 0.7 is an adjustable threshold; perform differential encoding on non-zero values, storing the offset and sign bits.

[0119] Focus on processing the top 30% of the critical layers instead of updating all layer parameters in full, thus significantly reducing the computational and transmission overhead;

[0120] The steps of binarized differential encoding can be specifically executed as follows:

[0121] Perform binarization processing (BinaryCoding) on the parameter changes (i.e., the differences between the old and new models) of the critical layers, only retaining the flag bit indicating whether a change has occurred, further reducing the data volume;

[0122] LZ4 compression: Use the LZ4 compression algorithm to perform secondary compression on the binarized differential data. This is an efficient and low-latency compression method, suitable for real-time scenarios.

[0123] In the ResNet-18 model, the original update volume is 189MB. After the above optimizations, the update volume is compressed to 56MB, and the compression rate is approximately 70%.

[0124] In step 105, migrate the full model to the lightweight model through dynamic knowledge distillation, and dynamically generate an adapted model in combination with the attention transfer loss function.

[0125] Optionally, edge-side incremental learning and lightweight adaptation.

[0126] In this embodiment, after receiving the differential model, the edge server migrates the knowledge of the full model to the lightweight model (such as MobileNetV3) through Dynamic Knowledge Distillation (Dynamic KD), combined with the attention transfer loss function (formula: L attn = ∑||Q T - Q S ||2), and the accuracy loss < 1.5%.

[0127] In this embodiment, the temperature adaptive mechanism of the dynamic distillation strategy: set a high temperature (T = 5) in the initial stage to smooth the distribution; exponentially decay to T = 1 during the training process.

[0128] Loss function combination: L total = 0.7L task + 0.2L attn + 0.1L kd , where L task is the task loss, L kd is the traditional knowledge distillation loss, and L attn is the attention loss function.

[0129] Edge devices usually have limited computing resources, so it is necessary to migrate the knowledge of the full model in the cloud to the lightweight model while keeping the model accuracy from dropping significantly.

[0130] Dynamic Knowledge Distillation is a transfer learning method aimed at transferring the knowledge of complex models to lightweight models.

[0131] The steps of Dynamic Knowledge Distillation can be specifically executed as follows:

[0132] After receiving the differential model transmitted from the cloud, the edge server migrates the knowledge of the full model to the lightweight model (such as MobileNetV3) through the distillation process.

[0133] Attention Transfer Loss Function (LAT):

[0134] LAT formula: L attn = ∑||Q T - Q S ||2, where Q T and Q S represent the attention distributions of the Teacher Model and the Student Model respectively.

[0135] By minimizing the difference between the attention distributions, it is ensured that the lightweight model can better inherit the key feature extraction ability of the teacher model. The accuracy loss < 1.5% indicates that the lightweight model is close to the full model in inference performance.

[0136] In this embodiment, a lightweight model version library is deployed, and an adaptive model is dynamically loaded according to the current resource status; a model interpolation algorithm is designed to smoothly switch between models of different complexities.

[0137] Combined with incremental learning, it can gradually adapt to the characteristics of new data without retraining the entire model. It is suitable for edge computing scenarios such as Internet of Things devices and mobile terminals, which usually require high performance but have limited resources.

[0138] Optionally, a mechanism for hot-switching the model on the device side is set.

[0139] In this embodiment, state awareness: 10-dimensional metrics of the device side (such as FPS, temperature, memory occupancy, etc.) are monitored in real time to build an anomaly detection model. The Isolation Forest algorithm is used for anomaly detection, which has good robustness to high-dimensional data and can quickly identify abnormal patterns.

[0140] Hot-switching process: When an anomaly is detected (such as temperature > 85°C for 5 seconds), the system will trigger the hot-switching mechanism. The switching process is divided into two steps:

[0141] 1. Switch to the backup model within 200 ms to ensure uninterrupted service.

[0142] 2. Trigger incremental rollback to restore to the previous state, and the system interruption time < 50 ms.

[0143] The hot-switching mechanism can ensure the continuous operation of the device side and improve the user experience in case of hardware failures or environmental anomalies. The interruption time < 50 ms meets the real-time requirements.

[0144] To cope with sudden abnormal situations (such as too high temperature, insufficient memory, etc.), the device side needs to be able to quickly switch to the backup model to ensure the stability and reliability of the system. It is suitable for application scenarios with high real-time requirements, such as autonomous driving, industrial control, medical devices, etc.

[0145] The three-level model dynamic update method forms a complete closed-loop optimization system from the cloud to the edge and then to the device side. Cloud: The data transmission volume is reduced through the differential compression protocol to improve the update efficiency; Edge: Dynamic knowledge distillation and attention transfer are used to achieve lightweight adaptation on resource-constrained devices; Device side: The high availability and stability of the system are guaranteed through the hot-switching mechanism.

[0146] The present invention not only solves the bandwidth and resource bottleneck problems in traditional model updates but also improves the overall performance and robustness of the system through a multi-level collaborative approach.

[0147] A heterogeneous computing and dynamic model updating method for a brain-inspired chip. The brain-inspired chip (KA200) and the ARM processor jointly extract spatio-temporal features in scenarios such as manufacturing and mining. Industrial-level lightweight updating is achieved through hierarchical compression and edge distillation to reduce bandwidth consumption. A hot-switching mechanism based on the device operating state ensures system continuity in extreme industrial environments (high temperature, vibration).

[0148] Embodiment 2

[0149] Reference is made below to Figure 2 , which shows a structural diagram of an electronic device 300 suitable for implementing the embodiments of the present application. The electronic device is intended to represent various forms of digital computers, such as, for example, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as, for example, personal digital assistants, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present application described and / or claimed herein.

[0150] As Figure 2 shown, the electronic device 300 may include a processing device 310, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 320 or a program loaded from a storage device 380 into a random access memory (RAM) 330. The processing device 310 may be various general-purpose and / or special-purpose processing components having processing and computing capabilities. Some examples of the processing device 310 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processing device 310 executes the various methods and processes described above.

[0151] In the RAM 330, various programs and data required for the operation of the electronic device 300 are also stored. The processing device 310, the ROM 320, and the RAM 330 are connected to each other through a bus 340. An input / output (I / O) interface 350 is also connected to the bus 340.

[0152] Typically, the following devices can be connected to the I / O interface 350: an input device 360 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 370 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 380 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 390. The communication device 390 can allow the electronic device 300 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 2 the electronic device 300 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices can be implemented or had.

[0153] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 390, or installed from the storage device 380, or installed from the ROM 320. When the computer program is executed by the processing device 310, the above functions defined in the method of the embodiment of the present application are executed. Alternatively, in other embodiments, the processing device 310 can be configured to execute the method in any other suitable way (for example, by means of firmware): obtain usage data information of the number to be detected within the current moment and the historical period before the current moment, and the usage data information includes voice call records, SMS details, and APP usage records; count abnormal features in the usage data information according to the historical rules of the FaceTime fraud scenario; judge whether the number to be detected has a fraud risk based on an AI model generated by training with the abnormal features and sample data.

[0154] Embodiment III

[0155] The computer-readable medium described above in this application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this application, a computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. And in this application, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0156] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0157] The above computer-readable medium can be included in the above electronic device; or it can exist separately without being assembled into the electronic device.

[0158] The above computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to: obtain usage data information of the number to be detected within the current moment and a historical period before the current moment, where the usage data information includes voice call records, SMS detail records, and APP usage records; statistically analyze abnormal features in the usage data information according to the historical patterns of FaceTime fraud scenarios; and determine whether there is a fraud risk for the number to be detected based on an AI model generated by training with the abnormal features and sample data.

[0159] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The programming languages include, but are not limited to, object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, by connecting through an Internet service provider using the Internet).

[0160] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0161] The modules described in the embodiments of this application can be implemented in software or in hardware. In some cases, the name of the module does not constitute a limitation on the module itself.

[0162] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. By way of example, and without limitation, the types of hardware logic components that can be used include: digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), system-on-a-chip systems (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof, and the like.

[0163] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general purpose computer, a special purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0164] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0165] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0166] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend, middleware, or frontend components. The components of the system can be interconnected with each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0167] A computer system can include a client and a server. The client and the server are generally far from each other and usually interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, solving the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services. The server can also be a server of a distributed system, or a server combined with blockchain.

[0168] Artificial intelligence is a discipline that studies how to make a computer simulate certain thinking processes and intelligent behaviors of humans (such as learning, reasoning, thinking, planning, etc.), and it has both hardware-level technologies and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies mainly include several major directions such as computer vision technology, speech recognition technology, natural language processing technology, machine learning / deep learning technology, big data processing technology, and knowledge graph technology.

[0169] Cloud computing refers to a technical system that accesses an elastic and scalable shared physical or virtual resource pool through a network. The resources can include servers, operating systems, networks, software, applications, and storage devices, etc., and the resources can be deployed and managed in a on-demand and self-service manner. Through cloud computing technology, it can provide efficient and powerful data processing capabilities for the application and model training of technologies such as artificial intelligence and blockchain.

[0170] The embodiments described above are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the embodiments of the present application.

[0171] In the description of the embodiments of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the electric vehicle or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0172] In the description of the embodiments of the present application, it should also be noted that unless otherwise clearly specified and defined, the terms "set", "installed", "connected", "connected to" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0173] Finally, it should be noted that the above-described embodiments are only specific implementation manners of the present application, used to illustrate the technical solutions of the present application, rather than limiting it. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the technical field of the present application can still modify the technical solutions described in the foregoing embodiments, or can easily think of changes, or make equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A heterogeneous computing and dynamic model updating method for a brain-inspired chip, characterized in that Including: Construct a parallel computing model for neuron spike coding and video features, heterogeneously integrate a brain-inspired chip supporting the SNN spiking neural network with a multi-core processor, and construct a spatio-temporal feature dual-channel processing unit; Develop a task load balancing algorithm based on dynamic allocation of synaptic weights, including constructing a resource status matrix, designing a task allocator based on reinforcement learning, and performing decision optimization in a dynamic environment; Establish a direct memory access channel between the brain-inspired chip and the video codec, expand the dedicated instruction set, and read the motion vector data of the video encoder through instruction-level cooperation; Perform binary differential coding on the key layers using hierarchical parameter importance sorting, and compress the key layer update amount in combination with a compression algorithm; Migrate the full-scale model to a lightweight model through dynamic knowledge distillation, and dynamically generate an adapted model in combination with an attention transfer loss function.

2. A heterogeneous computing and dynamic model updating method for a brain-inspired chip according to claim 1, characterized in that The construction of the parallel computing model for neuron spike coding and video features, the heterogeneous integration of the brain-inspired chip supporting the SNN spiking neural network with the multi-core processor, and the construction of the spatio-temporal feature dual-channel processing unit include: The brain-inspired chip supporting the SNN spiking neural network processes the temporal features in the video stream, and the parallel computing of the multi-core processor processes the spatial features; Extracting spatial features includes using the decoded video frames to extract the static features of the object contour using a lightweight convolutional network; Extracting temporal features includes that the brain-inspired chip encodes the dynamic features of the motion trajectory based on the spike-timing-dependent plasticity rule, and the spike-timing-dependent plasticity rule captures the causal relationship in the time series.

3. A heterogeneous computing and dynamic model updating method for a brain-inspired chip according to claim 1, characterized in that The development of the task load balancing algorithm based on dynamic allocation of synaptic weights, including constructing a resource status matrix, designing a task allocator based on reinforcement learning, and performing decision optimization in a dynamic environment includes: By updating the Q-value table, the task allocator executes the optimal allocation strategy under different load conditions. When the CPU load in the resource status matrix exceeds the set threshold, the LSTM time series prediction task is migrated to the neuromorphic computing unit of the brain-inspired chip.

4. A heterogeneous computing and dynamic model updating method for a brain-inspired chip according to claim 1, characterized in that The establishment of a direct memory access channel between the brain-inspired chip and the video codec, the expansion of the dedicated instruction set, and the reading of the motion vector data of the video encoder through instruction-level cooperation include: Instruction-level cooperation between the brain-inspired chip calculation and the video hardware, and the dedicated instruction set includes instructions that allow background difference operations to directly read the motion vector data of the encoder.

5. A method for heterogeneous computing and dynamic model updating of a brain-inspired chip according to claim 1, characterized in that The use of hierarchical parameter importance sorting to perform binary differential coding on the key layers and compress the key layer update amount in combination with a compression algorithm includes: Perform binary processing on the parameter changes of the key layer, and retain the changed flag bits; Perform secondary compression on the binary differential data using a compression algorithm.

6. A method for heterogeneous computing and dynamic model updating of a brain-inspired chip according to claim 1, characterized in that The migration of the full-scale model to a lightweight model through dynamic knowledge distillation and the dynamic generation of an adapted model in combination with an attention transfer loss function include: Attention transfer loss function L AT = ∑||Q T - Q S ||², where Q T and Q S represent the attention distributions of the teacher model and the student model, respectively; By minimizing the difference between the attention distributions, ensure that the lightweight model inherits the key feature extraction ability of the teacher model.

7. A heterogeneous computing and dynamic model updating method for a brain-like chip according to claim 1, characterized in that It also includes setting up an end-side model hot-switching mechanism, including real-time monitoring of multi-dimensional indicators of end-side devices, constructing an anomaly detection model, using the isolation forest algorithm for anomaly detection, and identifying anomaly patterns.

8. A method for heterogeneous computing and dynamic model updating of a brain-inspired chip according to claim 7, characterized in that It further includes that when an abnormality is detected, the system will trigger a hot swap mechanism. The switching process includes switching to a backup model within a specified time, and at the same time triggering an incremental rollback to restore to the previous state.

9. An electronic device, characterized in that, It includes a memory and a processor. A program running on the processor is stored on the memory. When the processor runs the program, it executes a heterogeneous computing and dynamic model updating method for a brain-inspired chip according to any one of claims 1-8.

10. A computer-readable storage medium having computer instructions stored thereon, characterized in that, When the computer instructions run, they execute a heterogeneous computing and dynamic model updating method for a brain-inspired chip according to any one of claims 1-8.

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