A storage device testing method, device, readable storage medium and electronic device

Abstract

The application discloses a storage device testing method and device, readable storage medium and electronic equipment, comprising: traversing each storage array in a storage matrix to be detected, obtaining a read-write sequence of adjacent storage arrays for a target storage array traversed; obtaining a target read-write sequence by reversing the read-write sequence, performing data writing and data reading on the target storage array in the target read-write sequence; sequentially performing data writing on storage cells in the target storage array in a manner that data in adjacent storage cells in the target storage array is reversed and data in the storage cells in the target storage array and the storage cells in adjacent storage arrays is reversed; judging whether the data written in the storage cells is consistent with the data read out of the storage cells, if not, judging that the storage cells have a fault; judging whether all storage arrays in the storage matrix complete data writing and data reading, if yes, ending the test. Various types of faults can be effectively detected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a storage device testing method and device, readable storage medium and electronic equipment. BACKGROUND

[0002] Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR) is a storage matrix composed of a plurality of basic storage cells. Due to the influence of manufacturing process and packaging technology, some storage cells may fail during data reading and writing, so it is necessary to test the memory.

[0003] Among them, the implementation of the test algorithm is to compare the value read from the storage cell with the value written, if the value read is not consistent with the value written, it is considered that the storage cell has failed. The current test algorithm is mainly divided into two categories, one is to read all the test cells after the content of the storage cell changes. Another is to read only the cells whose contents have changed after the content of the storage cell changes.

[0004] When applying the test algorithm to test, if more faults need to be covered, an algorithm with high complexity needs to be used and a large amount of time needs to be spent for testing. While using a test algorithm with low complexity for testing, although the test time is saved, the faults cannot be effectively covered. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a storage device testing method, device, readable storage medium and electronic equipment, to improve the efficiency and fault coverage of testing.

[0006] In order to solve the above technical problems, the technical scheme adopted by the present application is:

[0007] A storage device testing method, comprising:

[0008] Traverse each storage array in the storage matrix to be detected, and obtain the read-write sequence of the previous storage array for the target storage array traversed;

[0009] Obtain the target read-write sequence by reversing the read-write sequence, and perform data writing and data reading on the target storage array according to the target read-write sequence;

[0010] Write data in the target storage array in the manner that the data in the adjacent storage cells in the target storage array is opposite, and the data in the storage cells in the target storage array and the adjacent storage array is opposite;

[0011] determining whether the data written into the storage unit is consistent with the data read out of the storage unit, and if not, determining that the storage unit has a fault;

[0012] determining whether all the storage arrays in the storage matrix have completed data writing and data reading, and if so, ending the test.

[0013] To solve the above technical problems, another technical solution adopted by the present application is:

[0014] A storage device testing apparatus comprises:

[0015] a traversal module configured to traverse each storage array in a storage matrix to be detected, and obtain a read-write sequence of a previous storage array for a target storage array traversed;

[0016] a writing module configured to obtain a target read-write sequence by reversing the read-write sequence, and perform data writing and data reading on the target storage array according to the target read-write sequence; and perform data writing on storage units in the target storage array in a manner that data in adjacent storage units in the target storage array is opposite, and data in the storage units in the target storage array and in adjacent storage arrays is opposite;

[0017] a first determining module configured to determine whether the data written into the storage unit is consistent with the data read out of the storage unit, and if not, determine that the storage unit has a fault;

[0018] a second determining module configured to determine whether all the storage arrays in the storage matrix have completed data writing and data reading, and if so, end the test.

[0019] To solve the above technical problems, another technical solution adopted by the present application is:

[0020] A computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement each step in the storage device testing method described above.

[0021] To solve the above technical problems, another technical solution adopted by the present application is:

[0022] An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing each step in the storage device testing method described above when executing the computer program.

[0023] The beneficial effect of the present application is that: when testing the storage matrix to be detected, the opposite read-write sequence is used for data writing and reading in the adjacent storage arrays in the storage matrix, and when writing data, opposite data is written in the adjacent storage cells in the target storage array, and the data in the storage cells in the target storage array is opposite to the data in the storage cells in the adjacent storage array, that is, the flip relationship exists between the adjacent storage cells, which can more easily detect the pattern sensitive fault; at the same time, the test sequence is flipped after each group of storage arrays is read and written, which can more easily detect the fixed fault, the jump fault and other fault types, in this way, a plurality of types of faults can be effectively detected, and the test item switching time is also reduced, thereby improving the test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A step flow chart of a storage device test method in an embodiment of the present application;

[0025] Figure 2 A data writing schematic diagram of a storage device test method in an embodiment of the present application;

[0026] Figure 3 A structure schematic diagram of a storage device test device in an embodiment of the present application;

[0027] Figure 4 A structure schematic diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0028] To explain the technical content, the achieved purposes and effects of the present application in detail, the following will be explained in combination with the embodiments and the drawings.

[0029] A storage device test method, comprising:

[0030] Traverse each storage array in the storage matrix to be detected, and obtain the read-write sequence of the previous storage array for the target storage array traversed;

[0031] Reverse the read-write sequence to obtain a target read-write sequence, and perform data writing and data reading on the target storage array according to the target read-write sequence;

[0032] Write data in the storage cells in the target storage array in the opposite way, and write data in the storage cells in the target storage array and the adjacent storage array in the opposite way, and sequentially write data in the storage cells in the target storage array;

[0033] Determine whether the data written in the storage cell is consistent with the data read out of the storage cell, and if not, determine that the storage cell has a fault.

[0034] Determine whether all the storage arrays in the storage matrix have completed data writing and data reading. If so, end the test.

[0035] As described above, the beneficial effects of this invention are as follows: When testing the storage matrix to be tested, data is written and read from adjacent storage arrays in the storage matrix in opposite read and write orders. When writing data, opposite data is written into adjacent storage cells in the target storage array, and the data in the storage cells of the target storage array is reversed with that in the storage cells of the adjacent storage arrays. That is, there is a flipping relationship between adjacent storage cells, which makes it easier to detect pattern-sensitive faults. At the same time, the test sequence is flipped after each set of storage arrays is read and written, which also makes it easier to detect fault types such as fixed faults and jump faults. In this way, multiple types of faults can be effectively detected, and there is no need to use multiple algorithms to detect them sequentially, thereby reducing the time for switching test items and improving testing efficiency.

[0036] Further, the step of writing and reading data from the target storage array in the target read / write order includes:

[0037] According to the target read / write order, the target data is written to each of the storage cells in the target storage array in sequence until all the storage cells in the target storage array have been written with data.

[0038] According to the target read / write order, the data of each storage cell in the target storage array is read out sequentially until the data of all storage cells in the target storage array has been read out.

[0039] As described above, by testing data on a storage array basis during data writing and reading, the testing efficiency is improved compared to writing and reading each storage unit sequentially. Furthermore, compared to writing and reading the entire storage matrix, faulty storage units can be quickly identified, thereby improving testing efficiency.

[0040] Furthermore, determining that the data written into the storage unit is inconsistent with the data read from the storage unit includes:

[0041] Based on the data of each storage cell within the target storage array, a write data sequence is obtained;

[0042] The data of each storage cell in the target storage array is read out to obtain a read data sequence;

[0043] Determine whether the read data sequence and the write data sequence are consistent. If they are inconsistent, determine the faulty storage unit based on the read data sequence.

[0044] As described above, by obtaining a write data sequence from the written data and a read data sequence from the read data, and by comparing the read data sequence with the write data sequence, it is possible to more quickly identify faulty storage units.

[0045] Further, the step of writing and reading data from the target storage array in the target read / write order includes:

[0046] Determine whether the data writing to the target storage array is complete; if so, start the timer.

[0047] Determine whether the timing time has reached the delay threshold. If so, read data from the target storage array.

[0048] As described above, by adding a delay threshold after writing data, the data will be stored for a period of time after being written to the storage unit before being read out, thereby effectively detecting data retention faults in the storage unit.

[0049] Furthermore, after the timing is started, it also includes:

[0050] Data is written to the next storage array of the target storage array.

[0051] As described above, by writing data to the next storage array of the target storage array after the timing is started, the test time is increased due to the lack of operation during the delay period, thereby improving the test efficiency.

[0052] Furthermore, before traversing each storage array in the storage matrix to be detected, the process further includes:

[0053] Write zero data to each of the storage cells within the storage matrix.

[0054] As described above, by writing zero data to each storage cell in the storage matrix during testing, i.e., initializing the storage matrix, each storage cell is in the same storage state during testing, thereby ensuring the accuracy of the test.

[0055] Furthermore, each row of the storage matrix is ​​used as the storage array, or each column of the storage matrix is ​​used as the storage array.

[0056] As described above, each row or column of the storage matrix can be used as a storage array, meaning that the storage matrix can be tested row by row or column by column during testing, meeting the testing needs of different scenarios.

[0057] Another embodiment of the present invention provides a storage device testing apparatus, comprising:

[0058] The traversal module is used to traverse each storage array in the storage matrix to be detected, and for the target storage array traversed, obtain the read and write order of the previous storage array.

[0059] The write module is used to reverse the read-write order to obtain the target read-write order, and to write and read data from the target storage array in the target read-write order; and to write data to the storage units in the target storage array sequentially in such a way that the data in adjacent storage units in the target storage array is reversed, and that the data in the storage units in the target storage array is reversed from the data in the storage units in adjacent storage arrays.

[0060] The first judgment module is used to determine whether the data written into the storage unit is consistent with the data read out of the storage unit. If not, it is determined that the storage unit is faulty.

[0061] The second judgment module is used to determine whether all the storage arrays in the storage matrix have completed data writing and data reading. If so, the test ends.

[0062] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the various steps of the storage device testing method described above.

[0063] Another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the various steps in the storage device testing method described above.

[0064] The storage device testing method, apparatus, readable storage medium, and electronic device provided by this invention can be applied to different types of storage device testing scenarios. For example, they can be used to test different generations of products such as LPDDR3, LPDDR4, and LPDDR4X. The following is a detailed description of the specific embodiments:

[0065] Storage device failures are generally categorized into single-cell and multi-cell failures. Single-cell failures primarily include Stuck-at-Fault (SAF), Transition Fault (TF), and Address Faults. Address faults include short circuits, open circuits, or incorrect address decoding on address lines. Multi-cell failures include Bridging Fault (BF) and Coupling Fault (CF). Detection typically involves writing a 1 to the cell under test, then writing a 0, and then reading back a 0. Similarly, it requires writing a 0, then writing a 1, and then reading back a 1 for detection.

[0066] Common testing algorithms include MSCAN, Checkerboard, March C, Butterfly, and Pingpang. These algorithms differ significantly in their read / write methods and testing time complexity, as shown in Table 1.

[0067] Table 1. Time Complexity of the Test Algorithm

[0068]

[0069] The Checkerboard algorithm, also known as the "chessboard algorithm," can detect all Stuck at Fault (SAF) faults. However, its write pattern is a "1-0-1" interval, so it can only detect half of the faults; that is, which fault a cell can detect depends on whether the target cell performs an operation of "1->0" or "0->1".

[0070] The March C algorithm detects faults by performing a series of read and write operations in the memory cell. The basic operations include writing 0 (w0), writing 1 (w1), reading 0 (r0), and reading 1 (r1); it typically uses a read / write strategy of all "0"s or "1"s and is insensitive to coupled-type failure models, especially for pattern-sensitive faults (PSF); however, the March C algorithm can detect all SAF, TF, and AF type faults.

[0071] Both the Checkerboard and March C algorithms perform read and write operations on memory cells in a linear manner, with time complexity proportional to the number of memory cells. This embodiment combines the Checkerboard and March C algorithms. Specifically, the March C algorithm employs a checkerboard-style read / write strategy, using sequences of "010101..." and "101010..." for data writing and reading. This causes the test sequence to flip after each row of memory cells is read or written, ensuring that each cell is written with both 0s and 1s, enabling the detection of both types of faults (TF). The target cells are "1->0" and "0->1", thus reducing the number of test items and shortening the test time. Combining the effects of the two testing algorithms improves testing efficiency. The specific combination method is as follows:

[0072] Please refer to Figure 1 A method for testing a storage device, comprising:

[0073] S0. Write zero data to each of the storage cells in the storage matrix. That is, perform an initialization operation on the storage matrix, for example, starting from the beginning of the storage matrix, write "0" to the memory address cells row by row or column by column.

[0074] S1. Traverse each storage array in the storage matrix to be detected. For each target storage array traversed, obtain the read / write order of the previous storage array. Each row of the storage matrix can be used as a storage array, or each column of the storage matrix can be used as a storage array. For example, a storage device may include an M*N storage matrix. If each row is used as a storage array, it includes M storage arrays; if each column is used as a storage array, it includes N storage arrays.

[0075] S2. Reverse the read / write order to obtain the target read / write order, and perform data writing and data reading on the target storage array in the target read / write order; sequentially write data to the storage units in the target storage array in such a way that the data in adjacent storage units within the target storage array is opposite, and the data in storage units within the target storage array is opposite to the data in storage units within adjacent storage arrays.

[0076] During data writing: The target data is sequentially written to each storage cell within the target storage array according to the target read / write order, until all storage cells in the target storage array have been written with data. For example, in one specific implementation, the read / write order of the previous storage array is in ascending address order; then the target storage array is in descending address order; and "010101..." is sequentially written into the storage cells of the target storage array until the data writing operation to the target storage array is completed.

[0077] During data reading: Data from each storage cell in the target storage array is read sequentially according to the target read / write order until all data from all storage cells in the target storage array has been read. That is, "010101..." is read sequentially until the data reading operation on the target storage array is complete.

[0078] In an optional implementation, a delay time t is added between data writing and data reading to detect the ability of the memory cell (capacitor) to retain data (charge); that is, after writing data, a delay time t is allowed before data reading. There are dynamic RAM memory cells with defective resistance that release charge from the capacitor faster than normal memory cells; therefore, detecting this type of defect requires a delay to determine whether the amount of charge released is greater than that of normal cells. By setting a delay time t, data retention faults (RF) can be effectively detected, as detailed below:

[0079] S21. Determine whether the data writing to the target storage array is complete. If so, start the timer. In an optional implementation, after starting the timer, data can also be written to the next storage array of the target storage array, thereby reducing test time. For example, after writing the first and second rows, the first row is read again. There is a delay t in this process, but this delay t cannot be quantified. Therefore, setting a fixed time t, such as tRFEI (memory refresh interval) or tRFC (row address refresh cycle) defined in the JEDEC protocol, as a fixed delay time t, yields better test results.

[0080] S22. Determine whether the timing time has reached the delay threshold. If so, read the data from the target storage array.

[0081] S3. Determine whether the data written into the storage unit is consistent with the data read from the storage unit. If not, determine that the storage unit is faulty. In an optional implementation, the determination is made in the following way:

[0082] S31. Based on the data of each storage cell in the target storage array, a write data sequence is obtained, for example, the write data sequence is 010101.

[0083] S32. Read the data from each of the storage cells in the target storage array to obtain a read data sequence, for example, the read data sequence is: 010101.

[0084] S33. Determine whether the read data sequence and the write data sequence are consistent. If they are inconsistent, the faulty storage unit is obtained based on the read data sequence. Since the write data sequence is 010101 and the read data sequence is 010101, it indicates that the storage unit in the target storage array is not faulty.

[0085] S4. Determine whether all the storage arrays in the storage matrix have completed data writing and data reading. If so, end the test.

[0086] This embodiment provides a specific testing process, as follows:

[0087] For example, if the storage device is an M*N storage matrix, with each row of the storage matrix as a storage array, its read / write method is: {↑(w0); ↑(w1 or w0), delay t, ↑(r1 or r0); ↓(w0 or w1), delay t, ↓(r0 or r1)}; where ↑ indicates the order of address increment; ↓ indicates the order of address decrement; due to the use of a chessboard-style writing method, the data written to the storage unit is "0" or "1", represented as (w0 or w1); at the same time, the data read out is "0" or "1", represented as (r0 or r1).

[0088] T1. Initialize the storage matrix: Starting from the starting position (1,1), write "0" to each storage cell in ascending order of address.

[0089] T2. Writing the first row of chessboard data: Starting from the starting position (1,1), write the data "0" to the first storage unit and the data "1" to the next storage unit in ascending order of address, that is, write "010101..." in sequence until all storage units in the first row have completed the data writing.

[0090] T3. First row data read verification: Determine whether the time after writing the data has reached the delay time. If the delay time has been reached, start from the starting position (1,1) and read each storage unit in ascending address order, checking the read data "010101...". If the read data sequence is inconsistent with the written data sequence, the corresponding storage unit is faulty. Then, the test sequence is flipped and the read and write test is performed again.

[0091] T4. Proceed to the next row of chessboard data writing: Starting from the starting position (2, N), write data "0" to the first storage unit and data "1" to the next storage unit in descending order of address, and so on, writing "010101..." until all storage units in the second row have completed data writing.

[0092] T5. Second row data read verification: Determine whether the time after writing the data has reached the delay time. If the delay time has been reached, start from the starting position (2, N) and read each storage unit in descending order of address. Check the read data "010101...". If the read data sequence is inconsistent with the written data sequence, the corresponding storage unit is faulty. Then, the test sequence is flipped and the read and write test is performed again.

[0093] T6. Repeat steps T2-T5 above. For example, if row X is written to / read from memory cells in ascending address order, then row X+1 is written to / read from memory cells in descending address order; until all memory cells in the memory array have been read and written. Figure 2 As shown, after steps T1-T6, the changes in the data within the storage matrix are as follows: Figure 2 As shown, the entire string is transformed into a checkerboard pattern of alternating "0"s and "1"s. Steps T1-T6 above constitute the storage unit read / write test algorithm combining March C and Checkerboard; and based on this, a delay t is added between writing data and the next read, which can detect all SAF, TF, AF, CF and RF fault types.

[0094] Example 2

[0095] Please refer to Figure 3 A storage device testing apparatus 100 includes:

[0096] The traversal module 110 is used to traverse each storage array in the storage matrix to be detected, and for the target storage array traversed, to obtain the read and write order of the previous storage array.

[0097] The write module 120 is used to reverse the read-write order to obtain a target read-write order, and to write and read data from the target storage array in the target read-write order; and to write data to the storage units in the target storage array sequentially in such a way that the data in adjacent storage units in the target storage array is reversed, and that the data in the storage units in the target storage array is reversed from the data in the storage units in adjacent storage arrays.

[0098] The first judgment module 130 is used to determine whether the data written into the storage unit is consistent with the data read out of the storage unit. If not, it is determined that the storage unit is faulty.

[0099] The second judgment module 140 is used to determine whether all the storage arrays in the storage matrix have completed data writing and data reading. If so, the test ends.

[0100] Example 3

[0101] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the storage device testing method as described in Embodiment 1.

[0102] Example 4

[0103] Please refer to Figure 4 An electronic device 1 includes a memory 3, a processor 2, and a computer program stored on the memory 3 and executable on the processor 2. When the processor 2 executes the computer program, it implements the various steps in the storage device testing method as described in Embodiment 1.

[0104] In summary, the storage device testing method, apparatus, readable storage medium, and electronic device provided by this invention combine the March C algorithm with the Checkerboard algorithm. Compared to the traditional March C algorithm, the March C algorithm employs a chessboard-like read / write strategy, using sequences of "010101..." and "101010..." for data writing and reading. This causes the test sequence to flip after each row of storage cells is read or written, effectively detecting SAF, TF, AF, and CF fault types. The chessboard relationship between adjacent storage cells also makes it easier to detect pattern-sensitive faults. Furthermore, the addition of a delay between writing data and the next read effectively detects data retention faults compared to traditional algorithms. Both the March C and Checkerboard algorithms have low time complexity, making them applicable even for testing large memory storage devices. Merging the two test items into one reduces test item switching time, significantly improving testing efficiency. Therefore, it not only improves testing efficiency but also has low time complexity, making it suitable for mass production testing.

[0105] In the embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple components or modules may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices, components, or modules may be electrical, mechanical, or other forms.

[0106] The components described as separate parts may or may not be physically separate. The components shown as components may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the components can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each component can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0108] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0109] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0110] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0111] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for testing a storage device, characterized in that, include: Traverse each storage array in the storage matrix to be detected, and for each target storage array traversed, obtain the read / write order of the previous storage array. The target read / write order is obtained by reversing the read / write order, and data is written to and read from the target storage array in the target read / write order. Data is written sequentially to the storage cells within the target storage array in such a manner that the data in adjacent storage cells within the target storage array is opposite, and the data in storage cells within the target storage array is opposite to the data in storage cells within adjacent storage arrays. Determine whether the data written into the storage unit is consistent with the data read from the storage unit; if not, determine that the storage unit is faulty. Determine whether all the storage arrays in the storage matrix have completed data writing and data reading. If so, end the test.

2. The storage device testing method according to claim 1, characterized in that, The step of writing and reading data from the target storage array in the target read / write order includes: According to the target read / write order, the target data is written to each of the storage cells in the target storage array in sequence until all the storage cells in the target storage array have been written with data. According to the target read / write order, the data of each storage cell in the target storage array is read out sequentially until the data of all storage cells in the target storage array has been read out.

3. The storage device testing method according to claim 1, characterized in that, The step of determining whether the data written into the storage unit is consistent with the data read from the storage unit includes: Based on the data written to each of the storage cells in the target storage array, a write data sequence is obtained; The data of each storage cell in the target storage array is read out to obtain a read data sequence; Determine whether the read data sequence and the write data sequence are consistent. If they are inconsistent, determine the faulty storage unit based on the read data sequence.

4. The storage device testing method according to claim 1, characterized in that, The step of writing and reading data from the target storage array in the target read / write order includes: Determine whether the data writing to the target storage array is complete; if so, start the timer. Determine whether the timing time has reached the delay threshold. If so, read data from the target storage array.

5. A method for testing a storage device according to claim 4, characterized in that, After the timing is started, it also includes: Data is written to the next storage array of the target storage array.

6. The storage device testing method according to claim 1, characterized in that, The process of traversing each storage array in the storage matrix to be detected also includes: Write zero data to each of the storage cells within the storage matrix.

7. A method for testing a storage device according to claim 1, 2, 3 or 4, characterized in that, Each row of the storage matrix is ​​used as the storage array, or each column of the storage matrix is ​​used as the storage array.

8. A storage device testing apparatus, characterized in that, include: The traversal module is used to traverse each storage array in the storage matrix to be detected, and for the target storage array that has been traversed, to obtain the read and write order of the previous storage array. The write module is used to reverse the read-write order to obtain the target read-write order, and to write and read data from the target storage array in the target read-write order; and to write data to the storage units in the target storage array sequentially in such a way that the data in adjacent storage units in the target storage array is reversed, and that the data in the storage units in the target storage array is reversed from the data in the storage units in adjacent storage arrays. The first judgment module is used to determine whether the data written into the storage unit is consistent with the data read from the storage unit. If not, it is determined that the storage unit is faulty. The second judgment module is used to determine whether all the storage arrays in the storage matrix have completed data writing and data reading. If so, the test ends.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements each step of the storage device testing method as described in any one of claims 1-7.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements each step of the storage device testing method as described in any one of claims 1-7.

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