Packaging method for reducing chip RDSON resistance based on multi-layer metal structure

Abstract

The present invention discloses a packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure, relating to the technical field of chip packaging. The chip packaging structure based on the multi-layer metal structure includes a chip base layer, multiple metal layers, and an electroplating layer arranged in a straight line, wherein the multiple metal layers include an adhesion layer, a connection layer, and a bonding layer. The method comprises the following steps: performing cleaning pretreatment using a plasma cleaning method, and performing abnormality detection and analysis, and performing a first abnormality analysis and / or a second abnormality analysis after obtaining the detection data; performing sputtering deposition of the multiple metal layers using a physical vapor deposition process, and intelligently adjusting the sputtering parameters; applying photoresist to the top surface of the multiple metal layers, and performing exposure and development; and depositing thick copper using an electroplating process. The method can improve the deposition quality of each metal layer to ensure the stability and performance of the multi-layer metal structure.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure. Background Art

[0002] Wafer-Level Chip Scale Packaging (WLCSP) is an advanced semiconductor packaging technology. Its characteristic is that most or all packaging process steps are completed directly on the wafer. The size of the final cut single package is almost the same as the size of the chip itself, that is, the chip size, and the lead frame or substrate and bonding wires commonly used in traditional packaging are eliminated.

[0003] In addition, the RDSON value of a WLCSP chip is one of the important indicators for judging the chip's performance. That is, a smaller RDSON resistance value increases the chip's on-current. Specifically, WLCSP reduces the chip's RDSON resistance value through the following aspects: first, eliminating the resistance of the bond wire; second, constructing a three-dimensional low-resistance path through copper pillars and redistribution layers (RDL); and third, optimizing heat dissipation.

[0004] Currently, multi-layer metal sputtering combined with electroplating process is used to package chip RDSON, but how to accurately control the thickness and quality of each metal layer to ensure the stability and performance of the multi-layer metal structure has become an urgent problem to be solved by people in this field. Summary of the Invention

[0005] The object of the present invention is to provide a packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure, so as to solve the problems raised in the above background technology.

[0006] In order to solve the above technical problems, the present invention provides the following technical solution: a packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure, comprising the following steps:

[0007] S1: Perform cleaning pretreatment using plasma cleaning, and perform mutation detection and analysis. After obtaining the detection data, perform the first mutation analysis and / or the second mutation analysis;

[0008] S2: Using a physical vapor deposition process to perform sputtering deposition of multiple metal layers, and intelligently adjusting sputtering parameters, the sputtering parameters including sputtering power P and working pressure F, and the sputtering power and working pressure are both positively correlated with the deposition rate.

[0009] The chip packaging structure based on a multi-layer metal structure includes a chip base layer, multiple metal layers, and an electroplating layer arranged in a straight line. During the cleaning pretreatment cleaning, plasma technology is used in the cleaning chamber to remove pollutants such as oxides and / or organic matter on the surface of the chip base layer to ensure the adhesion of the multi-layer metal layer; then a vacuum robot is used to send the chip base layer to the magnetron sputtering equipment for subsequent deposition process.

[0010] The fixed movement path that the chip substrate travels from the cleaning pretreatment step to the sputtering deposition step is determined and recorded as the movement path distance L. A point p is set on the movement path distance L. The point p is used to perform the first step of the abnormality analysis. The first detection module and a number of detection points corresponding to the surface of the chip substrate are set at the point p. The point p position is determined by the p value. The p value is the ratio of the path distance from the starting point of the movement path to the location of the first detection module to the movement path distance L, and 0 < p ≤ 1;

[0011] The first step of variation analysis is used to determine the qualified status of the oxide layer thickness at each inspection point of the chip substrate and the normal status of the corresponding total variation value; the second step of variation analysis is to calculate the terminal oxidation data of the chip substrate based on the p value not equal to 1 and the normal total variation value, and then compare it with the oxide layer thickness limit and the total variation limit respectively to select the corresponding process, which includes sputtering, replacement, and local cleaning.

[0012] The present invention is further described, and further comprises:

[0013] S3: applying photoresist on the top surface of the multi-layer metal layer and performing exposure and development;

[0014] S4: depositing thick copper using electroplating, followed by stripping and annealing;

[0015] S5: Prepare solder bumps for connecting to PCB boards, then cut the wafers and perform corresponding electrical performance tests.

[0016] The present invention further illustrates that a cleaning chamber is used for cleaning pretreatment, and a magnetron sputtering device is used for sputtering deposition of multiple metal layers. A vacuum manipulator is arranged between the cleaning chamber and the magnetron sputtering device. A multi-target sputtering chamber is arranged in the magnetron sputtering device. Argon ions are used to continuously bombard the metal target material to continuously deposit different materials. The adhesion layer is used to block the diffusion of copper atoms. The connecting layer can be used as a seed layer for copper electroplating to provide a conductive base. The bonding layer is used to reduce the starting resistance of electroplating and ensure the uniform growth of the electroplated copper layer.

[0017] The present invention further describes that the first detection module is composed of several ranging units, the outer circle size of the first detection module is consistent with the chip base layer, and the several ranging units are evenly laid inside the outer circle; the ranging units use infrared emission and receiving technology to detect the degree of oxidation on the surface of the chip base layer.

[0018] The present invention further states that the first detection module is used to measure the thickness change of the chip substrate and record it as the total value of the abnormal change The formula for calculating the total value of the chip base layer mutation is: ;

[0019] n is the total number of distance measuring units laid out in the outer circle of the first detection module, i is the marking serial number of the distance measuring unit, i is an integer between 1 and n, h i Indicates the oxide layer thickness measured by the ranging unit marked with serial number i.

[0020] The present invention further illustrates that setting h s is the oxide layer thickness limit, when h i >h s When , it means that the thickness of the oxide layer at the i-th position of the chip base layer is unqualified;

[0021] set up s is the total mutation limit, when Between 0- s, it indicates that the total value of the abnormality is normal; the moving path distance L corresponds to the distance between the vacuum manipulator taking the cleaning chamber suction point as the starting point of the moving path and the magnetron sputtering equipment placement point as the end point of the moving path.

[0022] The present invention further illustrates that the first step of mutation analysis is as follows:

[0023] Case I: If h i ≤h s , 0≤ ≤ s, indicating that the oxide layer thickness of each test point on the chip substrate is qualified and the total value of the abnormal variation is normal;

[0024] Case II: If h i ≤h s , > When s, it means that the oxide layer thickness of each test point on the chip substrate is qualified, but the total value of the abnormal variation is higher than the normal range;

[0025] Case III: If there is at least one h i >h s , 0≤ ≤ s, it means that the thickness of the oxide layer at least at one detection point on the chip substrate is unqualified, but the total value of the abnormal variation is normal;

[0026] Case IV: If there is at least one h i >h s , > s, it means that the oxide layer thickness of at least one detection point on the chip substrate is unqualified, and the total value of the abnormality is higher than the normal range.

[0027] The present invention further illustrates that the second step of mutation analysis includes:

[0028] When the p-value is not equal to 1 and 0≤ ≤ s, the second step of asynchronous analysis is required;

[0029] For cases I and III, calculate the terminal oxidation data, and then compare them with the oxide layer thickness limit and the total variation limit to further determine the case:

[0030] when , 0≤ ≤ When s, it still belongs to case I, and the sputtering process in S2 is performed;

[0031] When there is , 0≤ ≤ At s, it still belongs to situation III. The vacuum robot will drive the chip substrate back to the cleaning chamber to perform plasma local cleaning at the chip substrate position corresponding to i, and then perform the sputtering process in S2.

[0032] The present invention further states that when the p value is equal to 1 or when the p value is not equal to 1 and > s, the second step of asynchronous analysis is not performed.

[0033] The present invention further states that the ideal layer thickness of the corresponding metal layer is recorded as A, A=V*T+§, where V is the deposition rate, T is the deposition time, and § is the compensation coefficient used to obtain the ideal layer thickness under the set deposition time;

[0034] During the sputtering process, an ellipsometer is used to monitor the actual layer thickness of the corresponding metal layer in real time, recorded as As. During the monitoring process, the actual layer thickness As is compared with the ideal layer thickness A, and the power and / or working pressure are adjusted in real time according to the comparison results.

[0035] Compared with the prior art, the beneficial effects achieved by the present invention are: vacuum transfer is used to transfer the chip substrate between the cleaning chamber and the magnetron sputtering equipment of the present invention, oxidation data is pre-detected during the transfer process, and the first step variation analysis and / or the second step variation analysis are performed; not only can the position point where the oxide layer thickness is unqualified be clearly located, but the terminal oxidation data of the chip substrate can also be inferred during the movement path of the vacuum manipulator, and remedial measures can be inferred in advance, which can not only save processing time but also ensure the adhesion of multiple metal layers in subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0037] Figure 1 It is a schematic diagram of the chip packaging structure of the present invention;

[0038] Figure 2 It is a schematic diagram of the packaging method of the present invention;

[0039] Figure 3 is a schematic diagram of a first detection module of the present invention;

[0040] Figure 4 It is a schematic diagram of the movement path of the vacuum manipulator of the present invention;

[0041] In the figure: 1. Chip base layer; 2. Multi-layer metal layer; 21. Adhesion layer; 22. Connection layer; 23. Bonding layer; 3. Electroplating layer; 4. First detection module; 41. Distance measurement unit. DETAILED DESCRIPTION

[0042] The following is a non-limiting detailed description of the technical solutions of the present invention in conjunction with preferred embodiments and the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are also within the scope of protection of the present invention.

[0043] See also Figure 1 The present invention provides a technical solution: a packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure. The packaging method is applied to a chip packaging structure based on a multi-layer metal structure, comprising a chip base 1, a multi-layer metal layer 2 is provided on the top surface of the chip base 1, and a plating layer 3 of a certain thickness is provided on the upper surface of the multi-layer metal layer 2. Figure 1The multilayer metal layer 2 includes an adhesion layer 21, a connection layer 22, and a bonding layer 23 arranged in sequence above the chip base layer 1. The adhesion layer 21 is preferably Ti metal, the connection layer 22 is preferably Ni metal layer, and the bonding layer 23 is preferably Ag metal layer. The thickness of the adhesion layer 21 is designed to be a, the thickness of the connection layer 22 is designed to be 2a, and the bonding layer 23 is designed to be 3a~5a; wherein, the multilayer metal layer 2 is formed in a magnetron sputtering device, and physical vapor deposition technology is adopted, that is, orthogonal electromagnetic fields are used to constrain electron motion, thereby increasing the gas ionization rate and enhancing the sputtering efficiency; based on the above-mentioned multilayer metal sputtering and electroplating process, the deposition of the multilayer metal layer 2 and the electroplating layer 3 is realized, so as to realize ultra-low resistance vertical interconnection for the subsequent copper pillar bump, thereby eliminating the bonding wire in the traditional package, thereby effectively reducing the chip RDSON resistance.

[0044] refer to Figure 2 The specific packaging method based on multi-layer metal structure to reduce the chip RDSON resistance is as follows:

[0045] S1: Use plasma cleaning to perform cleaning pretreatment and perform mutation detection and analysis.

[0046] The cleaning chamber for cleaning and pre-treating the chip substrate 1 and the magnetron sputtering equipment for depositing the multi-layer metal layer 2 can be a cluster design or a separate design; however, the chip substrate 1 is transferred between the cleaning chamber and the magnetron sputtering equipment by vacuum transfer, with the cleaning chamber using a low-pressure environment and the magnetron sputtering equipment using a vacuum environment;

[0047] During the cleaning pretreatment, plasma technology is used in the cleaning chamber to remove pollutants such as oxides and / or organic matter on the surface of the chip substrate 1 to ensure the adhesion of the multi-layer metal layer 2; then a vacuum robot is used to send the chip substrate 1 to the magnetron sputtering equipment for subsequent deposition process.

[0048] The fixed movement path that the chip substrate travels from the cleaning pretreatment step to the sputtering deposition step is determined and recorded as the movement path distance L. A point position p is set on the movement path distance L. Point position p is used for the first step of abnormality analysis. A first detection module is set at point p and a number of detection points corresponding to the surface of the chip substrate are set.

[0049] The position of point p is determined by the p value, which is the ratio of the path distance from the starting point of the moving path to the position of the first detection module 4 to the moving path distance L, where 0<p≤1.

[0050] The pressure inside the vacuum manipulator is not higher than 10 -5 Pa, the first detection module 4 set at point p in the fixed moving path of the vacuum manipulator is used to measure the thickness change of the chip substrate 1 and record it as the total value of the abnormal change ,refer to Figure 3 The first detection module is composed of several distance measuring units 41. The outer ring size of the first detection module 4 is consistent with the chip substrate 1. Several distance measuring units 41 are evenly laid inside the outer ring. The distance measuring units 41 use infrared emission and receiving technology to detect the oxidation degree of the surface of the chip substrate 1. The surface oxidation degree is determined according to the total value of the abnormality. And determined to ensure the subsequent deposition effect of the multi-layer metal layer 2;

[0051] Specifically, the general formula for calculating the total variation value of the chip substrate 1 is: , n is the total number of distance measuring units 41 laid in the outer circle of the first detection module 4, i is the marking number of the distance measuring unit 41, i is an integer between 1 and n, h i The thickness of the oxide layer measured by the distance measuring unit 41 marked with the serial number i, h i The ideal value of is 0, so the ideal value of the abnormal thickness is also 0.

[0052] Set h s is the oxide layer thickness limit, usually h s Not more than 3 angstroms, set according to specific needs; when h i >h s When , it means that the thickness of the oxide layer at the i-th location of the chip substrate 1 is unqualified. Here, you can return to the plasma equipment to perform local cleaning for this location, and ensure the qualified thickness of the oxide layer by supplementary cleaning;

[0053] set up s is the total mutation limit, when Between 0- When it is between s, it means that the total value of abnormality is normal;

[0054] Specifically, after obtaining the test data, the first step of mutation analysis and the second step of mutation analysis will be carried out;

[0055] The first step of mutation analysis is performed based on the mutation detection results of chip substrate 1:

[0056] Case I: If h i ≤h s , 0≤ ≤ s, indicating that the oxide layer thickness of each test point of chip substrate 1 is qualified and the total value of abnormal variation is normal;

[0057] Case II: If h i ≤h s , > s, indicating that the oxide layer thickness of each test point of chip substrate 1 is qualified, but the total value of abnormal variation is higher than the normal range;

[0058] Case III: If there is at least one h i >h s , 0≤ ≤ s, it means that the oxide layer thickness of at least one detection point of the chip substrate 1 is unqualified, but the total value of the abnormal variation is normal;

[0059] Case IV: If there is at least one h i >h s , > s, it means that the oxide layer thickness of at least one detection point of the chip substrate 1 is unqualified, and the total value of the abnormal variation is higher than the normal range;

[0060] refer to Figure 4 , L corresponds to the distance between the vacuum manipulator and the cleaning chamber suction point as the starting point of the moving path and the magnetron sputtering device placement point as the end point of the moving path, and the p value is the ratio of the path distance from the starting point of the moving path to the position of the first detection module to the moving path distance L, 0<p≤1;

[0061] The second step of mutation analysis is performed based on the mutation detection results of chip substrate 1:

[0062] The terminal oxide layer thickness prediction value is calculated by the back-end processor and the total predicted value of terminal mutation , thereby calculating the terminal oxidation data of the chip substrate 1, namely the terminal oxide layer thickness prediction value and the terminal variation sum prediction value, and then comparing them with the oxide layer thickness limit and the variation sum limit respectively;

[0063] First, when the p value is equal to 1, the second step of asynchronous analysis is not performed. Among the above four cases, only cases I and II meet the sputtering criteria; therefore, the sputtering process in S2 is executed.

[0064] Second, when the p-value is not equal to 1 and > s, the second step of mutation analysis is not performed because the > s, it is inferred that the mobile environment parameters need to be adjusted, and the calculation of the terminal oxidation data is meaningless. The amount of oxide layer generated can be reduced by adjusting the environmental parameters, including but not limited to vacuum upgrade, low temperature and / or plasma reduction, etc., to achieve effective oxidation prevention and control in the mobile environment where the vacuum manipulator is located, and ensure that the later RDSON and interconnection resistance reach the theoretical design value. The degree of adjustment is Positive correlation; therefore, directly replace the chip substrate 1, re-clean and pre-treat the new chip substrate 1, and apply it to the adjusted mobile environment;

[0065] Afterwards, when the p-value is not equal to 1 and 0≤ ≤ s, a second step of asynchronous analysis is required. Specifically, the terminal oxidation data is calculated for Cases I and III, and then compared with the oxide layer thickness limit and the total variation limit respectively to further determine the case:

[0066] when , 0≤ ≤ When s, it still belongs to case I, and the sputtering process in S2 is performed;

[0067] When there is , 0≤ ≤ At s, it still belongs to situation III. The vacuum robot will drive the chip substrate 1 back to the cleaning chamber to perform plasma local cleaning on the position of the chip substrate 1 corresponding to i, and then perform the sputtering process in S2;

[0068] Compared with the case of p=1, through the settings of the first step variation analysis and the second step variation analysis, not only the location point of the unqualified oxide layer thickness is clearly located, but it should be noted that the more n, the more accurate the positioning; in addition, the terminal oxidation data of the chip base layer 1 can be inferred during the movement path of the vacuum manipulator, and remedial measures can be taken in advance, which can not only save processing time but also ensure the adhesion of the multi-layer metal layer 2 in the subsequent process.

[0069] S2: performing sputtering deposition of the multi-layer metal layer 2 using a physical vapor deposition process, and intelligently adjusting the sputtering parameters.

[0070] A multi-target sputtering chamber is set in the magnetron sputtering equipment, and argon ions are used to continuously bombard the metal target material to continuously deposit different materials. The adhesion layer 21 is used to block the diffusion of copper atoms. The connecting layer 22 can serve as a seed layer for copper electroplating and provide a conductive base. The bonding layer 23 is used to reduce the starting resistance of electroplating and ensure the uniform growth of the electroplated copper layer.

[0071] The above-mentioned sputtering parameters include sputtering power P and working gas pressure F; sputtering power and working gas pressure are both positively correlated with deposition rate;

[0072] The ideal layer thickness of the corresponding metal layer is recorded as A, A=V*T+§, V is the deposition rate, T is the deposition time, § is the compensation coefficient, which has the same unit level as a, usually ranging from 0 to 0.1 times, and is determined according to the specific sputtering environment. It is used to obtain the ideal layer thickness under the set deposition time. Under the set parameters of V and T, the parameters in the actual sputtering process fluctuate. In order to ensure the ideal accuracy of the obtained data, the range of the ideal layer thickness of the corresponding metal layer is determined by setting the compensation coefficient, which is convenient for subsequent comparison.

[0073] Before the sputtering process begins, a vacuum robot moves the chip base layer 1 to the substrate mounting position and completes the installation. Subsequently, multiple metal layers 2 are sputtered sequentially under the initial sputtering parameters. During the sputtering process, the actual layer thickness of the corresponding metal layer is monitored in real time using an ellipsometer. During the monitoring process, the actual layer thickness As is compared with the ideal layer thickness A, and the power and / or working pressure are adjusted in real time based on the comparison results.

[0074] When sputtering the first metal layer, i.e., the adhesion layer 21, if the actual layer thickness As at the first set time point does not reach the corresponding ideal layer thickness A, the thickness difference ∆A is first determined, and then the sputtering power is adjusted and increased. The specific increase value is positively correlated with the thickness difference ∆A, so that the first metal layer can reach the ideal layer thickness within the preset deposition time.

[0075] When sputtering the second metal layer, i.e., the connecting layer 22, if the actual layer thickness As at the second set time point does not reach the corresponding ideal layer thickness A, the working gas pressure F is further adjusted first, and then the adjusted sputtering power is maintained to continue the deposition process of the second metal layer. After the working gas pressure F is adjusted, it is ensured that the deposition thickness can make up for the previously missing thickness difference. If the ideal layer thickness is still not reached at the third set time point, an alarm is issued, and sputtering of subsequent layers is discontinued. The magnetron sputtering equipment is then maintained and inspected to find the cause of the sputtering failure.

[0076] Otherwise, after the multi-level metal layer 2 is sputtered to an ideal layer thickness in the unadjusted or adjusted process, the magnetron sputtering equipment will be taken out and the next process will be carried out.

[0077] S3: Photoresist is applied to the top surface of the multi-layer metal layer, and is exposed and developed to determine the electroplating area and form a micron-level window.

[0078] S4: depositing thick copper using electroplating, followed by stripping and annealing;

[0079] The thickness of the electroplated copper layer is 20-25 microns, and the copper layer is deposited on the bonding layer 23 using an electroplating process; then the photoresist is removed, and thermal annealing is used to eliminate electroplating stress and enhance the bonding strength of the copper grains.

[0080] S5: Prepare solder bumps for connecting to the PCB board, then cut the wafer and perform corresponding electrical performance tests to verify whether the reduction in RDSON resistance meets the standard.

[0081] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only used to facilitate the description of the present invention, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0082] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will appreciate that modifications may be made to the technical solutions described in the aforementioned embodiments, or that some of the technical features may be replaced with equivalents. Such modifications or replacements do not deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A packaging method for reducing chip RDSON resistance based on a multi-layer metal structure, applied to a chip packaging structure based on a multi-layer metal structure, wherein the structure comprises a chip base layer, multiple metal layers, and an electroplating layer arranged in a straight line, wherein the multiple metal layers include an adhesion layer, a connection layer, and a bonding layer; characterized in that: The following steps are involved: S1: Perform cleaning pretreatment using plasma cleaning, and perform mutation detection and analysis. After obtaining the detection data, perform the first mutation analysis and / or the second mutation analysis; S2: Using a physical vapor deposition process to perform sputtering deposition of multiple metal layers, and intelligently adjusting sputtering parameters, including sputtering power P and working pressure F, which are both positively correlated with the deposition rate; The fixed movement path of the chip substrate from the cleaning pretreatment step to the sputtering deposition step is determined and recorded as the movement path distance L. A point position p is set on the movement path distance L. The point position p is used to perform the first step of the abnormality analysis. The first detection module is set at the point position p and a number of detection points corresponding to the surface of the chip substrate are correspondingly set. The position of point p is determined by a p value, which is the ratio of the path distance from the starting point of the moving path to the location of the first detection module to the moving path distance L, where 0<p value≤1; The first step of variation analysis is used to determine the qualified status of the oxide layer thickness at each detection point of the chip substrate and the normal status of the corresponding total variation value; the second step of variation analysis calculates the terminal oxidation data of the chip substrate based on the p value not being equal to 1 and the normal total variation value, and then compares it with the oxide layer thickness limit and the total variation limit respectively to select the corresponding process, which includes sputtering, replacement, and local cleaning.

2. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 1, characterized in that: Also includes: S3: applying photoresist on the top surface of the multi-layer metal layer and performing exposure and development; S4: depositing thick copper using electroplating, followed by stripping and annealing; S5: Prepare solder bumps for connecting to PCB boards, then cut the wafers and perform corresponding electrical performance tests.

3. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 1, characterized in that: The cleaning pretreatment uses a cleaning chamber, the sputtering deposition of the multi-layer metal layer uses a magnetron sputtering device, and a vacuum manipulator is provided between the cleaning chamber and the magnetron sputtering device.

4. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 3, characterized in that: The first detection module is composed of a plurality of distance measuring units. The outer circle size of the first detection module is consistent with the chip substrate, and the plurality of distance measuring units are evenly laid inside the outer circle.

5. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 4, characterized in that: The first detection module is used to measure the thickness change of the chip substrate and record it as the total value of the abnormal change The total calculation formula of the variation value of the chip substrate is: ; n is the total number of distance measuring units laid out in the outer circle of the first detection module, i is the marking serial number of the distance measuring unit, i is an integer between 1 and n, h i Indicates the oxide layer thickness measured by the ranging unit marked with serial number i.

6. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 5, characterized in that: Set h s is the oxide layer thickness limit, when h i >h s When , it means that the thickness of the oxide layer at the i-th position of the chip base layer is unqualified; set up s is the total mutation limit, when Between 0- s, it indicates that the total value of the abnormality is normal; the moving path distance L corresponds to the distance between the vacuum manipulator taking the cleaning chamber suction point as the starting point of the moving path and the magnetron sputtering equipment placement point as the end point of the moving path.

7. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 6, characterized in that: The first step of mutation analysis is as follows: Case I: If h i ≤h s , 0≤ ≤ s, indicating that the oxide layer thickness of each test point on the chip substrate is qualified and the total value of the abnormal variation is normal; Case II: If h i ≤h s , > When s, it means that the oxide layer thickness of each test point on the chip substrate is qualified, but the total value of the abnormal variation is higher than the normal range; Case III: If there is at least one h i >h s , 0≤ ≤ s, it means that the thickness of the oxide layer at least at one detection point on the chip substrate is unqualified, but the total value of the abnormal variation is normal; Case IV: If there is at least one h i >h s , > s, it means that the oxide layer thickness of at least one detection point on the chip substrate is unqualified, and the total value of the abnormality is higher than the normal range.

8. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 7, characterized in that: The second step of mutation analysis is as follows: When the p-value is not equal to 1 and 0≤ ≤ s, the second step of asynchronous analysis is required; For cases I and III, calculate the terminal oxidation data, and then compare them with the oxide layer thickness limit and the total variation limit to further determine the case: when , 0≤ ≤ When s, it still belongs to case I, and the sputtering process in S2 is performed; When there is , 0≤ ≤ At s, it still belongs to situation III. The vacuum robot will drive the chip substrate back to the cleaning chamber to perform plasma local cleaning at the chip substrate position corresponding to i, and then perform the sputtering process in S2.

9. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 7, characterized in that: When the p-value is equal to 1 or when the p-value is not equal to 1 and > s, the second step of asynchronous analysis is not performed.

10. The packaging method for reducing chip RDSON resistance based on a multi-layer metal structure according to claim 1 or 9, characterized in that: The ideal layer thickness of the corresponding metal layer is recorded as A, A=V*T+§, where V is the deposition rate, T is the deposition time, and § is the compensation coefficient used to obtain the ideal layer thickness under the set deposition time; During the sputtering process, an ellipsometer is used to monitor the actual layer thickness of the corresponding metal layer in real time, recorded as As. During the monitoring process, the actual layer thickness As is compared with the ideal layer thickness A, and the power and / or working pressure are adjusted in real time according to the comparison results.

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