Digital phase detector and digital phase-locked loop

Abstract

The invention discloses a digital phase detector and a digital phase-locked loop, and the digital phase detector comprises a bang-bang phase detector which is used for receiving a reference signal, and the reference signal generates a group of delay signals through a delay chain; the digital-to-time converter is used for receiving the first signal fed back from the multimode frequency eliminator and delaying the first signal to generate a feedback signal; the digital time converter is connected with the bang-bang phase detector and is used for compensating a quantization error in a decimal mode when the loop is locked; the multiplexer is used for selecting a first delay signal lagging behind the feedback signal; the digital-to-time converter is configured to generate an adjustable delay according to the first delayed signal to align the feedback signal with the first delayed signal. According to the embodiment of the invention, the wide detection range and fine resolution of the digital phase detector are improved under the condition that the linearity and power consumption are not sacrificed; the circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a digital phase detector and a digital phase-locked loop. Background Art

[0002] The development of cellular mobile communication technology requires higher and higher data throughput. The fifth-generation (5G) new radio technology makes full use of the high-frequency band, wide channel bandwidth, and complex modulation schemes to meet the demand for high data rates. However, this imposes strict constraints on the phase noise (PN) and spurs of the local oscillator (LO). For example, in the 28-GHz band, to accommodate 64-QAM and 2x2 MIMO under suboptimal conditions, the allowed LO integrated jitter is only 171 femtoseconds, while in the 39-GHz band, this threshold is further tightened to 126 femtoseconds. The LO integrated jitter ultimately depends on the performance of the phase-locked loop. In related technologies, the counter-based phase-locked loop is prone to generating in-band fractional spurs; the divider-based phase-locked loop is prone to generating accumulated quantization errors; the designs of other solutions have limited improvement in detection range and resolution, and will sacrifice linearity and power consumption at the same time. Summary of the Invention

[0003] The main purpose of the embodiments of this application is to propose an efficient digital phase detector and a digital phase-locked loop.

[0004] To achieve the above purpose, on the one hand, an embodiment of this application proposes a digital phase detector, including a bang-bang phase detector for receiving a reference signal, and the reference signal generates a set of delayed signals through a delay chain; a digital time converter for receiving a first signal fed back from a multi-mode divider, and generating a feedback signal after delaying the first signal; the digital time converter is connected to the bang-bang phase detector and is used to compensate for the quantization error in the fractional mode when the loop is locked; a multiplexer for selecting the first delayed signal that lags behind the feedback signal for the first time; the digital time converter is used to generate an adjustable delay according to the first delayed signal so that the feedback signal is aligned with the first delayed signal. Through the combination of the bang-bang phase detector and the digital time converter in the embodiments of this application, it is beneficial to improve the wide detection range and fine resolution of the digital phase detector without sacrificing linearity and power consumption.

[0005] In some embodiments, for the digital phase detector provided by the embodiments of this application, the digital phase detector further includes a decoder;

[0006] The bang-bang phase detector is used to compare the delay signal and the feedback signal to generate a first error signal, and the decoder is used to decode the first error signal into a digital signal to determine a significant signal based on the difference between the digital signal and the coarse precision control signal; the coarse precision control signal is generated by a digital calibration module, and the coarse precision control signal is also used to control the multiplexer; the significant signal is used to represent the significant part of the phase error.

[0007] In some embodiments, for the digital phase detector provided in the embodiments of the present application, the multiplexer is used to generate a fine signal based on the first error signal, and the fine signal is used to represent the fine part of the phase error;

[0008] The digital calibration module is used to receive the fine signal and the fractional frequency control word to generate a coarse precision control signal and a fine precision control signal, and the fine precision control signal is used to control the digital time converter.

[0009] In some embodiments, for the digital phase detector provided in the embodiments of the present application, the second error signal is the difference between the reference signal and the first signal;

[0010] When the second error signal is within the dead zone of the time-to-digital converter, the significant signal is 0 or -1; the function of the time-to-digital converter is provided by the bang-bang phase detector;

[0011] The fine signal is input to the main path of the digital loop filter to optimize the loop bandwidth with low integral jitter; the significant signal is input to the fast lock path of the digital loop filter to optimize the loop bandwidth for fast locking; the main path and the fast lock path have different coefficients;

[0012] When the digital phase-locked loop is approaching lock, the bang-bang phase detector is used to switch to bang-bang operation.

[0013] In some embodiments, for the digital phase detector provided in the embodiments of the present application, the second error signal is the difference between the reference signal and the first signal;

[0014] The digital time converter is used to generate an adjustable delay to compensate for the low significant bits of the second error signal;

[0015] The bang-bang phase detector is used to generate an adjustable delay to compensate for the high significant bits of the second error signal.

[0016] On the other hand, the embodiments of the present application provide a digital phase-locked loop, including the above digital phase detector, and the digital phase-locked loop further includes: a digital loop filter, an oscillator, and a multi-mode frequency divider;

[0017] The digital phase detector is connected to the oscillator through the digital loop filter, and the oscillator is connected to the digital loop filter through the multi-mode frequency divider.

[0018] In some embodiments, for the digital phase-locked loop provided in the embodiments of the present application, the digital phase detector further includes a frequency divider;

[0019] The signal output by the oscillator is divided by the frequency divider, and the divided signal is input to the multi-mode frequency divider;

[0020] The multi-mode frequency divider is controlled by a MASH1-1 differential integral modulator.

[0021] In some embodiments, for the digital phase-locked loop provided in the embodiments of the present application, the third error signal is a normalized quantization error; the digital phase-locked loop further includes a digital calibration module;

[0022] The digital calibration module is configured to receive the third error signal and the fine signal, and generate a fine precision control signal and a coarse precision control signal through processing by a least mean square algorithm.

[0023] The embodiments of the present application at least include the following beneficial effects: The digital phase detector provided in the embodiments of the present application includes: a bang-bang phase detector for receiving a reference signal, and the reference signal generates a set of delayed signals through a delay chain; a digital time converter for receiving a first signal fed back from a multi-mode frequency divider, and generating a feedback signal after delaying the first signal; the digital time converter is connected to the bang-bang phase detector for compensating for the quantization error in the fractional mode when the loop is locked; a multiplexer for selecting a first delayed signal that lags behind the feedback signal for the first time; the digital time converter is configured to generate an adjustable delay according to the first delayed signal so that the feedback signal is aligned with the first delayed signal. The embodiments of the present application combine a bang-bang phase detector with a digital time converter, which is beneficial to improving the wide detection range and fine resolution of the digital phase detector without sacrificing linearity and power consumption. Description of the Drawings

[0024] Figure 1 is a schematic structural diagram of an embodiment of a digital phase detector provided by the related art;

[0025] Figure 2 is a schematic structural diagram of an embodiment of a digital phase detector of DTC provided by the related art;

[0026] Figure 3 is a schematic principle diagram of an embodiment of a digital phase detector of DTC provided by the related art;

[0027] Figure 4 It is a schematic structural diagram of an embodiment of the digital phase detector of the TDC provided by the related art;

[0028] Figure 5 It is a schematic principle diagram of an embodiment of the digital phase detector of the TDC provided by the related art;

[0029] Figure 6 It is a schematic structural diagram of an embodiment of the digital phase detector provided by the present application;

[0030] Figure 7 It is a schematic principle diagram of an embodiment of the digital phase detector provided by the present application;

[0031] Figure 8 It is a schematic structural diagram of an embodiment of the digital phase-locked loop provided by the present application;

[0032] Figure 9 It is a schematic diagram of the output jitter of an embodiment of the digital phase-locked loop provided by the present application;

[0033] Figure 10 It is a schematic diagram of the frequency locking process of an embodiment of the digital phase-locked loop provided by the present application;

[0034] Figure 11 It is a schematic diagram of the frequency change process of an embodiment of the digital phase-locked loop provided by the present application;

[0035] Figure 12 It is a schematic diagram of the effect of fractional spurs of an embodiment of the digital phase-locked loop provided by the present application. Detailed implementation manners

[0036] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application described in detail in the appended claims.

[0037] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0038] The terms "at least one", "a plurality of", "each", "any one", etc. used in this application, where at least one includes one, two, or more than two, a plurality of includes two or more than two, each refers to each of the corresponding plurality, and any one refers to any one of the plurality.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0040] The development of cellular mobile communication technology requires increasingly high data throughput. The fifth-generation (5G) new radio technology makes full use of the high-frequency band, wide channel bandwidth, and complex modulation schemes to meet the demand for high data rates. However, this imposes strict constraints on the phase noise (PN) and spurs of the local oscillator (LO). For example, in the 28-GHz band, to accommodate 64-QAM and 2x2 MIMO under suboptimal conditions, the allowed LO integrated jitter is only 171 femtoseconds, while in the 39-GHz band, this threshold is further tightened to 126 femtoseconds. The LO integrated jitter ultimately depends on the performance of the phase-locked loop. In related technologies, the counter-based phase-locked loop is prone to generating in-band fractional spurs; referring to Figure 1 the frequency divider-based phase-locked loop shown, this structure is prone to generating accumulated quantization errors; the designs of other solutions have limited improvement in detection range and resolution, and at the same time will sacrifice linearity and power consumption.

[0041] In view of this, an embodiment of this application provides a digital phase detector, aiming to improve the detection range and resolution.

[0042] An embodiment of the digital phase detector provided by the embodiments of this application includes:

[0043] a bang-bang phase detector for receiving a reference signal, and the reference signal generates a set of delayed signals through a delay chain;

[0044] A digital time converter for receiving a first signal fed back from a multi-modulus divider, delaying the first signal and generating a feedback signal;

[0045] The digital time converter is connected to the bang-bang phase detector and is used to compensate for the quantization error in the fractional mode when the loop is locked;

[0046] A multiplexer for selecting a first delayed signal that lags behind the feedback signal for the first time; the digital time converter is used to generate an adjustable delay according to the first delayed signal so that the feedback signal is aligned with the first delayed signal.

[0047] It can be understood that a digital phase-locked loop (DPLL) is more suitable for deep sub-micron manufacturing processes because it is easy to adapt to low supply voltages and utilize a digital loop filter (LF) with a small area. In addition, the digital-intensive LF and calibration algorithms make it easier to migrate between different processes. In some embodiments, the DPLL can utilize a counter or a multi-modulus divider (MMD) in the feedback path. The counter-based DPLL only supports first-order DSM, which makes it easier to generate strong in-band fractional spurs in channels close to integers. The divider-based DPLL can rely on higher-order DSM to provide sufficiently random quantization error (QE), but the accumulated QE range expands (doubled for 2nd-order DSM and tripled for 3rd-order DSM). Figure 1 Shows the architecture of a DPLL based on a fractional-N divider. The input signal t_e of the digital phase detector is the time error between the reference signal (CK REF ) and the feedback signal (CK MMD , i.e., the first signal in the embodiments of the present application). When the reference signal source is clean and the MMD is well designed, the in-band phase noise of the DPLL is mainly dominated by the digital phase detector (PD). A digital phase detector with high linearity helps to eliminate fractional spurs, in-band noise folding, and out-of-band noise leakage in the PLL output spectrum, thus ensuring low integrated jitter. On the other hand, a digital phase detector with a large detection range is the key to achieving fast locking.

[0048] In some embodiments, as shown in Figure 2 , a digital-to-time converter (DTC) is used to compensate for the QE introduced by the delta-sigma modulator, and at the same time, a bang-bang phase detector (BBPD) is used for phase error detection. Refer to Figure 3, which greatly reduces the power consumption of the digital phase detector. To improve linearity, in some embodiments, the DTC is also calibrated by a piecewise linear method. This calibration method linearly divides the entire dynamic range of the DTC and estimates the transfer function of the DTC through a first-order function in each sub-region. In some embodiments, it can also be extended to a linearization in polynomial form. In this way, the fractional spurs close to the integer channels are improved, and the integration jitter is also reduced. However, the variable slope DTC (VS-DTC) with a large dynamic range and fine resolution exhibits a large integration non-linearity and generates a large inherent delay. The former will result in strong spurious waves, and the latter will introduce additional thermal noise, thus significantly reducing the integration jitter of the phase-locked loop output signal. In some embodiments, through an improved multi-mode frequency divider, the dynamic range of the DTC is halved, achieving low fractional harmonics and jitter performance close to the integer channels. This shows that reducing the dynamic range of the DTC is effective in improving its linearity. In some embodiments, by utilizing the eight output phases of the ring oscillator, the dynamic range of the DTC is reduced to 1 / 8, greatly enhancing its linearity and reducing the inherent delay of the DTC. However, this method cannot be directly migrated to the digital phase-locked loop based on the inductance-capacitance oscillator. Refer to Figure 4 , the time-to-digital converter (TDC) can provide accurate, fast and continuous phase error measurements, making faster frequency and phase adjustments possible and shortening the lock time. However, refer to Figure 5 , this requires a TDC with a large detection range and fine resolution, usually sacrificing linearity and power consumption.

[0049] Refer to Figure 6 As shown, the bang-bang phase detector in the embodiments of the present application is like Figure 6 the PS-BBPDs in REF , a group of delay signals such as CK R [1] to CK R [d], the digital time converter such as VS-DTC, the first signal such as CK MMD , generates a feedback signal CK DTC after delaying the first signal; the multiplexer such as MUX.

[0050] In some embodiments, for the digital phase detector provided by the embodiments of the present application, the digital phase detector further includes a decoder;

[0051] The bang-bang phase detector is used to compare the delayed signal and the feedback signal to generate a first error signal. The decoder is used to decode the first error signal into a digital signal to determine a significant signal based on the difference between the digital signal and the coarse precision control signal. The coarse precision control signal is generated by a digital calibration module and is also used to control the multiplexer. The significant signal is used to represent the significant part of the phase error.

[0052] In some possible implementation manners, the decoder is like Figure 6 Decoder in, the first error signal is like D[1] to D[m], the digital signal is like Dtdc, the coarse precision control signal is DCWc, the significant signal is e2, and the digital calibration module is Digital Calib.

[0053] In some embodiments, for the digital phase detector provided by the embodiments of the present application, the multiplexer is used to generate a fine signal according to the first error signal, and the fine signal is used to represent the fine part of the phase error;

[0054] The digital calibration module is used to receive the fine signal and the fractional frequency control word to generate a coarse precision control signal and a fine precision control signal, and the fine precision control signal is used to control the digital time converter.

[0055] Specifically, the fine signal is like Figure 6 signal e1 in.

[0056] In some embodiments, for the digital phase detector provided by the embodiments of the present application, the second error signal is the difference between the reference signal and the first signal;

[0057] When the second error signal is within the dead zone of the time-to-digital converter, the significant signal is 0 or -1. The function of the time-to-digital converter is provided by the bang-bang phase detector;

[0058] The fine signal is input into the main path of the digital loop filter to optimize the loop bandwidth with low integral jitter. The significant signal is input into the fast lock path of the digital loop filter to optimize the loop bandwidth for fast lock. The main path and the fast lock path have different coefficients;

[0059] When the digital phase-locked loop is approaching lock, the bang-bang phase detector is used to switch to bang-bang operation.

[0060] In some embodiments, for the digital phase detector provided by the embodiments of the present application, the second error signal is the difference between the reference signal and the first signal;

[0061] The digital time converter is used to generate an adjustable delay to compensate for the least significant bits of the second error signal;

[0062] The bang-bang phase detector is used to generate an adjustable delay to compensate for the most significant bits of the second error signal.

[0063] Specifically, in order to implement a digital phase detector with a wide detection range and fine resolution without sacrificing linearity, power consumption, and circuit complexity, the embodiments of the present application propose a hierarchical multi-functional digital phase detector, and its detailed implementation is as Figure 6 shown, where the coarse precision level is a group of path selection type bang-bang phase detectors (PS-BBPDs), and the fine precision level is a VS-DTC. The 4-bit buffer-based delay chain of the coarse precision level has a resolution of τ0 and is designed to cover the full range of the cumulative QE of 2×T CKV ideally, where T CKV is the period of the MMD input signal. In order to reliably cover 2×T CKV at the lowest output frequency and across process, voltage, and temperature (PVT) variations, the number of coarse steps is increased to m = 25.

[0064] When the loop is locked, the QE in the fractional mode is compensated by the PS-BBPDs and the VS-DTC. CK REF (i.e., the reference signal) passes through the delay chain and generates a set of delayed reference signals (i.e., the delayed signals in the embodiments of the present application, CK R [1:m]). Then, CK R [i] (1 ≤ i ≤ m) is compared with the feedback signal after delay (CK dtc ) by the BBPD in m paths to detect whether CK R [i] leads or lags behind CK dtc . The first CK dtc that lags behind CK R [i] is selected by the multiplexer controlled by DCW C (coarse precision control signal), and the VS-DTC (6-bit) controlled by DCW F (fine precision control signal) generates an adjustable delay to align CK dtc with the selected CK R [i], so that the corresponding BBPD operates in the linear region. Here, DCW C (DCW F ) is the digital control signal of the coarse (fine) precision level after calibration. In each reference signal period, the output of this specific BBPD is selected as the fine part (e1) of the phase error and sent to the main path of the digital loop filter (DLF).

[0065] Figure 7 illustrates the working principle of a multi-functional digital phase detector. Taking an example, where the fractional frequency control word (FCW frax ) is 2 -5 , and a typical MASH 1-1 delta-sigma modulator is used. Denote the normalized QE as φ qn Figure 6 . Then taking 3 / 8 ≤ t e < 1 / 2 as an example, then 3 ≤ φ qn < 4, and the 4th BBPD is selected. Therefore, the high significant bits of t e are compensated by a delay of size τ C generated by the coarse precision stage (PS-BBPDs). The low significant bits of t e are less than one least significant bit (LSB = 1 / 8 × T CKV ) of the coarse precision stage, and are compensated by a delay of size τ F generated by the fine precision stage (VS-DTC), finally achieving the alignment of CK dtc with CK R [4], fully compensating for t e . Through this method of combining and compensating the coarse and fine precision stages, the dynamic range (T F ) of the VS-DTC is reduced to one LSB of the coarse precision stage.

[0066] On the other hand, additional phase error information can be extracted from the output (D[1:m]) of the PS-BBPDs. After decoding the array D[1:m], the digital signal D tdc is obtained. Subtracting DCW tdc from D C generates the significant part (e2) of the phase error, which is then sent to the fast lock path of the DLF. Therefore, the PS-BBPDs are reused to implement a TDC with a large linear detection range, with a range of 2 × T CKV , and with almost no digital circuit overhead. When the input time error falls within the dead zone (τ0) of the TDC, D tdc will completely cancel out with DCW C , making e2 = 0 or -1, and then decoded to automatically disable the fast lock path. Therefore, during the locking process, the multi-functional digital phase detector acts as a coarse precision TDC, achieving fast frequency and phase error correction. Since e2 and e1 are sent to DLF paths with different coefficients, the loop bandwidths for fast lock and low integration jitter can be optimized separately, without an additional gear switching process. When approaching lock, the multi-functional digital phase detector can smoothly switch to bang-bang operation, thus achieving low integration jitter.

[0067] ​On the other hand, an embodiment of the present application provides a digital phase-locked loop, including the above-mentioned digital phase detector. The digital phase-locked loop further includes: a digital loop filter, an oscillator, and a multi-modulus divider;

[0068] The digital phase detector is connected to the oscillator through the digital loop filter, and the oscillator is connected to the digital loop filter through the multi-modulus divider.

[0069] In some embodiments, for the digital phase-locked loop provided by the embodiment of the present application, the digital phase-locked loop further includes a frequency divider;

[0070] The signal output by the oscillator is divided by the frequency divider, and the divided signal is input into the multi-modulus divider;

[0071] The multi-modulus divider is controlled by a MASH1-1 differential integral modulator.

[0072] In some embodiments, for the digital phase-locked loop provided by the embodiment of the present application, the third error signal is a normalized quantization error; the digital phase-locked loop further includes a digital calibration module;

[0073] The digital calibration module is configured to receive the third error signal and the fine signal, and generate a fine-precision control signal and a coarse-precision control signal through processing by the least mean square algorithm.

[0074] Exemplarily, Figure 8 shows the overall architecture of the proposed fractional-N DPLL. The errors e2 and e1 measured by the multi-functional digital phase detector are respectively fed into the main path and the fast lock path, and then the outputs of the DLF are combined to generate the tuning control word for the DCO (~18 GHz). The output of the DCO is divided by four through an inductorless low-power frequency divider to alleviate the speed requirement of the MMD. Controlled by the MASH1-1 DSM, the output signal of the MMD is about 100 MHz. The errors e1 and φ qn are fed into the digital calibration module based on the least mean square algorithm to generate the calibration control word for the multi-functional digital phase detector.

[0075] This fractional-N DPLL fabricated in a 28-nm CMOS process, without using a thick metal layer, occupies a core area of 0.11 square millimeters. It synthesizes frequencies from 16.4 to 19.3 GHz from a 100-MHz reference clock. The measurement is performed at the divided-by-four output. After calibration, the integrated jitter measured in the 4601.65-MHz fractional channel is reduced from 2.14 picoseconds to 124 femtoseconds, with an integration range from 1 kHz to 100 MHz, including all spurious frequencies ( Figure 9)). The power consumption is 14.8 mW, and the DPLL achieves a figure of merit of -246.4 dB. When further normalizing the multiplication factor N, the resulting figure of merit (FoM jitter,N ) is -269.1 dB. With a DCO frequency jump of 1.2 GHz, the PLL locks in 2.54 μs (254 reference cycles), achieving a frequency error within ±260 kHz (<60 ppm accuracy)( Figure 10 and Figure 11 ). During the locking process, the control word (OTW[20:15]) of the switched-capacitor array is automatically searched by the loop. Figure 11 Shows the measured fractional spurs. After calibration, the worst fractional spur is reduced from -16.3 dB to -68.5 dB. Near the fractional channel close to 4.6 GHz, the worst measured fractional spur is below -68.5 dB.

[0076] In Figure 11 , the DPLL performance is compared with previous technologies above 10 GHz. Compared with a single-stage PLL, considering the strict trade-off between performance and output frequency, the design implementation of this application achieves competitive fractional spurs, jitter, and FoM jitter,N . In addition, the DPLL proposed in this application completes locking within the shortest number of reference cycles.

[0077] The embodiments described in the embodiments of this application are for more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art can know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0078] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0079] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0080] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and their appropriate combinations.

[0081] In the description of this application and the above-mentioned accompanying drawings, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0082] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expression refers to any combination of these items, including any combination of single item (one) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0083] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above-mentioned division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0084] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0085] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, which does not limit the scope of rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of rights of the embodiments of the present application.

Claims

1. A digital phase detector, characterized in that, Comprising: A bang-bang phase detector for receiving a reference signal, and the reference signal generates a set of delayed signals through a delay chain; A digital time converter for receiving a first signal fed back from a multi-modulus divider, and generating a feedback signal after delaying the first signal; The digital time converter is connected to the bang-bang phase detector and is used to compensate for the quantization error in the fractional mode when the loop is locked; A multiplexer for selecting a first delayed signal that lags behind the feedback signal for the first time; the digital time converter is used to generate an adjustable delay according to the first delayed signal so that the feedback signal is aligned with the first delayed signal.

2. The digital phase detector according to claim 1, wherein The digital phase detector further includes a decoder; The bang-bang phase detector is used to compare the delayed signal and the feedback signal to generate a first error signal, and the decoder is used to decode the first error signal into a digital signal to determine a significant signal through the difference between the digital signal and a coarse precision control signal; the coarse precision control signal is generated by a digital calibration module, and the coarse precision control signal is further used to control the multiplexer; the significant signal is used to characterize a significant part of the phase error.

3. The digital phase detector according to claim 2, wherein The multiplexer is used to generate a fine signal according to the first error signal, and the fine signal is used to characterize a fine part of the phase error; The digital calibration module is used to receive the fine signal and a fractional frequency control word, and generate a coarse precision control signal and a fine precision control signal, and the fine precision control signal is used to control the digital time converter.

4. The digital phase detector according to claim 3, characterized in that A second error signal is the difference between the reference signal and the first signal; When the second error signal is within the dead zone of the time-to-digital converter, the significant signal is 0 or -1; the function of the time-to-digital converter is provided by the bang-bang phase detector; The fine signal is input to the main path of the digital loop filter to optimize the loop bandwidth with low integrated jitter; the significant signal is input to the fast lock path of the digital loop filter to optimize the loop bandwidth for fast locking; the main path and the fast lock path have different coefficients; When the digital phase-locked loop is approaching lock, the bang-bang phase detector is used to switch to bang-bang operation.

5. The digital phase detector according to claim 1, wherein A second error signal is the difference between the reference signal and the first signal; The digital time converter is used to generate an adjustable delay to compensate for the low significant bits of the second error signal; The bang-bang phase detector is used to generate an adjustable delay to compensate for the high significant bits of the second error signal.

6. A digital phase-locked loop, characterized in that Comprising the digital phase detector according to any one of claims 1 to 5, the digital phase-locked loop further includes: a digital loop filter, an oscillator, and a multi-modulus divider; The digital phase detector is connected to the oscillator through the digital loop filter, and the oscillator is connected to the digital loop filter through the multi-modulus divider.

7. The digital phase-locked loop according to claim 6, wherein The digital phase-locked loop further includes a frequency divider; The signal output by the oscillator is divided by the frequency divider, and the divided signal is input to the multi-modulus divider; The multi-mode frequency divider is controlled by a MASH 1-1 differential-integral modulator.

8. The digital phase-locked loop according to claim 6, wherein The third error signal is a normalized quantization error; the digital phase-locked loop further includes a digital calibration module; The digital calibration module is configured to receive the third error signal and the fine signal, process them through a least mean square error algorithm, and generate a fine-precision control signal and a coarse-precision control signal.

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