Gain calibration of digital-to-time converter (DTC) in fractional frequency divider

Abstract

The invention relates to an open loop modulator (OLM) in a fractional frequency divider. A high-pass filter is applied to a residual error output generated by a delta-sigma modulator (DSM) of the OLM. The filtering process is part of signal transfer function matching for the purpose of matching a signal transfer function of a combination of a DSM portion that generates a residual error and a matching block with a signal transfer function of a combination of a calibration PLL and a phase detector of a gain calibration circuit included in the OLM. A gain calibration circuit is used to cancel a gain error of a digital-to-time converter (DTC) in the OLM.

Description

[0001] Priority Statement

[0002] This patent application claims priority to the co-pending Indian provisional patent application titled "PLL based DTC Calibration in Low Jitter Fractional Frequency Dividers" with application number 202441029280, filed on April 10, 2024, and attorney docket number AURA-359-INPR; and claims priority to a U.S. patent application titled "GAIN CALIBRATION OF DIGITAL-TO-TIMECONVERTER (DTC) USED IN FRACTIONAL FREQUENCY DIVIDERS" with application number 19 / 023,493, filed on January 16, 2025. The entire content of the priority is incorporated herein to the extent not inconsistent with this specification. Technical Field

[0003] Embodiments of the present disclosure generally relate to digital-to-time converters (DTCs), and more particularly, to DTC gain calibration for fractional frequency dividers and the like. Background Art

[0004] A fractional frequency divider is a component that generates a fractional output clock whose frequency is a desired fraction of a reference clock. The desired fraction can have an integer part and a fractional part, which is well-known in the relevant art.

[0005] A digital-to-time converter (DTC) is typically used to generate an output signal whose corresponding edge is delayed by an amplitude specified by an input digital code value with respect to the edge of an input clock signal. DTCs can be used in fractional frequency dividers as well as other electronic devices such as sampling oscilloscopes, direct digital frequency synthesis, etc., which is well-known in the relevant art.

[0006] Ideally, the delay generated by the full-scale value of the input digital code value should be equal to the maximum possible delay designed for the DTC. However, in some practical scenarios, due to factors such as process, operating voltage, and temperature (PVT) variations, the actual delay value generated by the full-scale value of the input digital code value may deviate from the ideal value, which is well-known in the relevant art. The difference between the ideal delay of the full-scale value of the input digital code value and the actually generated delay value is called the "gain error" of the DTC. Gain calibration refers to determining the gain error in order to make appropriate corrections to cancel (compensate for) the gain error.

[0007] Aspects of the present disclosure relate to DTC gain calibration for a fractional frequency divider. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments of the present disclosure will be described with reference to the drawings briefly described below.

[0009] Figure 1 is a block diagram of an example device in which multiple aspects of the present disclosure can be implemented.

[0010] Figure 2 is a timing diagram (not drawn to scale) showing waveforms generated at various nodes of an open-loop modulator (OLM).

[0011] Figure 3A is a diagram showing implementation details of a Δ-Σ modulator (DSM) in an embodiment of the present disclosure.

[0012] Figure 3B is a diagram showing implementation details of a (digital-to-time converter) DTC gain calibration circuit in an embodiment of the present disclosure.

[0013] Figure 4 is a timing diagram (not drawn to scale) showing waveforms input to a correlator in the absence of the described technique.

[0014] Figure 5 is a timing diagram (not drawn to scale) showing example waveforms at various nodes of a gain calibration circuit in an embodiment of the present disclosure.

[0015] Figure 6 is a flowchart showing how DTC gain is calibrated in an embodiment of the present disclosure.

[0016] Figure 7 is a block diagram of a system in which a device implementing multiple aspects of the present disclosure can be integrated.

[0017] In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. The drawing in which an element first appears can be indicated by the leftmost digit of its corresponding reference numeral. DETAILED DESCRIPTION

[0018] 1. Overview

[0019] Aspects of the present disclosure relate to an open-loop modulator (OLM) circuit that generates a fractional output clock having a frequency that is a desired fraction of a reference clock, the desired fraction including an integer part and a fractional part. The OLM circuit includes a delta-sigma modulator (DSM) in which a first part generates a first sequence of coded values from the integer part and a second part generates a corresponding second sequence of coded values from the fractional part, where the first sequence of coded values includes a set of lower values and a set of higher values that, on average, represent the desired fraction overall.

[0020] A first frequency divider of the OLM circuit utilizes the reference clock and each coded value in the first sequence of coded values to generate a divided signal having a period that is an integer multiple of the period of the reference clock, the multiple being each coded value. A digital-to-time converter (DTC) of the OLM circuit utilizes the divided signal to generate the fractional output clock, and the DTC has a gain error. In generating the fractional output clock, the DTC delays an edge of interest of the divided signal by a delay time indicated by a series of adjusted coded values.

[0021] A DTC gain calibration circuit of the OLM circuit generates the series of adjusted coded values, where the DTC gain calibration circuit includes a calibration phase-locked loop (PLL) that uses the fractional output clock as a reference clock and generates a feedback clock. A phase detector of the DTC gain calibration circuit generates a series of error signals that represent a phase error between the fractional output clock and the feedback clock, the series of error signals indicating the gain error.

[0022] In one aspect, a matching block of the DTC gain calibration circuit generates a corresponding sequence of matching coded values from the second sequence of coded values. A first multiplier of the DTC gain calibration circuit calculates the product of corresponding elements of the sequence of matching coded values and the sequence of error signals to generate a first multiplier output sequence. A gain adjustment factor generator of the DTC gain calibration circuit generates a gain adjustment factor based on the first multiplier output sequence, the gain adjustment factor representing the reciprocal of the DTC gain. A second multiplier of the DTC gain calibration circuit multiplies the second sequence of codes by the gain adjustment factor to generate a sequence of adjusted coded values.

[0023] In one aspect, the signal transfer function of the second part of the DSM to the matching block matches the signal transfer function of the calibration PLL and the phase detector.

[0024] Aspects of the present disclosure will be described in conjunction with examples. However, those skilled in the relevant art will recognize that the present disclosure can be implemented without certain specific details, or other methods, components, materials, etc. may be used. In some cases, well-known structures, materials, or operations are not shown in detail to avoid obscuring the features of the present disclosure. Additionally, the described features / aspects can be applied in various combinations, although only some of these combinations are described herein for simplicity.

[0025] 2. Example Device

[0026] Figure 1 Details of an example device in which aspects of the present disclosure can be implemented are shown. Figure 1 An open-loop modulator (OLM) 100 (also referred to as an open-loop fractional divider or fractional frequency divider) implemented in accordance with various aspects of the present disclosure is shown. The OLM 100 receives a reference clock fref on path 125 and generates an output clock fout on path 165, and it includes a delta-sigma modulator (DSM) 130, a multi-mode divider (MMD) 140, a digital-to-time converter (DTC) 150, a duty cycle module (160), and a gain calibration circuit (gain cal) 170. It should be noted that Figure 1 Only the components relevant to the understanding of the present disclosure are shown, and the OLM 100 may include more or fewer modules than Figure 1 shown. Although the example embodiment shows an open-loop modulator, various aspects of the present disclosure are equally applicable to a closed-loop fractional divider, which will be understood by those skilled in the relevant art after reading the present disclosure.

[0027] The reference clock fref (125) can be generated by a phase-locked loop (PLL), an oscillator, etc. In one embodiment, the PLL 110 generates the reference clock fref (125) in a known manner.

[0028] DSM 130 receives a desired "fraction" ("fraction value"), which consists of an integer portion 105 and a fractional portion 107, and generates a series of related pairs of coded values on Ndiv1 132 and Ndtc 135 in a known manner. The first value of the coded value pair is an integer, and the second value represents the desired delay, and these two values are combined to achieve the desired fractional output clock on fout 165. For example, for the fraction 4.25, which consists of an integer portion "4" and a fractional portion "0.25", a (repeated) sequence of 4, 4, 4, and 5 (averaging 4.25) is sent on Ndiv1 (132), while a series of delay values 1 / 4, 2 / 4, 3 / 4, and 0 are sent on Ndtc (135). In the following description, multiple repetitions of the same value are referred to as a "group". As will be described later, the period of fout 165 (f-frac 155) is 4.25 times that of fref 125. dsm_carry (133) is 1 when a higher value (5) is sent on Ndiv1 (132), and is 0 otherwise. In one embodiment, DSM 130 follows Figure 3A The method is implemented.

[0029] MMD 140 receives reference clock fref on path 125 and code Ndiv1 on path 132, generates divided clock f-div based on each received Ndiv1 (132), and outputs it on path 145. Ndiv1 is a repeating divisor sequence (such as 4, 4, 4, and 5 in the above example). MMD 140 is a frequency divider that divides the frequency of fref by the corresponding divisor received on path 132 in the corresponding time interval, such as Figure 2 As shown. Ndiv1 (132) includes a set of lower values (4 in the above example) and a set of upper values (5), thereby generating corresponding lower and upper time periods on f-div (145), so that the average period of f-div (145) is equal to the period of the desired fractional clock. MMD 140 can be implemented in a known manner.

[0030] The DTC 150 delays each falling (or rising) edge of the divided clock f-div on path 145 by a time indicated by the corresponding gain adjustment code value received on path 173. As is known in the related art, the frequency of the divided clock f-div is not constant and varies with the value of Ndiv1. The DTC 150 delays the edge of interest (the falling edge in this example) of the output clock f-div by the received digital value of Ndtc. The delay caused by the DTC 150 has the effect of generating an f-frac where the intervals between falling edges are equal and are half the period of the desired output clock fout (165).

[0031] The duty cycle block (DCB) 160 generates an output clock fout with a desired duty cycle (specified by the Ndiv2 value 109) on path 165, which corresponds to the clock f_frac received on path 155. Generally, the DCB 160 operates as a divider, dividing the frequency of f-frac (155) by an even number to obtain a 50% duty cycle, and the integer part (105) and the fractional part (107) are scaled accordingly. The DCB 160 can be implemented in a known manner.

[0032] The gain of the DTC can be defined as the ratio of the delay and the corresponding coded value. Ideally, the delay generated by the DTC 150 for the Ndtc coded value of '0000' should be zero, and for the maximum Ndtc coded value, the delay should be equal to the maximum delay obtained using the DTC. In the above ideal case, the gain of the DTC 150 can be considered as 1 (i.e., ideal gain = 1). In Figure 1 the environment of, the maximum delay is designed to be equal to one period of fref. The gain of the DTC is usually expressed as a percentage of the ideal full range, or in terms of the least significant bit (LSB), as is well known in the relevant art. The Ndtc (135) value generated by the DSM 130 is designed according to the known (i.e., "ideal") gain of the DTC 150, which is determined by its design. However, in some practical scenarios, the actual delay value generated by the DTC 150 may deviate from the ideal value due to manufacturing process variations, operating voltage and temperature (PVT) variations, etc., as is well known in the relevant art. Generally, assuming no other types of errors (such as offset errors) exist, the gain error can be defined as the difference between the ideal delay and the actual delay value generated by the DTC 150 for the maximum input coded value, and is expressed as a percentage of the ideal delay. For example, for a -20% gain error, the actual delay will be 20% less than the ideal delay for the maximum input coded value. If the ideal gain is expressed as 1, when the gain error is -20%, the actual (non-ideal) gain will be 0.8.

[0033] In another case, the DTC 150 itself may have no gain error, but the error of fref (such as frequency error and jitter) may manifest as a gain error of the DTC 150. In addition, the DTC 150 may have an inherent gain error, plus the error of fref. The "effective gain error" to be canceled in the present disclosure is the sum of all these errors. However, in the following description, for simplicity of description, it is assumed that only the DTC 150 is the source of the gain error.

[0034] Gain error in the DTC 150 may cause unacceptable jitter in the signal f_frac(155), and this jitter is transmitted to the output clock fout of the OLM 100. Gain calibration refers to determining the gain error for appropriate correction to cancel (eliminate) the gain error.

[0035] Assume that there is a non-zero gain error in the DTC 150, so the gain of the DTC 150 is not equal to '1'. The gain calibration (Gaincal) 170 calibrates the gain of the DTC 150 by determining the gain error, generates a series of gain adjustment coding values according to the gain error, and sends them to the path 173. The DTC 150 delays each falling edge of the signal f-frac(155) according to the corresponding gain adjustment coding value (instead of the original Ndtc coding value generated by the DSM). In other words, if the gain error causes the DTC 150 to generate more delay than the ideal delay for a given Ndtc coding value, the amplitude of the gain adjustment coding value will be smaller than the corresponding original Ndtc coding value, so that the falling edge of f-frac is correctly placed to generate equally spaced falling edges of f-frac. On the contrary, if the gain error causes the DTC 150 to generate less delay than the ideal delay for a given Ndtc coding value, the amplitude of the gain adjustment coding value will be greater than the Ndtc coding value, so that the corresponding falling edge of f-frac is correctly placed. The ideal waveform (when the DTC 150 has no gain error) will be described in the following section.

[0036] Figure 2 is a timing diagram (not drawn to scale), showing the waveforms generated by different nodes in the OLM 100 under the assumption that the fraction is 8.5 and the DCB 160 is designed to divide by 2. Therefore, Ndiv1 132 shows the individual coding values of the repeating sequence 4, 4, 4, and 5, while Ndtc 135 shows the coding values corresponding to 1 / 4, 2 / 4, 3 / 4, and 0. f-div 145 represents the corresponding divided clock generated by dividing fref(125) by the coding value received on Ndiv1(132). The period of f-div(145) corresponds to the coding value on Ndiv1(132), as shown at time points t251, t254, t257, and t259. The waveform f-frac(155) represents the falling edge of f-div(145) after the delay time specified by Ndtc 135. The waveform fout 165 represents the required output signal with a 50% duty cycle obtained by dividing the frequency of f-frac(155) by 2.

[0037] This description will continue to elaborate on the implementation details of the DSM in the embodiments of the present disclosure.

[0038] 3. Δ-Σ Modulator

[0039] Figure 3A It is a schematic diagram showing the implementation details of the delta-sigma modulator (DSM) in an embodiment of the present disclosure. The DSM 130 includes a first circuit part 130-1 and a second circuit part 130-2. In this embodiment, the DSM 130 is implemented as a first-order (multistage noise shaping / MASH-1) delta-sigma modulator. Although this exemplary embodiment shows a first-order delta-sigma modulator, various aspects of the present disclosure are equally applicable to higher-order delta-sigma modulators, as will be understood by a skilled practitioner upon reading the disclosure herein.

[0040] The first circuit part 130-1 generates a sequence of Ndiv1 values on path 132, including delay element 301 and adder 302 (which act together to accumulate the integer part 105).

[0041] The second circuit part 130-2 generates a sequence of Ndtc values (residual error) on path 135, including delay element 304 and adder 303 (which act together to accumulate the fractional part 107). When the accumulator in 130-2 reaches its maximum value, a carry value of "1" is generated on path 306. Thus, the Ndtc encoded values contain a series of repeating values (cycles), and the sequence starts from the numerator of the fractional part and ends at the closest maximum value, then wraps around to the numerator of the next cycle. Delay elements 301 and 304 produce a sample delay corresponding to the f-div (145) clock period. In other words, although Figure 3A not shown, delay elements 301 and 304 are controlled by the falling-edge clock of f-div (145).

[0042] As described above, each Ndiv value represents an integer (i.e., the value by which the frequency of f-ref needs to be divided), and the corresponding Ndtc value represents a desired delay. The combination of the two enables the OLM 100 to generate the desired fractional output clock. The following description continues to illustrate the detailed implementation of the gain calibration circuit implemented according to the present disclosure.

[0043] 4. Gain Calibration Circuit

[0044] Figure 3B It is a block diagram showing the implementation details of the gain calibration circuit 170 in one implementation of the present disclosure and the related components of the OLM 100. Figure 3B Shown includes a phase-locked loop (PLL) 110, MMD 140, DTC 150, DSM 130, DCB 160, gain calibration circuit 170 ( Figure 1all components in), and an AND gate 390. The gain calibration circuit 170 further includes a calibration PLL (cal-PLL 360, including a cal-PLL-Fwd block 362 in the feedforward path, a frequency divider DIVN block 365, and an offset correction DTC (DTC-1, 367-1) in the feedback path), an offset correction block 370, a collision detection phase detector (BBPD) 375, a correlator 378, a circuit 380, a multiplier block 389, and a matching block 350. It should be noted that only in Figure 3B the relevant components shown for understanding the present disclosure. The gain calibration circuit 170 may include more or fewer modules than Figure 3B shown. Although Figure 3B not specified in, multiple digital modules shown in the figure may be controlled by corresponding clocks and operate synchronously. For example, DSM 130, blocks 350, 370, and 380, and multiplier 378 may be controlled by the f-div (145) clock.

[0045] As described above, it is assumed that there is a non-zero gain error in DTC 150, so the gain of DTC 150 is not equal to "1". The gain calibration circuit 170 operates to determine the gain error of DTC 150 and generate a gain adjustment code sequence based on the determined gain error, which is transmitted through path 173.

[0046] Specifically, cal-PLL 360 is used to detect the remaining phase error in the f-frac signal introduced due to the gain error of DTC 150. BBPD 375 and correlator 378 (a multiplier in this example) are used to capture the remaining phase error related to the Ndtc encoded value. A digital integrator (circuit 380) is used to accumulate the multiplier output (379) and adjust each Ndtc encoded value through negative feedback to cancel the gain error. Each component of the gain calibration circuit 170 will be described in detail later.

[0047] In one embodiment, cal-PLL 360 is implemented as an analog PLL based on a ring oscillator (RO). RO-PLL360 is a low-power, low-area PLL that only supports integer mode in this embodiment. The bandwidth (BW) of the RO-PLL can be configured according to the desired operating frequency range of fref (125), fout (165), and f-frac (155), the fraction to be achieved, etc. Although Figure 3B not shown, the cal-PLL-Fwd block 362 internally includes a phase detector (PD) block, a charge pump (CP), a low-pass filter (LPF), and a ring oscillator. The bandwidth of the RO-PLL can be changed by adjusting the current of the CP and / or adjusting the LPF elements (such as resistance (R) and capacitance (C) values).

[0048] The cal-PLL 360 receives f-frac as an input and generates fvco (353), whose frequency is locked to the phase and frequency of f-frac, and whose frequency is a multiple of f-frac, and the division ratio of the multiple is determined by the divider DIVN (365). The signal f-feedback (368) represents the feedback clock provided to the second input of the cal-PLL phase detector, and f-frac is the first input. The phase detector in the cal-PLL is used to determine the phase difference according to the falling edges of f-frac and f-feedback (368).

[0049] Assuming there is no gain error in the DTC 150, in steady-state operation, the phase difference between the falling edges of f-frac and f-feedback (368) should ideally be zero, because all the falling edges of f-frac should occur completely periodically. Further, even if there is a gain error, once the gain calibration circuit 170 is adjusted and provides the correct correction factor (through path 388, the gain adjustment factor), there will be no gain error in f-frac, and it is confirmed again that the phase difference between the falling edges of f-frac and f-feedback (368) is zero.

[0050] However, when there is a gain error, the falling edges of f-frac are not completely periodic. The delay error in the falling edges is proportional to the gain error and the corresponding Ndtc value. Therefore, there will be a corresponding phase error between at least most of the falling edges of f-frac and f-feedback. The bandwidth of the cal-PLL determines the accuracy with which its output fvco (and thus f-feedback) tracks f-frac, and thus determines the specific value stream of the phase error (377) generated by the BBPD (described later).

[0051] In one embodiment of the present disclosure, the OLM 100 is implemented without including the blocks 367-1 and 370. In this embodiment, the output path 366 of the DIVN (365) provides the feedback clock (path 368) to the cal-PLL-Fwd, and also serves as an input (path 369) to the BBPD 375.

[0052] In another embodiment of the present disclosure, the OLM 100 is implemented including the blocks 367-1 and 370 (as shown) to improve the performance of the gain calibration circuit 170. Specifically, the offset correction block 370 and the DTC-1 (367-1) work together to cancel the offset that may appear between the two inputs of the BBPD 375 due to reasons such as path routing delay and mismatches of internal circuit elements in the BBPD 375. Figure 3B shown) to improve the performance of the gain calibration circuit 170. Specifically, the offset correction block 370 and the DTC-1 (367-1) work together to cancel the offset that may appear between the two inputs of the BBPD 375 due to reasons such as path routing delay and mismatches of internal circuit elements in the BBPD 375.

[0053] To correct the above-mentioned offset, by using a pair of identical DTCs (DTC-1, 367-1 and DTC-2, 367-2), the falling edge of the output clock of each delay DIVN 365 is delayed. The total delay ranges of these two DTCs are the same and receive the input of the divided clock signal path 366. However, in an alternative embodiment, the delay ranges of the DTCs can be different and do not have to be the same. DTC-1 is used to provide a fixed delay (indicated by the digitally encoded value received by path 309) for the corresponding falling edge of the divided clock 366, while DTC-2 is continuously controlled by other blocks in the negative feedback loop such that, under steady-state operation, blocks 367-1 and 370 together cancel the offset. The offset cancellation process is briefly described below.

[0054] The offset error can be positive or negative. To be able to cancel both positive and negative offset errors, in addition to DTC-1, DTC-2 is also used. DTC-1 is placed in the feedback path of cal-PLL 360. Before the offset correction circuit first operates, DTC-1 is configured to provide a delay equal to half of its maximum delay, and thus is initialized to FS / 2 (half of the full-scale encoded value) by the digitally encoded value (received by path 309). Under this initialization, and assuming that DTC-1 and DTC-2 are identical (or at least their available delay ranges are the same), the offset correction loop formed by block 370 and BBPD 375 is able to correct the offset error between -X and +X, where X represents the delay duration provided by the DTC, in response to the digitally encoded value FS / 2. Thus, when the offset correction loop reaches steady state, if the final encoded value on path 376 is within the range [0 to FS / 2], the corrected offset error is within the range [0 to -X]. On the other hand, when the offset correction loop reaches steady state, if the final encoded value on path 376 is within the closed interval [FS / 2 to FS], the corrected offset error is within the range [0 to +X].

[0055] To accelerate the offset correction, when OLM 100 is powered on next time or released from RESET, the final encoded value 376 is used to determine the initialization encoded value of one or both DTCs. For example, if the final encoded value 376 is greater than 0 but less than FS / 2, DTC-1 is initialized to a delay encoded value whose magnitude is equal to (FS / 2 - final encoded value 376). This ensures a very fast or immediate convergence of the offset correction loop because the required final encoded value 376 will be 0. The steady-state magnitude of the final encoded value 376 is stored in a memory in OLM 100 ( Figure 3B not shown in the figure) and is read from the memory in a known manner to determine the above-mentioned initialization encoded value.

[0056] On the other hand, if the final encoded value 376 is greater than FS / 2 but less than FS, DTC-1 is initialized to a delay encoded value of size 0 (i.e., no delay). This ensures relatively fast convergence of the offset correction loop because the required final encoded value 376 will be (final encoded value 376 - FS / 2), rather than a value greater than FS / 2.

[0057] However, when the steady-state value of the final encoded value on path 376 is 0 or FS, there may still be a residual offset error. A technique of the present disclosure enables correction of such a residual error, that is, allowing an offset correction range of [-FS to +FS], rather than [-FS / 2 to +FS / 2] in the above description. The technique enabling an offset correction range of ±FS is described as follows:

[0058] A) If the final encoded value 376 is FS: DTC-1 is initialized to a delay of 0, allowing the offset correction loop to operate. DTC-2 may reach a steady state with a delay value within the closed interval [0 to FS].

[0059] B) If the final encoded value 376 is 0: DTC-1 is initialized to an encoded value of FS, allowing the offset correction loop to operate. DTC-2 may reach a steady state with a delay value within the closed interval [0 to FS].

[0060] The above case (A) covers the offset error interval from 0 to FS, while case (B) covers the offset error interval from 0 to (-FS).

[0061] The offset correction block 370 includes an adder 371, a delay block 373, a scaling block 374, and an offset correction DTC (DTC-2, 367-2). The adder 371 adds the values on paths 377 and 372. The delay block 373 produces a delay of one sample duration. The adder 371 and the delay block 373 together perform integration (accumulation or low-pass filtering) of the phase error signal received from path 377 and can be collectively referred to as an "accumulator". The accumulated (or low-pass filtered) value on path 372 is multiplied by a scaling factor 'K2' in block 374 to generate a scaled average value on path 376. The scaled average value 376 is then provided as a digital encoded value to DTC-2 (367-2) to delay the falling edge of the divided clock 366 transmitted through path 369.

[0062] The BBPD 375 can be implemented as a negative-edge triggered D-type flip-flop that receives the offset-corrected feedback clock (path 369) as its data (D) input and f-frac as its clock input (negative-edge triggered in this example). The BBPD generates a phase error signal (path 377) indicating whether the phase difference between the corresponding falling edge of f-frac and the corresponding falling edge of the offset-corrected feedback clock (path 369) is positive or negative. In this embodiment, a value of '+1' represents a positive phase error (the falling edge of f-frac lags the falling edge of the corresponding offset-corrected feedback clock), while a value of '-1' represents a negative phase error (the falling edge of f-frac leads the falling edge of the corresponding offset-corrected feedback clock). Once the gain calibration circuit 170 reaches a steady state (the gain correction factor has converged to the correct value and no gain error is exhibited in f-frac), the phase error signal 377 will randomly oscillate between positive and negative values, mainly due to circuit noise, resulting in a time average of zero for the phase error signal 377. Therefore, the value on path 379 will also randomly vary between the corresponding positive and negative values and will ultimately not further affect the steady-state value of signal 384 when averaged by blocks 381 and 382.

[0063] Prior to reaching the steady state, the DTC 150 will delay the falling edge of f-frac according to the time delay indicated by the corresponding "uncalibrated" Ndtc encoded value.

[0064] The correlator 378 multiplies the received phase error signal (+1 or -1 value) by the corresponding Ndtc match encoded value received via path 359 to generate the correlator output on path 379. The correlator 378 can be implemented in a known manner. In one embodiment, block 378 is implemented to perform the multiplication operation of signals 377 and 359 to generate the corresponding product (379).

[0065] The circuit 380 includes an adder 381, a delay block 382, a scaling block 383, an adder 385, and an offset block 387. The adder 381 adds the values on path 379 and path 386. The delay block 381 generates a delay of one sampling period. The adder 381 and the delay block 381 operate together to perform integration (accumulation or low-pass filtering) on the received product on path 379 and can be collectively referred to as an "accumulator". The combination of the multiplier 378 and the accumulator represents a correlator. The accumulated output is provided via path 386. Therefore, the magnitude of signal 386 represents the similarity (or dissimilarity) between signals 377 and 359, with a larger magnitude indicating a higher degree of similarity.

[0066] The accumulated (or low-pass filtered) value on path 386 is multiplied by a scaling factor "K1" in block 383 to generate a scaled average value on path 384. Then, the scaled average 384 is added by adder 385 to the offset value "1" received from block 387 to generate a "gain adjustment factor" on path 388.

[0067] Multiplier 389 multiplies each "raw" Ndtc encoded value (135) by the gain adjustment factor (388) to generate a gain-adjusted encoded value on path 173, and then DTC 150 uses these gain-adjusted encoded values to delay the corresponding falling edge of f-frac. The "main feedback loop" formed by cal-PLL 360, BBPD 375, multiplier 378, and circuit 380 represents the main part of the gain calibration 170. When the main feedback loop reaches a steady state, the gain adjustment factor (388) converges to the required correct value, thus eliminating the gain error of DTC 150. That is, the steady-state value of the gain adjustment factor represents the value by which each Ndtc encoded value needs to be multiplied to eliminate the gain error of DTC 150.

[0068] The steady-state value of the gain adjustment factor is equal to the reciprocal of the actual gain provided by DTC 150 when gain correction is not enabled. For example, assume the gain of DTC 150 is "1.2" (+20% FSR gain error), then the gain error is "+0.2". Therefore, at steady state, the scaled average (384) converges to "-0.2", so that the gain adjustment factor is "1 + (-0.2)" = 0.8. Thus, each Ndtc encoded value will be multiplied by "0.8" (i.e., the reciprocal 1 / 1.2 of the DTC 150 gain) to generate the corresponding gain-adjusted encoded value. The bandwidth of circuit 380 can be configured to have a higher value at startup of OLM 100 to achieve a faster settling time, and can be gradually reduced (by step setting or gear setting) to obtain better noise performance at steady state.

[0069] AND gate 390 is used to prevent the signal fout (165) from being output through path 395 before the gain calibration 170 reaches a steady state. In one embodiment, the signal unblock-fout 391 remains at logic low for a predetermined (fixed) duration before the gain calibration 170 reaches a steady state, and then turns to logic high. Therefore, the output fout-clean (395) represents a fractional output clock with relatively low jitter, which is due to the elimination of the gain error of DTC 150. The predetermined (fixed) duration required for the gain calibration 170 to reach a steady state can be obtained through Figure 3B testing circuits and / or simulations, and the signal unblock-fout can be generated by known methods.

[0070] The matching block 350 is used to modify each Ndtc encoded value received via path 135 and generate a corresponding Ndtc matching encoded value on path 359, such that the shape of the signal phase error 377 (in the time domain) is closer to the shape of the Ndtc matching encoded value (359) rather than the shape of the Ndtc encoded value 135. The requirements regarding this matching waveform shape will be described below with reference to Figure 4 for illustration.

[0071] 5. Matching block

[0072] The need for the matching block 350 is to make the shapes of the two input signals passed to the multiplier 378 similar. This can be better understood by observing the waveforms of the input signals (i.e., the shapes in the time domain if the amplitudes are plotted) when there is no matching block 350 and when Ndtc (135) is directly provided to the multiplier 378. Figure 4 (Not to scale) shows the waveform of the phase detector output in cal-PLL-Fwd 362 (labeled as cal-PLL-PD-output (360-s) in Figure 4 ), and the two input waveforms passed to the multiplier 378, namely Ndtc (335) and the phase error (377). Here, it should be noted that the low-pass filtered version of the phase error (assuming the effects of noise are removed) is depicted by the waveform 377 in Figure 4 .

[0073] The waveform of Ndtc has a linearly increasing ramp shape within the time interval t491 - t492. Figure 2Shows an example where the Ndtc value increases linearly (e.g., in the case of the above example fraction 1 / 4, successively 1 / 4, 2 / 4, 3 / 4) until the next coding value is 0. Thereafter, the shape of Ndtc repeats in a similar ramp fashion in the next time intervals (time intervals t492 - t494 and t494 - t496 are shown), and its waveform is similar to a sawtooth wave. The waveform of cal - PLL - PD - output generally remains flat and constant within the time interval t491 to t492. Within the time interval from t491 to t492, the rate of change of Ndtc is constant (the slope of the ramp shown in the figure), and is small enough that the phase change at the falling edge of f - frac(165) lies within the bandwidth (BW) of cal - PLL, so cal - PLL can track these changes very quickly. Thus, the change of cal - PLL - PD - output in this region is very small and remains approximately constant / flat on average, as shown in 360 - s. Within the same time interval, the input phase difference of BBPD 375 is close to zero. However, due to the use of a binary - output flip - flop to indicate the phase difference, noise causes the output to be +1 and -1 with equal probability.

[0074] However, at t492, there is a sharp change in Ndtc and Ndtc becomes equal to 0 (or the minimum starting value). Correspondingly, a large phase error occurs between f - frac and f - feedback(368) at t492. The bandwidth of cal - PLL is not sufficient to track this large phase error quickly. Thus, cal - PLL - PD - output produces a large amplitude and appears as a negative trough at t492. Thereafter, cal - PLL - PD - output decreases until at t493, it returns to the level before t492. Within the same time interval (t492 - t493), the output of BBPD 375 is '-1', indicating the sign of the phase difference. Thus, the waveform of the phase error(377) is largely similar to the waveform of cal - PLL - PD - output, as Figure 4 shown. The time interval t492 - t493 is determined by the bandwidth of cal - PLL. Thereafter (i.e., after t493), the waveforms of Ndtc and cal - PLL - PD - output will follow the previous similar pattern and repeat.

[0075] To obtain a numerical value that can be used to modify each Ndtc coding value(135) based on the output value of BBPD 375 and thus cancel the gain error, the output of BBPD 375 can be correlated with the corresponding value stream derived from the Ndtc value.

[0076] It can be understood that directly correlating the output value (377) generated by the BBPD 375 with the value of the corresponding Ndtc encoded value (135) (in time) may not produce a meaningful result because the "waveform" shapes of the phase error (377) and Ndtc (135) are very different. Therefore, by directly correlating these two numerical streams, an accurate "correction factor" may not be obtained, or any "correction factor" may not be obtained at all to cancel the gain error.

[0077] According to one aspect of the present disclosure, the Ndtc encoded value (135) is converted into a stream of "matched" encoded values (Ndtc-matched359), and the matched encoded values are correlated with the values in the phase error (377).

[0078] Referring again to Figure 3B , the matching block 350 includes a subtractor 358, an adder 352, a delay block 354, and a scaling block 356. The output of the delay block 354 is provided as an input to the adder 352 and the scaling block 356. Blocks 352 and 354 and the corresponding connections together perform low-pass filtering or accumulation on the values from path 359. The scaling block 356 multiplies the output of block 354 by a value K3 (further described below) to generate a scaled low-pass filtered output. The subtractor 358 subtracts the corresponding value from the scaling block 356 from each Ndtc encoded value received from path 135 to generate the matched Ndtc encoded value on path 359. The adder 352 adds each matched Ndtc encoded value to the corresponding "accumulated" encoded value received from the delay block 354. Thus, the matching block 350 represents a high-pass filter (HPF).

[0079] The operation of the matching block 350 converts the shape of the Ndtc (135) waveform into a shape similar to the shapes of the cal-PLL-PD-output and the phase error (377), as described below.

[0080] 6. Correlator Input

[0081] Figure 5 is a timing diagram (not drawn to scale) showing example waveforms of the cal-PLL-PD-output (360-s), the phase error (377), the Ndtc-matched (359), the output of the multiplier 378 (referred to as the "correlator output"), and the scaled average 384, where the matching block 350 is included in the gain calibration 170. The time intervals t501 - t510 show example waveforms before the gain calibration 170 converges (e.g., when the OLM 100 is started), while the time intervals t510 - t515 show example waveforms after the gain calibration 170 reaches a steady state.

[0082] Due to the design and operation of the matching block 350, the signal Ndtc-matched(359) is closer in shape (compared to the phase error 377 and cal-PLL-PD-output 360-s) to Ndtc(135).

[0083] Before t501, it is assumed that the offset correction block 370 has reached a steady state.

[0084] The "flat" portion of the Ndtc-matched(359) waveform (e.g., the time interval t505 - t506) represents the duration during which the Ndtc encoded value(135) increases linearly with time. The Ndtc encoded value(135) jumps to 0 (e.g., as shown at times t502, t506, t508), and Ndtc-matched jumps to a large negative value accordingly in response to such jumps. In the "spike" regions (e.g., the time intervals t502 - t503 and t508 - t509), Ndtc-matched increases in a manner similar to cal-PLL-PD-output in the same intervals.

[0085] Before the gain calibration 170 converges, in each cycle of the Ndtc encoded value, simultaneously with the Ndtc encoded value jumping to 0, cal-PLL-PD-output exhibits a large positive spike. Thereafter, cal-PLL-PD-output decreases until it returns to the level before the jump. The various regions / time intervals in one cycle of Ndtc are described in detail below.

[0086] For example, consider the cycle within the time interval t502 - t506:

[0087] At t502: Simultaneously with the Ndtc encoded value jumping to 0, cal-PLL-PD-output(360-s) exhibits a positive spike (in the example) with an amplitude of e1.

[0088] In the time interval t502 - t503: The amplitude of cal-PLL-PD-output(360-s) decreases (starting from e1) until it returns to the level before the jump. The duration of the time interval t502 - t503 and the slope of 360-s depend on the bandwidth of cal-PLL. The BBPD output phase error(377) is all '+1' values, representing the phase error between the BBPD inputs. The correlator output(379) is the product of the '+1' value on path 377 and the negative value on path 359, and thus has a corresponding negative value. The scaled average(384) starts accumulating the values on path 379 and exhibits a slight dip (corresponding to the encoded value jump).

[0089] During the time interval t503 - t505: The amplitude of cal-PLL-PD-output has recovered to the level before the jump, and Ndtc-matched(359) has flattened out. The BBPD output phase error (377) has all '-1' values (the number of '-1's is approximately the same as the number of '+1's in the time interval t502 - t503), which is due to the action of the offset correction block 370. During this period, since Ndtc-matched(359) remains approximately constant (and close to zero), the amplitude of the correlator output (379) does not change significantly. It should be noted that there is a time lag between the start of the '+1' value region in the BBPD output and the response of the offset correction loop. Therefore, the effect of the offset correction loop is only visible after t503 and stabilizes before t505.

[0090] During the time interval t505 - t506: The amplitude of cal-PLL-PD-output remains at the level before the jump because the cal-PLL has acquired lock and Ndtc-matched(359) remains flat. The BBPD output phase error (377) randomly jitters between positive and negative values (represented as blocks for illustration purposes in Figure 5 ), and its average value is zero. Therefore, the correlator output (379) and the scaled average (384) also remain approximately constant. Although the waveform of 360-s appears as a straight line, in reality, due to noise, its value oscillates around zero, as can be understood by those skilled in the relevant art by reading this text.

[0091] Thereafter (i.e., during the time interval t506 - t510), the waveforms of cal-PLL-PD-output (360-s), phase error (377), Ndtc-matched(359), and correlator output (379) follow a similar pattern as before and repeat, with the only difference being that the spike amplitude and width of the 360-s waveform gradually decrease in each cycle (e.g., e1 at t502 and e2 at t508), as the circuit 380 progresses towards convergence (indicated by the scaled average waveform 384). Correspondingly, the duration of time for which the BBPD output is '+1' also gradually decreases in each cycle, as shown in the examples of the time intervals t502 - t503 and t508 - t509.

[0092] At t510 (or slightly before), the circuit 380 converges (reaches a steady state). Therefore, after this (i.e., after t510), the waveform 384 shows a stable steady-state value, the cal-PLL-output (360-s) is approximately flat, and the BBPD output randomly jitters between positive and negative values.

[0093] It should be noted here that the time required for the circuit 380 to converge is proportional to the magnitude of the gain error. In other words, the greater the gain error of the DTC 150, the longer the time required for the circuit 380 to converge, and vice versa.

[0094] The update of the K1 loop is only valid when the encoded value jumps to 0 and within the subsequent update intervals, and during these update intervals, due to the delayed response of the K2 loop, the operation of the K2 loop does not affect the gain error calibration process, as described above.

[0095] Correlating Ndtc-matched (359) with the phase error (377) enables the correlation output on path 386 to converge to a value that can be used to correct each Ndtc encoded value (135), thereby canceling the gain error when the corrected encoded value (gain adjustment encoded value (173)) is used by the DTC 150 to delay the corresponding f-frac falling edge.

[0096] According to one aspect of the present disclosure, the "signal transfer function" (STF) of the circuit portion of the OLM 100 is matched to obtain the above-described Ndtc encoded value conversion. As is well known in the relevant art, the "signal transfer function" of a block is a mathematical function that represents the output of the block for each possible input, excluding the influence of noise. "Matching" the signal transfer functions of two blocks means that the curves / graphs of the outputs and inputs of these two blocks are similar within a threshold error range. Additionally, in the context described herein, "matching" is also used to indicate that the shapes of two matching signals are similar.

[0097] In one embodiment, the STF (STF-1) of the circuit portion 130-2 of the DSM 130 and the matching block 350 is matched with the STF (STF-2) of the cal-PLL (360) and the BBPD 375. The combination of 130-2 and 350 is referred to as the "first block", which receives the fractional component (107) as an input and generates Ndtc-matched (359) as an output. The combination of 360 and 375 is referred to as the "second block", which receives the time difference between f-frac (166) and f-feedback (387) as an input and generates the phase error (377) as an output. By matching the STFs of these two blocks, the shapes of these two waveforms (Ndtc-matched and phase error, and cal-PDD-PD-output) are more similar to each other (as Figure 5 shown), compared to the waveforms of Ndtc and phase error (as Figure 4 shown).

[0098] As described above, as part of matching the STF, the bandwidth of the cal-PLL 360 is also matched (e.g., set equal) to the bandwidth of the matching block / HPF 350 to achieve optimal correlation. Equivalently, the cut-off frequency of the HPF 350 is matched (e.g., set equal) to the unity-gain frequency (UGF) of the cal-PLL.

[0099] The OLM 100 typically needs to be designed to support a specific operating frequency range of the clock fout(165), which is well known in the relevant art. In one embodiment, for each specific fout(165) operating frequency range, simulations are run for the corresponding possible combinations of (f-frac and Ndiv2). An f-frac (or the corresponding Ndiv2 value) is selected such that the bandwidth of the matching block 350 can be more easily matched to the bandwidth of the cal-PLL 360. For example, the number of programming bits required to set the bandwidths of the matching block 350 and the cal-PLL 360 can be kept low (e.g., 4 bits each), and the division value of Ndiv2 is selected so that the gain calibration 170 converges faster. Considering the process corners of the integrated circuit (IC), the bandwidth configuration values and the gain factor K3 of the cal-PLL are stored in a look-up table (LUT) and configured in a known manner during the design phase of the OLM 100.

[0100] For example, assume fout = 150 megahertz (MHz) (for simplicity, a single fout value rather than a range is used in the example). There are at least 4 pairs of possible (f-frac, Ndiv2) combinations, namely (300 MHz, 2), (600 MHz, 4), (900 MHz, 6), and (1200 MHz, 8). Simulations are run for all the above possible combinations, and based on the simulation results, an f-frac value is selected such that the bandwidth of the matching block 350 can be more easily matched to the cal-PLL bandwidth. The value of f-frac and the corresponding bandwidth values of the cal-PLL and the matching block 350 are stored in the above LUT.

[0101] The operation of the OLM 100 is summarized below, with reference to Figure 6 the flowchart of

[0102] 7. Flowchart

[0103] Figure 6 is a flowchart showing the manner in which the DTC gain is calibrated according to aspects of the present disclosure. Although specific examples are provided in the description and reference is made to the components in Figure 3A and 3B the features of the present disclosure can be applied to the corresponding circuits / subsystems in other components and environments without departing from the scope and spirit of the aspects of the present disclosure, as would be apparent to those skilled in the relevant art by reading this text.

[0104] In addition, the execution order of certain steps may be different from that shown below to adapt to specific environments, as can be understood by those skilled in the relevant technical fields by reading this document. Many such implementations are considered to be covered by various aspects of the present disclosure. The flowchart starts from step 601, and control is immediately passed to step 610.

[0105] In step 610, the DSM 130 uses Δ-Σ modulation to generate a first sequence of coded values (Ndiv1) and a corresponding second sequence of coded values (Ndtc) from the desired fraction.

[0106] In step 620, the MMD 140 divides the reference clock fref(125) based on each coded value in the first sequence of coded values to form a divided signal (f-div, 145).

[0107] In step 630, within the first time interval (i.e., before the gain calibration 170 reaches steady-state operation), the DTC 150 delays the edges of interest of f-div (the falling edge in this embodiment) according to a series of uncalibrated coded values to generate a fractional output clock (f-frac, 155).

[0108] In step 640, the cal-PLL 360 generates a feedback clock (f-feedback, 368) phase-locked to f-frac.

[0109] In step 650, the BBPD 375 identifies a series of phase errors (377) between f-frac and f-feedback.

[0110] In step 660, the matching block 350 converts the original Ndtc coded values (135) into a corresponding sequence of matching coded values (359) by high-pass filtering. In one embodiment, the circuit part 130-2 of the DSM 130 and the STF of the matching block 350 are matched with the STF of the cal-PLL 360 and the BBPD 375. As described above, as part of the matching STF, the bandwidth of the cal-PLL 360 also matches the bandwidth of the matching block / HPF 350 (e.g., set to be equal) to achieve optimal correlation. Equivalently, the cut-off frequency of the HPF 350 matches the unity-gain frequency (UGF) of the cal-PLL 360 (e.g., set to be equal).

[0111] In step 670, circuit 380 generates a gain adjustment factor (388) based on the phase error sequence and the matched coding value sequence. Specifically, multiplier 378 multiplies each phase error in the phase error sequence by the corresponding coding value in the matched coding value sequence. An accumulator (formed by adder 381 and delay block 382) low-pass filters the product sequence (379), and block 383 scales the filtered output. Adder 385 adds the scaled value to a fixed offset value provided by offset block 387 to generate the gain adjustment factor (388). The gain adjustment factor (388) converges to a value at the end of the first time interval (i.e., when gain calibration 170 reaches a steady state), and this value is equal to the inverse of the gain magnitude provided by the DTC.

[0112] In step 680, multiplier 389 multiplies each original Ndtc coding value by the gain adjustment factor to generate a corresponding adjusted coding value (173).

[0113] In step 690, starting from the second time interval (steady-state operation), DTC 150 delays the falling edge of f-div according to the received adjusted coding value (the coding value on path 173). The flowchart ends at step 699.

[0114] In this way, aspects of the present disclosure provide calibration for the DTC gain in a fractional frequency divider. The OLM 100 described above can be integrated into a larger device or system, and the system will be briefly described next.

[0115] 8. System

[0116] Figure 7 is a block diagram of an example system that includes a PLL implemented according to aspects of the present disclosure, as described in detail above. System 700 is shown to include SyncE (Synchronous Ethernet) timing cards (710 and 720) and line cards 1 to N, where only two line cards 730 and 750 are shown for simplicity of illustration. Line card 730 is shown to include a jitter attenuation block 740 and a SyncE PHY transmitter 745. Line card 750 is shown to include a jitter attenuation block 760 and a SyncE PHY (Synchronous Ethernet Physical Layer) transmitter 765. Figure 7The components in it can operate according to the Synchronous Ethernet (SyncE) network standard. As is known in the relevant technical field, SyncE is a physical layer (PHY)-based technology used to achieve synchronization in packet-based Ethernet networks. The SyncE clock signal transmitted through the physical layer should be traceable to an external master clock (e.g., from a timing card such as card 710 or 720). Therefore, Ethernet data packets are re-timed according to the master clock and then transmitted on the physical layer. Thus, data packets (e.g., the data packets on paths 731 and 751) are re-timed and transmitted, and no timestamp information is recorded in the data packets. These data packets can be generated by corresponding applications such as IPTV (Internet Protocol Television), VoIP (Voice over Internet Protocol), etc.

[0117] Therefore, line card 730 receives data packets on path 731 and forwards the data packet through output 746 after the data packet is synchronized (re-timed) with the master clock. Similarly, line card 750 receives data packets on path 751 and forwards the data packet through output 766 after the data packet is synchronized (re-timed) with the master clock.

[0118] The master clock (711 / Clock 1) is generated by timing card 710. Timing card 720 generates a redundant clock (721 / Clock 2), which will be used by line cards 730 and 750 in case of a failure of master clock 711. The master clock 711 and the redundant clock 721 are provided to line cards 730 and 750 through the backplane (represented by the number 770).

[0119] In line card 730, the jitter attenuation module 740 includes a PLL 110 and an OLM 100 (as Figure 1 shown) and receives clocks 711 and 721. The jitter attenuation module 740 generates an output clock 741, which is used to synchronize (re-time) the data packets received on path 731 and forwards the re-timed data packets through path 746.

[0120] Similarly, in line card 750, the jitter attenuation module 760 also includes a PLL 110 and an OLM 100 (as Figure 1 shown) and receives clocks 711 and 721. The jitter attenuation module 760 generates an output clock 761, which is used to synchronize (re-time) the data packets received on path 751 and forwards the re-timed data packets through path 766.

[0121] 9. Conclusion

[0122] References in this specification to "one embodiment", "an embodiment", or similar language mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment", "in an embodiment", and similar language throughout this specification do not necessarily all refer to the same embodiment.

[0123] Although in Figure 1 , Figure 3A - 3B and Figure 7 schematic diagrams show the terminal / node directly connected (i.e., "connected to") various other terminals, it should be understood that there may be additional components in the path (depending on the requirements of the particular environment), and thus these connections can be considered "electrically coupled" to the same connection terminals.

[0124] In this application, power and ground terminals are referred to as constant reference potentials.

[0125] Although various embodiments of the present disclosure have been described above, it should be understood that these embodiments are described by way of example only and not in a limiting sense. Accordingly, the breadth and scope of the present disclosure should not be limited to the embodiments described above, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. An open-loop modulator (OLM) circuit for generating a fractional output clock having a frequency that is a desired fraction of a reference clock, where the desired fraction includes an integer part and a fractional part, the OLM comprising: A delta-sigma modulator (DSM) including: A first part coupled to receive the integer part and generate a first sequence of coded values; A second part coupled to receive the fractional part and generate a corresponding second sequence of coded values, where the first sequence of coded values includes a set of lower values and a set of higher values, and the two sets on average represent the desired fraction; A first frequency divider coupled to receive the reference clock and each coded value in the first sequence of coded values and generate a first divided frequency signal having a period that is a multiple of the reference clock period, where the multiple is the each coded value; A first digital-to-time converter (DTC) coupled to generate the fractional output clock from the first divided frequency signal, the DTC providing gain and having a gain error; A DTC gain calibration circuit for generating a series of adjusted coded values, the DTC gain calibration circuit including: A calibration phase-locked loop (PLL) coupled to receive the fractional output clock as a reference clock and generate a feedback clock, the calibration PLL for synchronizing the feedback clock with the reference clock, the calibration PLL having a forward path and a feedback path; A phase detector coupled to receive the fractional output clock and the feedback clock and generate a series of error signals representing the phase error between the fractional output clock and the feedback clock at corresponding time points, the sequence of error signals indicating the gain error; A matching block coupled to receive the second sequence of coded values and generate a corresponding sequence of matched coded values; A first multiplier coupled to receive the sequence of matched coded values and the sequence of error signals and generate the product of corresponding terms of the sequence of matched coded values and the sequence of error signals as a series of first multiplier outputs; A gain adjustment factor generator coupled to receive the series of first multiplier outputs and generate a gain adjustment factor, the gain adjustment factor representing the reciprocal of the gain provided by the DTC; A second multiplier coupled to receive the gain adjustment factor and multiply the gain adjustment factor by each coded value in the second sequence of coded values to generate the series of adjusted coded values, where the first DTC operates to delay an edge of interest of the first divided frequency signal by a delay time indicated by a corresponding adjusted coded value in the series of adjusted coded values, where the signal transfer functions of the second part of the DSM and the matching block match the signal transfer functions of the calibration PLL and the phase detector.

2. The OLM circuit according to claim 1, where the bandwidth of the matching block is configured to be equal to the bandwidth of the calibration PLL such that the waveform shape in time of the sequence of matched coded values is substantially similar to the waveform shape in time of the sequence of error signals.

3. The OLM circuit according to claim 1, wherein the matching block comprises: A first accumulator, coupled to receive the sequence of matched coded values and generate a series of accumulator values; A first gain block having a first gain factor of a first magnitude, wherein the first gain block receives the first sequence of accumulated values and scales each accumulated value in the first sequence of accumulated values by the first magnitude to generate a corresponding first sequence of scaled values; A subtractor block, coupled to receive one of the coded values in the second sequence of coded values and the corresponding scaled value in the first sequence of scaled values, and generate a series of differences as the sequence of matched coded values.

4. The OLM circuit according to claim 3, wherein the gain adjustment factor generator comprises: A second accumulator, coupled to receive the sequence of multiplier outputs and generate a series of accumulator values; A second gain block having a second gain factor of a second magnitude, wherein the second gain block receives the second sequence of accumulated values and scales each accumulated value in the second sequence of accumulated values by the second magnitude to generate a corresponding second sequence of scaled values, wherein the second sequence of scaled values converges to a single value in steady state; An offset block, providing a fixed offset value; An adder, adding each scaled value in the second sequence of scaled values to the offset value and generating a series of sums, wherein each sum in the series of sums is equal to the gain adjustment factor in steady state.

5. The OLM circuit according to claim 4, wherein the feedback path includes a feedback frequency divider, wherein there is an offset error between the fractional output clock and each input path receiving the feedback clock, and the OLM circuit further includes an offset correction circuit, the offset correction circuit comprising: A memory; A first offset correction DTC, coupled to receive the output of the feedback frequency divider and a first delayed coded value, and delaying each edge of interest of the output of the feedback frequency divider by a duration corresponding to the first delayed coded value, wherein the feedback clock is the output of the first offset correction DTC; A third accumulator, coupled to receive the sequence of error signals and generate a series of accumulator values; A third gain block having a third gain factor of a third magnitude, wherein the third gain block receives the third sequence of accumulated values and scales each accumulated value in the third sequence of accumulated values by the third magnitude to generate a corresponding third sequence of scaled values, wherein the third sequence of scaled values converges to an offset correction coded value in steady state; A second offset correction DTC, coupled to receive the output of the feedback frequency divider and the offset correction coded value, and generating an offset correction feedback clock by delaying each edge of interest of the second divided signal by a duration corresponding to the offset correction coded value, wherein the phase detector is coupled to receive the offset correction feedback clock.

6. The OLM circuit according to claim 4, wherein the calibration PLL is a ring oscillator PLL, and wherein the DSM is a first-order Δ-Σ modulator.

7. The OLM circuit according to claim 4, further comprising a look-up table containing corresponding bandwidth values of respective operating frequency ranges of each fractional output clock and respective bandwidths of the calibration PLL, wherein the bandwidth of the matching block is configured according to the look-up table.

8. The OLM circuit according to claim 5, wherein each of the first offset correction DTC and the second offset correction DTC is designed to provide a maximum delay corresponding to a full-scale coding value (FS), wherein in the calibration phase of the offset correction circuit: at a first time point before the first operation of the OLM circuit, the first delay coding value is initialized to FS / 2; within a second time interval after the first time point, the offset correction loop reaches a steady state and the offset correction coding value converges to a first coding value, wherein the magnitude of the first coding value is stored as the offset correction coding value in the memory.

9. The OLM circuit according to claim 8, wherein upon power-up after the first operation: the magnitude of the offset correction coding value is read from the memory; when the magnitude of the offset correction coding value is greater than zero and less than FS / 2, the first delay coding value is initialized to a magnitude equal to (FS / 2 minus the offset correction coding value); when the magnitude of the offset correction coding value is greater than FS / 2 and less than or equal to FS, the first delay coding value is initialized to a magnitude equal to zero; when the magnitude of the offset correction coding value is equal to zero, the first delay coding value is initialized to a magnitude equal to FS, wherein the offset correction loop is operated to reach a steady state and converges to a second coding value, wherein the magnitude of the second coding value is stored as the offset correction coding value in the memory.

10. The OLM circuit according to claim 6, further comprising: an AND gate connected to the fractional output clock and a control signal for generating a low-jitter fractional output clock as the AND gate output, wherein the control signal is at a logic low level before the DTC gain calibration circuit reaches a steady state operation, wherein the control signal is at a logic high level after the DTC gain calibration circuit reaches a steady state operation.

11. A method implemented in an open-loop modulator (OLM) circuit for generating a fractional output clock having a frequency that is a desired fraction of a reference clock, wherein the desired fraction includes an integer part and a fractional part, the method comprising: generating a first sequence of coding values from the integer part and a corresponding second sequence of coding values from the fractional part by Δ-Σ modulation techniques; dividing the reference clock based on each coding value in the first sequence of coding values to form a divided signal, the period of the divided signal being a multiple of the period of the reference clock, wherein the multiple is each coding value; During a first time interval, delay an edge of interest of the divided signal according to a corresponding coded value among a series of uncalibrated coded values to generate the fractional output clock; Generate a feedback clock synchronized with the fractional output clock; Identify a sequence of phase errors between the fractional output clock and the feedback clock; Convert the second sequence of coded values into a corresponding sequence of matched coded values by high-pass filtering the second sequence of coded values; Generate a gain adjustment factor by the following steps: Multiply each phase error in the sequence of phase errors by a corresponding coded value in the sequence of matched coded values; Low-pass filter and scale the multiplication result; Apply a fixed offset to the scaled output; Multiply each coded value in the second sequence of coded values by the gain adjustment factor to generate a corresponding sequence of adjusted coded values; where the gain adjustment factor converges to a value equal to the reciprocal of the gain magnitude provided by the DTC at the end of the first time interval, where, starting from a second time interval after the first time interval, the edge of interest generates the fractional output clock with a time delay indicated by a corresponding adjusted coded value in the sequence of adjusted coded values by the DTC.

12. A system, comprising: A line card for receiving data packets, the line card retiming the data packets according to a selected clock and sending the retimed data packets; A first timing card for generating a first clock; And A power supply, where the line card comprises: A phase-locked loop (PLL) connected to the first clock, the PLL for generating a reference clock locked to the first clock; An open-loop modulator (OLM) connected to the reference clock and generating a fractional output clock, the frequency of the fractional output clock being a desired fraction of the reference clock, where the OLM comprises: A delta-sigma modulator (DSM), comprising: A part connected to the integer part for generating a first sequence of coded values; and A part connected to the fractional part for generating a corresponding second sequence of coded values, where the first sequence of coded values includes a set of lower values and a set of higher values, jointly representing an average value of the desired fraction; A first frequency divider for receiving the reference clock and each coded value in the first sequence of coded values and generating a first divided signal having a period that is a multiple of the reference clock period, where the multiple is each coded value; A first digital-to-time converter (DTC) for generating the fractional output clock from the first divided signal, the DTC providing gain and the DTC having a gain error; A DTC gain calibration circuit for generating a sequence of adjusted coded values, the DTC gain calibration circuit comprising: A calibration phase-locked loop (PLL) for receiving the fractional output clock as a reference clock and generating a feedback clock, the calibration PLL for synchronizing the feedback clock with the reference clock, the calibration PLL having a feedforward path and a feedback path, A phase detector for receiving the fractional output clock and the feedback clock and generating a series of error signals representing the phase error between the fractional output clock and the feedback clock, the error signal sequence indicating the gain error; A matching block for receiving the second sequence of coded values and generating a corresponding sequence of matched coded values; A first multiplier for receiving the sequence of matched coded values and the sequence of error signals and generating the product of the corresponding coded values in the sequence of matched coded values and the sequence of error signals as a first multiplier output sequence; A gain adjustment factor generator for receiving the first multiplier output sequence and generating a gain adjustment factor, the gain adjustment factor representing the reciprocal of the gain magnitude provided by the DTC; A second multiplier for receiving the gain adjustment factor and multiplying the gain adjustment factor by each coded value in the second sequence of coded values to generate the adjusted sequence of coded values, wherein the first DTC is for delaying the edge of interest of the first divided signal by a time delay indicated by the corresponding adjusted coded value in the adjusted sequence of coded values, wherein the signal transfer function of the combination of the second part of the DSM and the matching block matches the signal transfer function of the combination of the calibration PLL and the phase detector.

13. The system according to claim 12, wherein the bandwidth of the matching block is configured to be equal to the bandwidth of the calibration PLL, such that the waveform shape in time of the sequence of matched coded values is substantially similar to the waveform shape in time of the sequence of error signals.

14. The system according to claim 12, wherein the matching block comprises: A first accumulator for receiving the sequence of matched coded values and generating a first sequence of accumulated values; A first gain block having a first gain factor of a first magnitude, wherein the first gain block receives the first sequence of accumulated values and scales each accumulated value in the first sequence of accumulated values by the first magnitude to generate a corresponding first sequence of scaled values; A subtraction block for receiving one coded value in the second sequence of coded values and the corresponding scaled value in the first sequence of scaled values and generating a series of differences as the sequence of matched coded values.

15. The system according to claim 14, wherein the gain adjustment factor generator comprises: A second accumulator for receiving the multiplier output sequence and generating a second sequence of accumulated values; A second gain block having a second gain factor of a second magnitude, wherein the second gain block receives the second sequence of accumulated values and scales each accumulated value in the second sequence of accumulated values by the second magnitude to generate a corresponding second sequence of scaled values, wherein the second sequence of scaled values converges to a single value in steady state; An offset block providing a fixed offset value; An adder for adding each scaled value in the second sequence of scaled values to the offset value and generating a series of sums, wherein each sum in the series of sums is equal to the gain adjustment factor in steady state.

16. The system according to claim 15, wherein the calibration PLL is a ring oscillator PLL, and wherein the DSM is a first-order Δ-Σ modulator.

17. The system according to claim 15, further comprising a look-up table for containing bandwidth values of the matching block under corresponding operating frequency ranges of each of the fractional output clocks and corresponding bandwidth combinations of the calibration PLL, wherein the bandwidth of the matching block is configured based on the look-up table.

18. The system according to claim 15, further comprising: an AND gate connected to the fractional output clock and the control signal for generating a low-jitter fractional output clock as the AND gate output, wherein the control signal is logic low before the DTC gain calibration circuit reaches steady-state operation, wherein the control signal is logic high when the DTC gain calibration circuit reaches steady-state operation.

19. The system according to claim 15, wherein the feedback path includes a feedback frequency divider, and wherein there is an offset error between respective input paths receiving the fractional output clock and the feedback clock, and the OLM circuit further includes an offset correction circuit including: a memory; a first offset correction DTC, coupled to receive the output of the feedback frequency divider and a first delay coding value, and delaying each edge of interest of the output of the feedback frequency divider according to the first delay coding value, wherein the feedback clock is the output of the first offset correction DTC; a third accumulator, coupled to receive the error signal sequence and generating a third accumulation value sequence; a third gain block having a third gain factor of a third magnitude, wherein the third gain block receives the third accumulation value sequence and scales each accumulation value in the third accumulation value sequence by the third magnitude to generate a corresponding third scaled value sequence, wherein the third scaled value sequence converges to an offset correction coding value in steady state; a second offset correction DTC, coupled to receive the output of the feedback frequency divider and the offset correction coding value, and generating an offset correction feedback clock by delaying each edge of interest of the second divided signal by a delay corresponding to the offset correction coding value; wherein the phase detector is coupled to receive the offset correction feedback clock.

20. The system according to claim 19, wherein each of the first offset correction DTC and the second offset correction DTC is designed to provide a maximum delay corresponding to a full-scale coding value (FS), and wherein during a calibration phase of the offset correction circuit: at a first time point before the OLM circuit first operates, the first delay coding value is initialized to FS / 2; during a subsequent second time interval, the offset correction loop reaches steady state and the offset correction coding value converges to a first coding value, wherein the magnitude of the first coding value is stored in the memory as the offset correction coding value, at power-on after first operation: the magnitude of the offset correction coding value is read from the memory; When the magnitude of the offset correction coding value is greater than zero and less than FS / 2, the first delay coding value is initialized to (FS / 2 minus the magnitude of the offset correction coding value); When the magnitude of the offset correction coding value is greater than FS / 2 and less than or equal to FS, the first delay coding value is initialized to zero; When the magnitude of the offset correction coding value is zero, the first delay coding value is initialized to FS, wherein the offset correction loop is operated to reach a steady state and converge to a second coding value, wherein the magnitude of the second coding value is stored in the memory as the offset correction coding value.

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