Method and system for setting digital equalizer

Abstract

The invention discloses a method and a system for setting a digital equalizer, which are suitable for a signal receiver. The signal receiver comprises a digital signal processor, the digital signal processor comprises a target digital equalizer, the target digital equalizer has equalizer coefficients, and the method comprises the following steps: in an analog phase, obtaining a plurality of coefficient initial values and a plurality of coefficient limit values respectively corresponding to a plurality of preset transmission channels; and setting the equalizer coefficient of the target digital equalizer according to the coefficient initial value and the coefficient limit value corresponding to one of the preset transmission channels in the connection stage.

Description

Technical Field

[0001] The present invention relates to a method and system for setting a digital equalizer, and more particularly to a method and system for setting the equalizer coefficients of a digital equalizer. Background Art

[0002] Generally, when the analog transmission signal sent by a signal transmitter in digital communication technology passes through a non-ideal transmission channel, inter-symbol interference (ISI) is introduced, resulting in a decrease in the signal-to-noise ratio (SNR) of the input signal of the slicer of the signal receiver, so that the signal receiver is not easy to identify the analog transmission signal sent by the signal transmitter. Therefore, a digital equalizer is added to the signal receiver.

[0003] A digital equalizer is a filter that can perform channel equalization on the channel response of a transmission channel to filter out inter-symbol interference and improve the signal-to-noise ratio of the input signal of the slicer. However, the filtering ability of the digital equalizer for inter-symbol interference is affected by the equalizer coefficients (or called filter coefficients). Therefore, how to set the equalizer coefficients of the digital equalizer is an important issue in this field. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method and system for setting the equalizer coefficients of a digital equalizer in view of the deficiencies of the prior art.

[0005] To solve the above technical problem, one of the technical solutions adopted by the present invention is to provide a method for setting a digital equalizer. The method is applicable to a signal receiver, the signal receiver includes a digital signal processor, the digital signal processor includes a target digital equalizer, the target digital equalizer has equalizer coefficients, and the method includes the following steps: in the analog stage, configure a first electronic device as a connection partner to sequentially select one of a plurality of preset transmission channels to connect to the signal receiver, and configure a second electronic device to execute a search program each time the first electronic device connects to the signal receiver through one of the preset transmission channels to obtain a plurality of coefficient initial values and a plurality of coefficient limit values respectively corresponding to the plurality of preset transmission channels; and in the connection stage, configure the processor to set the equalizer coefficients of the target digital equalizer according to the coefficient initial value and the coefficient limit value corresponding to one of the preset transmission channels.

[0006] To solve the above technical problems, another technical solution adopted by the present invention is to provide a system for setting a digital equalizer. The system is applicable to a signal receiver, the signal receiver includes a digital signal processor, the digital signal processor includes a target digital equalizer, the target digital equalizer has equalizer coefficients, and the system includes a first electronic device, a second electronic device, and a processor. In the analog stage, the first electronic device is configured as a connection partner to sequentially select one of a plurality of preset transmission channels to connect to the signal receiver. The second electronic device is coupled to the first electronic device and the signal receiver in the analog stage, and is configured to execute a search program each time the first electronic device connects to the signal receiver through one of the preset transmission channels to obtain a plurality of coefficient initial values and a plurality of coefficient limit values respectively corresponding to the plurality of preset transmission channels. The processor is disposed in the signal receiver and is configured to set the equalizer coefficients of the target digital equalizer according to the coefficient initial value and the coefficient limit value corresponding to one of the preset transmission channels in the connection stage.

[0007] In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and illustration, and are not intended to limit the present invention. Brief Description of the Drawings

[0008] Figure 1 is a functional block diagram of a signal receiver according to an embodiment of the present invention.

[0009] Figure 2 is a functional block diagram of a system for setting a digital equalizer according to an embodiment of the present invention.

[0010] Figure 3 is a flowchart of steps of a method for setting a digital equalizer according to an embodiment of the present invention.

[0011] Figure 4A and 4B is a flowchart of steps of a search program according to an embodiment of the present invention. Detailed Embodiments

[0012] The following are specific embodiments to illustrate the implementation manners of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not drawn according to actual sizes. The following embodiments will further detail the related technical content of the present invention, but the content provided is not intended to limit the protection scope of the present invention.

[0013] Please refer toFigure 1 , Figure 1 is a functional block diagram of a signal receiver according to an embodiment of the present invention. As Figure 1 shown, the signal receiver 1 can receive an analog received signal Arx and includes an analog-to-digital converter (ADC) 11 and a digital signal processor 13. The analog-to-digital converter 11 is coupled to the digital signal processor 13 and is configured to convert the analog received signal Arx into a digital input signal Din according to a sampling phase SP. The digital signal processor 13 includes a target digital equalizer 131, a slicer 133, and a signal-to-noise ratio monitor 135.

[0014] The target digital equalizer 131 receives the digital input signal Din and outputs a slicer input signal SLin after filtering inter-symbol interference. It should be noted that the target digital equalizer 131 has equalizer coefficients, and the filtering ability of the target digital equalizer 131 for inter-symbol interference is affected by the equalizer coefficients. In addition, the target digital equalizer 131 may functionally include a feed-forward equalizer 1311 and a decision feedback equalizer 1313, but the present invention does not limit the specific implementation manner of the target digital equalizer 131. Generally speaking, both the feed-forward equalizer 1311 and the decision feedback equalizer 1313 can be used to filter post-index inter-symbol interference, and the feed-forward equalizer 1311 can also be used to filter pre-index inter-symbol interference.

[0015] The slicer 133 is coupled to the target digital equalizer 131 and generates a received symbol Syr according to the slicer input signal SLin. In addition, the slicer 133 also calculates a slicer error ER according to the slicer input signal SLin and the received symbol Syr. The signal-to-noise ratio monitor 135 is coupled to the slicer 133 and calculates the signal-to-noise ratio SNR1 of the slicer input signal SLin according to the slicer error ER. Since the working principle of the digital signal processor 13 is well known to those skilled in the art, details thereof will not be elaborated herein.

[0016] Furthermore, the analog received signal Arx received by the signal receiver 1 may be the result of inter-symbol interference introduced after the analog transmission signal Atx transmitted by the signal transmitter 3 passes through the transmission channel CH. However, different transmission channels CH (for example, transmission channels CH with different lengths and medium characteristics) have different channel responses and correspond to different equalizer coefficients. In addition, during the long-term signal transmission and reception process between the signal transmitter 3 and the signal receiver 1, the transmission channel CH may be affected by external environmental changes and have time-varying characteristics.

[0017] In other words, the channel response of the transmission channel CH may vary with time. Therefore, in order to find the equalizer coefficients corresponding to the current transmission channel CH and maintain the correctness of the coefficients during the long-term signal transceiver process, the target digital equalizer 131 may be an adaptive equalizer that automatically updates the equalizer coefficients according to an optimization algorithm to adapt to channel changes. In this embodiment, the optimization algorithm may be the gradient descent algorithm, but the present invention is not limited thereto.

[0018] Specifically, as the equalizer coefficients are continuously updated, the filtering ability of the target digital equalizer 131 for inter-symbol interference becomes stronger and stronger, making the slicer error ER smaller and smaller, and the signal-to-noise ratio SNR1 of the slicer input signal SLin higher and higher. Finally, when the slicer error ER approaches zero, the equalizer coefficients of the target digital equalizer 131 will no longer be updated to achieve coefficient convergence. Therefore, in order to be able to achieve coefficient convergence faster and ensure the success of coefficient convergence, the present invention provides a method and system for setting a digital equalizer, which can obtain a plurality of coefficient initial values and a plurality of coefficient limit values corresponding to a plurality of preset transmission channels respectively, and set the equalizer coefficients of the target digital equalizer 131 according to the coefficient initial value and coefficient limit value corresponding to one of the preset transmission channels.

[0019] Furthermore, before the target digital equalizer 131 automatically updates the equalizer coefficients, the present invention can set the value of the equalizer coefficients to the coefficient initial value, and the so-called coefficient limit value refers to the limit value of the equalizer coefficients during update. That is to say, the coefficient limit value may include an upper limit value and a lower limit value. Please refer to Figure 2 and Figure 3 , Figure 2 is a functional block diagram of a system for setting a digital equalizer according to an embodiment of the present invention, and Figure 3 is a step flow chart of a method for setting a digital equalizer according to an embodiment of the present invention. As Figure 2 shown, the system 5 of this embodiment can be applied to the signal receiver 1, and includes a first electronic device 51, a second electronic device 53, and a processor 55.

[0020] In the simulation stage, the first electronic device 51 is configured as a connection partner to sequentially select one of the plurality of preset transmission channels to connect to the signal receiver 1. It should be noted that the so-called simulation stage may refer to the product verification and testing stage before the signal receiver 1 leaves the factory, but the present invention is not limited thereto. In addition, the stage when the signal receiver 1 transceives signals with the signal transmitter 3 through the current transmission channel CH after leaving the factory will be defined as the connection stage.

[0021] For the convenience of the following description, the plurality of preset transmission channels in this embodiment are taken as N preset transmission channels 7(1) to 7(N) as an example, but Figure 2Only the first electronic device 51 is drawn to be connected to the signal receiver 1 through the x-th preset transmission channel 7(x) among the N preset transmission channels 7(1) to 7(N). That is, N is an integer greater than 1, and x is an integer from 1 to N. However, the present invention does not limit the specific values of N and x. Additionally, the first electronic device 51 can be a chip capable of communicating with the signal receiver 1, but the present invention also does not limit the specific implementation manner of the first electronic device 51.

[0022] The preset transmission channels 7(1) to 7(N) can be transmission channels with different lengths and medium characteristics. In this embodiment, the signal receiver 1 can be the receiving end of an Ethernet network. Therefore, the preset transmission channels 7(1) to 7(N) can be multiple Ethernet cables with different line lengths and wire materials, but the present invention is not limited thereto. Additionally, in order to ensure that there is no frequency offset between the sending end and the receiving end (i.e., the first electronic device 51 and the signal receiver 1), the system 5 can further include an oscillator 57. The oscillator 57 is configured to provide a clock frequency to the first electronic device 51 and the signal receiver 1 during the analog stage.

[0023] In other words, in this embodiment, the sending end and the receiving end in the analog stage share an oscillator to eliminate the situation where the oscillation frequencies of different oscillators may vary, ensuring that the clock frequencies of the sending end and the receiving end in the analog stage are consistent. Additionally, the second electronic device 53 is coupled to the first electronic device 51 and the signal receiver 1 during the analog stage, and the second electronic device 53 can be implemented by hardware (e.g., a central processing unit and a computer memory) in combination with software and / or firmware, but the present invention also does not limit the specific implementation manner of the second electronic device 53.

[0024] Specifically, the second electronic device 53 can be a computer and is configured to execute a search program each time the first electronic device 51 is connected to the signal receiver 1 through one of the preset transmission channels to obtain a plurality of coefficient initial values and a plurality of coefficient limit values respectively corresponding to the preset transmission channels 7(1) to 7(N). For Figure 2 example, the second electronic device 53 will execute a search program once when the first electronic device 51 is connected to the signal receiver 1 through the x-th preset transmission channel 7(x) to obtain the coefficient initial value and the coefficient limit value corresponding to the x-th preset transmission channel 7(x). Additionally, the second electronic device 53 can also write the obtained plurality of coefficient initial values and a plurality of coefficient limit values respectively corresponding to the preset transmission channels 7(1) to 7(N) into the memory (not shown) of the signal receiver 1.

[0025] Furthermore, since the preset transmission channels 7(1) to 7(N) can be multiple Ethernet cables with different line lengths and wire materials, each preset transmission channel can be represented by the combination of its line length and wire material. And the second electronic device 53 can obtain multiple coefficient initial values and multiple coefficient limit values under multiple combinations of different line lengths and wire materials. In addition, the memory of the signal receiver 1 can record the line length and wire material of each preset transmission channel, and record the multiple coefficient initial values and multiple coefficient limit values corresponding to the preset transmission channels 7(1) to 7(N) respectively. That is to say, the memory of the signal receiver 1 can record multiple combinations of different line lengths and wire materials, and record the multiple coefficient initial values and multiple coefficient limit values under multiple combinations of different line lengths and wire materials.

[0026] The processor 55 is disposed in the signal receiver 1 and is coupled to the digital signal processor 13. In the connection stage, the processor 55 is configured to set the equalizer coefficients of the target digital equalizer 131 according to the coefficient initial value and the coefficient limit value corresponding to one of the preset transmission channels. In this embodiment, the processor 55 can determine whether one of the preset transmission channels matches the current transmission channel CH, and in response to determining that one of the preset transmission channels matches the current transmission channel CH, set the equalizer coefficients of the target digital equalizer 131 according to the coefficient initial value and the coefficient limit value corresponding to the preset transmission channel that matches the current transmission channel CH.

[0027] According to the above content, the processor 55 can determine whether there is a combination of the line length and wire material of the current transmission channel CH among the multiple combinations of different line lengths and wire materials recorded in the memory of the signal receiver 1. If there is a combination of the line length and wire material of the current transmission channel CH among the multiple combinations of different line lengths and wire materials recorded in the memory of the signal receiver 1, it means that one of the preset transmission channels matches the current transmission channel CH.

[0028] Furthermore, if the line length and wire material of the x-th preset transmission channel 7(x) recorded in the memory are the same as those of the current transmission channel CH, it means that the x-th preset transmission channel 7(x) matches the current transmission channel CH. Therefore, the processor 55 will read out the coefficient initial value and the coefficient limit value corresponding to the x-th preset transmission channel 7(x) from the memory to set the equalizer coefficients of the target digital equalizer 131. It should be noted that the signal receiver 1 can first obtain the line length and wire material of the current transmission channel CH by performing channel estimation in the connection stage, but the present invention is not limited thereto.

[0029] In other words, if the memory of the signal receiver 1 records the initial coefficient value and the coefficient limit value under the combination of the current line length and the wire material, the processor 55 can read the initial coefficient value and the coefficient limit value under the combination of the current line length and the wire material from the memory and use them to set the equalizer coefficients of the target digital equalizer 131. Additionally, as described above, before the target digital equalizer 131 automatically updates the equalizer coefficients, the processor 55 can read the initial coefficient value and the coefficient limit value under the combination of the current line length and the wire material from the memory, then set the value of the equalizer coefficients to the initial coefficient value, and set the upper and lower limit values of the equalizer coefficients during the update to the coefficient limit value.

[0030] On the other hand, according to the above content, as Figure 3 shown, the method applicable to the signal receiver 1 for setting the digital equalizer in this embodiment may mainly include the following steps.

[0031] Step S300: In the simulation stage, configure the first electronic device as a connection partner to sequentially select one of multiple preset transmission channels to connect to the signal receiver, and configure the second electronic device to execute a search program each time the first electronic device connects to the signal receiver through one of the preset transmission channels to obtain multiple initial coefficient values and multiple coefficient limit values respectively corresponding to the aforementioned multiple preset transmission channels.

[0032] Step S302: In the connection stage, configure the processor to set the equalizer coefficients of the target digital equalizer according to the initial coefficient value and the coefficient limit value corresponding to one of the preset transmission channels.

[0033] It should be understood that the method of this embodiment may further include configuring the second electronic device to write the multiple initial coefficient values and multiple coefficient limit values respectively corresponding to the aforementioned multiple preset transmission channels into the memory of the signal receiver. Since the implementation details of each step have been described above, no further elaboration will be provided here.

[0034] Furthermore, please refer to Figure 4A and 4B , Figure 4A and 4B which are the step flowcharts of the search program according to the embodiments of the present invention. As Figure 4A and 4B shown, the search program executed by the second electronic device 53 when the first electronic device 51 connects to the signal receiver 1 through the x-th preset transmission channel 7(x) may include the following steps.

[0035] Step S400: The second electronic device replaces the clock recovery circuit to provide the sampling phase to the analog-to-digital converter, and the second electronic device sequentially selects one of multiple preset phases as the sampling phase to provide to the analog-to-digital converter.

[0036] Step S402: Configure the first electronic device to send an analog transmission signal.

[0037] Step S404: Determine whether the signal receiver has received an analog reception signal. If not, the search program returns to step S404; if so, the search program proceeds to step S406.

[0038] Step S406: Take the preset phase currently provided to the analog-to-digital converter as the phase zero point.

[0039] Step S408: Reset the equalizer coefficients of the target digital equalizer.

[0040] Step S410: Configure the target digital equalizer to perform automatic update of the equalizer coefficients (i.e., enable coefficient convergence).

[0041] Step S412: Determine whether the equalizer coefficients of the target digital equalizer have reached coefficient convergence. If not, the search program returns to step S412; if so, the search program proceeds to step S414.

[0042] Step S414: Record the signal-to-noise ratio and coefficient convergence value of the slicer input signal and the equalizer coefficients at the preset phase currently provided to the analog-to-digital converter.

[0043] Specifically, when the first electronic device 51 is connected to the signal receiver 1 through the x-th preset transmission channel 7(x), the second electronic device 53 can configure the first electronic device 51 to send an analog transmission signal Atx. Therefore, at this time, the analog reception signal Arx received by the signal receiver 1 will be the result of the symbol interference introduced after the analog transmission signal Atx sent by the first electronic device 51 passes through the x-th preset transmission channel 7(x). In addition, the second electronic device 53 can also configure the target digital equalizer 131 to perform automatic update of the equalizer coefficients until coefficient convergence is achieved. However, the analog-to-digital converter 11 samples the analog reception signal Arx according to the sampling phase SP to generate a digital input signal Din.

[0044] If the sampling phase SP deviates too much, the sampling result will be distorted and lead to the generation of an incorrect digital input signal Din, and it is likely to cause the equalizer coefficients of the target digital equalizer 131 to fail to converge normally. Therefore, the convergence of the equalizer coefficients of the target digital equalizer 131 depends on the analog-to-digital converter 11 sampling the analog reception signal Arx according to the correct sampling phase SP. That is to say, the quality of the convergence of the equalizer coefficients of the target digital equalizer 131 is affected by the sampling phase SP. In addition, as Figure 1 shown, the signal receiver 1 may further include a clock recovery circuit 15.

[0045] The clock recovery circuit 15 is coupled to the digital signal processor 13 and the analog-to-digital converter 11 and is configured to provide a sampling phase SP. Generally, the clock recovery circuit 15 estimates a phase error based on the received symbol Syr and the slicer error ER, and adjusts the sampling phase SP accordingly. When the clock recovery circuit 15 is adjusted to the optimal sampling phase SP, the estimated phase error approaches zero, achieving clock recovery circuit convergence. Therefore, the convergence of the equalizer coefficients of the target digital equalizer 131 is also affected by the convergence of the clock recovery circuit.

[0046] On the other hand, to accurately estimate the phase error, the digital signal processor 13 must ensure the accuracy of the received symbol Syr and slicer error ER input to the clock recovery circuit 15. This is because the target digital equalizer 131's ability to filter intersymbol interference (ISI) affects the accuracy of the received symbol Syr and slicer error ER, and the convergence of the target digital equalizer 131's equalizer coefficients in turn affects the target digital equalizer 131's ability to filter ISI. In other words, the target digital equalizer 131's ability to filter ISI must be sufficiently strong (i.e., the target digital equalizer 131 must be able to reduce ISI within the signal to a certain level) for the clock recovery circuit 15 to operate properly and achieve convergence. Therefore, in the signal receiver 1, the target digital equalizer 131 and the clock recovery circuit 15 inevitably face the problem of mutual constraints, affecting convergence.

[0047] In order to solve the above problem, the present invention is designed to replace the clock recovery circuit 15 with the second electronic device 53 in the search process to provide the sampling phase SP to the analog-to-digital converter 11, that is, step S400. In actual operation, if Figure 2 As shown, the system 5 may further include a multiplexer 59. The multiplexer 59 has two input terminals and one output terminal, which are respectively coupled to the second electronic device 53, the clock recovery circuit 15, and the analog-to-digital converter 11. In addition, the multiplexer 59 may also have a control terminal for receiving a selection signal Sel. Based on the selection signal Sel, the multiplexer 59 may select and output the sampling phase SP provided by the second electronic device 53 or the clock recovery circuit 15 to the analog-to-digital converter 11.

[0048] Specifically, during the connection stage, the multiplexer 59 selects and outputs the sampling phase SP provided by the clock recovery circuit 15. However, during the search procedure, the user can output a selection signal Sel through the second electronic device 53, causing the multiplexer 59 to select and output the sampling phase SP provided by the second electronic device 53 to the analog-to-digital converter 11, so as to solve the problem of mutual restraint between the target digital equalizer 131 and the clock recovery circuit 15. Additionally, different from the clock recovery circuit 15 which adjusts the sampling phase SP according to the phase error, the second electronic device 53 sequentially selects one of multiple preset phases (for example, 128 preset phases) as the sampling phase SP to provide to the analog-to-digital converter 11.

[0049] Furthermore, the second electronic device 53 can record the convergence results of the equalizer coefficients of the target digital equalizer 131 under different preset phases (i.e., different sampling phases SP) to obtain the initial coefficient value and the coefficient limit value corresponding to the x-th preset transmission channel 7(x). Therefore, in order to identify different preset phases, the second electronic device 53 takes the preset phase currently provided to the analog-to-digital converter 11 (for example, the first preset phase among 128 preset phases) as the phase zero point in step S406. Additionally, the digital signal processor 13 outputs the signal-to-noise ratio SNR1 of the slicer input signal SLin and the equalizer coefficients (not shown) of the target digital equalizer 131 to the second electronic device 53, and in response to the equalizer coefficients of the target digital equalizer 131 reaching coefficient convergence, the second electronic device 53 records the signal-to-noise ratio SNR1 and the coefficient convergence value of the slicer input signal SLin and the equalizer coefficients under the preset phase currently provided to the analog-to-digital converter 11.

[0050] Furthermore, in order to record the convergence results of the equalizer coefficients of the target digital equalizer 131 under each preset phase, the search procedure executed by the second electronic device 53 when the first electronic device 51 is connected to the signal receiver 1 through the x-th preset transmission channel 7(x) may further include the following steps.

[0051] Step S416: Determine whether each preset phase has been used as the sampling phase to be provided to the analog-to-digital converter. If not, the search procedure proceeds to steps S418 to S420, and after step S420, the search procedure returns to step S408; if so, the search procedure proceeds to steps S422 to S426.

[0052] Step S418: Stop the target digital equalizer from automatically updating the equalizer coefficients (i.e., turn off coefficient convergence).

[0053] Step S420: Change the preset phase currently provided to the analog-to-digital converter.

[0054] It can be seen that through continuous cyclic execution, the second electronic device 53 can record the signal-to-noise ratio SNR1 and the coefficient convergence value at each preset phase. Additionally, in response to determining that each preset phase has been provided to the analog-to-digital converter 11 as the sampling phase SP, the search program can proceed to steps S422 to S426.

[0055] Step S422: Select the coefficient convergence value at the preset phase with the maximum signal-to-noise ratio as the initial coefficient value corresponding to the x-th preset transmission channel.

[0056] Step S424: Within a range centered on the preset phase with the maximum signal-to-noise ratio, select the two coefficient convergence values with the maximum and minimum values as the upper limit and the lower limit of the coefficient limit value corresponding to the x-th preset transmission channel.

[0057] Step S426: Write the initial coefficient value and the coefficient limit value corresponding to the x-th preset transmission channel into the memory of the signal receiver.

[0058] Specifically, if the 64th preset phase among the 128 preset phases has the maximum signal-to-noise ratio SNR1, the second electronic device 53 can select the coefficient convergence value at the 64th preset phase as the initial coefficient value corresponding to the x-th preset transmission channel 7(x). Additionally, within a range centered on the 64th preset phase, select the two coefficient convergence values with the maximum and minimum values as the upper limit and the lower limit of the coefficient limit value corresponding to the x-th preset transmission channel 7(x).

[0059] Furthermore, in this embodiment, M / 2 preset phases before and after the center are used to determine the range size, and the size of M is determined according to the total number of preset transmission channels (i.e., N). In this embodiment, M is N * 20%. Therefore, in the case of 128 preset phases, M / 2 is 13. That is to say, the range at this time will include 13 preset phases before and after the 64th preset phase, that is, the range is from the 51st preset phase to the 77th preset phase. Then, the second electronic device 53 can select the two coefficient convergence values with the maximum and minimum values within this range as the upper limit and the lower limit of the coefficient limit value corresponding to the x-th preset transmission channel 7(x).

[0060] For example, the coefficient convergence value at the 64th preset phase is 0.1, and within the 51st to 77th preset phases, the maximum and minimum coefficient convergence values are 0.13 and 0.05 respectively. Therefore, the second electronic device 53 can record the initial coefficient value corresponding to the xth preset transmission channel 7(x) as 0.1, and record the upper limit and lower limit of the coefficient limit value corresponding to the xth preset transmission channel 7(x) as 0.13 and 0.05 respectively. Additionally, during the connection stage, if the xth preset transmission channel 7(x) matches the current transmission channel CH, the processor 55 can set the value of the equalizer coefficient to 0.1 before automatically updating the equalizer coefficient of the target digital equalizer 131, and set the upper limit and lower limit of the equalizer coefficient during update to 0.13 and 0.05 respectively.

[0061] In summary, one of the beneficial effects of the present invention is that the method and system provided by the present invention can, through the technical means of "configuring the first electronic device as a connection partner during the simulation stage to sequentially select one of multiple preset transmission channels to connect to the signal receiver, and configuring the second electronic device to execute a search program each time the first electronic device connects to the signal receiver through one of the preset transmission channels", obtain multiple initial coefficient values and multiple coefficient limit values corresponding to the aforementioned multiple preset transmission channels, thereby enabling the setting of the equalizer coefficient of the target digital equalizer during the connection stage.

[0062] The content provided above is only the preferred feasible embodiment of the present invention and is not used to limit the protection scope of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the application scope of the present invention.

[0063] Description of Reference Numerals

[0064] 1: Signal Receiver

[0065] 11: Analog-to-Digital Converter

[0066] 13: Digital Signal Processor

[0067] 15: Clock Recovery Circuit

[0068] SP: Sampling Phase

[0069] 131: Target Digital Equalizer

[0070] 1311: Feed-Forward Equalizer

[0071] 1313: Decision Feedback Equalizer

[0072] 133: Slicer

[0073] 135: Signal-to-Noise Ratio Monitor

[0074] Arx: Analog received signal

[0075] Din: Digital input signal

[0076] SLin: Slicer input signal

[0077] Syr: Received symbol

[0078] ER: Slicer error

[0079] SNR1: Signal-to-noise ratio

[0080] 3: Signal transmitter

[0081] Atx: Analog transmitted signal

[0082] CH: Transmission channel

[0083] 5: System

[0084] 51: First electronic device

[0085] 53: Second electronic device

[0086] 55: Processor

[0087] 57: Oscillator

[0088] 59: Multiplexer

[0089] Sel: Selection signal

[0090] 7(x): Preset transmission channel

[0091] S300, S302, S400, S402, S404, S406, S408, S410, S412, S414, S416,

[0092] S418, S420, S422, S424, S426: Steps

Claims

1. A method for setting a digital equalizer, applicable to a signal receiver, the signal receiver including a digital signal processor, the digital signal processor including a target digital equalizer having equalizer coefficients, and the method comprising: In an analog stage, configuring a first electronic device as a connection partner to sequentially select one of a plurality of preset transmission channels to connect to the signal receiver, and configuring a second electronic device to execute a search program each time the first electronic device connects to the signal receiver through one of the preset transmission channels to obtain a plurality of coefficient initial values and a plurality of coefficient limit values respectively corresponding to the plurality of preset transmission channels; And In a connection stage, configuring a processor to set the equalizer coefficients of the target digital equalizer according to the coefficient initial values and the coefficient limit values corresponding to one of the preset transmission channels.

2. The method according to claim 1, wherein the connection stage refers to a stage in which the signal receiver and a signal transmitter transmit and receive signals through a current transmission channel, and the step of the processor setting the equalizer coefficients of the target digital equalizer according to the coefficient initial values and the coefficient limit values corresponding to one of the preset transmission channels comprises: Determining whether one of the preset transmission channels matches the current transmission channel, and in response to determining that one of the preset transmission channels matches the current transmission channel, setting the equalizer coefficients of the target digital equalizer according to the coefficient initial values and the coefficient limit values corresponding to the preset transmission channel that matches the current transmission channel.

3. The method according to claim 2, wherein the signal receiver further includes: An analog-to-digital converter, coupled to the digital signal processor and configured to convert an analog received signal into a digital input signal according to a sampling phase, wherein the target digital equalizer receives the digital input signal and outputs a slicer input signal after filtering inter-symbol interference; And A clock recovery circuit, coupled to the digital signal processor and the analog-to-digital converter and configured to provide the sampling phase.

4. The method according to claim 3, wherein the search program executed by the second electronic device each time the first electronic device connects to the signal receiver through one of the preset transmission channels comprises the following steps: The second electronic device replaces the clock recovery circuit to provide the sampling phase to the analog-to-digital converter, and the second electronic device sequentially selects one of a plurality of preset phases as the sampling phase to provide to the analog-to-digital converter; Configuring the first electronic device to send an analog transmission signal; Determining whether the signal receiver receives the analog received signal; In response to determining that the signal receiver receives the analog received signal, taking the preset phase currently provided to the analog-to-digital converter as a phase zero point; Resetting the equalizer coefficients of the target digital equalizer; Configuring the target digital equalizer to perform automatic update of the equalizer coefficients. Determine whether the equalizer coefficients of the target digital equalizer have reached coefficient convergence; and In response to determining that the equalizer coefficients of the target digital equalizer have reached coefficient convergence, record the signal-to-noise ratio and the coefficient convergence value of the slicer input signal and the equalizer coefficients at the preset phase currently provided to the analog-to-digital converter.

5. The method according to claim 4, wherein the search program executed by the second electronic device each time the first electronic device connects to the signal receiver through one of the preset transmission channels further comprises the following steps: Determine whether each of the preset phases has been provided to the analog-to-digital converter as the sampling phase; In response to determining that each of the preset phases has not been provided to the analog-to-digital converter as the sampling phase, stop the target digital equalizer from automatically updating the equalizer coefficients, and change the preset phase currently provided to the analog-to-digital converter; and After changing the preset phase currently provided to the analog-to-digital converter, execute again the step of resetting the equalizer coefficients of the target digital equalizer.

6. The method according to claim 5, wherein the search program executed by the second electronic device each time the first electronic device connects to the signal receiver through one of the preset transmission channels further comprises the following steps: In response to determining that each of the preset phases has been provided to the analog-to-digital converter as the sampling phase, select the coefficient convergence value at the preset phase with the maximum signal-to-noise ratio as the initial coefficient value corresponding to the preset transmission channel, and within a range centered on the preset phase with the maximum signal-to-noise ratio, select the maximum and minimum of the two coefficient convergence values as the upper limit and the lower limit of the coefficient limit value corresponding to the preset transmission channel; and Write the initial coefficient value and the coefficient limit value corresponding to the preset transmission channel into the memory of the signal receiver.

7. A system for setting a digital equalizer, applicable to a signal receiver, the signal receiver includes a digital signal processor, the digital signal processor includes a target digital equalizer, the target digital equalizer has equalizer coefficients, and the system includes: A first electronic device, configured as a connection partner in the analog stage to sequentially select one of a plurality of preset transmission channels to connect to the signal receiver; A second electronic device, coupled to the first electronic device and the signal receiver in the analog stage, and configured to execute a search program each time the first electronic device connects to the signal receiver through one of the preset transmission channels to obtain a plurality of initial coefficient values and a plurality of coefficient limit values corresponding to the plurality of preset transmission channels; and A processor, disposed in the signal receiver, configured to set the equalizer coefficients of the target digital equalizer according to the initial coefficient value and the coefficient limit value corresponding to one of the preset transmission channels in the connection stage.

8. The system according to claim 7, wherein the connection stage refers to the stage in which the signal receiver and the signal transmitter transmit and receive signals through the current transmission channel, and the step of the processor setting the equalizer coefficients of the target digital equalizer according to the initial coefficient value and the coefficient limit value corresponding to one of the preset transmission channels includes: Determining whether one of the preset transmission channels matches the current transmission channel, and in response to determining that one of the preset transmission channels matches the current transmission channel, setting the equalizer coefficients of the target digital equalizer according to the initial coefficient value and the coefficient limit value corresponding to the preset transmission channel that matches the current transmission channel.

9. The system according to claim 7, further comprising: An oscillator configured to provide a clock frequency to the first electronic device and the signal receiver in the analog stage.

10. The system according to claim 8, wherein the signal receiver further comprises: An analog-to-digital converter coupled to the digital signal processor and configured to convert an analog received signal into a digital input signal according to a sampling phase, wherein the target digital equalizer receives the digital input signal and outputs a slicer input signal after filtering inter-symbol interference; And A clock recovery circuit coupled to the digital signal processor and the analog-to-digital converter and configured to provide the sampling phase.

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