Semiconductor device, power module and electronic equipment

Abstract

The invention provides a semiconductor device, a power module and electronic equipment, relates to the technical field of semiconductors, and is used for enabling the semiconductor device to realize conduction under reverse bias voltage under an enhanced condition. The semiconductor device comprises a substrate, a grid electrode, a conductive electrode, a first current blocking layer, a first doping layer, a first electrode, a second current blocking layer, a second doping layer, a second electrode, a dielectric layer and a third electrode, wherein the conductive electrode is arranged on one side, close to the substrate, of the grid electrode; the first current blocking layer, the first doping layer and the first electrode are arranged in a stacked mode in the first direction and in the direction away from the substrate and are arranged on the first side of the grid electrode; the second current blocking layer, the second doping layer and the second electrode are arranged in a stacked mode in the first direction and in the direction away from the substrate; the second doped layer and the second electrode are arranged on the second side of the grid electrode; the second current blocking layer is located on the side, close to the substrate, of the conductive electrode and the second current blocking layer. The semiconductor device is applied to the power module.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor device, a power module, and an electronic device. Background Art

[0002] As a new type of ultra-wide bandgap (UWBG) semiconductor material, Ga2O3 (gallium oxide) has an ultra-wide bandgap of more than 4.8 eV, a theoretical breakdown electric field strength of 8 MV / cm, and a lower on-resistance, showing broad application prospects in the field of high-power devices. However, currently, in an enhanced gallium oxide-based metal-oxide-semiconductor field-effect transistor (MOSFET), conduction cannot be achieved under reverse bias, which greatly limits the development of gallium oxide-based power devices. Summary of the Invention

[0003] An object of an embodiment of the present disclosure is to provide a semiconductor device, a power module, and an electronic device, which are used to enable the semiconductor device to achieve conduction under reverse bias under enhanced conditions.

[0004] To achieve the above object, the embodiments of the present disclosure provide the following technical solutions: On the one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a gate, a conductive electrode, a first current blocking layer, a first doping layer, a first electrode, a second current blocking layer, a second doping layer, a second electrode, a dielectric layer, and a third electrode.

[0005] Wherein, the gate is disposed on one side of the substrate in a first direction, and the first direction is the thickness direction of the substrate; the conductive electrode is disposed on the side of the gate close to the substrate; the first current blocking layer, the first doping layer, and the first electrode are stacked in the first direction and away from the substrate, and are disposed on a first side of the gate; the second current blocking layer, the second doping layer, and the second electrode are stacked in the first direction and away from the substrate; the second doping layer and the second electrode are disposed on a second side of the gate, and the first side and the second side of the gate are respectively opposite sides of the gate in a second direction, and the second direction is perpendicular to the thickness direction of the substrate; the second current blocking layer is located on the side of the conductive electrode and the second current blocking layer close to the substrate; the dielectric layer is located between each of the first current blocking layer, the first doping layer, the first electrode, the second doping layer, the second current blocking layer, and the conductive electrode and the gate; the dielectric layer also covers the surface of the conductive electrode close to the substrate and two opposite sides of the conductive electrode in the second direction; the third electrode is disposed on the side of the substrate away from the gate.

[0006] In the above semiconductor device, the gate is disposed on one side of the substrate in the first direction. The first current blocking layer, the first doping layer, and the first electrode are stacked in the first direction and away from the substrate. The third electrode is disposed on the side of the substrate away from the gate. Thus, when the gate voltage of the semiconductor device is less than the threshold voltage and the voltage of the third electrode is greater than the voltage of the first electrode, the semiconductor device is in the off state; when the gate voltage of the semiconductor device is greater than the threshold voltage of the semiconductor device and the voltage of the third electrode is greater than the voltage of the first electrode, the conductivity of the side of the first current blocking layer close to the gate increases, and the semiconductor device conducts. At this time, the current flows from the third electrode through the substrate, the side of the first current blocking layer close to the gate, the first doping layer to the first electrode. Therefore, the semiconductor device provided by this embodiment is an enhancement-mode semiconductor device.

[0007] On the other hand, since the conductive electrode is disposed on the side of the gate close to the substrate, the second current blocking layer, the second doping layer, and the second electrode are stacked in the first direction and away from the substrate. The second doping layer and the second electrode are disposed on the second side of the gate. The first side and the second side of the gate are respectively the opposite sides of the gate in the second direction. Therefore, when the gate voltage of the semiconductor device is less than the threshold voltage, the voltage of the second electrode is greater than the voltage of the third electrode, and a voltage is also applied to the conductive electrode, the conductive electrode can be regarded as a gate. In this case, the conductivity of the side of the second current blocking layer close to the gate increases, so that the semiconductor device can also be turned on. At this time, the current flows from the second electrode through the second doping layer, the side of the second current blocking layer close to the gate, the substrate to the third electrode. Thus, the enhancement-mode semiconductor device provided by this embodiment can be turned on under reverse bias without applying a voltage to the gate, thereby improving the passive freewheeling ability of the semiconductor device, that is, the operating ability of the semiconductor device in the third quadrant.

[0008] In addition, when the semiconductor device is conducting forward and backward, there is no PN junction, the generated capacitance is small, the switching speed is fast, and the current density is high.

[0009] In some embodiments, it further includes: a third doping layer, and the third doping layer includes a first doping portion; the first doping portion is disposed on the side of the first current blocking layer close to the substrate and on one side of the conductive electrode in the second direction.

[0010] In some embodiments, the surface of the third doping layer close to the substrate is flush with the surface of the second current blocking layer away from the substrate.

[0011] In some embodiments, the third doping layer further includes a second doping portion. The second doping portion is disposed on the side of the first doping portion close to the substrate and is connected to the first doping portion; the side surface of the second doping portion is in contact with the side surface of the second current blocking layer.

[0012] In some embodiments, in the orthographic projection onto the substrate, a part of the conductive electrode overlaps with a part of the second current blocking layer; alternatively, in the orthographic projection onto the substrate, the conductive electrode is located within the boundary range of the second current blocking layer.

[0013] In some embodiments, the doping concentration of the first doped layer is greater than that of the first current blocking layer; the doping concentration of the second doped layer is greater than that of the second current blocking layer.

[0014] In some embodiments, the doping concentration of the third doped layer is greater than that of the first current blocking layer.

[0015] In some embodiments, the first doped layer, the second doped layer, the third doped layer and the substrate have the same doping type.

[0016] In some embodiments, the first electrode, the second electrode and the conductive electrode are electrically connected.

[0017] In some embodiments, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the second sub-dielectric layer is closer to the gate than the first sub-dielectric layer; the conductive electrode is located between the first sub-dielectric layer and the second sub-dielectric layer.

[0018] In some embodiments, further included is: a drift layer, disposed between the substrate and the first current blocking layer, and between the substrate and the second current blocking layer; the doping type of the drift layer is the same as that of the substrate, and the doping concentration of the drift layer is less than that of the substrate.

[0019] In some embodiments, the materials of the first doped layer and the second doped layer both include gallium oxide, and the doping ions both include silicon ions; the materials of the first current blocking layer and the second current blocking layer both include gallium oxide, and the doping ions both include magnesium ions.

[0020] In some embodiments, the material of the third doped layer includes gallium oxide, and the doping ions include silicon ions.

[0021] On the other hand, a power module is provided, including the semiconductor device as described in any of the above embodiments.

[0022] On the other hand, an electronic device is provided, including the power module as described in any of the above embodiments.

[0023] The power module and the electronic device have the same structure and beneficial technical effects as the semiconductor device provided in some of the above embodiments, which will not be elaborated here. Brief Description of the Drawings

[0024] To more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings required in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, the actual timings of the signals, etc.

[0025] Figure 1 Structural diagram of an electronic device provided in some embodiments of the present disclosure; Figure 2 Structural diagram of a semiconductor device provided in some embodiments of the present disclosure; Figure 3 Structural diagram of another semiconductor device provided in some embodiments of the present disclosure; Figure 4 Structural diagram of another semiconductor device provided in some embodiments of the present disclosure; Figure 5 Structural diagram of another semiconductor device provided in some embodiments of the present disclosure; Figure 6 Structural diagram of another semiconductor device provided in some embodiments of the present disclosure; Figure 7 Structural diagram of another semiconductor device provided in some embodiments of the present disclosure; Figure 8 Output characteristic curve diagram of a semiconductor device provided in some embodiments of the present disclosure when it is forward-conducting; Figure 9 Transfer characteristic curve diagram of a semiconductor device provided in some embodiments of the present disclosure when it is forward-conducting; Figure 10 Conduction characteristic curve diagram of a semiconductor device provided in some embodiments of the present disclosure under reverse bias voltage; Figure 11 Flow schematic diagram of a preparation method of a semiconductor device provided in some embodiments of the present disclosure; Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 and Figure 23Schematic diagram of the process of a method for manufacturing a display panel provided by some embodiments of the present disclosure. Detailed implementation manners

[0026] Next, in combination with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0027] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples", etc., are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily directed to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0028] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0029] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content herein.

[0030] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0031] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0032] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude As used herein, "parallel", "perpendicular", and "equal" include the stated situations and situations similar to the stated situations, where the range of the similar situations is within an acceptable deviation range, and the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal values is less than or equal to 5% of either one of them.

[0033] It should be understood that when a layer or element is referred to as being on another layer or substrate, the layer or element can be directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0034] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Therefore, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0035] As Figure 1 shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 can be an electronic device such as a fast charger, an uninterruptible power supply (UPS), a power motor, etc.

[0036] Continuing to refer to Figure 1 , the electronic device 1000 includes a power module 1001 and a circuit board 1002. The power module 1001 and the circuit board 1002 are electrically connected, and the circuit board 1002 converts an external power supply into the voltage or current required for the operation of the power module 1001.

[0037] Exemplarily, the circuit board 1002 can include a printed circuit board (PCB), etc.

[0038] Exemplarily, the circuit board 1002 may include a plurality of conductive layers. The plurality of conductive layers within the circuit board 1002 may be separated from each other by dielectric layers.

[0039] The above-mentioned power module 1001 includes semiconductor devices.

[0040] The above-mentioned semiconductor devices will be described in detail below.

[0041] Reference Figure 2 , the semiconductor device 100 includes a substrate 10, a gate 70, a conductive electrode 80, a first current blocking layer 41, a first doping layer 31, a first electrode 51, a second current blocking layer 42, a second doping layer 32, a second electrode 52, a dielectric layer 60, and a third electrode 53.

[0042] Among them, the gate 70 is provided on one side of the substrate 10 in the first direction X, and the first direction X is the thickness direction of the substrate 10; the conductive electrode 80 is provided on the side of the gate 70 close to the substrate 10; the first current blocking layer 41, the first doping layer 31, and the first electrode 51 are stacked in the first direction X and away from the substrate 10, and are provided on the first side C1 of the gate 70.

[0043] The second current blocking layer 42, the second doping layer 32, and the second electrode 52 are stacked in the first direction X and away from the substrate 10; the second doping layer 32 and the second electrode 52 are provided on the second side C2 of the gate 70, and the first side C1 and the second side C2 of the gate 70 are respectively the opposite sides of the gate 70 in the second direction Y, and the second direction Y is perpendicular to the thickness direction of the substrate 10; the second current blocking layer 42 is located on the side of the conductive electrode 80 and the second current blocking layer 42 close to the substrate 10.

[0044] The dielectric layer 60 is located between each of the first current blocking layer 41, the first doping layer 31, the first electrode 51, the second doping layer 32, the second current blocking layer 42, and the conductive electrode 80 and the gate 70; the dielectric layer 60 also covers the surface of the conductive electrode 80 close to the substrate 10, and the two opposite sides of the conductive electrode 80 along the second direction Y; the third electrode 53 is provided on the side of the substrate 10 away from the gate 70.

[0045] In the above semiconductor device 100, a gate 70 is provided on one side of a substrate 10 in a first direction X. A first current blocking layer 41, a first doping layer 31, and a first electrode 51 are stacked in the first direction X and away from the substrate 10. A third electrode 53 is provided on a side of the substrate 10 away from the gate 70. Thus, when the voltage of the gate 70 of the semiconductor device 100 is less than the threshold voltage and the voltage of the third electrode 53 is greater than the voltage of the first electrode 51, the semiconductor device 100 is in an off state; when the voltage of the gate 70 of the semiconductor device 100 is greater than the threshold voltage of the semiconductor device 100 and the voltage of the third electrode 53 is greater than the voltage of the first electrode 51, the conductivity of a side of the first current blocking layer 41 close to the gate 70 increases, and the semiconductor device 100 conducts. At this time, current flows from the third electrode 53 through the substrate 10, the side of the first current blocking layer 41 close to the gate 70, the first doping layer 31 to the first electrode 51. Thus, the semiconductor device 100 provided in this embodiment is an enhancement-mode semiconductor device.

[0046] On the other hand, since a conductive electrode 80 is provided on a side of the gate 70 close to the substrate 10, a second current blocking layer 42, a second doping layer 32, and a second electrode 52 are stacked in the first direction X and away from the substrate 10. The second doping layer 32 and the second electrode 52 are provided on a second side C2 of the gate 70. A first side C1 and the second side C2 of the gate 70 are respectively opposite sides of the gate 70 in a second direction Y. Therefore, when the voltage of the gate 70 of the semiconductor device 100 is less than the threshold voltage, the voltage of the second electrode 52 is greater than the voltage of the third electrode 53, and a voltage is also applied to the conductive electrode 80, the conductive electrode 80 can be regarded as a gate. In this case, the conductivity of a side of the second current blocking layer 42 close to the gate 70 increases, so that the semiconductor device 100 can also be turned on. At this time, current flows from the second electrode 52 through the second doping layer 32, the side of the second current blocking layer 42 close to the gate 70, the substrate 10 to the third electrode 53. Thus, for the enhancement-mode semiconductor device provided in this embodiment, conduction can be achieved under a reverse bias without applying a voltage to the gate 70, thereby improving the passive freewheeling ability of the semiconductor device 100, that is, the operating ability of the semiconductor device 100 in the third quadrant.

[0047] In addition, when the semiconductor device 100 conducts in the forward and reverse directions, there is no PN junction, the generated capacitance is small, the switching speed is fast, and the current density is high.

[0048] In the semiconductor device 100, the first electrode 51 and the second electrode 52 are source electrodes, and the third electrode 53 is a drain electrode.

[0049] In some embodiments, refer to Figure 3, in the orthographic projection onto the substrate 10, the conductive electrode 80 is within the boundary of the second current blocking layer 42. When the gate 70 voltage of the semiconductor device 100 is less than the threshold voltage, the voltage of the second electrode 52 is greater than the voltage of the third electrode 53, and a voltage is applied to the conductive electrode 80 at the same time, the conductive electrode 80 can be regarded as a gate. Since the conductive electrode 80 is within the boundary of the second current blocking layer 42, the overlapping area between the conductive electrode 80 and the second current blocking layer 42 is large, enabling the electric field of the conductive electrode 80 to more effectively modulate the depletion region of the second current blocking layer 42, enhancing the electric field control ability, and also improving the stability of the threshold voltage of the semiconductor device 100 and reducing the leakage current. In addition, the control area of the conductive electrode 80 can be expanded, which is beneficial to forming a more uniform conductive channel.

[0050] In some embodiments, referring to Figure 2 , in the orthographic projection onto the substrate 10, part of the conductive electrode 80 overlaps with part of the second current blocking layer 42. This can reduce the parasitic capacitance between the conductive electrode 80 and the second current blocking layer 42, thereby improving the switching speed of the semiconductor device 100. In addition, it is beneficial to reduce the area of the high-resistance region, which can increase the operating current density of the semiconductor device 100.

[0051] In some embodiments, the doping concentration of the first doped layer 31 is greater than the doping concentration of the first current blocking layer 41. The high doping concentration of the first doped layer 31 enhances the carrier concentration and migration efficiency, provides a low-resistance channel for carriers, and is beneficial to the efficient vertical transport of carriers (e.g., from the source to the drain), thereby reducing the power loss of the semiconductor device 100. The low doping concentration of the first current blocking layer 41 is beneficial to forming a uniformly distributed electric field, avoiding local electric field concentration, and improving the breakdown voltage of the semiconductor device 100. When the semiconductor device 100 is in the on state, the low-concentration first current blocking layer 41 has less resistance to the vertical current path. Combining with the high-concentration first doped layer 31 is beneficial to achieving charge balance, reducing the on-resistance while maintaining high breakdown voltage.

[0052] Exemplarily, the doping concentration of the first doped layer 31 is 5E18 cm -3 ~5E19 cm -3 , such as 5E18 cm -3 , 6E18 cm -3 or 5E19 cm -3 .

[0053] Exemplarily, the doping concentration of the first current blocking layer 41 is 5E14 cm -3 ~5E15 cm -3 , such as 5E14 cm -3 , 6E14 cm-3 、 7E14 cm -3 or 5E15 cm -3 。

[0054] In some embodiments, the doping concentration of the second doping layer 32 is greater than that of the second current blocking layer 42. The high doping concentration of the second doping layer 32 enhances the carrier concentration and migration efficiency, provides a low-resistance channel for carriers, and is conducive to the efficient vertical transport of carriers (e.g., from the source to the drain), thereby reducing the power loss of the semiconductor device 100. The low doping concentration of the second current blocking layer 42 is conducive to forming a uniformly distributed electric field, avoiding local electric field concentration, and enhancing the breakdown voltage of the semiconductor device 100. When the semiconductor device 100 is in the on state, the low-concentration second current blocking layer 42 has less resistance to the vertical current path, and in combination with the high-concentration second doping layer 32, it is conducive to achieving charge balance and reducing the on-resistance while maintaining high breakdown voltage.

[0055] In addition, due to the high doping concentration of the second doping layer 32, the semiconductor device 100 can increase the current density flowing through the second doping layer 32 under reverse bias voltage.

[0056] Exemplarily, the doping concentration of the second doping layer 32 is 5E18 cm -3 ~5E19 cm -3 , such as 5E18 cm -3 、 6E18 cm -3 or 5E19 cm -3 。

[0057] Exemplarily, the doping concentration of the second current blocking layer 42 is 5E14 cm -3 ~5E15 cm -3 , such as 5E14 cm -3 、 6E14 cm -3 、 7E14 cm -3 or 5E15 cm -3 。

[0058] In some embodiments, the materials of the first doping layer 31 and the second doping layer 32 both include gallium oxide, and the doping ions both include silicon ions. Since the bandgap of gallium oxide (β-Ga2O3) is 4.8 eV, far exceeding that of silicon carbide (3.2 eV) and gallium nitride (3.4 eV), it has an ultra-high breakdown electric field strength and higher breakdown voltage resistance. In addition, gallium oxide also has a lower on-resistance and higher power conversion efficiency. The low on-resistance of gallium oxide can also reduce the conduction loss.

[0059] Among them, the doping ions in the first doping layer 31 and the second doping layer 32 both include silicon ions. The silicon ions act as shallow donor impurities in gallium oxide and can provide a high concentration of free electrons. In this way, the first doping layer 31 and the second doping layer 32 are N-type conductive. The N-type conductivity and the wide bandgap characteristic of gallium oxide work together to withstand a high critical breakdown electric field of 8 MV / cm, making the semiconductor device 100 suitable for high-voltage application scenarios. Moreover, the diffusion coefficient of silicon ions in gallium oxide is low, which not only helps to form a steep doping interface but also helps to suppress doping drift. In this way, the carrier distribution can be accurately controlled, and the stability is better when working under high-temperature conditions.

[0060] In addition, due to the extremely low p-type doping efficiency of gallium oxide and the poor hole mobility, doping silicon ions in the first doping layer 31 and the second doping layer 32 can avoid this technical problem.

[0061] In some embodiments, the thickness of the first doping layer 31 is 0.4 μm to 0.6 μm, such as 0.4 μm, 0.5 μm or 0.6 μm.

[0062] In some embodiments, the materials of the first current blocking layer 41 and the second current blocking layer 42 both include gallium oxide. Since the first current blocking layer 41 is in contact with the first doping layer 31 and the materials of the first current blocking layer 41 and the first doping layer 31 both include gallium oxide, it can not only eliminate the heterointerface defects, reduce the interface state density, improve the carrier transport efficiency, but also simplify the epitaxial growth process, avoid the lattice mismatch problem caused by heteroepitaxy, and significantly improve the manufacturing yield of the semiconductor device.

[0063] Similarly, since the second current blocking layer 42 is in contact with the second doping layer 32 and the materials of the second current blocking layer 42 and the second doping layer 32 both include gallium oxide, it can also eliminate the heterointerface defects, reduce the interface state density, improve the carrier transport efficiency, and simplify the epitaxial growth process, avoid the lattice mismatch problem caused by heteroepitaxy, and significantly improve the manufacturing yield of the semiconductor device.

[0064] Among them, the doping ions in the first current blocking layer 41 and the second current blocking layer 42 both include magnesium ions. Since magnesium ion doping can form deep-level acceptor states in gallium oxide and effectively compensate for the intrinsic carriers, the first current blocking layer 41 and the second current blocking layer 42 both exhibit high-resistance characteristics, thereby suppressing the leakage current and improving the breakdown voltage capability of the semiconductor device 100.

[0065] In some embodiments, the thickness of the first current blocking layer 41 is 0.8 μm to 1.2 μm, such as 0.8 μm, 1.0 μm or 1.2 μm.

[0066] In some embodiments, the conductive electrode 80, the first electrode 51, and the second electrode 52 are made of the same material. In this way, the conductive electrode 80, the first electrode 51, and the second electrode 52 can be prepared simultaneously and formed in the same preparation step, thereby reducing process steps such as photolithography and deposition, and lowering the manufacturing complexity and production cost.

[0067] Exemplarily, the materials of the conductive electrode 80, the first electrode 51, and the second electrode 52 all include gold or nickel. In other embodiments, the materials of the conductive electrode 80, the first electrode 51, and the second electrode 52 may also include other conductive metals.

[0068] In some embodiments, the material of the third electrode 53 may be the same as that of the first electrode 51 and the second electrode 52.

[0069] Exemplarily, the materials of the third electrode 53 all include gold or titanium. In other embodiments, the materials of the third electrode 53 may also include other conductive metals.

[0070] In some embodiments, the first electrode 51, the second electrode 52, and the conductive electrode 80 are electrically connected. That is, the potentials of the first electrode 51, the second electrode 52, and the conductive electrode 80 can be input using the same input terminal, which can not only reduce the structural complexity of the semiconductor device 100, but also improve the response speed of the semiconductor device 100.

[0071] In some embodiments, the semiconductor device 100 further includes: a connection part (not shown), the connection part is disposed on at least one side of the opposite sides of the gate 70 in the third direction Z, the third direction Z is perpendicular to the first direction X and perpendicular to the second direction Y; one end of the connection part is electrically connected to the conductive electrode 80, and the other end is electrically connected to the first electrode 51 and the second electrode 52; the dielectric layer 60 is located between the gate 70 and the connection part. In this way, the connection part electrically connects the first electrode 51, the second electrode 52, and the conductive electrode 80, which can reduce the structural complexity of the semiconductor device 100 and improve the response speed of the semiconductor device 100.

[0072] In some embodiments, the dielectric layer 60 includes a first sub-dielectric layer 61 and a second sub-dielectric layer 62, the second sub-dielectric layer 62 is closer to the gate 70 than the first sub-dielectric layer 61; the conductive electrode 80 is located between the first sub-dielectric layer 61 and the second sub-dielectric layer 62. The first sub-dielectric layer 61 and the second sub-dielectric layer 62 are separate film layers on the side of the gate 70 close to the substrate 10, and the first sub-dielectric layer 61 and the second sub-dielectric layer 62 are in contact with each other on the sidewalls of the gate 70.

[0073] In some embodiments, the materials of the first sub-medium layer 61 and the second sub-medium layer 62 may be the same. In other embodiments, the materials of the first sub-medium layer 61 and the second sub-medium layer 62 may also be different.

[0074] Exemplarily, the materials of both the first sub-medium layer 61 and the second sub-medium layer 62 are silicon dioxide (SiO2); or, the materials of both the first sub-medium layer 61 and the second sub-medium layer 62 are aluminum oxide (Al2O3).

[0075] Exemplarily, the material of the first sub-medium layer 61 is silicon dioxide (SiO2), and the material of the second sub-medium layer 62 is aluminum oxide (Al2O3).

[0076] Exemplarily, the material of the first sub-medium layer 61 is aluminum oxide (Al2O3), and the material of the second sub-medium layer 62 is silicon dioxide (SiO2).

[0077] In some embodiments, with continued reference to Figure 2 , the semiconductor device 100 further includes: a drift layer 20, which is disposed between the substrate 10 and the first current blocking layer 41, and between the substrate 10 and the second current blocking layer 42. The drift layer 20 is configured to withstand the high voltage of the semiconductor device 100 in the off state or reverse bias.

[0078] Wherein, the doping type of the drift layer 20 is the same as that of the substrate 10, and the doping concentration of the drift layer 20 is less than that of the substrate 10. The doping type of the drift layer 20 is the same as that of the substrate 10, so that the drift layer 20 can be directly epitaxially grown on the substrate 10 without switching the doping type, which can not only reduce interface defects and stress, but also avoid the distortion of the interface electric field of the heterojunction; secondly, the substrate 10 is highly doped (low resistance) so that it can serve as a mechanical support and current path, and the drift layer 20 is lightly doped, so that the drift layer 20 can bear high voltage and form a wider depletion layer, thereby dispersing the electric field strength, avoiding breakdown, and improving the breakdown voltage withstand ability of the semiconductor device 100.

[0079] In some embodiments, the materials of both the substrate 10 and the drift layer 20 include gallium oxide.

[0080] Wherein, the doping ions of both the substrate 10 and the drift layer 20 include silicon ions.

[0081] Exemplarily, the doping concentration of the substrate 10 is greater than 5E18 cm -3 . For example, the doping concentration of the substrate 10 is 5E18 cm -3 ~5E19 cm -3 .

[0082] Exemplarily, the doping concentration of the drift layer 20 is 1E16 cm-3 ~5E17 cm -3 For example, the doping concentration of the drift layer 20 is 1E16 cm -3 or 5E17 cm -3 。

[0083] In some embodiments, the thickness of the substrate 10 is 600 μm to 700 μm, for example: 600 μm, 650 μm or 700 μm.

[0084] In some embodiments, the thickness of the drift layer 20 is 6 μm to 8 μm, such as 6 μm, 7 μm or 8 μm.

[0085] Reference Figure 4 or Figure 5 , the semiconductor device 100 further includes: a third doping layer 33, and the third doping layer 33 includes a first doping portion 331; the first doping portion 331 is disposed on a side of the first current blocking layer 41 close to the substrate 10 and is located on a side of the conductive electrode 80 along the second direction Y. In this way, when the semiconductor device 100 operates under a forward bias voltage, the depletion of the third doping layer 33 by the conductive electrode 80 can be weakened, so as to ensure that the channel formed by the gate 70 will not be blocked by the depletion layer formed by the conductive electrode 80, which is beneficial to improving the current density of the semiconductor device 100 under the forward bias voltage.

[0086] In some embodiments, reference Figure 4 or Figure 5 , the surface of the third doping layer 33 close to the substrate 10 is flush with the surface of the second current blocking layer 42 away from the substrate 10. In this way, it can be ensured to the greatest extent that the channel formed by the gate 70 will not be blocked by the depletion layer formed by the conductive electrode 80, and the current density of the semiconductor device 100 under the forward bias voltage is improved.

[0087] In some embodiments, reference Figure 6 or Figure 7 , the third doping layer 33 further includes a second doping portion 332, the second doping portion 332 is disposed on a side of the first doping portion 331 close to the substrate 10 and is connected to the first doping portion 331; the side surface of the second doping portion 332 is in contact with the side surface of the second current blocking layer 42. In this way, not only can the current density of the semiconductor device 100 when operating under a forward bias voltage be improved, but also the current density of the semiconductor device 100 when operating under a reverse bias voltage can be improved.

[0088] When the semiconductor device 100 includes the third doping layer 33, the doping concentration of the third doping layer 33 is greater than that of the first current blocking layer 41. In this way, when the semiconductor device 100 operates under a forward bias voltage, it can ensure that the channel formed by the gate 70 will not be blocked by the depletion layer formed by the conductive electrode 80, improving the current density of the semiconductor device 100 under the forward bias voltage; it can also improve the current density of the semiconductor device 100 when operating under a reverse bias voltage.

[0089] Exemplarily, the doping concentration of the third doping layer 33 is 5E18 cm -3 ~5E19 cm -3 , for example 5E18 cm -3 、6E18 cm -3 or 5E19 cm -3 .

[0090] Exemplarily, the doping concentration of the first current blocking layer 41 is 5E14 cm -3 ~5E15 cm -3 , for example 5E14 cm -3 、6E14 cm -3 、7E14 cm -3 or 5E15 cm -3 .

[0091] In some embodiments, the doping types of the first doping layer 31, the second doping layer 32, the third doping layer 33 and the substrate 10 are the same. This can provide a continuous conduction path for electrons, reduce the on-resistance of the semiconductor device 100, and can also simplify the epitaxial growth process, reducing the accumulation of interface defects caused by doping type switching, thereby improving the reliability of the semiconductor device 100.

[0092] In some embodiments, the material of the third doping layer 33 includes gallium oxide, and the doping ions include silicon ions. That is, the materials of the first doping layer 31 and the third doping layer 33 located on both sides of the first current blocking layer 41 are the same, and the doped ions are also the same. In this way, a PN junction will not be formed in the semiconductor device 100, the capacitance can be reduced, the switching speed can be increased, and the operating current of the semiconductor device 100 can be increased.

[0093] Similarly, under a reverse bias voltage, the materials of the second doping layer 32 and the third doping layer 33 on both sides of the second current blocking layer 42 are the same, and the doped ions are also the same. In this way, a PN junction will not be formed in the semiconductor device 100, the capacitance can be reduced, the switching speed can be increased, and the operating current of the semiconductor device 100 can be increased.

[0094] Figure 8 FIG. is an output characteristic curve diagram of a semiconductor device 100 provided by some embodiments of the present disclosure when forward conducting.Figure 8 The abscissa in it represents the voltage V DS (that is, the third electrode 53 is the drain of the semiconductor device 100, the first electrode 51 is the source of the semiconductor device 100, and V DS is the voltage difference between the third electrode 53 and the first electrode 51), and the ordinate represents the current I DS magnitude (I DS refers to the magnitude of the current from the drain to the source, that is, the magnitude of the current from the third electrode 53 to the first electrode 51). Figure 9 This is a transfer characteristic curve graph of a semiconductor device 100 provided by some embodiments of the present disclosure when it is forward-conducting, Figure 9 where the abscissa represents the gate voltage V g magnitude, and the ordinate represents the current I DS magnitude. In Figure 8 and Figure 9 , it can be seen from Figure 8 that the semiconductor device 100 has a field effect, and the current I DS increases as the gate voltage V g increases. When the gate voltage V g = 0, there is no current in the semiconductor device 100. In Figure 9 , when the fixed voltage V DS = 20V, it can be seen that the threshold voltage V th of the semiconductor device 100 is about 3V, and the semiconductor device 100 is an enhancement-type semiconductor device.

[0095] Figure 10 This is a conduction characteristic curve graph of a semiconductor device 100 provided by some embodiments of the present disclosure under reverse bias, Figure 10 where the abscissa represents the voltage V SD magnitude (that is, the third electrode 53 is the drain of the semiconductor device 100, the second electrode 52 is the source of the semiconductor device 100, and V SD is the voltage difference between the second electrode 52 and the third electrode 53), and the ordinate represents the current I SD magnitude (I SD refers to the magnitude of the current from the source to the drain, that is, the magnitude of the current from the second electrode 52 to the third electrode 53). Among them, V DS = -10V, that is, V SD = 10V (where the second electrode 52 is electrically connected to the conductive electrode 80, the second electrode 52 is the source, and the third electrode 53 is the drain), and the gate voltage V g = 0V. In this case, from the I-V curve of the semiconductor device 100, it can be seen that the semiconductor device 100 is turned on when V SD = 3V, and at VSD = Current I at 10V SD Higher density.

[0096] Embodiments of the present disclosure also provide a method for manufacturing a semiconductor device. Refer to Figure 11 , including the following steps: Step S1: Referring to Figures 12 - 16 , form a first stacked structure D1 and a second stacked structure D2 on one side of the substrate 10 along the first direction X, where the first direction X is the thickness direction of the substrate 10; the first stacked structure D1 and the second stacked structure D2 are spaced apart along the second direction Y, and a first groove G1 is formed therebetween, the second direction Y is perpendicular to the first direction X; the first stacked structure D1 includes a first current blocking layer 41 and a first doping layer 31 disposed on the side of the first current blocking layer 41 away from the substrate 10; the second stacked structure D2 includes a second current blocking layer 42 and a second doping layer 32 disposed on the side of the second current blocking layer 42 away from the substrate 10; a part of the surface of the second current blocking layer 42 is exposed by the first groove G1.

[0097] Among them, step S1 includes: Step S11: Referring to Figure 12 , sequentially form an initial drift layer 200, an initial first current blocking layer 410, and an initial first doping layer 310 on one side of the substrate 10.

[0098] Here, the materials of the substrate 10, the initial drift layer 200, the initial first current blocking layer 410, and the initial first doping layer 310 all include gallium oxide.

[0099] Among them, the doping ions of the substrate 10 include silicon ions, and the doping concentration of the substrate 10 is greater than 5E18 cm -3 .

[0100] For example, the doping concentration of the substrate 10 is 5E18 cm -3 ~5E19 cm -3 .

[0101] In some embodiments, the thickness of the substrate 10 is 600 μm to 700 μm, for example: 600 μm, 650 μm, or 700 μm.

[0102] In some embodiments, the processes for forming the initial drift layer 200, the initial first current blocking layer 410, and the initial first doping layer 310 include a metal organic chemical vapor deposition process (Metal-Organic Chemical Vapor Deposition, MOCVD).

[0103] In some embodiments, during the process of forming the initial drift layer 200, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700°C to 800°C, such as 700°C, 750°C or 800°C, and the growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar or 45 mbar.

[0104] Among them, the molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, such as 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0105] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, such as 17000 μmol / min, 18000 μmol / min or 19000 μmol / min.

[0106] The molar flow rate of silane is 0.0004 μmol / min to 0.0006 μmol / min, such as 0.0004 μmol / min, 0.0005 μmol / min or 0.0006 μmol / min.

[0107] In some embodiments, the thickness of the initial drift layer 200 is 6 μm to 8 μm, such as 6 μm, 7 μm or 8 μm.

[0108] In some embodiments, during the process of forming the initial first current blocking layer 410, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the magnesium source used includes bis(cyclopentadienyl) magnesium (Cp2Mg), the carrier gas used is argon, the growth temperature is 700°C to 800°C, such as 700°C, 750°C or 800°C, and the growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar or 45 mbar.

[0109] Among them, the molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, such as 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0110] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, such as 17000 μmol / min, 18000 μmol / min or 19000 μmol / min.

[0111] The molar flow rate of magnesium bis(cyclopentadienyl) is 2.4 μmol / min to 2.6 μmol / min, such as 2.4 μmol / min, 2.5 μmol / min, or 2.6 μmol / min.

[0112] In some embodiments, the thickness of the initial first current blocking layer 410 is 0.8 μm to 1.2 μm, such as 0.8 μm, 1 μm, or 1.2 μm.

[0113] In some embodiments, during the formation of the initial first doped layer 310, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700 °C to 800 °C, such as 700 °C, 750 °C, or 800 °C, and the growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar, or 45 mbar.

[0114] Among them, the molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, such as 35 μmol / min, 38 μmol / min, or 40 μmol / min.

[0115] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, such as 17000 μmol / min, 18000 μmol / min, or 19000 μmol / min. [[ID=1S]]

[0116] The molar flow rate of silane is 1.0 μmol / min to 1.2 μmol / min, such as 1.0 μmol / min, 1.1 μmol / min, or 1.2 μmol / min.

[0117] In some embodiments, the thickness of the initial first doped layer 310 is 0.4 μm to 0.6 μm, such as 0.4 μm, 0.5 μm, or 0.6 μm.

[0118] In some embodiments, step S11 further includes: between the formation of the initial drift layer 200 and the formation of the initial first current blocking layer 410, further including: forming an initial third doped layer 330.

[0119] In some embodiments, during the process of forming the initial third doped layer 330, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700°C to 800°C, such as 700°C, 750°C or 800°C, and the growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar or 45 mbar.

[0120] Among them, the molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, such as 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0121] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, such as 17000 μmol / min, 18000 μmol / min or 19000 μmol / min.

[0122] The molar flow rate of silane is 1.0 μmol / min to 1.2 μmol / min, such as 1.0 μmol / min, 1.1 μmol / min or 1.2 μmol / min.

[0123] In some embodiments, the thickness of the initial third doped layer 330 is 0.4 μm to 0.6 μm, such as 0.4 μm, 0.5 μm or 0.6 μm.

[0124] Step S12: Refer to Figure 13 , remove the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 located in the first target area X1 to form a first opening K1; the bottom surface of the first opening K1 is lower than the bottom surface of the initial first current blocking layer 410.

[0125] Here, the steps of removing the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 located in the first target area X1 include: setting a mask on the surface of the initial first doped layer 310 away from the substrate 10, and the mask exposes the initial first doped layer 310 located in the first target area X1.

[0126] Among them, the material of the mask includes metal. For example, the material of the mask is nickel.

[0127] In some embodiments, the process of removing the initial drift layer 200, the initial first current blocking layer 410, and the initial first doping layer 310 located in the first target region X1 includes dry etching. Specifically, inductively coupled plasma (ICP) can be used. When etching, set the radio frequency power on the inductively coupled coil to 300 W, the bias power to 200 W, and the pressure in the process chamber to 1 Pa. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, such as 80 nm / min, 100 nm / min, or 120 nm / min.

[0128] In some embodiments, the flow rate of carbon tetrafluoride (CF4) is 25 sccm to 35 sccm, such as 25 sccm, 30 sccm, or 35 sccm.

[0129] In some embodiments, the flow rate of argon (Ar) is 5 sccm to 6 sccm, such as 5 sccm or 6 sccm.

[0130] In some embodiments, during the process of removing the initial drift layer 200, the initial first current blocking layer 410, and the initial first doping layer 310 located in the first target region X1, a part of the thickness of the initial drift layer 200 is also removed. After that, the initial drift layer 200 forms the drift layer 20.

[0131] For example, the thickness of the removed initial drift layer 200 is 450 nm to 550 nm, such as 500 nm.

[0132] In some embodiments, referring to Figure 13 , in the case of forming the initial third doping layer 330, during the process of removing the initial drift layer 200, the initial first current blocking layer 410, and the initial first doping layer 310 located in the first target region X1 and forming the first opening K1, the initial third doping layer 330 located in the first target region X1 is also removed.

[0133] Step S13: Referring to Figure 14 and Figure 15 , form the initial second current blocking layer 420 and the initial second doping layer 320 in the first opening K1.

[0134] In some embodiments, during the process of forming the initial second current blocking layer 420, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the magnesium source used includes bis(cyclopentadienyl) magnesium (Cp2Mg), the carrier gas used is argon, the growth temperature is 700°C to 800°C, such as 700°C, 750°C or 800°C, and the growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar or 45 mbar.

[0135] Among them, the molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, such as 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0136] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, such as 17000 μmol / min, 18000 μmol / min or 19000 μmol / min.

[0137] The molar flow rate of bis(cyclopentadienyl) magnesium is 2.4 μmol / min to 2.6 μmol / min, such as 2.4 μmol / min, 2.5 μmol / min or 2.6 μmol / min.

[0138] In some embodiments, the thickness of the initial second current blocking layer 420 is 0.4 μm to 0.6 μm, such as 0.4 μm, 0.5 μm or 0.6 μm.

[0139] In some embodiments, during the process of forming the initial first doped layer 310, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700°C to 800°C, such as 700°C, 750°C or 800°C, and the growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar or 45 mbar.

[0140] Among them, the molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, such as 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0141] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, such as 17000 μmol / min, 18000 μmol / min or 19000 μmol / min.

[0142] The molar flow rate of the silane is 1.0 μmol / min to 1.2 μmol / min, such as 1.0 μmol / min, 1.1 μmol / min, or 1.2 μmol / min.

[0143] In some embodiments, the thickness of the initial second doped layer 320 is 1 μm to 3 μm, such as 1 μm, 2 μm, or 3 μm.

[0144] Since the initial second current blocking layer 420 and the initial second doped layer 320 are formed in the first opening K1, the initial second current blocking layer 420 and the initial second doped layer 320 will also be formed on the surface of the initial first doped layer 310 away from the substrate 10. Therefore, it is also necessary to remove the initial second current blocking layer 420 and the initial second doped layer 320 on the surface of the initial first doped layer 310 away from the substrate 10.

[0145] In some embodiments, the process of removing the initial second current blocking layer 420 and the initial second doped layer 320 on the surface of the initial first doped layer 310 away from the substrate 10 includes dry etching. Specifically, inductively coupled plasma can be used. When etching, set the radio frequency power on the inductively coupled coil to 300 W, the bias power to 200 W, and the pressure in the process chamber to 1 Pa. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, such as 80 nm / min, 100 nm / min, or 120 nm / min.

[0146] Among them, the flow rate of carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, such as 28 sccm, 30 sccm, or 32 sccm; the flow rate of argon (Ar) is 4 sccm to 6 sccm, such as 4 sccm, 5 sccm, or 6 sccm.

[0147] Step S14: Refer to Figure 16 , remove the initial first doped layer 310, the initial first current blocking layer 410, and the initial second doped layer 320 located in the second target area X2 to form the first groove G1.

[0148] Here, the step of removing the initial first doped layer 310, the initial first current blocking layer 410, and the initial second doped layer 320 located in the second target area X2 includes: setting a mask on the surfaces of the initial first doped layer 310 and the initial second doped layer 320 away from the substrate 10, and the mask exposes the initial first doped layer 310 and the initial second doped layer 320 located in the second target area X2.

[0149] Among them, the material of the mask includes metal. For example, the material of the mask is nickel.

[0150] The mask is a metal prepared by a lift-off process.

[0151] In some embodiments, the process of removing the initial first doping layer 310, the initial first current blocking layer 410, and the initial second doping layer 320 located in the second target region X2 includes dry etching. Specifically, inductively coupled plasma can be used. The depth of the first groove G1 formed is 2 μm.

[0152] When etching, set the radio frequency power on the inductively coupled coil to 300 W, the bias power to 200 W, and the pressure in the process chamber to 1 Pa. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, such as 80 nm / min, 100 nm / min, or 120 nm / min.

[0153] Among them, the flow rate of carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, such as 28 sccm, 30 sccm, or 32 sccm; the flow rate of argon (Ar) is 4 sccm to 6 sccm, such as 4 sccm, 5 sccm, or 6 sccm.

[0154] After step S14, with reference to Figure 15 and Figure 16 , the initial first current blocking layer 410 forms the first current blocking layer 41, the initial first doping layer 310 forms the first doping layer 31, the initial third doping layer 330 forms the third doping layer 33, and the initial second doping layer 320 forms the second doping layer 32.

[0155] In the manufacturing method of the semiconductor device 100, the first stack structure D1 and the second stack structure D2 are arranged at intervals along the second direction Y, and a first groove G1 is formed therebetween. Since only one trench structure needs to be formed during the manufacturing process of the semiconductor device 100 and no side grooving is required, the manufacturing process of the semiconductor device 100 is simple.

[0156] Step S2: With reference to Figures 17 - 21 , a dielectric layer 60 and a conductive electrode 80 are formed in the first groove G1; the conductive electrode 80 is located at the bottom of the first groove G1, the dielectric layer 60 is located between the bottom surface of the first groove G1 and the conductive electrode 80, the dielectric layer 60 also covers the surface of the conductive electrode 80 away from the substrate 10, the two opposite side surfaces of the conductive electrode 80 along the second direction Y, and the side walls of the first groove G1.

[0157] Among them, step S2 includes: Step S21: With reference to Figure 17 and Figure 18, a first sub-dielectric layer 61 is formed on the bottom surface and the side wall of the first groove G1, and the first sub-dielectric layer 61 forms a second groove G2.

[0158] Specifically, with reference to Figure 17 and Figure 18 , a first sub-dielectric layer 61 is formed on the surface of the sample having the first groove G1, and the first sub-dielectric layer 61 located on the side of the first doping layer 31 and the second doping layer 32 away from the substrate 10 is removed, so that the first sub-dielectric layer 61 is formed on the bottom surface and the side wall of the first groove G1.

[0159] Here, the process of forming the first sub-dielectric layer 61 includes an atomic layer deposition process (Atomic Layer Deposition, ALD).

[0160] Among them, the material of the first sub-dielectric layer 61 includes hafnium dioxide (HfO2). The thickness of the first sub-dielectric layer 61 is 18 nm to 22 nm, such as 18 nm, 20 nm or 22 nm.

[0161] The first sub-dielectric layer 61 has a relative dielectric constant measurement value of 25 at an alternating electric field frequency of 1 megahertz (1 MHz).

[0162] During the process of forming the first sub-dielectric layer 61, the sources used are tetrakis(ethylmethylamino)hafnium (TEMAHf) and H2O, the growth temperature is 200 °C, the growth pressure is 1000 Pa, and 400 growth cycles are performed.

[0163] In some embodiments, the process of removing the first sub-dielectric layer 61 located on the side of the first doping layer 31 and the second doping layer 32 away from the substrate 10 includes dry etching. Inductively coupled plasma can be specifically used. When etching, the radio frequency power on the inductively coupled coil is set to 300 W, the bias power is 200 W, and the pressure in the process chamber is 1 Pa. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, such as 80 nm / min, 100 nm / min or 120 nm / min.

[0164] Among them, the flow rate of carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, such as 28 sccm, 30 sccm or 32 sccm; the flow rate of argon (Ar) is 4 sccm to 6 sccm, such as 4 sccm, 5 sccm or 6 sccm.

[0165] Step S22: Refer to Figure 19 , a conductive electrode 80 is formed at the bottom of the second groove G2.

[0166] Here, the Lift-off technique can be used to form the conductive electrode 80 at the bottom of the second groove G2. The process of forming the conductive electrode 80 includes an electron beam evaporation process, with a vacuum degree of 5E-6 Torr during evaporation and an evaporation rate of 0.5 Å / s.

[0167] The material of the conductive electrode 80 includes a metal, such as titanium.

[0168] The thickness of the conductive electrode 80 is 18 nm to 22 nm, such as 18 nm, 20 nm, or 22 nm.

[0169] Step S23: Refer to Figure 20 , a second sub-dielectric layer 62 is formed on the side of the conductive electrode 80 away from the substrate 10 and on the sidewalls of the second groove G2; the first sub-dielectric layer 61 and the second sub-dielectric layer 62 form the dielectric layer 60.

[0170] Specifically, in combination with referring to Figure 19 , Figure 20 and Figure 21 , a second sub-dielectric layer 62 is formed on the surface of the sample with the second groove G2, and the second sub-dielectric layer 62 located on the sides of the first doping layer 31 and the second doping layer 32 away from the substrate 10 is removed. The first sub-dielectric layer 61 and the second sub-dielectric layer 62 form the dielectric layer 60.

[0171] Here, the process of forming the second sub-dielectric layer 62 includes a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or an Atomic Layer Deposition (ALD) process.

[0172] The material of the second sub-dielectric layer 62 includes silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0173] The thickness of the second sub-dielectric layer 62 is 280 nm to 320 nm, such as 280 nm, 300 nm, or 320 nm.

[0174] Among them, when depositing silicon dioxide by PECVD, the sources used are SiH4 and N2O. The pressure is maintained at 100 Pa during growth, and the power is 150 W. The flow rate of SiH4 is 20 sccm, the flow rate of N2O is 1400 sccm, the flow rate of N2 is 1500 sccm, the growth temperature is 250 °C, and the growth rate is 300 nm / h.

[0175] In some embodiments, the process of removing the second sub-dielectric layer 62 on the side of the first doped layer 31 and the second doped layer 32 away from the substrate 10 includes dry etching. Specifically, inductively coupled plasma can be used. When etching, the radio frequency power on the inductive coupling coil is set to 300 W, the bias power is 200 W, and the pressure in the process chamber is 1 Pa. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, such as 80 nm / min, 100 nm / min, or 120 nm / min.

[0176] Among them, the flow rate of carbon tetrafluoride (CF4) is 8 sccm to 12 sccm, such as 8 sccm, 10 sccm, or 12 sccm; the flow rate of argon (Ar) is 1 sccm to 3 sccm, such as 1 sccm, 2 sccm, or 3 sccm.

[0177] Step S3: Refer to Figure 19 , form a first electrode 51 on the side of the first doped layer 31 away from the first current blocking layer 41, and form a second electrode 52 on the side of the second doped layer 32 away from the second current blocking layer 42.

[0178] Here, the process of forming the first electrode 51 and the second electrode 52 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr, and the evaporation rate is 0.5 Å / second.

[0179] Among them, the conductive electrode 80, the first electrode 51, and the second electrode 52 are formed in the same step. And the conductive electrode 80, the first electrode 51, and the second electrode 52 are electrically connected.

[0180] Step S4: Refer to Figure 22 , form a gate 70 on the dielectric layer 60.

[0181] Here, the gate 70 is formed on the dielectric layer 60 through a lift-off process.

[0182] Among them, the process of forming the gate 70 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr.

[0183] The material of the gate 70 includes metals, such as: nickel or gold. Among them, during the preparation process, the evaporation rate of nickel is 0.5 Å / second, and the evaporation rate of gold is 1 Å / second.

[0184] When the material of the gate 70 is nickel, the thickness of the gate 70 is 15 nm to 25 nm, such as 15 nm, 20 nm, or 20 nm. When the material of the gate 70 is gold, the thickness of the gate 70 is 80 nm to 120 nm, such as 80 nm, 100 nm, or 120 nm.

[0185] Step S5: Refer to Figure 23 , and form a third electrode 53 on the side of the substrate 10 away from the gate 70.

[0186] Here, the process of forming the third electrode 53 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr.

[0187] The material of the third electrode 53 includes titanium or gold. During the preparation process, the evaporation rate of titanium is 0.5 Å / second, and the evaporation rate of gold is 1 Å / second.

[0188] The thickness of the third electrode 53 is 20 nm to 100 nm, such as 20 nm, 50 nm, 80 nm, or 100 nm. For example, when the material of the third electrode 53 is titanium, the thickness of the third electrode 53 is 20 nm. When the material of the third electrode 53 is gold, the thickness of the third electrode 53 is 100 nm.

[0189] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A gate provided on one side of the substrate in a first direction, the first direction being the thickness direction of the substrate; A conductive electrode provided on the side of the gate close to the substrate; A first current blocking layer, a first doped layer, and a first electrode are stacked in the first direction and away from the substrate, and are provided on a first side of the gate; A second current blocking layer, a second doped layer, and a second electrode are stacked in the first direction and away from the substrate; the second doped layer and the second electrode are provided on a second side of the gate, the first side and the second side of the gate are respectively opposite sides of the gate in a second direction, the second direction being perpendicular to the thickness direction of the substrate; the second current blocking layer is located on the side of the conductive electrode and the side of the second current blocking layer close to the substrate; A dielectric layer is located between each of the first current blocking layer, the first doped layer, the first electrode, the second doped layer, the second current blocking layer, and the conductive electrode and the gate; the dielectric layer also covers the surface of the conductive electrode close to the substrate and the two opposite side surfaces of the conductive electrode in the second direction; A third electrode is provided on the side of the substrate away from the gate.

2. The semiconductor device according to claim 1, wherein Further comprising: A third doped layer, the third doped layer including a first doped portion; The first doped portion is provided on the side of the first current blocking layer close to the substrate and is located on one side of the conductive electrode in the second direction.

3. The semiconductor device according to claim 2, wherein, The surface of the third doped layer close to the substrate is flush with the surface of the second current blocking layer away from the substrate.

4. The semiconductor device according to claim 2, wherein The third doped layer further includes a second doped portion, the second doped portion is provided on the side of the first doped portion close to the substrate and is connected to the first doped portion; the side surface of the second doped portion is in contact with the side surface of the second current blocking layer.

5. The semiconductor device according to claim 1, wherein, In the orthographic projection onto the substrate, a part of the conductive electrode overlaps with a part of the second current blocking layer; or, In the orthographic projection onto the substrate, the conductive electrode is located within the boundary range of the second current blocking layer.

6. The semiconductor device according to claim 1, wherein The doping concentration of the first doped layer is greater than the doping concentration of the first current blocking layer; The doping concentration of the second doped layer is greater than the doping concentration of the second current blocking layer.

7. The semiconductor device according to claim 2, wherein The doping concentration of the third doped layer is greater than the doping concentration of the first current blocking layer.

8. The semiconductor device according to claim 2, wherein, The doping types of the first doped layer, the second doped layer, the third doped layer, and the substrate are the same.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The first electrode, the second electrode, and the conductive electrode are electrically connected.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the second sub-dielectric layer is closer to the gate than the first sub-dielectric layer; The conductive electrode is located between the first sub-dielectric layer and the second sub-dielectric layer.

11. The semiconductor device according to any one of claims 1 to 8, wherein: Further comprising: A drift layer is provided between the substrate and the first current blocking layer, and between the substrate and the second current blocking layer; The doping type of the drift layer is the same as the doping type of the substrate, and the doping concentration of the drift layer is less than the doping concentration of the substrate.

12. The semiconductor device according to any one of claims 1 to 8, wherein: The materials of the first doping layer and the second doping layer both include gallium oxide, and the doping ions both include silicon ions; The materials of the first current blocking layer and the second current blocking layer both include gallium oxide, and the doping ions both include magnesium ions.

13. The semiconductor device according to any one of claims 2 to 4, characterized in that, The material of the third doping layer includes gallium oxide, and the doping ions include silicon ions.

14. A power module, characterized in that, Comprising: The semiconductor device according to any one of claims 1 to 13.

15. An electronic device, characterized in that, Comprising: The power module according to claim 14.

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