Semiconductor device and memory device

Abstract

The invention provides a semiconductor device and a memory device capable of realizing miniaturization or high integration. The semiconductor device includes an oxide semiconductor layer, first to third insulating layers, and first to third conductive layers. The first and second conductive layers are isolated from each other on the first insulating layer. The first insulating layer has a groove portion between the first and second conductive layers. The oxide semiconductor layer has a region in contact with the top surface and the side surface of the first conductive layer, a region in contact with the top surface and the side surface of the second conductive layer, and a region in contact with the side surface of the trench portion. The second insulating layer is on the oxide semiconductor layer. The third conductive layer is on the second insulating layer. Side surfaces of the third conductive layer, the second insulating layer, and the oxide semiconductor layer are aligned or substantially aligned. The third insulating layer has a region in contact with each side surface of the oxide semiconductor layer, the second insulating layer, and the third conductive layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, and an electronic device. Further, one aspect of the present invention relates to a method for manufacturing a semiconductor device or a storage device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, there can be mentioned a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), and a driving method or a manufacturing method of the above devices.

[0003] In the present specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.) and a device including such a circuit. Further, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as an example of a semiconductor device, there are an integrated circuit, a chip having an integrated circuit, and an electronic component in which a chip is housed in a package. Further, sometimes a storage device, a display device, a light-emitting device, a lighting device, and an electronic device itself are semiconductor devices, or include a semiconductor device. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI (Large Scale Integration), CPU (Central Processing Unit), a memory (storage device), etc. are mainly used for semiconductor devices. A CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit (including transistors and a memory) formed by processing a semiconductor wafer to form a chip and having electrodes as connection terminals formed thereon.

[0005] An integrated circuit (IC chip) such as an LSI, a CPU, or a memory is mounted on a circuit board such as a printed wiring board and is used as one of the components of various electronic devices.

[0006] Further, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as an integrated circuit (IC) and a display device. As a semiconductor material that can be applied to a transistor, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have drawn attention.

[0007] In addition, it is known that transistors using an oxide semiconductor have extremely small leakage current in the off state. For example, Patent Document 1 has disclosed a low-power CPU or the like that utilizes the property of small leakage current of transistors using an oxide semiconductor. In addition, for example, Patent Document 2 has disclosed a storage device or the like that achieves long-term retention of stored content by utilizing the property of small leakage current of transistors using an oxide semiconductor.

[0008] In addition, in recent years, with the miniaturization and lightening of electronic devices, the demand for further high-density integration of integrated circuits has increased. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 have disclosed a technique in which a plurality of memory cells are arranged overlappingly by laminating a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit. In addition, Patent Document 4 has disclosed a technique in which the channels of transistors using an oxide semiconductor film are arranged in the vertical direction to achieve high-density integration of the integrated circuit.

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537

[0010] [Non-Patent Document 1] M. Oota et.al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 Summary of the Invention

[0011] One of the objects of one embodiment of the present invention is to provide a transistor having good electrical characteristics. One of the objects of one embodiment of the present invention is to provide a transistor having a large on-state current. One of the objects of one embodiment of the present invention is to provide a transistor having a small parasitic capacitance. One of the objects of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or storage device. One of the objects of one embodiment of the present invention is to provide a transistor, semiconductor device, or storage device capable of miniaturization or high integration. One of the objects of one embodiment of the present invention is to provide a semiconductor device or storage device having low power consumption. One of the objects of one embodiment of the present invention is to provide a storage device having a high operating speed. One of the objects of one embodiment of the present invention is to provide a method for manufacturing the above-described transistor, semiconductor device, or storage device.

[0012] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all of the above objects. Objects other than the above objects can be extracted from the description of the specification, drawings, and claims.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, first to third insulating layers, and first to third conductive layers. The first conductive layer and the second conductive layer are isolated from each other on the first insulating layer. The first insulating layer has a groove portion between the first conductive layer and the second conductive layer. The oxide semiconductor layer has a region in contact with the top surface of the first conductive layer and the side surface on one side of the groove portion, a region in contact with the top surface of the second conductive layer and the side surface on one side of the groove portion, and a region in contact with the side surface of the groove portion. The second insulating layer is provided on the oxide semiconductor layer. The third conductive layer is provided on the second insulating layer. The side surfaces of the third conductive layer, the second insulating layer, and the oxide semiconductor layer are aligned or substantially aligned. The third insulating layer has a region in contact with the top surface of the first conductive layer, the top surface of the second conductive layer, the side surface of the oxide semiconductor layer, the side surface of the second insulating layer, and the side surface of the third conductive layer outside the groove portion, and has a region in contact with the side surface of the oxide semiconductor layer, the side surface of the second insulating layer, and the side surface of the third conductive layer inside the groove portion.

[0014] Preferably, the above semiconductor device further includes a fourth conductive layer in contact with the top surface of the third conductive layer, and the extending direction of the fourth conductive layer intersects the extending direction of the groove portion.

[0015] Preferably, the above semiconductor device further includes a fifth conductive layer having regions respectively overlapping the first conductive layer and the second conductive layer with the first insulating layer therebetween, and the fifth conductive layer has a concave portion in a region overlapping the groove portion, and the oxide semiconductor layer has a region in contact with the side surface and the bottom of the concave portion.

[0016] In the above semiconductor device, the recess preferably has a curved portion.

[0017] One aspect of the present invention is a storage device including a capacitor, a transistor on the capacitor, a first insulating layer, and a second insulating layer. The transistor includes an oxide semiconductor layer, a third insulating layer, and first to fourth conductive layers. The first insulating layer is provided so as to cover the first conductive layer. The second conductive layer and the third conductive layer are isolated from each other on the first insulating layer. The first insulating layer has a groove portion between the second conductive layer and the third conductive layer. The first conductive layer has a recess in a region overlapping with the groove portion. The oxide semiconductor layer has a region in contact with the top surface of the second conductive layer and the side surface on one side of the groove portion, a region in contact with the top surface of the third conductive layer and the side surface on one side of the groove portion, a region in contact with the side surface of the groove portion, and a region in contact with the side surface and the bottom of the recess. The third insulating layer is provided on the oxide semiconductor layer. The fourth conductive layer is provided on the third insulating layer. The side surfaces of the fourth conductive layer, the third insulating layer, and the oxide semiconductor layer are aligned or substantially aligned. The second insulating layer has a region in contact with the top surface of the second conductive layer, the top surface of the third conductive layer, the side surface of the oxide semiconductor layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer outside the groove portion, and has a region in contact with the side surface of the oxide semiconductor layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer inside the groove portion.

[0018] Preferably, the above storage device further includes a fifth conductive layer that contacts the top surface of the fourth conductive layer, and the extending direction of the fifth conductive layer intersects with the extending direction of the groove portion.

[0019] In the above storage device, the recess preferably has a curved portion.

[0020] In the above storage device, the capacitor preferably includes a sixth conductive layer, a fourth insulating layer on the sixth conductive layer, and a first conductive layer on the fourth insulating layer.

[0021] Preferably, in the above storage device, the third insulating layer includes a first layer containing an oxide of hafnium.

[0022] In the above storage device, the first layer preferably contains hafnium zirconium oxide.

[0023] Preferably, in the above storage device, the third insulating layer includes a second layer on the first layer, and the second layer contains silicon nitride.

[0024] One aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a first transistor, and a second transistor. The first insulating layer has a groove portion. The first transistor includes a first oxide semiconductor layer having a channel formation region. The second transistor includes a second oxide semiconductor layer having a channel formation region. At least a part of the first oxide semiconductor layer and the second oxide semiconductor layer is located in the groove portion. When viewed in plan, the first oxide semiconductor layer and the second oxide semiconductor layer face each other with the second insulating layer therebetween in a direction perpendicular to the extending direction of the groove portion.

[0025] Preferably, in the above semiconductor device, the first transistor includes first to third conductive layers. The second conductive layer is provided on the first insulating layer. The first conductive layer has a region overlapping with the second conductive layer with the first insulating layer therebetween. The first conductive layer has a recess in a region overlapping with the groove portion. The first oxide semiconductor layer has a region in contact with side surfaces and a bottom surface of the recess of the first conductive layer and regions in contact with a top surface and side surfaces of the second conductive layer. The third conductive layer is provided above the first oxide semiconductor layer.

[0026] Preferably, in the above semiconductor device, the second insulating layer has a region in contact with side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer inside the groove portion.

[0027] Preferably, the above semiconductor device further includes a fourth conductive layer connected to a gate of the first transistor and a gate of the second transistor. The extending direction of the fourth conductive layer intersects with the extending direction of the groove portion.

[0028] One aspect of the present invention is a storage device including the above semiconductor device and a capacitor. The capacitor is located below the first transistor. The first conductive layer has a region serving as one of a pair of electrodes of the capacitor.

[0029] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-state current can be provided. According to one aspect of the present invention, a transistor with a small parasitic capacitance can be provided. According to one aspect of the present invention, a highly reliable transistor, semiconductor device, or storage device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or storage device capable of miniaturization or high integration can be provided. According to one aspect of the present invention, a semiconductor device or storage device with low power consumption can be provided. According to one aspect of the present invention, a storage device with a high operating speed can be provided. According to one aspect of the present invention, a manufacturing method of the above transistor, semiconductor device, or storage device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the descriptions in the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A1 and Figure 1A2 is a plan view showing an example of a semiconductor device, Figures 1B to 1E is a cross-sectional view showing an example of a semiconductor device; Figure 2 is a perspective view showing an example of a semiconductor device; Figures 3A to 3C is a cross-sectional view showing an example of a semiconductor device; Figure 4A and Figure 4B is a cross-sectional view showing an example of a semiconductor device; Figure 5A and Figure 5B is a cross-sectional view showing an example of a semiconductor device; Figure 6A and Figure 6B is a cross-sectional view showing an example of a semiconductor device; Figures 7A to 7F is a cross-sectional view showing an example of a semiconductor device; Figure 8A is a plan view showing an example of a method of manufacturing a semiconductor device, Figures 8B to 8E is a cross-sectional view showing an example of a method of manufacturing a semiconductor device; Figure 9A is a plan view showing an example of a method of manufacturing a semiconductor device, Figures 9B to 9E is a cross-sectional view showing an example of a method of manufacturing a semiconductor device; Figure 10A is a plan view showing an example of a method of manufacturing a semiconductor device, Figures 10B to 10E is a cross-sectional view showing an example of a method of manufacturing a semiconductor device; Figure 11A is a plan view showing an example of a method of manufacturing a semiconductor device, Figures 11B to 11E is a cross-sectional view showing an example of a method of manufacturing a semiconductor device; Figure 12A is a plan view showing an example of a method of manufacturing a semiconductor device, Figures 12B to 12E is a cross-sectional view showing an example of a method of manufacturing a semiconductor device; Figure 13A is a plan view showing an example of a method of manufacturing a semiconductor device, Figures 13B to 13EIt is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Figure 14A It is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 14B to 14E It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Figure 15A It is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 15B to 15E It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Figure 16A and Figure 16B It is a cross-sectional view showing an example of a semiconductor device; Figure 17A It is a plan view showing an example of a semiconductor device, Figures 17B to 17D It is a cross-sectional view showing an example of a semiconductor device; Figure 18A It is a plan view showing an example of a semiconductor device, Figures 18B to 18E It is a cross-sectional view showing an example of a semiconductor device; Figure 19 It is a cross-sectional view showing an example of a semiconductor device; Figure 20A It is a plan view showing an example of a semiconductor device, Figure 20B and Figure 20C It is a cross-sectional view showing an example of a semiconductor device; Figure 21A1 and Figure 21A2 It is a plan view showing an example of a semiconductor device, Figures 21B to 21E It is a cross-sectional view showing an example of a semiconductor device; Figure 22A and Figure 22B It is a cross-sectional view showing an example of a semiconductor device; Figure 23A It is a plan view showing an example of a semiconductor device, Figure 23B and Figure 23C It is a cross-sectional view showing an example of a semiconductor device; Figure 24 It is a perspective view showing an example of a semiconductor device; Figures 25A to 25C It is a cross-sectional view showing an example of a semiconductor device; Figures 26A to 26C It is a cross-sectional view showing an example of a semiconductor device; Figure 27 It is an energy band diagram of an oxide semiconductor layer; Figure 28A It is a plan view showing an example of a storage device, Figure 28B and​ is a cross-sectional view showing an example of a storage device; ​ is a plan view showing an example of a storage device, ​ is a diagram illustrating an example of the circuit structure of a memory cell; ​ is a perspective schematic view showing an example of a semiconductor device; ​ and ​ is a cross-sectional view showing an example of a storage device; ​ is a plan view showing an example of a storage device, ​ is a cross-sectional view showing an example of a storage device, ​ is a diagram illustrating an example of the circuit structure of a memory cell; ​ is a perspective schematic view showing an example of a semiconductor device; ​ is a plan view showing an example of a storage device, ​ is a diagram illustrating an example of the circuit structure of a memory cell; ​ is a cross-sectional view showing an example of a storage device; ​ is a cross-sectional view showing an example of a storage device; ​ is a cross-sectional view showing an example of a storage device; ​ is a cross-sectional view showing an example of a storage device; ​ is a graph showing an example of a hysteresis characteristic; ​ is an equivalent circuit diagram of a semiconductor device, ​ is a diagram illustrating the Id-Vg characteristics of a transistor; ​ is a timing diagram for explaining the operation of a semiconductor device, ​ is a circuit diagram for explaining the operation of a semiconductor device; ​ is a timing diagram for explaining the operation of a semiconductor device, ​ is a circuit diagram for explaining the operation of a semiconductor device; ​ is a timing diagram for explaining the operation of a semiconductor device, ​ is a circuit diagram for explaining the operation of a semiconductor device; ​ is a block diagram illustrating an example of the structure of a semiconductor device; ​ is a diagram showing an example of the circuit structure of a memory cell; ​ and ​ is a perspective view showing an example of the structure of a semiconductor device; ​ is a block diagram showing a CPU; ​ and ​ is a perspective view of a semiconductor device; ​ and ​ is a perspective view of a semiconductor device; ​ is a schematic diagram showing the hierarchy of a storage device; ​ and ​ is a circuit diagram of a semiconductor device according to one embodiment of the present invention, ​ is a diagram showing an example of an electronic component using a semiconductor device according to one embodiment of the present invention; ​ is a diagram showing an example of an electronic component; ​ is a diagram showing an example of a mainframe computer, ​ is a diagram showing an example of a space device, ​ is a diagram showing an example of a storage system that can be used in a data center; ​ is a diagram showing an example of an electronic device; ​ is a diagram showing an example of an electronic device; ​ is a diagram showing an example of an electronic device. Detailed Description of the Embodiment

[0032] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understood by those skilled in the art that its modes and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments.

[0033] Note that in the invention structure described below, the same symbols are used in different drawings to represent the same parts or parts having the same function, and repeated descriptions are omitted. In addition, the same hatching is sometimes used when representing parts having the same function, and no special symbols are added.

[0034] In addition, for ease of understanding, the positions, sizes, ranges, etc. of the respective constituent elements shown in the drawings sometimes do not represent their actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

[0035] Note that in this specification, etc., for convenience, ordinal numbers such as "first" and "second" are added, and they do not limit the number of constituent elements or the order of constituent elements (for example, the process order or the stacking order). In addition, the ordinal numbers added to a constituent element in a certain part of this specification are sometimes inconsistent with the ordinal numbers added to the same constituent element in other parts of this specification or in the claims.

[0036] A transistor is a type of semiconductor element and can perform functions such as amplifying current or voltage, and controlling on / off switching operations, etc. The transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs: Thin Film Transistors).

[0037] In this specification, etc., a transistor using an oxide semiconductor or a metal oxide for the semiconductor layer and a transistor including an oxide semiconductor or a metal oxide in the channel formation region are sometimes referred to as OS transistors. In addition, a transistor including silicon in the channel formation region is sometimes referred to as an Si transistor.

[0038] In addition, in this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a region where a channel is formed (also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification, etc., the channel formation region refers to the region where current mainly flows.

[0039] In addition, in cases where transistors of different polarities are used or the direction of current in the circuit operation changes, etc., the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged with each other.

[0040] Note that impurities in a semiconductor refer to elements other than the main components constituting the semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity. When impurities are included, for example, an increase in the density of defect states of the semiconductor or a decrease in crystallinity may occur. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, for example, there are Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, for example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water sometimes acts as an impurity. Further, for example, the incorporation of impurities sometimes leads to the formation of oxygen vacancies (also denoted as V O ) in the oxide semiconductor.

[0041] Note that in this specification, etc., an oxynitride refers to a material in which the oxygen content in its composition is more than the nitrogen content. A nitride oxide refers to a material in which the nitrogen content in its composition is more than the oxygen content.

[0042] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in a film can be analyzed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy or ESCA: Electron Spectroscopy for Chemical Analysis, that is, electron spectroscopy for chemical analysis). When the content rate of the target element is high (for example, 0.5 atomic% or more or 1 atomic% or more), XPS is suitable. On the other hand, when the content rate of the target element is low (for example, 0.5 atomic% or less or 1 atomic% or less), SIMS is suitable. When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analysis techniques.

[0043] Note that the content rate in this specification, etc., refers to the proportion of the components contained in the film. For example, when the oxide semiconductor layer contains metal element X, metal element Y, and metal element Z, and the respective atomic numbers of metal element X, metal element Y, and metal element Z contained in the oxide semiconductor layer are A X , A Y , A Z respectively, the content rate of metal element X can be expressed as A X / (A X + A Y + A Z ). Further, when the atomic number ratio (atomic ratio) of metal element X, metal element Y, and metal element Z in the oxide semiconductor layer is expressed as B X: B Y : B Z When it is possible, the content rate of the metallic element X can be expressed as B X / (B X + B Y + B Z ).

[0044] In addition, depending on the situation or state, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be changed to "conductive film". In addition, "insulating film" can be changed to "insulating layer".

[0045] In this specification and the like, "parallel" means a state where the angle formed by two straight lines is -10 degrees or more and 10 degrees or less. Therefore, it also includes the state where the angle is -5 degrees or more and 5 degrees or less. "Substantially parallel" means a state where the angle formed by two straight lines is -20 degrees or more and 20 degrees or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80 degrees or more and 100 degrees or less. Therefore, it also includes the state where the angle is 85 degrees or more and 95 degrees or less. "Substantially perpendicular" means a state where the angle formed by two straight lines is 70 degrees or more and 110 degrees or less.

[0046] "Connection" in this specification includes, for example, "electrical connection". Note that sometimes, in order to define the connection relationship of circuit elements as an object, it is described as "electrical connection". In addition, "electrical connection" includes "direct connection" and "indirect connection". "A is directly connected to B" means a situation where A and B are connected without passing through circuit elements (for example, transistors, switches, etc. Note that wiring is not a circuit element). On the other hand, "A is indirectly connected to B" means a situation where A and B are connected through one or more circuit elements.

[0047] For example, in the case of assuming the operation of a circuit including A and B, when there is an opportunity for the transfer of electrical signals or the interaction of potentials between A and B during the operation of the circuit, this circuit can be defined as an object as "A is indirectly connected to B". In addition, even if there is no opportunity for the transfer of electrical signals or the interaction of potentials between A and B during the operation of the circuit, and there is an opportunity for the transfer of electrical signals or the interaction of potentials between A and B during the operation of the circuit, it can also be defined as "A is indirectly connected to B".

[0048] As an example of "A is indirectly connected to B", there is a situation where A and B are connected through the source and drain of one or more transistors. On the other hand, as an example where it cannot be said that "A is indirectly connected to B", there is a situation where there is an insulator on the path from A to B. Specifically, there are the following situations: a situation where a capacitor is connected between A and B; and a situation where there is a gate insulating film of a transistor between A and B, etc. Therefore, it cannot be said that "the gate (A) of the transistor is indirectly connected to the source or drain (B) of the transistor".

[0049] As other examples where it cannot be said that "A is indirectly connected to B", there are the following cases: A plurality of transistors are connected via source and drain electrodes on the path from A to B, and a fixed potential V is supplied to the nodes between the transistors and other transistors from a power supply, GND, etc.

[0050] In this specification, etc., unless otherwise specified, the off-state current refers to the leakage current between the source and drain electrodes when the transistor is in the off state (also referred to as the non-conducting state, cut-off state). Unless otherwise specified, in an n-channel transistor, the off state means that the voltage V between the gate and the source gs is lower than the threshold voltage V th (in a p-channel transistor, V gs is higher than V th ).

[0051] In this specification, etc., the always-on characteristic refers to a state where a channel exists even when no voltage is applied to the gate, and current flows through the transistor. In addition, the always-off characteristic refers to a state where current does not flow through the transistor when no potential is applied to the gate or when a ground potential is supplied to the gate.

[0052] In this specification, etc., the conical shape refers to a shape in which at least a part of the side surface of the component is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferably a region having an angle (also referred to as the conical angle) formed by the inclined side surface and the substrate surface or the surface to be formed that is greater than 0 degrees and less than 90 degrees. Here, the side surface, substrate surface, and surface to be formed of the component do not necessarily have to be completely flat, and may be an approximately planar shape having a minute curvature or an approximately planar shape having fine irregularities.

[0053] In this specification, etc., when it is described that A is located on B, at least a part of A is located on B. Therefore, for example, it can be equivalently stated that A has a region located on B. Similarly, when it is described that A is in contact with B or A overlaps with B, at least a part of A is in contact with B or overlaps with B. Therefore, it can be equivalently stated that A has a region in contact with B or A has a region overlapping with B. Similarly, when it is described that A covers B, at least a part of A covers B. Therefore, for example, it can be equivalently stated that A has a region covering B.

[0054] In this specification, etc., disconnection refers to a phenomenon in which a layer, film, or electrode is disconnected due to the shape of the surface to be formed (e.g., steps, etc.).

[0055] Note that sometimes arrows indicating the X direction, Y direction, and Z direction are attached in the drawings of this specification, etc. Note that in this specification, etc., the "X direction" refers to the direction along the X-axis, and unless otherwise specified, the forward and reverse directions are sometimes not distinguished. The same applies to the "Y direction" and "Z direction". In addition, the X direction, Y direction, and Z direction are directions that intersect each other. For example, the X direction, Y direction, and Z direction are directions that are orthogonal to each other.

[0056] The groove includes, for example, an opening, a groove, a slit, etc. In addition, the region where the groove is formed is sometimes referred to as a groove portion.

[0057] Embodiment 1 In this embodiment, with reference to ​ a semiconductor device according to one aspect of the present invention and a method for manufacturing the same will be described.

[0058] <Structural Example 1 of Semiconductor Device> With reference to ​ and ​ , ​ the structure of a semiconductor device according to one aspect of the present invention will be described.

[0059] ​ is a plan view of a semiconductor device including transistors. ​ is a plan view showing an example of arranging a plurality of transistors. ​ is along the ​ indicated dash-dotted line A1 - A2 cross-sectional view. ​ is along the ​ indicated dash-dotted line A3 - A4 cross-sectional view. ​ is along the ​ indicated dash-dotted line B1 - B2 cross-sectional view. ​ is along the ​ indicated dash-dotted line B3 - B4 cross-sectional view. Note that for clarity, in the ​ and ​ plan views, some constituent elements are omitted. Sometimes some constituent elements are also omitted in the subsequent plan views.

[0060] ​ is ​ , ​ , ​ shown in the three-dimensional schematic diagram of the semiconductor device. Specifically, ​ is a three-dimensional schematic diagram of a semiconductor device including four transistors. In addition, regarding the ​ partial constituent elements (interlayer insulating layer, etc.) in, only the outline indicated by the dashed line is shown.

[0061] In ​ , ​ , ​ and​ In this figure, the X, Y, and Z directions are indicated by arrows. Note that ​ , ​ , ​ and ​ all use the same symbols for X, Y, and Z, but the directions do not necessarily have to be consistent between these figures.

[0062] In addition, ​ is a cross-sectional view along the dashed line A1 - A2 shown in ​ . ​ This is an example of an enlarged view corresponding to ​ .

[0063] ​ , ​ , ​ The semiconductor device shown in

[0064] [Transistor 200] includes: a conductive layer 220 on the insulating layer 210; a conductive layer 240a and a conductive layer 240b on the insulating layer 280; an oxide semiconductor layer 230 on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b; an insulating layer 250 on the oxide semiconductor layer 230; and a conductive layer 260 on the insulating layer 250.

[0065] In ​ , an example is shown where the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1, the conductive layer 240a has a two-layer structure of a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1, and the conductive layer 240b has a two-layer structure of a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1.

[0066] ​ shows a cross-sectional view along the dashed line C1 - C2 shown in ​ . In addition, ​ shows a cross-sectional view of the XY plane including the conductive layer 240a2.

[0067] In transistor 200, an oxide semiconductor layer 230 is used as a semiconductor layer, a conductive layer 260 is used as a gate electrode, an insulating layer 250 is used as a gate insulating layer, a conductive layer 220 is used as one of a source electrode and a drain electrode, and at least one of a conductive layer 240a and a conductive layer 240b is used as the other of the source electrode and the drain electrode. For example, when the conductive layer 240a and the conductive layer 240b are connected, the conductive layer 240a and the conductive layer 240b are used as the other of the source electrode and the drain electrode. In addition, when the conductive layer 240a and the conductive layer 240b are not connected, one of the conductive layer 240a and the conductive layer 240b is used as the other of the source electrode and the drain electrode.

[0068] The conductive layer 265 has a region in contact with the top surface of the conductive layer 260. In addition, the conductive layer 265 can also be regarded as a component of the transistor 200. The conductive layer 265 is provided so as to extend in the X direction. The conductive layer 265 is used as a gate wiring.

[0069] In ​ 、 ​ 、 ​ In the semiconductor device shown, the conductive layer 220 is provided so as to extend in the Y direction. In addition, the conductive layer 220 can also be provided in an island shape.

[0070] An insulating layer 280 is located on the conductive layer 220.

[0071] As ​ and ​ 、 ​ 、 ​ shown, a groove portion 290 reaching the conductive layer 220 is provided in the insulating layer 280. The groove portion 290 extends in the Y direction. At this time, the extending direction of the conductive layer 265 intersects with the extending direction of the groove portion 290.

[0072] In ​ , the conductive layer 220 has a concave portion in a region overlapping with the groove portion 290. In addition, as ​ shown, when the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2, the bottom surface of this concave portion corresponds to the bottom surface of the concave portion of the conductive layer 220_2, and the side surface of this concave portion corresponds to the side surface of the concave portion of the conductive layer 220_2. Here, it can be considered that the bottom of the groove portion 290 includes the bottom surface of the concave portion of the conductive layer 220_2, and the side surface of the groove portion 290 includes the side surface of the concave portion of the conductive layer 220_2 and the side surface of the insulating layer 280.

[0073] The conductive layer 240a and the conductive layer 240b are isolated from each other on the insulating layer 280. In addition, the conductive layer 240a and the conductive layer 240b are arranged in a manner that extends in the Y direction. In addition, the conductive layer 240a and the conductive layer 240b may also be arranged in an island shape.

[0074] In ​ etc., the side surface of the conductive layer 240a on the side of the groove portion 290 is aligned or substantially aligned with the side surface of the groove portion 290. In addition, the side surface of the conductive layer 240b on the side of the groove portion 290 is aligned or substantially aligned with the side surface of the groove portion 290. By adopting such a structure, the conductive layer 240a, the conductive layer 240b, and the groove portion 290 can be formed at one time. In addition, when the side surface of the conductive layer 240a in the groove portion 290 is aligned or substantially aligned with the side surface of the insulating layer 280 and the side surface of the conductive layer 240b is aligned or substantially aligned with the side surface of the insulating layer 280, the thickness distribution of the oxide semiconductor layer 230 etc. provided inside the groove portion 290 can be set uniformly. In addition, it is possible to suppress the oxide semiconductor layer 230 etc. from being broken due to the steps between the conductive layer 240a and the insulating layer 280 and the steps between the conductive layer 240b and the insulating layer 280 etc. Here, it can be considered that the side surface of the groove portion 290 includes the side surface of the conductive layer 240a on the side of the groove portion 290 and the side surface of the conductive layer 240b on the side of the groove portion 290.

[0075] At least a part of the components of the transistor 200 is arranged in the groove portion 290. Specifically, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are all arranged in a manner that at least a part of them is located in the groove portion 290.

[0076] The oxide semiconductor layer 230 is arranged to cover at least a part of the side surface and at least a part of the bottom surface of the groove portion 290. The oxide semiconductor layer 230 has a region in contact with the side surface of the insulating layer 280, a region in contact with the side surface of the conductive layer 240a on the side of the groove portion 290, a region in contact with the side surface of the conductive layer 240b on the side of the groove portion 290, and a region in contact with the side surface and the bottom surface of the concave portion of the conductive layer 220 in the groove portion 290. In addition, the oxide semiconductor layer 230 has a region in contact with the top surface of the conductive layer 240a and a region in contact with the top surface of the conductive layer 240b outside the groove portion 290.

[0077] In addition, the end portion of the oxide semiconductor layer 230 is located inside the end portion of the conductive layer 240a and inside the end portion of the conductive layer 240b outside the groove portion 290.

[0078] The insulating layer 250 is arranged to cover the oxide semiconductor layer 230. The insulating layer 250 is in contact with the top surface of the oxide semiconductor layer 230. The insulating layer 250 has a concave portion at a position overlapping with the groove portion 290.

[0079] The conductive layer 260 has a portion located in the recess of the insulating layer 250. The conductive layer 260 has a region facing the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween in the groove portion 290.

[0080] As ​ shown, outside the groove portion 290, the side surfaces of the conductive layer 260, the insulating layer 250, and the oxide semiconductor layer 230 are aligned or substantially aligned. In addition, as ​ and ​ shown, inside the groove portion 290, the side surfaces of the conductive layer 260, the insulating layer 250, and the oxide semiconductor layer 230 that contact the insulating layer 284 side are aligned or substantially aligned.

[0081] As described above, the oxide semiconductor layer 230 has a portion located inside the groove portion 290. In addition, one of the source electrode and the drain electrode of the transistor 200 (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, at least one of the conductive layer 240a and the conductive layer 240b) is located above, so that current flows in the vertical direction. That is, a channel is formed along the side surface of the groove portion 290.

[0082] In other words, in the ​ , ​ , ​ shown transistor 200, the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. That is to say, the channel length direction has a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc.

[0083] ​ , ​ , ​ shown, the source electrode, the semiconductor layer, and the drain electrode of the transistor 200 can be overlapped, whereby the occupied area can be significantly reduced compared with a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0084] The region where the oxide semiconductor layer 230 faces the conductive layer 260 with the insulating layer 250 interposed therebetween in the groove portion 290 and the vicinity thereof are used as the channel formation region of the transistor 200. The region near the conductive layer 220 of the oxide semiconductor layer 230 is used as one of the source region and the drain region, and at least one of the region near the conductive layer 240a and the region near the conductive layer 240b of the oxide semiconductor layer 230 is used as the other of the source region and the drain region. That is to say, the channel formation region is sandwiched between the source region and the drain region.

[0085] By adopting the above structure, a channel formation region, a source region, and a drain region can be formed in the groove portion 290. Therefore, compared with a planar transistor in which the channel formation region, the source region, and the drain region are separately provided in the XY plane, the occupied area of the transistor 200 can be reduced. As a result, high integration of the semiconductor device can be achieved. In addition, when the semiconductor device according to one embodiment of the present invention is used for a storage device, the storage capacity per unit area can be increased.

[0086] As ​ shown, the side surface of the conductive layer 260 provided at the center of the groove portion 290 and facing the side surface of the groove portion 290 faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. In other words, when viewed from the plane, the two side surfaces on the insulating layer 250 side of the oxide semiconductor layer 230 are channel formation regions. At this time, for example, the channel width of the transistor 200 is determined according to the length of the oxide semiconductor layer 230 in the Y direction. In addition, it can be said that the channel width of the transistor 200 is determined according to the width of the conductive layer 260 in the Y direction, the width of the insulating layer 250 in the Y direction, or the like. ​ The length H230 of the oxide semiconductor layer 230 in the Y direction is shown. The channel width of the transistor 200 can be calculated as "2 × H230".

[0087] By increasing the length H230 of the oxide semiconductor layer 230 in the Y direction, the channel width per unit area can be increased and the on-state current can be increased. On the other hand, the occupied area of the transistor 200, for example, the area of the transistor 200 when viewed from the plane, is roughly determined by the length H230. By reducing the length H230, the occupied area of the transistor 200 can be reduced, and thus high integration of the semiconductor device can be achieved.

[0088] When the groove portion 290 is formed by photolithography, the width of the groove portion 290 in the X direction is set according to the exposure limit of photolithography. In addition, the width of the groove portion 290 in the X direction is set according to the thicknesses of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the groove portion 290. The width of the groove portion 290 in the X direction is preferably 5 nm or more, 10 nm or more, or 20 nm or more and 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, for example.

[0089] ​ , ​ , ​The channel length of the transistor 200 shown is the distance between the source region and the drain region. For example, the channel length of the transistor 200 can be considered as the distance between the end of the region where the oxide semiconductor layer 230 contacts the conductive layer 220 and the end of the region where the oxide semiconductor layer 230 contacts the conductive layer 240a or the conductive layer 240b when viewed in cross section. That is to say, the channel length of the transistor 200 is determined according to the thickness of the insulating layer 280 on the conductive layer 220. In ​ the channel length L of the transistor 200 is indicated by a double-headed arrow in dashed line.

[0090] In a planar transistor, the channel length is limited by the exposure limit of photolithography, and it is difficult to further miniaturize. However, the channel length of the transistor 200 can be set according to the thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of photolithography (for example, below 60 nm, below 50 nm, below 40 nm, below 30 nm, below 20 nm or below 10 nm and above 0.1 nm, above 1 nm or above 5 nm). Thereby, the on-state current of the transistor 200 increases, and thus the frequency characteristics can be improved.

[0091] Note that since the channel length of the transistor 200 is determined according to the thickness of the insulating layer 280, this channel length does not affect the occupied area of the transistor 200, such as the area of the transistor 200 when viewed from the plane. In addition, by setting the channel length of the transistor 200, for example, to 1 μm or less, 500 nm or less, or 300 nm or less, the productivity and the yield rate, etc. when forming the groove portion 290, etc. can be improved.

[0092] Therefore, the channel length of the transistor included in the semiconductor device according to one aspect of the present invention is preferably above 0.1 nm, above 1 nm or above 5 nm and below 1 μm, below 500 nm or below 300 nm.

[0093] ​ 、 ​ 、 ​ The channel length of the shown transistor can be controlled according to the thickness of the insulating layer 280. Therefore, a transistor with an extremely short channel length that is difficult to achieve in a planar transistor can be realized. Therefore, a transistor with a small occupied area and a large on-state current can be realized.

[0094] The channel length L of the transistor 200 is preferably less than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 times or more and 0.99 times or less, more preferably 0.5 times or more and 0.8 times or less, of the channel width W of the transistor 200. By adopting such a structure, a transistor with good electrical characteristics and high reliability can be realized. Note that the channel width W of the transistor 200 may also be equal to or less than the channel length L of the transistor 200. By adopting such a structure, miniaturization or high integration of the semiconductor device can be realized.

[0095] As described above, the insulating layer 250 and the conductive layer 260 are provided along the shape of the oxide semiconductor layer 230. Thus, the distance between the conductive layer 260 and the oxide semiconductor layer 230 is substantially uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 substantially uniformly.

[0096] ​ The shown conductive layer 220_2 has a concave portion. By including a concave portion in the conductive layer 220_2 at a position overlapping with the groove portion 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the groove portion 290 can be made lower than the height of the top surface of the conductive layer 220_2 in contact with the insulating layer 280 when taking the top surface of the insulating layer 210 in the region overlapping with the conductive layer 220 as a reference, as compared with the case where the concave portion is not included. Here, the height of each surface can be determined based on the surface on which the transistor is formed. Here, the top surface of the insulating layer 210 in the region overlapping with the conductive layer 220 is taken as a reference. The surface used as a reference is not limited to the surface on which the transistor is formed. For example, the top surface of the substrate on which the transistor or the semiconductor device is provided may also be taken as a reference.

[0097] Since the conductive layer 220_2 has a concave portion, the side surface of the conductive layer 220_2 is in contact with the oxide semiconductor layer 230. Thus, the contact area between the conductive layer 220_2 and the oxide semiconductor layer 230 can be increased, and thereby the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be reduced. Therefore, a reduction in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed.

[0098] In addition, a gate electric field is easily applied to the channel formation region of the oxide semiconductor layer 230, so that the electrical characteristics of the transistor 200 can be improved. Furthermore, a gate electric field is also easily applied to the region where the oxide semiconductor layer 230 is in contact with the conductive layer 220_2, and thus the on-state current of the transistor 200 can be increased. In addition, regardless of whether the conductive layer 220, the conductive layer 240a, or the conductive layer 240b is used as the drain electrode, the transistor 200 can have good electrical characteristics.

[0099] In addition, as ​As shown, the concave portion of the conductive layer 220_2 preferably has a bent portion. When the concave portion has a bent portion, the electric field concentration is alleviated, the breakdown voltage of the transistor is increased, and thus electrostatic breakdown of the transistor can be suppressed. Therefore, the reliability of the semiconductor device can be improved.

[0100] Note that when a concave portion is provided in the conductive layer 220_2, a concave portion may be provided at a position where the insulating layer 210 overlaps with the groove portion 290.

[0101] ​ A structure in which the conductive layer 220 has a concave portion is shown. Note that the present invention is not limited thereto. For example, the top surface of the conductive layer 220 may be flat.

[0102] As ​ shown, the insulating layer 284 is provided on the insulating layer 280, the conductive layer 240a, and the conductive layer 240b. In addition, the insulating layer 284 has a region in contact with the top surface and the side surface of each of the conductive layer 240a and the conductive layer 240b, a region in contact with the side surface of the oxide semiconductor layer 230, a region in contact with the side surface of the insulating layer 250, and a region in contact with the side surface of the conductive layer 260 on the outside of the groove portion 290. In addition, as ​ and ​ shown, the insulating layer 284 has a region in contact with the side surface of the oxide semiconductor layer 230, a region in contact with the side surface of the insulating layer 250, a region in contact with the side surface of the conductive layer 260, and a region in contact with the side surface of the insulating layer 280 in the groove portion 290. In addition, the insulating layer 284 has a region in contact with the side surface of the conductive layer 240a on the side of the groove portion 290 and a region in contact with the side surface of the conductive layer 240b on the side of the groove portion 290.

[0103] The insulating layer 284 is preferably an insulating layer having a function of capturing or fixing hydrogen. By making the insulating layer 284 have a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 can be diffused into the insulating layer 284 to capture or fix the hydrogen. In addition, diffusion of hydrogen from above the insulating layer 284 into the oxide semiconductor layer 230 can be suppressed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 284, an alumina film, a hafnium oxide film, a hafnium silicate film, or the like can be used.

[0104] In addition, as the insulating layer 284, a hydrogen barrier insulating layer is preferably used. Thereby, diffusion of hydrogen from above the insulating layer 284 into the oxide semiconductor layer 230 can be suppressed. Since both a silicon nitride film and a silicon oxynitride film have characteristics of having few impurities (for example, water and hydrogen) released from themselves and being difficult for oxygen and hydrogen to permeate, they can be used for the insulating layer 284.

[0105] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably deposited by a sputtering method. Since the sputtering method can also use a molecule not containing hydrogen as a deposition gas, the hydrogen concentration of the insulating layer 284 can be reduced. In addition, by depositing the insulating layer 284 using the sputtering method, a silicon nitride film with high density can be formed.

[0106] In addition, as the insulating layer 284, a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a hydrogen-blocking insulating layer may also be employed. For example, as the insulating layer 284, a stacked film of an alumina film and a silicon nitride film on the alumina film may also be used.

[0107] The insulating layer 284 has an opening 270 reaching the insulating layer 250 at a position overlapping with the groove portion 290. The conductive layer 260 is disposed such that at least a part of it is located within the opening 270. The conductive layer 260 contacts the insulating layer 250 within the opening 270.

[0108] In addition, the insulating layer 284 also has an opening in the groove portion 290 in a region not overlapping with the insulating layer 250. The insulating layer 285 is provided so as to be embedded in the opening.

[0109] Since the insulating layer 285 is used as an interlayer film, it is preferably made of the above-described material having a low relative dielectric constant. For example, the insulating layer 285 preferably has a silicon oxide film.

[0110] The conductive layer 260 is disposed so as to be embedded in the groove portion 290 and the opening 270. The conductive layer 260 has a portion facing the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween within the groove portion 290 and a portion located within the opening 270.

[0111] The portion of the conductive layer 265 not overlapping with the groove portion 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240a with the insulating layer 284 and the insulating layer 285 interposed therebetween. Thereby, the physical distance between the conductive layer 265 and the conductive layer 240a can be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240a can be reduced. In addition, the conductive layer 240a and the conductive layer 265 may also have a portion that overlaps without the insulating layer 285 therebetween. The position of the conductive layer 240b and the conductive layer 265 is the same.

[0112] That is to say, the transistor 200 has a structure for reducing the parasitic capacitance generated between another one of the source electrode and the drain electrode and the gate wiring. Therefore, the frequency characteristics of a circuit using this transistor can be improved.

[0113] ​An example in which the width of the opening portion 270 is greater than the width of the groove portion 290 is shown. Note that it is preferable that the overlapping area of the opening portion 270 and the groove portion 290 is small when viewed from the plane. The smaller the overlapping area of the opening portion 270 and the groove portion 290, the greater the physical distance between the conductive layer 240a and the conductive layer 260 can be increased, thereby reducing the parasitic capacitance generated between the conductive layer 240a and the conductive layer 260. Similarly, the physical distance between the conductive layer 240b and the conductive layer 260 can be increased, thereby reducing the parasitic capacitance generated between the conductive layer 240b and the conductive layer 260.

[0114] Note that this embodiment shows an example in which the shape of the opening portion 270 when viewed from the plane is a quadrangle, but the present invention is not limited thereto. The shape of the opening portion 270 when viewed from the plane can be, for example, a circle, an ellipse or other approximately circular shapes, a triangle, a quadrangle (including a rectangle, a rhombus, a square), a pentagon, a star-shaped polygon or other polygonal shapes, or a shape in which the corners of these polygonal shapes are arc-shaped. The polygon can also be a concave polygon (a polygon in which at least one interior angle exceeds 180 degrees) or a convex polygon (a polygon in which all interior angles are less than 180 degrees).

[0115] In addition, the width of the opening portion 270 sometimes changes in the depth direction. Here, in particular, as the width of the opening portion 270, the maximum value of the width of the opening portion 270 provided in the insulating layer 284 when viewed from the cross section is used.

[0116] The height of the top surface of the conductive layer 260 preferably coincides with or is substantially the same as the height of the top surface of the insulating layer 285 or the insulating layer 284. The conductive layer 265 is provided on the insulating layer 285, on the insulating layer 284, and on the conductive layer 260, and contacts the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0117] <Constituent materials of the semiconductor device> The materials that can be used for the semiconductor device of this embodiment are described below. Each layer constituting the semiconductor device of this embodiment can have a single-layer structure or a laminated structure. Note that hereinafter, the conductive layer 240a and the conductive layer 240b are sometimes collectively referred to as the conductive layer 240.

[0118] [Oxide semiconductor layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 also has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 can have a single-layer structure or a laminated structure of two or more layers.

[0119] There is no particular limitation on the crystallinity of the semiconductor material for the oxide semiconductor layer 230, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in a part thereof) can be used. When a single crystal semiconductor or a semiconductor having crystallinity is used, deterioration of the characteristics of the transistor can be suppressed, which is therefore preferable.

[0120] The transistor 200 preferably contains a metal oxide (also referred to as an oxide semiconductor) used as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. In the case where a metal oxide used as a semiconductor is used for the oxide semiconductor layer 230, the transistor 200 can be said to be an OS transistor.

[0121] In an OS transistor, when oxygen vacancies (V O ) and impurities are present in the channel formation region of the oxide semiconductor, the electrical characteristics may easily change, resulting in a decrease in reliability. In addition, sometimes defects are formed in which hydrogen enters the oxygen vacancies (hereinafter sometimes referred to as V O H), and electrons serving as carriers are generated. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the OS transistor has a normally-on characteristic. Thus, in the channel formation region of the oxide semiconductor, it is preferable to minimize oxygen vacancies and impurities as much as possible. In other words, it is preferable that in the channel formation region of the oxide semiconductor, the carrier concentration is reduced and it is i-type (intrinsic) or substantially i-type.

[0122] On the other hand, the source region and the drain region of the OS transistor are preferably regions where there are more oxygen vacancies, more V O H, or higher concentrations of impurities such as hydrogen, nitrogen, and metal elements than in the channel formation region, so that the carrier concentration increases and the resistance is lowered. That is, compared with the channel formation region, the source region and the drain region of the OS transistor are preferably n-type regions having a higher carrier concentration and a lower resistance.

[0123] The bandgap of the metal oxide used as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wider bandgap for the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Since the off-state current of the OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. In addition, since the frequency characteristics of the OS transistor are high, the semiconductor device can operate at high speed.

[0124] Regarding the oxide semiconductor layer that can be used as the semiconductor layer of the transistor according to one embodiment of the present invention, reference can be made to the description of Embodiment 2. The detailed description thereof is omitted here.

[0125] In addition, transistors using other semiconductor materials in the channel formation region may also be used in the semiconductor device of the present embodiment. As such other semiconductor materials, for example, semiconductors composed of single elements or compound semiconductors can be cited.

[0126] As semiconductors composed of single elements that can be used as semiconductor materials, for example, silicon and germanium can be cited. In addition, as silicon that can be used as a semiconductor material for transistors, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0127] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide, etc. can be cited. Boron nitride that can be used in the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used in the semiconductor layer preferably contains crystals having a cubic crystal structure. In addition, as compound semiconductors, for example, organic semiconductors and nitride semiconductors can be cited. The above oxide semiconductors are also one kind of compound semiconductors. These semiconductor materials may also contain impurities as dopants.

[0128] In addition, transistors using a layered material used as a semiconductor in the channel formation region may also be used in the semiconductor device of the present embodiment. The details of the layered material will be described in Embodiment 7.

[0129] [Insulating layer] As the insulating layers (insulating layer 210, insulating layer 280, insulating layer 284, insulating layer 285, insulating layer 250, etc.) included in the semiconductor device, an inorganic insulating film is preferably used. As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitrogen oxide insulating film can be cited. As the oxide insulating film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminum oxide film can be cited. As the nitride insulating film, for example, a silicon nitride film and an aluminum nitride film can be cited. As the oxynitride insulating film, for example, a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, a yttrium oxynitride film, and a hafnium oxynitride film can be cited. As the nitrogen oxide insulating film, for example, a silicon nitrogen oxide film and an aluminum nitrogen oxide film can be cited. In addition, as the insulating layer included in the semiconductor device, an organic insulating film may also be used.

[0130] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a material with a high relative dielectric constant (high-k) as the gate insulating layer, it is possible to achieve a low voltage during transistor operation while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT: Equivalent Oxide Thickness) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative dielectric constant for the insulating layer used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulating layer. In addition, a material with a low relative dielectric constant is also a material with a high dielectric strength.

[0131] Examples of materials with a high relative dielectric constant include alumina, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0132] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, and acrylic resin. In addition, examples of inorganic insulating materials with a low relative dielectric constant other than the above include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. In addition, porous silicon oxide can be cited. In addition, these silicon oxides can also contain nitrogen.

[0133] In addition, as the insulating layer included in the semiconductor device, a material that can have ferroelectricity can also be used. Examples of materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. In addition, as a material that can have ferroelectricity, a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide can be cited. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or around it. In addition, as a material that can have ferroelectricity, a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide can be cited. In addition, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or around it. Note that the above lanthanum can also be a lanthanide element. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X) Piezoelectric ceramics with a perovskite structure such as strontium barium titanate (BST), strontium titanate, lead zirconate titanate (PZT), bismuth strontium tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0134] In addition, as materials that can have ferroelectricity, metal nitrides containing element M1, element M2, and nitrogen can be cited. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic ratio of element M1 to element M2 can be appropriately set. In addition, metal oxides containing element M1 and nitrogen sometimes have ferroelectricity even if they do not contain element M2. In addition, as materials that can have ferroelectricity, materials obtained by adding element M3 to the above metal nitrides can be cited. Note that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the atomic ratio of element M1, element M2, and element M3 can be appropriately set.

[0135] In addition, as materials that can have ferroelectricity, perovskite oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina can be cited.

[0136] Note that in the above description, although examples of metal oxides and metal nitrides are shown, it is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitroxides obtained by adding oxygen to the above metal nitrides can also be used.

[0137] In addition, as materials that can have ferroelectricity, for example, mixtures or compounds composed of multiple materials selected from the above materials can be used. In addition, the insulating layer 130 described in Embodiment 3 can have a stacked structure composed of multiple materials selected from the above materials. Note that the crystal structures (properties) of the materials and the like listed above may change not only according to the deposition conditions but also according to various processes, etc. Therefore, in this specification, etc., materials that exhibit ferroelectricity are not only called ferroelectrics but also called materials that can have ferroelectricity.

[0138] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when processed into a thin film of several nm. In addition, metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when their area is small. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0139] In the present specification and the like, a material that can have ferroelectricity and is formed in a layer form is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in the present specification and the like, a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0140] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen in the crystal contained in the ferroelectric layer is displaced by the action of an externally applied electric field. In addition, it is presumed that the exhibition of ferroelectricity depends on the structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulating layer to exhibit ferroelectricity, the insulating layer 130 needs to contain a crystal. In particular, the insulating layer preferably has a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystal contained in the insulating layer may be any one or more selected from the tetragonal system, the orthorhombic system, the monoclinic system, and the hexagonal system. In addition, the insulating layer may have an amorphous structure. At this time, the insulating layer may also have a composite structure of an amorphous structure and a crystal structure.

[0141] In addition, by adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide is increased, and thus it is easy to form a crystal having an orthorhombic crystal structure. As a result, the proportion of the crystal having an orthorhombic crystal structure increases, and the remanent polarization can be enhanced, so it is preferred. On the other hand, when the addition amount of the Group 3 element is too large, the crystallinity of the oxide may decrease, and thus it is not easy to exhibit ferroelectricity. Therefore, the content rate of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and further preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content rate of the Group 3 element refers to the proportion of the number of atoms of the Group 3 element in the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0142] In addition, by surrounding a transistor using a metal oxide with an insulating layer having a function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As the insulating layer having a function of suppressing the permeation of impurities and oxygen, for example, a single layer or a laminate of an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as the material of the insulating layer having a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, nitrides such as aluminum nitride and silicon nitride, and oxynitrides such as silicon oxynitride can be used.

[0143] Specifically, as materials for an insulating layer having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, for example, metal oxides such as alumina, magnesia, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and an oxide containing aluminum and hafnium (hafnium aluminate) can be cited. In addition, for example, nitrides such as aluminum nitride, titanium aluminum nitride, and silicon nitride can be cited. In addition, for example, oxynitrides such as silicon oxynitride can be cited.

[0144] In addition, an insulating layer in contact with the oxide semiconductor layer such as a gate insulating layer or an insulating layer provided near the oxide semiconductor layer preferably has a region containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). For example, by bringing an insulating layer having a region containing excess oxygen into contact with the oxide semiconductor layer or by positioning it near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. As materials for an insulating layer that easily forms a region containing excess oxygen, silicon oxide, silicon oxynitride, or porous silicon oxide can be cited.

[0145] As an insulating layer in contact with the oxide semiconductor layer or an insulating layer provided near the oxide semiconductor layer, a hydrogen-blocking insulating layer is preferably used. By making this insulating layer have hydrogen-blocking properties, hydrogen diffusion into the oxide semiconductor layer can be suppressed.

[0146] As materials for an insulating layer having a function of capturing or fixing hydrogen, metal oxides such as hafnium-containing oxide, magnesium-containing oxide, aluminum-containing oxide, aluminum and hafnium-containing oxide (hafnium aluminate), hafnium and zirconium-containing oxide (hafnium zirconium oxide), and hafnium and silicon-containing oxide (hafnium silicate) can be cited. In addition, these metal oxides may further contain zirconium, and for example, hafnium and zirconium-containing oxide can be cited.

[0147] An insulating layer having a function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, since some oxygen atoms have dangling bonds, the ability to capture or fix hydrogen is high. Therefore, by making this insulating layer have an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, by adding silicon to the above metal oxide, an amorphous structure can also be achieved. For example, hafnium and silicon-containing oxide (hafnium silicate) is preferably used.

[0148] By making the above insulating layer have an amorphous structure, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of this insulating layer can be improved. As a result, the thickness distribution of the insulating layer becomes uniform, and parts with an extremely thin thickness can be reduced, so the withstand voltage of the insulating layer can be improved. In addition, the thickness distribution of the film provided on the insulating layer can be made uniform. In addition, by suppressing the formation of grain boundaries in the above insulating layer, the leakage current of defect energy levels caused by grain boundaries can be reduced. As a result, the insulating layer can be used as an insulating film with less leakage current.

[0149] Note that sometimes the above-mentioned insulating layer has one or both of a crystalline region and grain boundaries in a part thereof.

[0150] In addition, the function of capturing or fixing a corresponding substance can also be said to have the property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing a corresponding substance can also be alternatively referred to as a barrier property.

[0151] In this specification and the like, a barrier insulating layer refers to an insulating layer having a barrier property. In addition, the barrier property refers to the property of not easily diffusing a corresponding substance (also referred to as the property of not easily permeating a corresponding substance, the property of low permeability of a corresponding substance, or the function of suppressing the diffusion of a corresponding substance). In addition, the hydrogen referred to as the corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and a substance hydrogen-bonded to OH - and the like. In addition, unless otherwise specified, the impurity referred to as the corresponding substance refers to an impurity in the channel formation region or the semiconductor layer, and is, for example, at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, etc.), a copper atom, and the like. In addition, the oxygen referred to as the corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0152] Examples of materials for the hydrogen barrier insulating layer include alumina, magnesia, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride.

[0153] Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesia, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride. In addition, examples of oxides containing one or both of aluminum and hafnium include alumina, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), and the like.

[0154] Since the insulating layer 210 is used as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0155] As the insulating layer 210, it is preferable to use a hydrogen barrier insulating layer. By providing the insulating layer 210 below the oxide semiconductor layer 230 with a hydrogen barrier property, the diffusion of hydrogen from below the transistor 200 into the oxide semiconductor layer 230 can be suppressed. For example, as the insulating layer 210, it is preferable to use a silicon nitride film.

[0156] In addition, as the insulating layer 210, an insulating layer having a function of capturing or fixing hydrogen is preferably used. By providing the insulating layer 210 with the function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210, and thus the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0157] In addition, the concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced. Thereby, mixing of impurities such as hydrogen or water into the channel formation region of the oxide semiconductor layer 230 can be suppressed.

[0158] ​ An example in which the insulating layer 210 has a single-layer structure is shown. In addition, the insulating layer 210 may have a stacked structure of two or more layers. For example, the insulating layer 210 may have a two-layer structure including a first insulating layer and a second insulating layer on the first insulating layer. At this time, for example, it is preferable to use a hydrogen-blocking insulating layer as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0159] Since the insulating layer 280 is used as an interlayer film, it is preferable to use the above-described material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 280, for example, silicon oxide or silicon oxynitride can be used.

[0160] In addition, the concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. Thereby, mixing of impurities such as hydrogen or water into the channel formation region of the oxide semiconductor layer 230 can be suppressed.

[0161] For example, an insulating layer having a region containing excess oxygen can be formed by a sputtering method in an oxygen-containing atmosphere. By using a sputtering method that does not require a hydrogen-containing molecule as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Thus, by depositing a layer that constitutes at least a part of the insulating layer 280 using a sputtering method, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, and oxygen vacancies and V O H can be reduced.

[0162] Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200, so the thickness of the insulating layer 280 is appropriately set according to the design value of the channel length of the transistor 200.

[0163] ​ An example in which the insulating layer 280 has a single-layer structure is shown. In addition, the insulating layer 280 may have a stacked structure of two or more layers. For example, as ​As shown, the insulating layer 280 may have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. At this time, preferably, the material with a low relative dielectric constant described above is used as the insulating layer 280_2, and an oxygen barrier insulating layer is used as the insulating layer 280_1 and the insulating layer 280_3. Thereby, oxidation of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b can be suppressed, and high resistance can be suppressed.

[0164] For example, preferably, a silicon nitride film or an aluminum oxide film is used as the insulating layer 280_1 and the insulating layer 280_3, and a silicon oxide film is used as the insulating layer 280_2. In addition, both the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0165] As the insulating layer 250, a hydrogen barrier insulating layer is preferably used. By having hydrogen barrier properties, the insulating layer 250 provided on the oxide semiconductor layer 230 can suppress hydrogen contained in the conductive layer 260 from diffusing into the oxide semiconductor layer 230. For example, since a silicon nitride film has high hydrogen barrier properties, it is suitable for use as the insulating layer 250.

[0166] In addition, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, an insulating layer having a function of capturing or fixing hydrogen is preferably used. Thereby, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed more effectively. Thereby, the hydrogen concentration in the oxide semiconductor layer 230 (especially, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Thereby, V O H can be reduced, and the channel formation region can be made i-type or substantially i-type.

[0167] In addition, the insulating layer 250 is preferably an insulating layer having a region containing excess oxygen. Thereby, oxygen can be supplied from the insulating layer 250 to the oxide semiconductor layer 230 to reduce oxygen vacancies in the oxide semiconductor layer 230. In addition, since a silicon oxide film or an oxynitride film has thermal stability, it is suitable for use as the insulating layer 250.

[0168] ​ An example in which the insulating layer 250 has a single-layer structure is shown. In addition, the insulating layer 250 may have a stacked structure of two or more layers. At this time, the insulating layer 250 is preferably formed of two or more films. By using two or more films as the insulating layer 250, the insulating layer 250 can have multiple functions. As functions of the insulating layer 250, for example, a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing hydrogen diffusion into the oxide semiconductor layer 230 can be cited.

[0169] For example, the insulating layer 250 may have a two-layer structure including a first insulating layer and a second insulating layer on the first insulating layer. At this time, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, preferably, an insulating layer having a function of capturing or fixing hydrogen is used as the first insulating layer, and a hydrogen-blocking insulating layer is used as the second insulating layer. By adopting such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer, and a silicon nitride film can be used as the second insulating layer.

[0170] Alternatively, for example, preferably, an insulating layer having a region containing excess oxygen is used as the first insulating layer, and a hydrogen-blocking insulating layer is used as the second insulating layer. Alternatively, for example, preferably, an insulating layer having a region containing excess oxygen is used as the first insulating layer, and an insulating layer having a function of capturing or fixing hydrogen is used as the second insulating layer. By adopting such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and thus the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0171] In addition, for example, the insulating layer 250 may include a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 may have a three-layer structure including a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0172] For example, preferably, an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low relative dielectric constant is used as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen is used as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen is used as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. In addition, by providing the second insulating layer, the oxygen contained in the third insulating layer can be prevented from diffusing into the conductive layer 260, and thus the oxidation of the conductive layer 260 can be suppressed. In addition, the reduction in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0173] In addition, for example, the insulating layer 250 may include a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 may have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0174] As the fourth insulating layer, an insulating layer having an oxygen barrier property is preferably used. The first to third insulating layers may have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. When the fourth insulating layer has an oxygen barrier property, oxygen detachment from the oxide semiconductor layer 230 can be suppressed. In addition, oxidation of the side surface of the conductive layer 240 can be suppressed, and an oxide film can be prevented from forming on the side surface. Therefore, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200 can be suppressed.

[0175] As the fourth insulating layer, for example, an alumina film is preferably used. The alumina film has a function of capturing or fixing hydrogen, and thus is suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an alumina film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from the oxide semiconductor layer 230 side.

[0176] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as the S value), which is one of the transistor characteristics, can be reduced. The S value refers to the change amount of the gate voltage when the drain current changes by one digit at a constant drain voltage in the subthreshold region.

[0177] In addition, the thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, still more preferably 0.5 nm or more and 5 nm or less, yet still more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. At least a part of each layer constituting the insulating layer 250 may include a region having the above thickness.

[0178] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. For example, as ​As shown, alumina with a thickness of 1 nm can be used as the insulating layer 250a, silica with a thickness of 2 nm can be used as the insulating layer 250b, hafnium oxide, hafnium zirconium oxide, or hafnium zirconium oxide containing yttrium with a thickness of 2 nm can be used as the insulating layer 250d, and silicon nitride with a thickness of 1 nm can be used as the insulating layer 250c. Here, the insulating layer 250a corresponds to the above-mentioned fourth insulating layer, the insulating layer 250b corresponds to the above-mentioned third insulating layer, the insulating layer 250d corresponds to the above-mentioned first insulating layer, and the insulating layer 250c corresponds to the above-mentioned second insulating layer. In this case, the insulating layer 250 includes the insulating layer 250a on the oxide semiconductor layer 230, the insulating layer 250b on the insulating layer 250a, the insulating layer 250d on the insulating layer 250b, and the insulating layer 250c on the insulating layer 250d. Note that, as ​ shown, etc., when locally observing within the groove portion 290, it can be considered that: the insulating layer 250a is provided inside the oxide semiconductor layer 230, the insulating layer 250b is provided inside the insulating layer 250a, the insulating layer 250d is provided inside the insulating layer 250b, and the insulating layer 250c is provided inside the insulating layer 250d. In addition, ​ corresponds to ​ an enlarged view of the region A shown.

[0179] In addition, when forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to adopt an atomic layer deposition (ALD: Atomic Layer Deposition) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed by the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and thickness uniformity of the insulating layer 250 can be improved. In addition, by continuously forming two or more films, such as two or more insulating films, using the ALD process, the productivity can be improved.

[0180] In addition, in ​ the structure shown, an insulator having a function of capturing or fixing hydrogen can be provided in the insulating layer 250d. For example, as the insulating layer 250d, an oxide containing hafnium is preferably used. As the oxide containing hafnium, for example, hafnium oxide, hafnium aluminate, hafnium silicate, hafnium zirconium oxide, hafnium zirconium oxide containing yttrium, etc. can be used. In addition, as the insulating layer 250d, hafnium zirconium oxide containing lanthanide elements such as lanthanum can also be used.

[0181] By providing an insulating layer 250d between the insulating layer 250c and the insulating layer 250b, hydrogen contained in the insulating layer 250b or the like can be captured or fixed more effectively. The channel formation region of the oxide semiconductor layer 230, the insulating layer 250a having a function of capturing or fixing hydrogen, and the insulating layer 250d are provided under the insulating layer 250c having a function of suppressing the diffusion of hydrogen. In a region where hydrogen diffusing from above is blocked by the insulating layer 250c, hydrogen contained in the channel formation region of the oxide semiconductor layer 230 or the like can be captured or fixed by the insulating layer 250a and the insulating layer 250d. Thereby, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and thus the negative drift of the initial characteristics of the transistor 200 can be suppressed to achieve the normally-off characteristic. In addition, the negative drift degradation in the +GBT (Gate Bias-Temperature) stress test can be suppressed.

[0182] In addition, a structure in which the insulating layer 250c is not provided and the insulating layer 250a, the insulating layer 250b, and the insulating layer 250d are provided may be employed. In this case, an insulator (for example, silicon nitride or the like) having a function of suppressing the diffusion of hydrogen is preferably provided as the insulating layer 284 on the insulating layer 250. By adopting such a structure, the oxide semiconductor layer 230, the insulating layer 250a having a function of capturing or fixing hydrogen, and the insulating layer 250d are formed in a region covered with silicon nitride having high hydrogen barrier properties. Therefore, hydrogen contained in the channel formation region of the oxide semiconductor layer 230 or the like can be captured or fixed by the insulating layer 250a and the insulating layer 250d.

[0183] By adopting the above structure, the channel formation region can be i-type or substantially i-type and the source region and the drain region can be n-type, and a semiconductor device having good electrical characteristics can be provided. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200, the high-frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0184] In addition, the hafnium-containing metal oxide for the insulating layer 250d preferably functions as a high-k material. By adopting such a structure, the gate potential applied during the operation of the transistor can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0185] In addition, the insulating layer 250d preferably has ferroelectricity. For example, the insulating layer 250d can use hafnium zirconium oxide with ferroelectricity, yttrium-containing hafnium zirconium oxide, etc. In addition, the insulating layer 250d can also adopt a structure in which a layer of hafnium zirconium oxide is stacked on a layer of yttrium-containing hafnium zirconium oxide. In addition, when a ferroelectric is used for the insulating layer 250d, the insulating layer 250d does not necessarily need to have a function of capturing or fixing hydrogen. In addition, the insulating layer 250d can use the above materials that can have ferroelectricity.

[0186] In this way, by using a ferroelectric as the insulating layer 250d, the transistor 200 can be used as a FeFET (Ferroelectric Field Effect Transistor). The FeFET is used as a storage element alone. Therefore, compared with a DRAM (Dynamic Random Access Memory) type storage element having a transistor and a capacitor, the structure of the storage element can be reduced. As a result, miniaturization and high integration of the storage device including the transistor 200 can be achieved. In addition, the productivity of the storage device including the transistor 200 can be improved.

[0187] Although the three-layer structure of the insulating layers 250a to 250c or the four-layer structure of the insulating layers 250a to 250d of the insulating layer 250 is described above, the present invention is not limited thereto. The insulating layer 250 can have a single-layer structure, a two-layer structure, or a stacked structure of five or more layers. In addition, the insulating layer 250 can have a structure including at least one of the insulating layers 250a to 250d. For example, the insulating layer 250 can also have a single-layer structure of the insulating layer 250c. At this time, the insulating layer 250 can also be formed of a single layer of hafnium zirconium oxide. By forming the insulating layer 250 with one, two, or three layers of the insulating layers 250a to 250d, the manufacturing process of the semiconductor device can be simplified, thereby improving the productivity.

[0188] In the case where the insulating layer 250 has a four-layer structure or a five-layer structure, for example, it can also have ​ the stacked structure shown. Here, ​ is an enlarged view corresponding to ​ the region A shown.

[0189] ​ An example of a stacked structure of the insulating layer 250 having the insulating layer 250a on the oxide semiconductor layer 230, the insulating layer 250d on the insulating layer 250a, the insulating layer 250b on the insulating layer 250d, and the insulating layer 250c on the insulating layer 250b is shown. In other words, ​ the insulating layer 250 shown is an interchange ​The insulating layer at the position of insulating layer 250b and insulating layer 250d in the shown insulating layer 250. For example, alumina with a thickness of 1 nm can be used as insulating layer 250a, hafnium zirconium oxide or hafnium zirconium oxide containing yttrium with a thickness of 2 nm can be used as insulating layer 250d, silicon oxide with a thickness of 2 nm can be used as insulating layer 250b, and silicon nitride with a thickness of 1 nm can be used as insulating layer 250c. In addition, insulating layer 250d may also have a structure in which a layer of hafnium zirconium oxide is laminated on a layer of hafnium zirconium oxide containing yttrium. However, it is not limited thereto, and the above insulating materials can be appropriately selected for insulating layers 250a to 250d, and the thicknesses of insulating layers 250a to 250d can also be appropriately selected. As ​ shown, by laminating insulating layers 250a to 250d, insulating layers 250a and 250d having the function of capturing or fixing hydrogen are disposed adjacent to each other, so that hydrogen can be captured or fixed more effectively.

[0190] In addition, as ​ shown, a structure in which the positions of insulating layer 250c and insulating layer 250b are interchanged can also be adopted. In this case, insulating layer 250 has a stacked structure of insulating layer 250a on oxide semiconductor layer 230, insulating layer 250d on insulating layer 250a, insulating layer 250c on insulating layer 250d, and insulating layer 250b on insulating layer 250c.

[0191] In addition, insulating layer 250c can also be disposed in ​ in such a manner as to be in contact with the top surface and the bottom surface of insulating layer 250b. In this case, as ​ shown, insulating layer 250 has a stacked structure of insulating layer 250a on oxide semiconductor layer 230, insulating layer 250d on insulating layer 250a, insulating layer 250c1 on insulating layer 250d, insulating layer 250b on insulating layer 250c1, and insulating layer 250c2 on insulating layer 250b. Here, the above insulators that can be used for insulating layer 250c can be used as insulating layers 250c1 and 250c2. For example, silicon nitride with a thickness of 1 nm can be used as insulating layers 250c1 and 250c2.

[0192] ​ An example showing that insulating layer 250 has a stacked structure of insulating layer 250a on oxide semiconductor layer 230, insulating layer 250b on insulating layer 250a, insulating layer 250d1 on insulating layer 250b, insulating layer 250c on insulating layer 250d1, and insulating layer 250d2 on insulating layer 250c. That is, ​ the shown insulating layer 250 has in ​The structure of the insulator that can be used for the insulating layer 250d is provided in the insulating layer 250 as shown in a manner that contacts the top and bottom surfaces of the insulating layer 250c. Here, as the insulating layer 250d1, an insulator having a function of capturing or fixing hydrogen (e.g., hafnium oxide) can be used, and as the insulating layer 250d2, an insulator having ferroelectricity (e.g., hafnium zirconium oxide or hafnium zirconium oxide containing yttrium) can be used. In addition, the insulating layer 250d2 may also have a structure in which a layer of hafnium zirconium oxide is laminated on a layer of hafnium zirconium oxide containing yttrium. By adopting such a structure and using a ferroelectric for the insulating layer 250d2, the transistor 200 can be used as a FeFET. Furthermore, since hydrogen can be captured or fixed by the insulating layer 250d1, the electrical characteristics and reliability of the transistor 200 can be improved.

[0193] In addition, in the case where the insulating layer 250d2 is formed and a ferroelectric material such as hafnium zirconium oxide is used as the insulating layer 250d2, as ​ shown, the conductive layer 252 can also be provided in a manner that contacts the bottom surface of the insulating layer 250d2. As the conductive layer 252, a material that is easy to polarize the insulating layer 250d2 is preferably used, for example, titanium nitride is preferably used. In addition, in this case, the portion of the lower part of the conductive layer 260 that contacts the insulating layer 250d2 is also preferably made of titanium nitride. By adopting such a structure, a ferroelectric can be used as the insulating layer 250d2 to use the transistor 200 as a FeFET.

[0194] [Conductive layer] As the conductive layers (the conductive layer 220, the conductive layer 240, the conductive layer 260, the conductive layer 265, etc.) included in the semiconductor device, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys composed of the above metal elements, or alloys combining the above metal elements, etc. are preferably used. As the alloy composed of the above metal elements, a nitride or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, highly conductive semiconductors represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0195] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide, or lanthanum and nickel oxide, materials containing metal elements such as titanium, tantalum or ruthenium, etc. are conductive materials that are not easily oxidized, conductive materials having a function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Examples of the conductive material containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In-Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide, etc. In this specification, etc., a conductive film formed by depositing a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0196] Conductive materials mainly composed of tungsten, copper or aluminum have high conductivity, so they are preferred.

[0197] In addition, a plurality of conductive layers formed of the above materials can be laminated. For example, a laminated structure combining the above material containing a metal element and a conductive material containing oxygen can be adopted. In addition, a laminated structure combining the above material containing a metal element and a conductive material containing nitrogen can be adopted. In addition, a laminated structure combining the above material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can be adopted.

[0198] In addition, when a metal oxide is used for the channel formation region of a transistor, a laminated structure combining the above material containing a metal element and a conductive material containing oxygen is preferably adopted as the conductive layer used as the gate electrode. In this case, it is preferable to dispose the conductive material containing oxygen on the side of the channel formation region. By disposing the conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.

[0199] Since both the conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material having a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Thereby, a decrease in the conductivity of the conductive layer 220 and the conductive layer 240 can be suppressed.

[0200] By using a conductive material containing oxygen as the conductive layer 220, the conductivity can be maintained even if the conductive layer 220 absorbs oxygen. Similarly, by using a conductive material containing oxygen as the conductive layer 240, the conductivity can be maintained even if the conductive layer 240 absorbs oxygen. In addition, in the case of using an oxygen-containing insulating layer such as hafnium oxide as the insulating layer 210, the conductive layer 220 can also maintain conductivity, which is preferable. As the conductive layer 220 and the conductive layer 240, for example, ITO, ITSO, In-Zn oxide, etc. are preferably used.

[0201] When the conductive layer 220 and the conductive layer 240 have a stacked structure, by using a conductive material containing oxygen for the layer with the largest contact area with the oxide semiconductor layer 230 in the stacked structure, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0202] ​ The shown conductive layer 220 has a two-layer structure of the conductive layer 220_1 and the conductive layer 220_2 on the conductive layer 220_1. At this time, preferably, for example, a conductive material containing oxygen is used as the conductive layer 220_2, and a material with higher conductivity than the conductive layer 220_2 is used as the conductive layer 220_1. Specifically, for example, an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) is preferably used for the conductive layer 220_2, and tungsten is preferably used for the conductive layer 220_1. In addition, ruthenium, titanium nitride, or tantalum nitride, etc. can also be used as the conductive layer 220_1. By using an oxide conductor as the conductive layer 220_2 that mainly contacts the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. In addition, by using a material with higher conductivity than the oxide conductor as the layer constituting the conductive layer 220, the conductivity of the conductive layer 220 can be improved.

[0203] Note that a conductive material containing oxygen can also be used as the conductive layer 220_1, and a material with higher conductivity than the conductive layer 220_1 can also be used as the conductive layer 220_2. At this time, the material with high conductivity is used for the layer in the conductive layer 220 closest to the channel formation region of the oxide semiconductor layer 230. Thereby, the current path between the source and the drain can be shortened, and thus the on-state current of the transistor 200 can be increased.

[0204] ​ Examples showing that both the conductive layer 220_1 and the conductive layer 220_2 have a single-layer structure are shown. One or both of the conductive layer 220_1 and the conductive layer 220_2 may also have a stacked structure of two or more layers. For example, as ​As shown, the conductive layer 220_1 may also have a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 on the conductive layer 220_11. At this time, the conductive layer 220 has a three-layer structure including the conductive layer 220_11, the conductive layer 220_12 on the conductive layer 220_11, and the conductive layer 220_2 on the conductive layer 220_12. Preferably, for example, a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion is used as the conductive layer 220_11, a material with high conductivity is used as the conductive layer 220_12, and a conductive material containing oxygen (more preferably, an oxide conductor) is used as the conductive layer 220_2. Specifically, preferably, titanium nitride is used as the conductive layer 220_11, tungsten is used as the conductive layer 220_12, and an oxide conductor (for example, ITO, ITSO, or In-Zn oxide) is used as the conductive layer 220_2. In this case, the titanium nitride film contacts the insulating layer 210, and the oxide conductive film contacts the oxide semiconductor layer 230. In addition, an oxide conductor is used for the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared with tungsten, the oxide conductor has a lower contact resistance with the oxide semiconductor layer 230, so the current path between the source and the drain can be shortened, and thus the on-state current of the transistor 200 can be increased. By adopting such a structure, even when the conductive layer 220 contacts the oxide semiconductor layer 230, conductivity can be maintained. In addition, when an oxide insulating layer is used as the insulating layer 210, excessive oxidation of the conductive layer 220 due to the insulating layer 210 can be suppressed. In addition, by using a metal material (tungsten in this case) with higher conductivity than the oxide conductor and titanium nitride as the conductive layer 220_12, the conductivity of the conductive layer 220 can be improved.

[0205] ​ The shown conductive layer 240a has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. At this time, for example, preferably, a conductive material containing oxygen is used as the conductive layer 240a2, and a material with higher conductivity than the conductive layer 240a2 is used as the conductive layer 240a1. Specifically, preferably, for example, an oxide conductor (for example, ITO, ITSO, or In-Zn oxide) is used as the conductive layer 240a2, and tungsten is used as the conductive layer 240a1. In addition, ruthenium, titanium nitride, tantalum nitride, etc. may also be used as the conductive layer 240a1. By using an oxide conductor as the conductive layer 240a2 that mainly contacts the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. In addition, by using a material with higher conductivity than the oxide conductor for the layer constituting the conductive layer 240a, the conductivity of the conductive layer 240a can be improved.

[0206] Note that a conductive material containing oxygen can also be used as the conductive layer 240a1, and a material with higher conductivity than the conductive layer 240a1 can be used as the conductive layer 240a2. In this case, an oxide conductor is used for the layer closest to the channel formation region of the oxide semiconductor layer 230 in the conductive layer 240a. Thereby, the current path between the source and the drain can be shortened, and thus the on-state current of the transistor 200 can be increased.

[0207] The conductive layer 260 has a region serving as a gate electrode. As the conductive layer 260, a material with high conductivity such as tungsten is preferably used. In addition, as the conductive layer 260, a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion is preferably used. As such a conductive material, as described above, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be cited. Thereby, a decrease in the conductivity of the conductive layer 260 can be suppressed.

[0208] In addition, the conductive layer 260 preferably uses a conductive material containing the metal element and oxygen included in the metal oxide forming the channel. In addition, a conductive material containing the above metal element and nitrogen (for example, titanium nitride, tantalum nitride, etc.) can also be used. In addition, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, sometimes the hydrogen included in the metal oxide forming the channel can be captured. Or, sometimes the hydrogen mixed in from an external insulating layer or the like can be captured.

[0209] ​ An example in which the conductive layer 260 has a single-layer structure is shown. In addition, the conductive layer 260 can have a stacked structure of two or more layers. For example, as ​ shown, the conductive layer 260 has a two-layer structure of the conductive layer 260_1 and the conductive layer 260_2 on the conductive layer 260_1. At this time, for example, a titanium nitride film is preferably used as the conductive layer 260_1, and a tungsten film is preferably used as the conductive layer 260_2. Or, a tantalum nitride film is preferably used as the conductive layer 260_1, and a copper film is preferably used as the conductive layer 260_2. By adopting such a structure, the conductivity of the conductive layer 260 can be increased.

[0210] In addition, the conductive layer 260 can also have a stacked structure of three or more layers. The conductive layer 260 can, for example, also have a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0211] The conductive layer 265 is used as a gate wiring. As the conductive layer 265, for example, the materials that can be used for the conductive layer 260 can be used. As the conductive layer 265, high melting point materials such as tungsten or molybdenum having both heat resistance and conductivity are preferably used. Alternatively, low-resistance conductive materials such as aluminum or copper can be used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0212] ​ An example in which the conductive layer 265 has a single-layer structure is shown. In addition, the conductive layer 265 can have a stacked structure of two or more layers.

[0213] [Substrate] As the substrate for forming the transistor, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), a resin substrate, etc. can be cited. In addition, as the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be cited. Also, a semiconductor substrate having an insulator region inside the above semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, can be cited. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can be cited. Alternatively, a substrate provided with elements on these substrates can also be used. As the elements provided on the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a storage element, etc. can be cited.

[0214] The materials for the semiconductor device applicable to the present embodiment are described above.

[0215] The semiconductor device according to one aspect of the present invention may also include an insulating layer on the transistor 200. Specifically, an insulating layer may also be provided on the conductive layer 265 and the insulating layer 285.

[0216] As the above insulating layer, a hydrogen barrier insulating layer is preferably used. By adopting such a structure, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0217] Although in ​The structure in which the side surface of the conductive layer 240 in the groove portion 290 is flush (it can also be said to be aligned, substantially aligned, consistent, substantially consistent) with the side surface of the insulating layer 280 in the groove portion 290 is shown, but the present invention is not limited thereto. For example, the side surface of the conductive layer 240a in the groove portion 290 may be discontinuous with the side surface of the insulating layer 280 in the groove portion 290. In addition, the inclination degree of the side surface of the conductive layer 240a in the groove portion 290 and the inclination degree of the side surface of the insulating layer 280 in the groove portion 290 may be different from each other. At this time, a part of the side surface of the groove portion 290 has a conical shape.

[0218] ​ and ​ Examples showing that at least a part of the side surface of the groove portion 290 has a conical shape are shown. ​ Examples showing that the side surface of the conductive layer 240a in the groove portion 290 has a conical shape are shown, ​ Examples showing that both the side surface of the conductive layer 240a in the groove portion 290 and the side surface of the insulating layer 280 have a conical shape are shown.

[0219] By making the side surface of the groove portion 290 have a conical shape, the coverage of the oxide semiconductor layer 230, the insulating layer 250, etc. can be improved, and thus defects such as voids can be reduced. When the side surface of the groove portion 290 has a conical shape, for example, the conical angle (angle θ240) of the side surface of the conductive layer 240a on the groove portion 290 side and the conical angle (angle θ280) of the side surface of the insulating layer 280 in the groove portion 290 are preferably both 45 degrees or more and less than 90 degrees. Specifically, the conical angle is preferably 80 degrees or more and less than 90 degrees, and thus miniaturization or high integration of the semiconductor device can be achieved as described above. In addition, the conical angle is preferably 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, and thus the coverage of the film formed in the groove portion 290 is improved.

[0220] In addition, for example, the angle θ240 is preferably smaller than the angle θ280. By adopting such a structure, the coverage of the oxide semiconductor layer 230, etc. on the side surface of the conductive layer 240a on the groove portion 290 side is improved, and thus defects such as voids can be reduced. In addition, in the case where the insulating layer 280 has a laminated structure, the inclination degrees of the side surfaces of the respective layers in the groove portion 290 may also be different. Similarly, in the case where the conductive layer 240a has a laminated structure, the inclination degrees of the side surfaces of the respective layers on the groove portion 290 side may also be different.

[0221] As described above, the oxide semiconductor layer 230 may have a laminated structure of two or more layers.

[0222] ​ Show ​An example of a two-layer structure of the oxide semiconductor layer 230 included in the semiconductor device shown. ​ The oxide semiconductor layer 230 shown may have a two-layer structure including an oxide semiconductor layer 230_1 and an oxide semiconductor layer 230_2 on the oxide semiconductor layer 230_1.

[0223] In addition, ​ shows ​ An example of a three-layer structure of the oxide semiconductor layer 230 included in the semiconductor device shown. ​ The oxide semiconductor layer 230 shown may have a three-layer structure including an oxide semiconductor layer 230_1, an oxide semiconductor layer 230_2 on the oxide semiconductor layer 230_1, and an oxide semiconductor layer 230_3 on the oxide semiconductor layer 230_2.

[0224] Regarding the oxide semiconductor layers that can be used for the oxide semiconductor layers 230_1 to 230_3, refer to the description of Embodiment 2.

[0225] <Example of a method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that descriptions of materials and formation methods of each component may sometimes omit parts that are the same as those already described.

[0226] Note that thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0227] Examples of the sputtering method include an RF sputtering method using a high-frequency power source as a sputtering power source, a DC sputtering method using a DC power source, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing insulating films, and the DC sputtering method is mainly used when depositing metal conductive films. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0228] In addition, the CVD method can be classified into a plasma CVD method (PECVD) using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0229] By using the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. In addition, since plasma is not used, the thermal CVD method is a deposition method that can reduce plasma damage to the object to be processed. For example, wirings, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above plasma damage does not occur in the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during formation does not occur, so a film with fewer defects can be obtained.

[0230] As the ALD method, a thermal ALD method that uses only heat energy to react a precursor and a reactant, a PEALD method that uses a reactant excited by plasma, etc. are adopted.

[0231] In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine than the film formed by other deposition methods. In addition, the quantification of these elements can be performed using XPS or SIMS. Note that, as a deposition method of a metal oxide according to one aspect of the present invention, the ALD method is used, but since one or both of the conditions of a high substrate temperature during deposition and an impurity removal process are adopted, the amounts of carbon and chlorine contained in the film are sometimes less than those in the case of using the ALD method without adopting the above conditions.

[0232] The ALD method is different from a deposition method in which particles released from a target material, etc. are deposited, and is a deposition method in which a film is formed by a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so it is suitable for forming a film that covers the surface of an opening or a groove with a high aspect ratio.

[0233] The CVD method and the ALD method are different from the sputtering method in which particles released from a target or the like are deposited. Therefore, they are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has high step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of openings or grooves with a high aspect ratio, etc. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferable to use it in combination with other deposition methods such as the CVD method with a high deposition rate.

[0234] In addition, when using the CVD method, a film of any composition can be deposited according to the flow rate ratio of the source gases. For example, when using the CVD method, a film with a continuously changing composition can be deposited by changing the flow rate ratio of the source gases while performing deposition. When depositing while changing the flow rate ratio of the source gases, since there is no need for the time required for transferring or adjusting the pressure, the deposition time can be shortened compared to the case of depositing using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0235] When using the ALD method, a film of any composition can be deposited by simultaneously introducing a plurality of different precursors. Alternatively, when introducing a plurality of different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0236] The thin films (such as insulating films, semiconductor films, and conductive films) constituting the semiconductor device can be formed by wet deposition methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife method, slot die coating, roll coating, curtain coating, or blade coating.

[0237] In addition, when processing the thin films constituting the semiconductor device, photolithography or the like can be used. Alternatively, nanoimprinting, sandblasting, lift-off, etc. can be used to process the thin films. In addition, island-shaped thin films can be directly formed by a deposition method using a masking mask such as a metal mask.

[0238] Typically, there are the following two photolithography methods. One is a method of forming a resist mask on the thin film to be processed, processing the thin film by etching or the like, and removing the resist mask. The other is a method of depositing a photosensitive thin film and then performing exposure and development to process the thin film into a desired shape.

[0239] In photolithography, as the light for exposure, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light mixed with these rays can be used. In addition, ultraviolet light, KrF laser, ArF laser, etc. can also be used. In addition, immersion exposure technology can also be used for exposure. In addition, as the light for exposure, extreme ultraviolet (EUV) light or X-rays can also be used. In addition, instead of the light for exposure, an electron beam can also be used. When using extreme ultraviolet light, X-rays, or an electron beam, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0240] As an etching method for the thin film, a dry etching method, a wet etching method, a sandblasting method, etc. can be used.

[0241] Refer to ​ Description ​ 、 ​ 、 ​ The example of the manufacturing method of the semiconductor device shown.

[0242] First, as shown in ​ An insulating layer 210 is formed on a substrate (not shown), and a conductive layer 220 is formed on the insulating layer 210. For example, by forming a first conductive film that becomes the conductive layer 220_1 and forming a second conductive film that becomes the conductive layer 220_2 on the first conductive film and processing the first conductive film and the second conductive film, a conductive layer 220 including the conductive layer 220_1 and the conductive layer 220_2 can be formed.

[0243] Next, as shown in ​ An insulating layer 280 is formed on the conductive layer 220 and the insulating layer 210. In addition, it is preferable to perform a planarization process after depositing the insulating layer 280 to planarize the top surface of the insulating layer 280. As the planarization process, a planarization process using a chemical mechanical polishing (CMP) method (also referred to as a CMP process) is preferred. By performing a planarization process on the insulating layer 280, the formed surfaces of the conductive layers 240a and 240b having regions used as wirings can be made flat, thereby suppressing disconnection of the conductive layers 240a and 240b. In addition, the planarization process may not be performed, and in this case, the manufacturing cost can be reduced.

[0244] It is preferable to perform a process of supplying oxygen after forming the insulating layer 280. Thus, oxygen is supplied to the insulating layer 280, and oxygen can be supplied from the insulating layer 280 to the oxide semiconductor layer 230 by heat applied after forming the oxide semiconductor layer 230.

[0245] As a treatment for supplying oxygen, for example, heat treatment in an oxygen-containing atmosphere, plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere, etc. can be cited. Alternatively, oxygen can be supplied to the insulating layer 280 by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film can be immediately removed or can remain. In the case where the deposited oxide film remains, the oxide film can be used as a part of the insulating layer 280. Note that as the oxygen-containing atmosphere, in addition to oxygen gas (O2), an atmosphere containing an oxygen-containing compound gas such as ozone (O3) or nitrous oxide (N2O) is also included. In addition, the substrate temperature during plasma treatment is 25°C or higher and 450°C or lower.

[0246] Next, as ​ shown, a conductive layer 240f is formed on the insulating layer 280. For example, by forming a first conductive film that becomes the conductive layer 240a1 and the conductive layer 240b1 and forming a second conductive film that becomes the conductive layer 240a2 and the conductive layer 240b2 on the first conductive film and processing the first conductive film and the second conductive film, a conductive layer 240f including a first conductive layer and a second conductive layer can be formed.

[0247] Next, as ​ shown, a groove portion 290 is formed in the conductive layer 240f and the insulating layer 280. The groove portion 290 is formed so as to expose at least a part of the top surface of the conductive layer 220. By forming the groove portion 290, the conductive layer 240a and the conductive layer 240b that are isolated from each other can be formed from the conductive layer 240f. At this time, it is preferable to provide a recess at a position where the conductive layer 220 overlaps with the groove portion 290. It is preferable to expose the bottom surface and the side surface of the recess of the conductive layer 220 by forming the groove portion 290.

[0248] In order to perform microfabrication and reduce the size of the transistor, it is preferable to use anisotropic etching to process a part of the conductive layer 220, a part of the insulating layer 280, and a part of the conductive layer 240f when forming the groove portion 290. In particular, processing using a dry etching method is suitable for microfabrication and is therefore preferable. In addition, the groove portion 290 can also be formed under processing conditions that vary according to each layer. In addition, depending on the materials and processing conditions of the conductive layer 220, the insulating layer 280, and the conductive layer 240f, the inclination angles of the side surfaces of the conductive layer 220, the insulating layer 280, and the conductive layer 240f in the groove portion 290 may be different.

[0249] In addition, depending on the formation process of the groove portion 290 or the like, a halogen-containing region may be provided on at least one of the bottom surface and side surfaces of the concave portion of the conductive layer 220, the side surfaces of the insulating layer 280, and the top surface and side surfaces of the conductive layer 240f. As such a region, for example, a fluorine-containing region, a chlorine-containing region, or a region containing fluorine and chlorine can be cited. For example, halogens derived from the etching gas used in dry etching may remain in this region.

[0250] Next, a heat treatment is preferably performed. As the heat treatment, for example, it can be carried out at 250°C or higher and 650°C or lower, preferably at 300°C or higher and 500°C or lower, and more preferably at 320°C or higher and 450°C or lower.

[0251] The heat treatment is carried out in an atmosphere of nitrogen gas or inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be carried out under a reduced pressure state. Alternatively, the heat treatment can be carried out in an atmosphere of nitrogen gas or inert gas, and then, in order to replenish the escaped oxygen, the heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 or the like can be reduced before the deposition of the oxide semiconductor layer 230 described later.

[0252] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the moisture content of the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture or the like from being absorbed by the insulating layer 280 or the like as much as possible.

[0253] Next, as ​ shown, an oxide semiconductor layer 230 is formed so as to cover the groove portion 290, the conductive layer 240a, the conductive layer 240b, and the insulating layer 280. The oxide semiconductor layer 230 is provided in contact with the bottom surface and side surfaces of the concave portion of the conductive layer 220, the side surfaces of the insulating layer 280, and the top surface and side surfaces of the conductive layer 240a and the conductive layer 240b.

[0254] Regarding the manufacturing method of the oxide semiconductor layer 230, reference can be made to the description of Embodiment 2.

[0255] In the present embodiment, a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film are sequentially formed as the oxide semiconductor layer 230. The first oxide semiconductor film is the one that becomes ​The oxide semiconductor film of the oxide semiconductor layer 230_1 shown, and this second oxide semiconductor film becomes ​ The oxide semiconductor film of the oxide semiconductor layer 230_2 shown, and this third oxide semiconductor film becomes ​ The oxide semiconductor film of the oxide semiconductor layer 230_3 shown.

[0256] For example, an In-Ga-Zn oxide film is deposited using thermal ALD as the first oxide semiconductor film, an indium oxide film is deposited using thermal ALD as the second oxide semiconductor film, and an In-Ga-Zn oxide film is deposited using sputtering as the third oxide semiconductor film.

[0257] Preferably, the first oxide semiconductor film and the second oxide semiconductor film are continuously deposited in a manner not exposed to the atmosphere. By continuously depositing the first oxide semiconductor film and the second oxide semiconductor film in a manner not exposed to the atmosphere, productivity can be improved. In addition, impurities (typically moisture, etc.) absorbed at the interface between the first oxide semiconductor film and the second oxide semiconductor film and in the vicinity thereof can be reduced.

[0258] In addition, a process of supplying oxygen to the second oxide semiconductor film can also be performed after depositing the second oxide semiconductor film. Thus, oxygen can be supplied to the oxide semiconductor layer 230 by heat or the like applied after this process. In addition, the details of the oxygen supply process can be referred to the above description.

[0259] Next, a heat treatment is preferably performed. The temperature of the heat treatment is preferably 100°C or higher and 650°C or lower, more preferably 250°C or higher and 600°C or lower, and further preferably 350°C or higher and 550°C or lower. The details of the heat treatment can be referred to the above description.

[0260] In addition, the gas used in the above heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being absorbed by the oxide semiconductor layer 230 as much as possible.

[0261] By performing the above heat treatment, impurities such as carbon, hydrogen, or water in the oxide semiconductor layer 230 can be reduced. Thus, by reducing the impurities in the film, the crystallinity of the oxide semiconductor layer 230 is improved and a denser structure with a higher density can be obtained. Therefore, the crystalline region in the oxide semiconductor layer 230 of the oxide film can be increased, and the in-plane non-uniformity of the crystalline region in the oxide semiconductor layer 230 can be reduced. Therefore, the in-plane non-uniformity of the electrical characteristics of the transistor can be reduced.

[0262] In addition, when the insulating layer 280 contains oxygen, it is preferable to supply oxygen from the oxygen-containing insulating film to the channel formation region of the oxide semiconductor layer 230 by the above-described heat treatment. Thereby, oxygen vacancies and V O H can be reduced.

[0263] Thus, sometimes excess oxygen is supplied from the insulating layer 280 in contact with the oxide semiconductor layer 230 to the oxide semiconductor layer 230. Since excess oxygen has a function of capturing electrons, negative charges are easily formed. Therefore, a transistor having normally-off characteristics can be realized by shifting the threshold voltage of the transistor in the positive direction.

[0264] In addition, microwave plasma treatment may be performed after depositing the second oxide semiconductor film or the third oxide semiconductor film. By performing this microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. In addition, sometimes the crystal region of the oxide semiconductor layer 230 grows. In addition, the details of the microwave plasma treatment will be described in Embodiment 2.

[0265] Next, as ​ shown, an insulating layer 250 is formed over the oxide semiconductor layer 230. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. In addition, the insulating layer 250 is formed in the groove portion 290 having a large aspect ratio. Therefore, it is preferable to deposit the insulating layer 250 by a deposition method with good coverage, and it is more preferable to deposit the insulating layer 250 by a CVD method or an ALD method or the like.

[0266] It is preferable to perform microwave plasma treatment after depositing the insulating layer 250. By performing this microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. In addition, sometimes the crystal region of the oxide semiconductor layer 230 grows.

[0267] In addition, when the insulating layer 250 has a four-layer structure including a fourth insulating layer, a third insulating layer over the fourth insulating layer, a first insulating layer over the third insulating layer, and a second insulating layer over the first insulating layer, microwave plasma treatment may be performed after depositing the third insulating layer. Furthermore, microwave plasma treatment may be performed again after depositing the first insulating layer. Thus, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice).

[0268] In addition, a treatment for supplying oxygen to the third insulating layer may be performed after depositing the third insulating layer. Thereby, oxygen can be supplied to the oxide semiconductor layer 230. In addition, the details of the treatment for supplying oxygen can be referred to the above description.

[0269] In the present embodiment, as the insulating layer 250, an alumina film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially deposited by an ALD method. In addition, a hafnium zirconium oxide film or the like may be deposited instead of the hafnium oxide film.

[0270] Next, as ​ shown, a sacrificial layer 262 is formed on the insulating layer 250. The sacrificial layer 262 is provided so as to overlap at least a part of the groove portion 290. As the sacrificial layer 262, an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are preferably used. The sacrificial layer 262 preferably has a two-layer structure of an SOC film and an SOG film on the SOC film, for example.

[0271] By providing the sacrificial layer 262 in contact with the insulating layer 250, compared with the case where the sacrificial layer 262 is provided in contact with the oxide semiconductor layer 230, damage to the oxide semiconductor layer 230 during the manufacturing process of the semiconductor device can be reduced, which is preferable. In the case where the insulating layer 250 has a stacked structure, a layer constituting a part of the insulating layer 250 may be formed before forming the sacrificial layer 262, and other parts of the layer may be formed after removing the sacrificial layer 262.

[0272] Next, as ​ shown, by using the sacrificial layer 262 as a mask for etching treatment, a part of the insulating layer 250 and a part of the oxide semiconductor layer 230 are removed. Thus, an island-shaped insulating layer 250 and an island-shaped oxide semiconductor layer 230 can be formed.

[0273] Preferably, the sacrificial layer 262 overlaps a relatively large part of the top surfaces of the conductive layer 240a and the conductive layer 240b. By performing the above etching treatment, the oxide semiconductor layer 230 in the region overlapping the sacrificial layer 262 remains. Therefore, by adopting this structure, the contact area between the oxide semiconductor layer 230 and the conductive layer 240a can be increased, and thus the contact resistance between the conductive layer 240a and the oxide semiconductor layer 230 can be reduced. Therefore, a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 240a and the oxide semiconductor layer 230 can be suppressed. In addition, the same applies to the conductive layer 240b and the oxide semiconductor layer 230.

[0274] In addition, the overlapping portion of the sacrificial layer 262 with the top surfaces of the conductive layer 240a and the conductive layer 240b can also be relatively small. Since the gate electrode (conductive layer 260) is provided in the region where the sacrificial layer 262 is provided in a subsequent process, by adopting such a structure, the distance between the conductive layer 240a and the conductive layer 260 provided in the subsequent process can be increased, and the parasitic capacitance generated between the conductive layer 240a and the gate electrode can be reduced. In addition, the same applies to the conductive layer 240b and the oxide semiconductor layer 230.

[0275] Note that by performing the above etching process, sometimes the thickness of the portion of the conductive layer 240a that does not overlap with the sacrificial layer 262 becomes thin (thinned). Or, sometimes the portion of the conductive layer 240a that does not overlap with the sacrificial layer 262 is removed. In addition, the same applies to the conductive layer 240b.

[0276] In addition, by performing the above etching process, sometimes the thickness of the portion of the insulating layer 280 that does not overlap with the conductive layer 240a and the conductive layer 240b becomes thin (thinned).

[0277] Next, as Figures 13A to 13E shown, an insulating layer 284 is formed to cover the conductive layer 220, the conductive layer 240a, the conductive layer 240b, the insulating layer 280, and the sacrificial layer 262, and an insulating layer 285 is formed on the insulating layer 284.

[0278] By increasing the thickness of the insulating layer 285, the distance between the conductive layer 240a or the conductive layer 240b and the conductive layer 265 provided in a subsequent process can be increased, and the parasitic capacitance generated between the conductive layer 240a or the conductive layer 240b and the gate electrode can be reduced.

[0279] For example, it is preferable to deposit a silicon oxide film as the insulating layer 285 by a sputtering method.

[0280] Here, when the silicon oxide film is formed as the insulating layer 285 by the sputtering method without providing the insulating layer 284, the sacrificial layer 262 is exposed to the plasma containing oxygen, so sometimes a part or all of the sacrificial layer 262 is etched. Thus, depending on the formation method of the insulating layer 285, there is a concern that the shape of the sacrificial layer 262 is reduced or the sacrificial layer 262 disappears. For the above reasons, the insulating layer formed on the sacrificial layer 262 preferably has a stacked structure of the insulating layer 284 and the insulating layer 285 rather than a single-layer structure of the insulating layer 285. Thereby, effects such as an expanded selection range of the materials of the sacrificial layer 262 and the insulating layer 285 and a reduced manufacturing difficulty of the semiconductor device are exhibited.

[0281] When an oxide film is used as the insulating layer 284, it is preferably formed by a method other than the sputtering method, such as the ALD method. For example, as the insulating layer 284, an aluminum oxide film or a hafnium oxide film is preferably formed by the ALD method. Alternatively, a nitride film (such as a silicon nitride film) is preferably used for the insulating layer 284. Thereby, it is possible to suppress the unintentional processing of the sacrificial layer 262 when forming the insulating layer 284 and the insulating layer 285.

[0282] In addition, the insulating layer 284 is preferably formed by the CVD method or the ALD method, and more preferably by the ALD method. Thereby, the insulating layer 284 can also be provided with high coverage on the side surface of the sacrificial layer 262 or the like.

[0283] Next, as Figures 14A to 14E shown, by performing a planarization process, the top surface of the sacrificial layer 262 is exposed, and the top surfaces of the sacrificial layer 262, the insulating layer 284, and the insulating layer 285 are planarized. As the planarization process, the CMP process is preferably used. In the planarization process, at least a part of the insulating layer 284 and the insulating layer 285 is removed. Furthermore, a part of the sacrificial layer 262 may also be removed.

[0284] Next, as Figures 14A to 14E shown, the sacrificial layer 262 is removed. There is no particular limitation on the method for removing the sacrificial layer 262. For example, the sacrificial layer 262 can be removed by dry etching. It can be said that by removing the sacrificial layer 262, the insulating layer 284 has an opening 270 at a position overlapping the groove portion 290 and the insulating layer 250.

[0285] Next, as Figures 15A to 15E shown, a conductive layer 260 is formed on the insulating layer 250. The conductive layer 260 is preferably provided so as to be embedded in the groove portion 290 and the opening 270.

[0286] The conductive layer 260 is formed in the groove portion 290 having a large aspect ratio. Therefore, it is preferable to deposit the conductive layer 260 by a deposition method with good coverage, and more preferably to deposit the conductive layer 260 by the CVD method or the ALD method or the like.

[0287] Next, a conductive layer 265 is formed on the conductive layer 260, the insulating layer 284, and the insulating layer 285.

[0288] As described above, it is possible to manufacture Figure 1A1 , Figure 1A2 , Figures 1B to 1E shown semiconductor device.

[0289] As described above, by using the sacrificial layer 262 as a mask for etching, the thickness of the portion of the conductive layer 240a that does not overlap with the sacrificial layer 262 sometimes becomes thinner (thinned). Figure 16A Shows the semiconductor device manufactured at this time. In Figure 16AIn the structure shown, the contact area between the conductive layer 240a and the oxide semiconductor layer 230 and the contact area between the conductive layer 240b and the oxide semiconductor layer 230 do not decrease either.

[0290] In addition, Figure 16B A semiconductor device is shown which is manufactured by using the sacrificial layer 262 as a mask for an etching process to remove the portion of the conductive layer 240a that does not overlap with the sacrificial layer 262. In Figure 16B In the structure shown, the contact area between the conductive layer 240a and the oxide semiconductor layer 230 and the contact area between the conductive layer 240b and the oxide semiconductor layer 230 do not decrease either.

[0291] In addition, in the example of the manufacturing method of the above semiconductor device, the sacrificial layer 262 is formed on the insulating layer 250, but the present invention is not limited thereto. For example, the sacrificial layer 262 can be formed before forming the insulating layer 250 and the insulating layer 250 can be formed after removing the sacrificial layer 262 (refer to Figures 14A to 14E ) to manufacture a semiconductor device. In other words, the sacrificial layer 262 can be formed on the oxide semiconductor layer 230 to manufacture a semiconductor device.

[0292] Refer to Figures 17A to 17D to describe other structures of a semiconductor device according to one aspect of the present invention. Figure 17A is a plan view of a semiconductor device including a transistor. Figure 17B is a cross-sectional view along Figure 17A the dotted line A1 - A2 shown. Figure 17C is a cross-sectional view along Figure 17A the dotted line B1 - B2 shown. Figure 17D shows a cross-sectional view along Figure 17B the dotted line C1 - C2 shown. Regarding the cross-sectional view along Figure 17A the dotted line A3 - A4 shown, reference can be made to Figure 1C , and regarding the cross-sectional view along Figure 17A the dotted line B3 - B4 shown, reference can be made to Figure 1E .

[0293] Figures 17A to 17C The semiconductor device shown includes: an insulating layer 210 on a substrate (not shown); a transistor 200 on the insulating layer 210; an insulating layer 280 on the insulating layer 210; an insulating layer 284 on the insulating layer 280; an insulating layer 285 on the insulating layer 284; and a conductive layer 265 on the insulating layer 284.

[0294] Figures 17A to 17CThe transistor 200 shown includes: a conductive layer 220 on an insulating layer 210; a conductive layer 240a and a conductive layer 240b on an insulating layer 280; an oxide semiconductor layer 230 on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b; an insulating layer 250 on the oxide semiconductor layer 230; and a conductive layer 260 on the insulating layer 250.

[0295] Figures 17A to 17C The semiconductor device shown and Figure 1A1 , Figure 1A2 , Figures 1B to 1E The semiconductor device shown are different in that: in Figures 17A to 17C the semiconductor device shown, the insulating layer 250 includes a portion in contact with the conductive layer 265, etc.

[0296] In Figures 17A to 17C the transistor 200 shown, the stacked structure of the conductive layer 220 to the oxide semiconductor layer 230 is the same as that of the above transistor 200, so detailed description is omitted.

[0297] The insulating layer 250 contacts the oxide semiconductor layer 230 and the insulating layer 284 within the opening 270. The insulating layer 250 has a region in contact with at least a part of the bottom surface of the conductive layer 265. In addition, the portion of the insulating layer 250 disposed within the opening 270 reflects the shape of the opening 270. Specifically, the insulating layer 250 is disposed so as to cover the side surface (the side surface of the insulating layer 284) of the opening 270. In addition, the conductive layer 260 is disposed so as to embed at least a part of the concave portion of the insulating layer 250 reflecting the shape of the opening 270.

[0298] In Figures 17A to 17C the transistor 200 shown, the insulating layer 250 is located between the insulating layer 284 and the conductive layer 260 within the opening 270, whereby the overlapping area of the conductive layer 240a and the conductive layer 260 becomes smaller when viewed from a plane. Therefore, compared with Figure 1A1 , Figure 1A2 , Figures 1B to 1E the transistor 200 shown, the physical distance between the conductive layer 240a and the conductive layer 260 can be increased. Thereby, the parasitic capacitance generated between the conductive layer 240a and the conductive layer 260 can be reduced. In addition, the same applies to the conductive layer 240b and the conductive layer 260.

[0299] That is to say, Figures 17A to 17C the transistor 200 shown has a structure in which the parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate electrode and the parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring are reduced. Therefore, the frequency characteristics of the circuit using this transistor can be improved.

[0300] AsFigure 17D As shown, within the groove portion 290, the conductive layer 260 is surrounded by the insulating layer 250. That is to say, the conductive layer 260 does not come into contact with the insulating layer 284. Therefore, in the case where the insulating layer 284 is an oxide insulating layer, oxidation of the conductive layer 260 by the insulating layer 284 can be suppressed, thereby suppressing an increase in resistance.

[0301] In addition, in the case where the conductive layer 260 has a two-layer structure including the conductive layer 260_1 and the conductive layer 260_2, a sacrificial layer 262 can also be formed on the conductive layer 260_1 and, after removing the sacrificial layer 262 (refer to Figures 14A to 14E ), the conductive layer 260_2 can be formed to manufacture a semiconductor device.

[0302] In addition, in the example of the manufacturing method of the above semiconductor device, the oxide semiconductor layer 230 is formed after the groove portion 290 is formed, but the present invention is not limited thereto. For example, a semiconductor device can be manufactured by forming the insulating layer 225 before forming the oxide semiconductor layer 230.

[0303] Refer to Figures 18A to 18E to describe other structures of the semiconductor device according to one aspect of the present invention. Figure 18A is a plan view of a semiconductor device including a transistor. Figure 18B is a cross-sectional view along the Figure 18A indicated dash-dotted line A1 - A2. Figure 18C is a cross-sectional view along the Figure 18A indicated dash-dotted line A3 - A4. Regarding the cross-sectional view along the Figure 18A indicated dash-dotted line B1 - B2, reference can be made to Figure 1D , and regarding the cross-sectional view along the Figure 18A indicated dash-dotted line B3 - B4, reference can be made to Figure 1E .

[0304] In addition, Figure 18D shows a cross-sectional view along the Figure 18B indicated dash-dotted line C1 - C2, Figure 18E shows a cross-sectional view of the XY plane including the conductive layer 240a2.

[0305] Figures 18A to 18C The semiconductor device shown in

[0306] Figures 18A to 18CThe transistor 200 shown includes: a conductive layer 220 on an insulating layer 210; a conductive layer 240a and a conductive layer 240b on an insulating layer 280; an insulating layer 225; an oxide semiconductor layer 230 on the conductive layer 220, the insulating layer 225, the conductive layer 240a, and the conductive layer 240b; an insulating layer 250 on the oxide semiconductor layer 230; and a conductive layer 260 on the insulating layer 250.

[0307] Figures 18A to 18C The semiconductor device shown and Figure 1A1 , Figure 1A2 , Figures 1B to 1E The semiconductor device shown are different in that: in the semiconductor device shown, an insulating layer 225 is included in the groove portion 290. Figures 18A to 18C In the semiconductor device shown, an insulating layer 225 is included in the groove portion 290.

[0308] In Figures 18A to 18C In the transistor 200 shown, the stacked structure of the conductive layer 220 to the conductive layer 240 and the stacked structure of the oxide semiconductor layer 230 to the conductive layer 260 are the same as those of the above-mentioned transistor 200, so the detailed description is omitted.

[0309] The insulating layer 225 is provided along at least a part of the side surface of the groove portion 290. In Figures 18B to 18E , the insulating layer 225 is provided so as to cover the side surface of the groove portion 290. Specifically, the insulating layer 225 has a region in contact with the side surface of the insulating layer 280 in the groove portion 290. In addition, the insulating layer 225 has a region in contact with the side surface of the conductive layer 240a on the side of the groove portion 290, a region in contact with the side surface of the conductive layer 240b on the side of the groove portion 290, and a region in contact with the conductive layer 220. The insulating layer 225 may also be referred to as a sidewall, a sidewall insulating layer, a side surface protection layer, etc.

[0310] The insulating layer 225 may use an insulating material that can be used for the insulating layer 250.

[0311] As described above, in the channel formation region in the oxide semiconductor layer, it is preferable to minimize oxygen vacancies and impurities. In particular, in the channel formation region in the oxide semiconductor layer, it is preferable to minimize hydrogen.

[0312] Then, as the insulating layer 225 provided outside the oxide semiconductor layer 230, it is preferable to use a hydrogen barrier insulating layer. Thereby, hydrogen diffusion into the oxide semiconductor layer 230 can be suppressed, thereby improving the reliability of the transistor 200. For example, as the insulating layer 225, it is preferable to use a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, and more preferably a silicon nitride film.

[0313] In addition, the silicon nitride film also has oxygen barrier properties. Therefore, by using the silicon nitride film for the insulating layer 225, it is possible to suppress the formation of oxygen vacancies in the oxide semiconductor layer 230 due to oxygen being extracted from the oxide semiconductor layer 230. In addition, by using the silicon nitride film for the insulating layer 225, it is possible to prevent excessive oxygen from being supplied to the oxide semiconductor layer 230. Therefore, oxygen excess in the channel formation region of the oxide semiconductor layer 230 can be prevented, so the reliability of the transistor 200 can be improved. In addition, the insulating layer 225 sometimes contacts the side surface of the conductive layer 240a in the groove portion 290. At this time, by using the silicon nitride film for the insulating layer 225, it is possible to suppress the formation of an oxide film on the side surface due to oxidation of the side surface of the conductive layer 240a in the groove portion 290. Therefore, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200 can be suppressed.

[0314] The silicon nitride film included in the insulating layer 225 is preferably formed by the PEALD method. Thereby, the coverage of the insulating layer 225 on the side surface of the groove portion 290 can be improved, and thus an insulating layer 225 with a uniform thickness can be formed.

[0315] Figure 18B An example in which the insulating layer 225 has a single-layer structure is shown. In addition, the insulating layer 225 can have a laminated structure of two or more layers.

[0316] In addition, as Figure 19 shown, the conductive layer 220_2 preferably includes a first recess and a second recess located outside the first recess. The depth of the first recess is deeper than that of the second recess. In other words, the bottom surface of the first recess is located below the bottom surface of the second recess (on the side of the insulating layer 210). When forming the groove portion 290, the second recess is provided in the conductive layer 220_2, and then, when processing the insulating layer 225, the first recess is provided in the conductive layer 220_2. Therefore, in Figure 19 the side surface of the second recess is aligned with the side surface of the insulating layer 280 in the groove portion 290, and the side surface of the first recess is aligned with the side surface on the oxide semiconductor layer 230 side of the insulating layer 225. Hereinafter, the first recess and the second recess are sometimes collectively referred to as recesses.

[0317] In Figure 19 the insulating layer 225 contacts the bottom surface and the side surface of the recess (specifically, the second recess) of the conductive layer 220, and contacts the side surface of the insulating layer 280, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b in the groove portion 290. The oxide semiconductor layer 230 contacts the bottom surface and the side surface of the recess (specifically, the first recess) of the conductive layer 220 and the side surface of the insulating layer 225 in the groove portion 290. The insulating layer 250 is located inside the oxide semiconductor layer 230 in the groove portion 290, and the conductive layer 260 is located inside the insulating layer 250 in the groove portion 290.

[0318] The conductive layer 220_2 has a first concave portion and a second concave portion, and the side surface of the conductive layer 220_2 is in contact with the oxide semiconductor layer 230. Thus, the contact area between the conductive layer 220_2 and the oxide semiconductor layer 230 can be increased, and accordingly, the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be reduced. Therefore, a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed.

[0319] In addition, in the example of the method for manufacturing the semiconductor device described above, the groove portion 290 is formed after the conductive layer 240f is formed, but the present invention is not limited thereto. For example, the semiconductor device can be manufactured by forming the groove portion 290 after the first conductive film and the second conductive film that will become the conductive layer 240f are formed.

[0320] Refer to Figures 20A to 20C to describe other structures of the semiconductor device according to one aspect of the present invention. Figure 20A is a plan view of a semiconductor device including a transistor. In addition, Figure 20A is a plan view showing a region including two transistors adjacent to each other in the X direction. Figure 20B is along Figure 20A the cross-sectional view taken along the dotted line A1 - A2 shown. Figure 20C is along Figure 20A the cross-sectional view taken along the dotted line A3 - A4 shown. Regarding the cross-sectional view taken along Figure 20A the dotted line B1 - B2 shown, reference can be made to Figure 1D and regarding the cross-sectional view taken along Figure 20A the dotted line B3 - B4 shown, reference can be made to Figure 1E .

[0321] Figures 20A to 20C The semiconductor device shown includes: an insulating layer 210 on a substrate (not shown); transistors 200[1] and 200[2] on the insulating layer 210; an insulating layer 280 on the insulating layer 210; an insulating layer 284 on the insulating layer 280; an insulating layer 285 on the insulating layer 284; and a conductive layer 265 on the insulating layer 284. The transistors 200[1] and 200[2] are adjacent to each other in the X direction.

[0322] The transistor 200[1] includes: a conductive layer 220[1] on the insulating layer 210; conductive layers 240[1] and 240[2] on the insulating layer 280; an oxide semiconductor layer 230 on the conductive layer 220[1], the conductive layer 240[1], and the conductive layer 240[2]; an insulating layer 250 on the oxide semiconductor layer 230; and a conductive layer 260 on the insulating layer 250.

[0323] The transistor 200[2] includes: a conductive layer 220[2] on an insulating layer 210; conductive layers 240[2] and 240[3] on an insulating layer 280; an oxide semiconductor layer 230 on the conductive layers 220[2], 240[2], and 240[3]; an insulating layer 250 on the oxide semiconductor layer 230; and a conductive layer 260 on the insulating layer 250.

[0324] Figures 20A to 20C The semiconductor device shown and Figure 1A1 , Figure 1A2 , Figures 1B to 1E The semiconductor device shown is different in that: in the semiconductor device shown in Figures 20A to 20C , adjacent transistors 200 in the X direction share the conductive layer 240. Specifically, transistor 200[1] and transistor 200[2] share the conductive layer 240[2]. By having adjacent transistors 200 in the X direction share the conductive layer 240, the occupied area of the semiconductor device can be reduced.

[0325] Regarding the materials, structures, etc. that can be used for the conductive layer 220[1] and the conductive layer 220[2], reference can be made to the description of the conductive layer 220 above. Regarding the materials, structures, etc. that can be used for the conductive layers 240[1] to 240[3], reference can be made to the description of the conductive layer 240 above.

[0326] <Structural Example 2 of Semiconductor Device> Hereinafter, with reference to Figure 21A1 , Figure 21A2 , Figures 21B to 22B A structural example of a semiconductor device whose partial components are different from those of the semiconductor device shown in <Structural Example 1 of Semiconductor Device> will be described. Note that the description of the parts that are the same as those above is omitted, and only the differences will be described in detail. In addition, even if the positions or shapes of the components are different, the same reference numerals may be added when their functions are the same, and the description may be omitted.

[0327] Figure 21A1 is a plan view of a semiconductor device including transistors. Figure 21A2 is a plan view showing an example of arranging a plurality of transistors. Figure 21B is a cross-sectional view along the Figure 21A1 indicated dash-dotted line A1 - A2. Figure 21C is a cross-sectional view along the Figure 21A1 indicated dash-dotted line A3 - A4. Figure 21D is a cross-sectional view along the Figure 21A1 indicated dash-dotted line B1 - B2. Figure 21E is a cross-sectional view along the Figure 21A1 indicated dash-dotted line B3 - B4. Note that in Figure 21A1 and Figure 21A2In the plan view, some constituent elements are omitted for clarity.

[0328] Figures 21A1 to 21E The semiconductor device shown includes: an insulating layer 210 on a substrate (not shown); a transistor 200A on the insulating layer 210; an insulating layer 280 on the insulating layer 210; an insulating layer 284 on the insulating layer 280; an insulating layer 285 on the insulating layer 284; and a conductive layer 265 on the transistor 200A, the insulating layer 284, and the insulating layer 285.

[0329] [Transistor 200A] Transistor 200A includes: a conductive layer 240a and a conductive layer 240b on the insulating layer 280; an oxide semiconductor layer 230 on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b; an insulating layer 250 on the oxide semiconductor layer 230; and a conductive layer 260 on the insulating layer 250.

[0330] Figures 21A1 to 21E The transistor 200A shown and Figure 1A1 , Figure 1A2 , Figures 1B to 1E The transistor 200 shown are different in that: Figures 21A1 to 21E The transistor 200A shown does not include the conductive layer 220.

[0331] In transistor 200A, the oxide semiconductor layer 230 is used as the semiconductor layer, the conductive layer 260 is used as the gate electrode, the insulating layer 250 is used as the gate insulating layer, the conductive layer 240a is used as one of the source electrode and the drain electrode, and the conductive layer 240b is used as the other of the source electrode and the drain electrode.

[0332] The oxide semiconductor layer 230 is used as the channel formation region of the transistor 200A in the region where it faces the conductive layer 260 across the insulating layer 250 within the groove portion 290 and in its vicinity. The region of the oxide semiconductor layer 230 near the conductive layer 240a is used as one of the source region and the drain region, and the region of the oxide semiconductor layer 230 near the conductive layer 240b is used as the other of the source region and the drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0333] Here, Figure 22A Shows a cross-sectional view along Figure 21B The dotted line A1 - A2 shown. Figure 22A Corresponds to Figure 21B An example of an enlarged view.

[0334] As Figure 22AAs shown, the channel length of the transistor 200A is the distance between the source region and the drain region. For example, the channel length of the transistor 200A can be regarded as the sum of the height of the side on the conductive layer 240a side of the groove portion 290, the width of the bottom, and the height of the side on the conductive layer 240b side. That is to say, the channel length of the transistor 200A is determined according to the depth of the groove portion of the insulating layer 280. In Figure 22A the channel length L of the transistor 200A is represented by a double-headed arrow in dashed lines.

[0335] Compared with a planar transistor, in the transistor 200A, the deeper the depth of the groove portion 290, the more the channel length can be extended. That is to say, the channel length can be extended without changing the occupied area of the transistor 200A. By extending the channel length of the transistor, the non-uniformity of the threshold voltage of the transistor can be reduced.

[0336] In addition, in the case of manufacturing the transistor 200A whose channel length is equal to that of the vertical transistor, compared with the vertical transistor, the depth of the groove portion of the insulating layer 280 can be reduced. In other words, the depth of the groove portion 290 can be shallower. Therefore, compared with the transistor 200, the micro groove portion 290 can be formed with a high yield.

[0337] The channel width of the transistor 200A is the same as or approximately the same as the length in the Y direction of the oxide semiconductor layer 230 ( Figure 3B the length H230 shown). In addition, it can be said that the channel width of the transistor 200A is the same as or approximately the same as the width in the Y direction of the conductive layer 260 or the width in the Y direction of the insulating layer 250.

[0338] In addition, the same structure as that of the transistor 200 can also be applied to the transistor 200A. For example, as Figure 22B shown, the transistors 200A adjacent in the X direction can share the conductive layer 240. Specifically, the transistors 200A[1] and 200A[2] adjacent in the X direction share the conductive layer 240[2]. Thereby, the occupied area of the semiconductor device can be reduced.

[0339] The above description includes an example of the structure of a semiconductor device including the transistor 200A.

[0340] In the semiconductor device shown in the above <Example of the structure of a semiconductor device 1>, one transistor is provided in the region where one groove portion 290 overlaps with the gate wiring. Note that the present invention is not limited to this. For example, the semiconductor device may include two transistors in the region where the groove portion 290 overlaps with the gate wiring.

[0341] <Example of the structure of a semiconductor device 3> Hereinafter, with reference to Figures 23A to 26CAn example of the structure of a semiconductor device in which some of its constituent elements are different from those of the semiconductor device shown in <Example 1 of the structure of a semiconductor device>. Note that the description of the parts that are the same as the above is omitted, and only the differences are described in detail. In addition, even if the positions or shapes of the constituent elements are different, the same reference numerals may be attached when their functions are the same, and the description may be omitted.

[0342] Figure 23A is a plan view of a semiconductor device including two transistors. Figure 23B is along Figure 23A the sectional view taken along the dash-dotted line A1 - A2 shown. Figure 23C is along Figure 23A the sectional view taken along the dash-dotted line A3 - A4 shown.

[0343] Figure 24 is Figures 23A to 23C a perspective schematic view of the semiconductor device shown. Specifically, Figure 24 is a perspective schematic view of a semiconductor device including four transistors. In addition, regarding Figure the constituent elements (interlayer insulating layers, etc.) in, only the outlines indicated by the dashed lines are shown.

[0344] ​ The semiconductor device shown in

[0345] ​ includes: an insulating layer 210 on a substrate (not shown); transistors 200Ba and 200Bb on the insulating layer 210; an insulating layer 280 on the insulating layer 210; an insulating layer 284 on the insulating layer 280; an insulating layer 285 on the insulating layer 284; and a conductive layer 265 on the transistors 200Ba, transistors 200Bb, insulating layer 284, and insulating layer 285. In addition, hereinafter, the transistors 200Ba and 200Bb may be collectively referred to as the transistor 200B.

[0345] ​ The semiconductor device shown in ​ 、 ​ 、 ​ is different from the semiconductor devices shown in ​ in that, in the semiconductor device shown in ​ the region where the conductive layer 265 overlaps with the groove portion 290 includes the transistors 200Ba and 200Bb.

[0346] [Transistor 200B] The transistor 200Ba includes: a conductive layer 220a on an insulating layer 210; a conductive layer 240a on an insulating layer 280; an oxide semiconductor layer 230a on the conductive layer 220a and the conductive layer 240a; an insulating layer 250a on the oxide semiconductor layer 230a; and a conductive layer 260a on the insulating layer 250a. The insulating layer 284 has an opening 270a reaching the insulating layer 250a at a position overlapping with the groove portion 290. The conductive layer 260a is arranged such that at least a part thereof is located within the opening 270a.

[0347] Similarly, the transistor 200Bb includes: a conductive layer 220b on an insulating layer 210; a conductive layer 240b on an insulating layer 280; an oxide semiconductor layer 230b on the conductive layer 220b and the conductive layer 240b; an insulating layer 250b on the oxide semiconductor layer 230b; and a conductive layer 260b on the insulating layer 250b. The insulating layer 284 has an opening 270b reaching the insulating layer 250b at a position overlapping with the groove portion 290. The conductive layer 260b is arranged such that at least a part thereof is located within the opening 270b.

[0348] When viewed in plan, the transistors 200Ba and 200Bb have an axially symmetric structure with the perpendicular bisector of the dotted line A1 - A2 as the axis of symmetry. Therefore, regarding the structure of the transistor 200Bb, the description of the structure of the transistor २००Ba can be referred to by appropriately replacing the transistor 200Ba, the conductive layer 220a, the conductive layer 240a, the oxide semiconductor layer 230a, the insulating layer 250a, and the conductive layer 260a with the transistor 200Bb, the conductive layer 220b, the conductive layer 240b, the oxide semiconductor layer 230b, the insulating layer 250b, and the conductive layer 260b, respectively. Hereinafter, the transistor 200Ba will be mainly described.

[0349] In the transistor 200Ba, the oxide semiconductor layer 230a is used as a semiconductor layer, the conductive layer 260a is used as a gate electrode, the insulating layer 250a is used as a gate insulating layer, the conductive layer 220a is used as one of a source electrode and a drain electrode, and the conductive layer 240a is used as the other of the source electrode and the drain electrode. The conductive layer 265 has a region used as a gate wiring.

[0350] Here, ​ shows a cross-sectional view along ​ the dotted line C1 - C2 shown. In addition, ​ is a cross-sectional view of the XY plane including the conductive layer 240a2.

[0351] As ​ and ​As shown, the insulating layer 284 is provided in contact with the side surface of the oxide semiconductor layer 230a inside the groove portion 290. By using an insulating layer having a function of capturing or fixing hydrogen as the insulating layer 284, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230a can be suppressed, and hydrogen contained in the oxide semiconductor layer 230a can be captured or fixed. Therefore, the hydrogen concentration of the oxide semiconductor layer 230a can be reduced.

[0352] By providing two transistors in a region where the groove portion 290 overlaps with the conductive layer 265, the occupied area of the semiconductor device can be reduced, and thus miniaturization or high integration of the semiconductor device can be achieved.

[0353] The transistor 200Ba and the transistor 200Bb can be formed, for example, by providing two sacrificial layers 262 in a region where the conductive layer 265 is disposed in the groove portion 290 in a manner isolated from each other.

[0354] In addition, a structure similar to at least one of the transistor 200 and the transistor 200A can also be applied to the transistor 200B. For example, as ​ shown, the transistors 200Ba and 200Bb adjacent to each other in the X direction can share the conductive layer 240. Specifically, the transistor 200Bb[1] and the transistor 200Ba[2] share the conductive layer 240[2]. Thereby, the occupied area of the semiconductor device can be reduced. Note that at least a part of each component of the transistor 200Ba[1] and the transistor 200Bb[1] is disposed inside the groove portion 290[1], and at least a part of each component of the transistor 200Ba[2] and the transistor 200Bb[2] is disposed inside the groove portion 290[2].

[0355] Note that ​ shows a structure in which the transistor 200Bb[1] and the transistor 200Ba[2] are connected to the same conductive layer 265, but the present invention is not limited thereto. For example, the transistor 200Bb[1] and the transistor 200Ba[2] can be respectively connected to different conductive layers 265.

[0356] In addition, ​ shows a structure in which the oxide semiconductor layer 230a and the oxide semiconductor layer 230b adjacent to each other in the X direction in one groove portion 290 face each other with the insulating layer 285 interposed therebetween, but the present invention is not limited thereto.

[0357] For example, as ​As shown, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b located in a groove portion 290 may also be arranged offset in the Y direction or alternately. Specifically, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b may be arranged so as not to face each other when viewed from the plane. By adopting such a structure, the width of the groove portion 290 in the X direction can be reduced, and thus miniaturization or high integration of the semiconductor device can be achieved. ​ shows a structure in which the width of the groove portion 290 in the X direction is smaller than that of the structure shown. ​ compared with the structure shown.

[0358] In addition, as ​ shown, the conductive layer 260a, the insulating layer 250a, and the oxide semiconductor layer 230a may also be formed such that each side surface when viewed from the plane is inclined to the X direction. By adopting such a structure, the width of the groove portion 290 in the X direction can be reduced, and sometimes miniaturization and high integration of the semiconductor device can be achieved. Alternatively, by adopting ​ the structure shown, a structure in which foreign matters such as dust and fine particles generated during the manufacturing process can be easily discharged from the groove portion 290 through the cleaning process can be achieved. Therefore, a semiconductor device with a high yield can be provided.

[0359] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when a plurality of structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0360] Embodiment 2 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. As an oxide semiconductor layer according to one aspect of the present invention, a single layer or a stacked layer including a layer containing a metal oxide can be used. Note that in an oxide semiconductor layer having a stacked structure, as described later, it is sometimes difficult to confirm the boundary between the stacked films.

[0361] [Metal oxide] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Further, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components, and may also contain element M. Note that element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, a metal element and a metalloid element may be collectively referred to as a "metal element", and the "metal element" described in this specification and the like may include a metalloid element.

[0362] As the metal oxide according to one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide, also denoted as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also denoted as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. may be used. Alternatively, gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. may be used. Further, indium oxide may be used as the metal oxide according to one embodiment of the present invention. Further, gallium oxide, zinc oxide, etc. may be used as the metal oxide according to one embodiment of the present invention.

[0363] By increasing the indium content rate of the metal oxide, a transistor can obtain a large on-state current and high-frequency characteristics.

[0364] Note that the metal oxide may also contain one or more metal elements with a large period number in the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in the periodic table in addition to indium. There is a tendency that the larger the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metal elements with a large period number in the periodic table, the field-effect mobility of the transistor can sometimes be improved. As the metal elements with a large period number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited, etc. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium can be cited, etc. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0365] In addition, the metal oxide may also contain one or more non-metal elements. When the metal oxide contains non-metal elements, the field-effect mobility of the transistor can sometimes be improved. As the non-metal element, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen can be cited, etc.

[0366] In addition, by increasing the zinc content rate of the metal oxide, the metal oxide has high crystallinity, so that the diffusion of impurities in the metal oxide can be suppressed. Thereby, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0367] In addition, by increasing the content rate of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, and thereby a transistor with a small off-state current can be realized. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0368] An example of the structure of the oxide semiconductor layer that can improve the field-effect mobility of the transistor will be described. For example, indium oxide or a stacked structure of indium oxide and IGZO is preferably adopted. Specifically, the oxide semiconductor layer preferably contains indium oxide and IGZO on the indium oxide. In addition, as the oxide semiconductor layer, IGZO containing nitrogen is preferably used. For example, by performing N2O plasma treatment during or after deposition, IGZO containing nitrogen can be formed. In addition, as the oxide semiconductor layer, at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO is preferably used.

[0369] In the present embodiment, sometimes In-M-Zn oxide is taken as an example of the metal oxide for description.

[0370] One embodiment of the present invention preferably includes a metal oxide having crystallinity in the oxide semiconductor layer. Examples of the structure of the metal oxide having crystallinity include a CAAC (c-axis aligned crystalline) structure, a polycrystalline structure, and a nano-crystalline (nc) structure. By using a metal oxide having crystallinity in the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor using the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device equipped with the transistor can be improved.

[0371] Note that there is no particular limitation on the crystallinity of the metal oxide included in the oxide semiconductor layer. For example, the oxide semiconductor layer sometimes includes one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor in which a part thereof has a crystalline region). When the oxide semiconductor layer has crystallinity, deterioration of the transistor characteristics can sometimes be suppressed.

[0372] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, it is also possible to analyze by combining a plurality of the above methods.

[0373] One embodiment of the present invention preferably includes a metal oxide having a CAAC structure in the oxide semiconductor layer. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and the plurality of microcrystals are not oriented and connected on the a-b plane. In addition, when observing a cross section of the oxide semiconductor layer having a CAAC structure using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in layers in the crystalline part. Therefore, it can also be said that the oxide semiconductor layer having a CAAC structure has a layered crystalline part.

[0374] The CAAC structure is formed, for example, such that the c-axis is perpendicular or substantially perpendicular to the formation surface or the surface of the oxide semiconductor layer. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the formation surface. In a region having the CAAC structure, the angle of the c-axis with respect to the formation surface is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), still more preferably within 90° ± 10° (80° or more and 100° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0375] When the oxide semiconductor layer has the CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross-section of the oxide semiconductor layer observed using a TEM image. Specifically, it is observed that the bright spots are arranged in layers in a direction parallel or substantially parallel to the formation surface.

[0376] When performing electron diffraction on an oxide semiconductor layer having the CAAC structure, spots (bright spots) indicating the c-axis orientation are observed in the electron diffraction pattern.

[0377] In addition, the FFT pattern obtained by performing a fast Fourier transform (FFT) process on the TEM image reflects the same reciprocal space information as the electron diffraction pattern.

[0378] A cross-sectional TEM image of an oxide semiconductor layer having the CAAC structure is obtained, and an FFT pattern is formed by performing FFT processing on each region in the cross-sectional TEM image. The direction of the crystal axis of each region can be calculated based on the produced FFT pattern. Specifically, in the spots observed in the produced FFT pattern, the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center is the crystal axis direction. The angle of the crystal axis direction of each region calculated based on the FFT pattern with respect to the formation surface is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), still more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) regions are regarded as the CAAC structure.

[0379] When observing an oxide semiconductor layer having the CAAC structure from a direction perpendicular to the formation surface using a TEM image, a triangular or hexagonal atomic arrangement is observed on the a-b plane and shows crystallinity.

[0380] [Composition of Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content rate. By using a metal oxide with a high In content rate as the oxide semiconductor layer, the on-state current of the transistor can be increased, thereby improving the frequency characteristics. For example, indium oxide is preferably used as the oxide semiconductor layer.

[0381] In addition, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, the metal oxide is a highly crystalline metal oxide, such as a metal oxide having a CAAC structure. For example, an In-Zn oxide can be used as the oxide semiconductor layer. Specifically, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or around it, In:Zn = 2:1 [atomic ratio] or around it, or In:Zn = 4:1 [atomic ratio] or around it can be used. Note that the composition around it includes a range of ±30% of the desired atomic ratio.

[0382] In addition, the metal oxide according to one embodiment of the present invention may contain element M. When the metal oxide contains element M, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of the transistor using the oxide semiconductor layer can be improved.

[0383] For example, an In-Zn oxide containing a trace amount of element M can be used as the oxide semiconductor layer. Specifically, a metal oxide having a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or around it, In:Ga:Zn = 2:0.1:1 [atomic ratio] or around it, or In:Ga:Zn = 1:0.1:1 [atomic ratio] or around it can be used. In addition, a metal oxide having a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or around it, In:Sn:Zn = 2:0.1:1 [atomic ratio] or around it, or In:Sn:Zn = 1:0.1:1 [atomic ratio] or around it can be used.

[0384] In addition, as the oxide semiconductor layer, an In-Zn oxide containing element M can be used. Specifically, an In:M:Zn = 1:1:1 [atomic ratio] or a composition near it, an In:M:Zn = 1:1:1.2 [atomic ratio] or a composition near it, an In:M:Zn = 1:1:0.5 [atomic ratio] or a composition near it, an In:M:Zn = 1:1:2 [atomic ratio] or a composition near it, an In:M:Zn = 4:2:3 [atomic ratio] or a composition near it, an In:M:Zn = 1:3:2 [atomic ratio] or a composition near it, or an In:M:Zn = 1:3:4 [atomic ratio] or a composition near it can be used as the metal oxide.

[0385] Note that in the case of forming a metal oxide by a sputtering method, the composition of the formed metal oxide is sometimes different from that of the sputtering target. In particular, the zinc content rate of the formed metal oxide sometimes decreases to about 50% of the zinc content rate of the sputtering target.

[0386] In addition, in the case of depositing a metal oxide containing multiple metal elements such as In-Ga-Zn oxide by an ALD method, the ratio of the number of cycles of the precursors containing each metal element can be set according to the target composition. For example, when depositing an In-Ga-Zn oxide with an In:Ga:Zn = 1:3:2 [atomic ratio], the cycle of depositing the precursor containing In and the treatment using an oxidant can be performed once, the cycle of depositing the precursor containing Ga and the treatment using an oxidant can be performed three times, and the cycle of depositing the precursor containing Zn and the treatment using an oxidant can be performed twice. Note that the ratio of the number of cycles of the precursors containing each metal element sometimes does not match the atomic ratio of each metal element in the deposited metal oxide.

[0387] For the composition analysis of the metal oxide for the oxide semiconductor layer, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Or, multiple of the above methods can be combined for analysis. Note that elements with a low content rate are sometimes affected by the analysis accuracy, and the actual content rate is different from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis is sometimes lower than the actual content rate.

[0388] The oxide semiconductor layer of one embodiment of the present invention may also have a stacked structure of two or more layers. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer on the first layer, the composition of the second layer is preferably different from that of the first layer. In addition, when the oxide semiconductor layer has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the composition of the second layer is preferably different from that of the first layer and the third layer. In addition, the same composition as that of the third layer may be employed as the composition of the first layer. Alternatively, the compositions of the first layer and the third layer may also be different from each other.

[0389] The first to third layers may each use the above metal oxides.

[0390] For example, indium oxide, In-Zn oxide, or In-Zn oxide containing a trace amount of element M may be used for the second layer. Specifically, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or around it, a composition of In:Zn = 2:1 [atomic ratio] or around it, or a composition of In:Zn = 4:1 [atomic ratio] or around it may be used. For example, a metal oxide having a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or around it, a composition of In:Ga:Zn = 2:0.1:1 [atomic ratio] or around it, or a composition of In:Ga:Zn = 1:0.1:1 [atomic ratio] or around it may be used. In addition, for example, a metal oxide having a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or around it, a composition of In:Sn:Zn = 2:0.1:1 [atomic ratio] or around it, or a composition of In:Sn:Zn = 1:0.1:1 [atomic ratio] or around it may be used. By increasing the In content rate of the second layer, the on-state current can be increased and the frequency characteristics can be improved.

[0391] The conduction band bottom of each of the first layer and the third layer is preferably closer to the vacuum energy level side than the conduction band bottom of the second layer. In other words, the energy of the conduction band bottom of each of the first layer and the third layer is preferably less than the energy of the conduction band bottom of the second layer. At this time, the second layer is sandwiched between the first layer and the third layer whose conduction band bottoms are closer to the vacuum energy level side, and can mainly be used as a current path (channel).

[0392] When the second layer is sandwiched between the first layer and the third layer, the carriers trapped at the interface of the second layer and its vicinity can be reduced. In addition, the channel can be separated from the surface of the gate insulating layer, and the influence of surface scattering can be reduced. As a result, an embedded channel type transistor in which the channel is separated from the insulating layer interface can be realized, and thus the field effect mobility can be improved. In addition, the influence of the interface energy level that can be formed on the back channel side is reduced, and the photo-degradation (for example, photo negative bias degradation) of the transistor can be suppressed, and thus the reliability of the transistor can be improved.

[0393] For example, ​ The energy band diagram of the oxide semiconductor layer 230 including the oxide semiconductor layer 230_1 to the oxide semiconductor layer 230_3 and its vicinity is as ​ shown. In ​ , the vertical axis represents energy, and the horizontal direction represents the thickness direction at the center of the channel formation region. ​ The valence band maximum (VBM) and conduction band minimum (CBM) of the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, the oxide semiconductor layer 230_3, the insulating layer 280, and the insulating layer 250 are shown in a state where no voltage is applied between the gate and the source. In addition, in ​ , the vacuum level Vac is indicated by a dashed line.

[0394] Note that the energy of the valence band maximum and the energy of the conduction band minimum vary depending on the constituent elements and composition of the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, the oxide semiconductor layer 230_3, the insulating layer 280, and the insulating layer 250. Therefore, the energy band diagram used ​ mainly illustrates the high-low relationship between the energies of the valence band maximum and the high-low relationship between the energies of the conduction band minimum.

[0395] According to the constituent elements and composition of the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, and the oxide semiconductor layer 230_3, as ​ shown, the oxide semiconductor layer 230_2 is sandwiched between the oxide semiconductor layer 230_1 and the oxide semiconductor layer 230_3 whose conduction band minimum is closer to the vacuum level side than the oxide semiconductor layer 230_2. By adopting this structure, an embedded channel can be realized. In other words, in this structure, a path through which more current (electrons are shown as carriers in ​ ) can flow is formed in the oxide semiconductor layer 230_2. Therefore, an increase in the on-state current or an improvement in reliability can be achieved.

[0396] In the case where the first to third layers are used to form an embedded channel, for example, a metal oxide with a higher Ga content ratio than the second layer can be used as the first and third layers. Specifically, for each of the first and third layers, a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or near it, a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it, or a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or near it can be used. Alternatively, a Ga-Zn oxide or gallium oxide can be used. When increasing the Ga content ratio of the first and third layers, sometimes the conduction band bottoms of the first and third layers are closer to the vacuum level side than that of the second layer.

[0397] In addition, by increasing the Ga content ratio of the first and third layers, the hydrogen barrier property of the first and third layers can be improved. Therefore, diffusion of hydrogen from below the first layer or above the third layer to the second layer can be suppressed. In addition, by increasing the Ga content ratio of the first and third layers, impurities such as hydrogen or water contained in the oxide semiconductor layer can be reduced by heat or the like applied after forming the oxide semiconductor layer. In addition, sometimes the same effect can be obtained by using a metal oxide with a lower In content ratio than the second layer as the first and third layers.

[0398] For example, it is preferable to use, as the third layer, a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or near it, a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it, or a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or near it. At this time, the third layer contains indium and gallium.

[0399] In addition, by increasing the Ga content ratio of the first and third layers, the oxygen barrier property of the first and third layers can be improved. Therefore, release of oxygen from the second layer forming the channel can be suppressed, and formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer can be suppressed. Thereby, the electrical characteristics of the transistor can be improved.

[0400] In addition, when increasing the Ga content ratio of the first layer, sometimes the resistivity of the first layer can be made higher than that of the second layer. When the first layer is provided on the back channel side, by providing a layer with a high resistivity as the first layer, negative drift of the threshold voltage or a decrease in the on-state current can be suppressed. Therefore, the threshold voltage of the transistor drifts in the positive direction, and thus constant-off of the transistor can be achieved. Thereby, the electrical characteristics of the transistor can be made good and the reliability of the transistor can be improved.

[0401] When evaluating the band gap of a metal oxide, optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence method, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS) can be used. In addition, multiple of the above methods can be combined for analysis. The electron affinity or the bottom of the conduction band can be obtained from the ionization potential and the band gap of the energy difference between the vacuum level and the top of the valence band. When evaluating the ionization potential, for example, ultraviolet photoelectron spectroscopy (UPS) can be used.

[0402] In addition, the first layer and the third layer can also use a metal oxide with a higher In content ratio than the second layer. In addition, one of the first layer and the third layer and the other layer can respectively use a metal oxide with a higher In content ratio than the second layer and a metal oxide with a higher Ga content ratio than the second layer.

[0403] In addition, the first layer, the second layer, and the third layer can each include a stack of multiple layers having the above composition. For example, the first layer can have a structure in which a metal oxide with a high Ga content is stacked on a metal oxide with a high In content. In addition, for example, the third layer can have a structure in which a metal oxide with a high In content is stacked on a metal oxide with a high Ga content.

[0404] [Method for manufacturing an oxide semiconductor layer] The oxide semiconductor layer according to one embodiment of the present invention can be formed by a sputtering method, a CVD method, a vacuum evaporation method, an MBE method, a PLD method, an ALD method, or the like.

[0405] In addition, the oxide semiconductor layer according to one embodiment of the present invention can be manufactured by forming a metal oxide using two deposition methods. For example, the oxide semiconductor layer according to one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method.

[0406] The oxide semiconductor layer according to one embodiment of the present invention can have a two-layer structure including a first layer and a second layer on the first layer. When the oxide semiconductor layer has a two-layer structure, the oxide semiconductor layer can be manufactured by forming the first layer on the formation surface using the first deposition method and then forming the second layer above it using the second deposition method.

[0407] As the first deposition method, a deposition method that causes less damage to the surface to be formed than the second deposition method is preferably used. Thereby, formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the surface to be formed of the oxide semiconductor layer can be suppressed. In addition, since mixing of impurities such as silicon into the second layer formed on the first layer can be suppressed, the crystallinity of the oxide semiconductor layer can sometimes be further improved.

[0408] As the first deposition method, for example, an ALD method, a CVD method, an MBE method, etc. can be cited. In addition, as the CVD method, a PECVD method, a thermal CVD method, an optical CVD method, an MOCVD method, etc. can be cited. The MBE method is a deposition method in which a thin film having a crystal structure reflecting the crystal system of the substrate grows, and can be said to be one of the deposition methods with less damage to the surface to be formed. In addition, as the first deposition method, a wet method can be used. The wet method is one of the deposition methods with less damage to the surface to be formed. As the wet method, for example, a spraying method, etc. can be cited.

[0409] As the second deposition method, a method capable of depositing a crystalline metal oxide is preferably used. The metal oxide deposited at this time particularly preferably has a CAAC structure. As the second deposition method, for example, a sputtering method, a PLD method, etc. can be cited. The metal oxide deposited by the sputtering method easily has crystallinity, and thus the sputtering method is suitable as the second deposition method.

[0410] In addition, when a metal oxide is formed on the surface to be formed by the second deposition method, the damage to the surface to be formed sometimes causes alloying of the components contained in the metal oxide and the components contained in the layer on the surface to be formed. When alloying occurs, a mixed layer sometimes forms at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer can also be said to be an alloying region. In addition, the formation of the mixed layer can also be said to be alloying.

[0411] For example, when the sputtering method is used as the second deposition method, a mixed layer is sometimes formed due to particles released from a target or the like (also referred to as sputtering particles) or energy supplied to the substrate side by sputtering particles or the like. Specifically, when a silicon-containing insulating layer such as a silicon oxide film is used as the surface to be formed and a metal oxide is deposited by the second deposition method, there is a concern that silicon may be mixed into the metal oxide. When impurities such as silicon are mixed into the metal oxide, crystallization of the metal oxide may be blocked. In addition, when an oxide semiconductor layer containing impurities is used for a transistor, there is a concern that it may have a negative impact on the initial characteristics or reliability of the transistor. In addition, it is also difficult to improve the crystallinity of the alloying region in the case of performing heat treatment described later.

[0412] Thus, as described above, by forming a metal oxide using a first deposition method before forming the metal oxide using a second deposition method, impurity incorporation into the oxide semiconductor layer can be suppressed. In addition, alloying with the layer on the formation surface can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. In addition, the crystallinity of the oxide semiconductor layer can be further improved.

[0413] Note that a mixed layer is sometimes formed at the interface between the first layer and the second layer. The mixed layer contains the components contained in the first layer and the components contained in the second layer. For example, in the case where gallium oxide is used as the first layer and a metal oxide containing indium is used as the second layer, the mixed layer contains gallium and indium. For example, when the indium content rate of the second layer is higher than that of the first layer, the indium content rate of the mixed layer is equal to or higher than that of the first layer and equal to or lower than that of the second layer.

[0414] Compared with the sputtering method, the ALD method can suppress damage to the formation surface, so it is suitable as the first deposition method. In addition, the ALD method is a deposition method with higher coverage than the sputtering method. By using the ALD method as the deposition method for the first layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be used to well cover steps, grooves, etc. with a high aspect ratio.

[0415] As the first layer, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure may be formed. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by performing heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the nucleus. Thus, the crystallinity of the entire oxide semiconductor layer including the vicinity of the interface with the formation surface can sometimes be improved.

[0416] The layer on the formation surface is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. In addition, depending on the transistor structure, the layer on the formation surface may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. In addition, the layer on the formation surface may not have crystallinity. In addition, when the layer has crystallinity, it may also have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor layer.

[0417] The first layer is preferably formed using the ALD method. Here, a method of forming an In-M-Zn oxide using the ALD method as the first layer will be described.

[0418] First, a source gas including a precursor containing indium is introduced into a reaction chamber (also referred to as a processing chamber), and the precursor is adsorbed onto the surface to be formed. Then, an oxidant is introduced into the reaction chamber as a reactant to react with the adsorbed precursor, and components other than indium are removed in a state where indium is adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are bonded.

[0419] Next, a source gas including a precursor containing element M is introduced into the reaction chamber and adsorbed onto the layer formed by bonding indium and oxygen. Then, an oxidant is introduced into the reaction chamber as a reactant to react with the adsorbed precursor, and components other than element M are removed in a state where element M is adsorbed onto the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0420] Next, a source gas including a precursor containing zinc is introduced into the reaction chamber and adsorbed onto the layer formed by bonding element M and oxygen. Then, an oxidant is introduced into the reaction chamber as a reactant to react with the adsorbed precursor, and components other than zinc are removed in a state where zinc is adsorbed onto the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0421] By repeating the above method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on the layer of the surface to be formed using the ALD method.

[0422] In the case of forming an oxide semiconductor layer using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as the oxidant. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as the oxidant, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0423] In the above, preferably, after the precursor is adsorbed, the introduction of the source gas including the precursor is stopped, purging is performed in the reaction chamber, and then the remaining precursor, reaction products, etc. are discharged from the reaction chamber. In the above, preferably, after the adsorbed precursor reacts with the oxidant, the introduction of the oxidant is stopped, purging is performed in the reaction chamber, and then the remaining reactants and reaction products, etc. are discharged from the reaction chamber.

[0424] In addition, in the descriptions such as this specification, when ozone, oxygen, or water is used as a reactant or an oxidant without special description, they also include plasma states, radical states, and ion states and are not limited to gas states or molecular states.

[0425] The second layer is preferably formed by a sputtering method.

[0426] As a target for sputtering method, In-M-Zn oxide can be used. For example, in the case of forming a metal oxide by sputtering method, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased.

[0427] In addition, sometimes the higher the flow ratio of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as oxygen flow ratio), the more crystalline metal oxide can be formed.

[0428] In the case of forming a metal oxide by sputtering method, by depositing under the condition that the proportion of oxygen contained in the sputtering gas is higher than 30% and 100% or less, preferably 70% or more and 100% or less, an oxygen-excess type metal oxide can sometimes be formed. Using the oxygen-excess type metal oxide for the transistor in the channel formation region can obtain higher reliability. Note that one embodiment of the present invention is not limited to this. By depositing under the condition that the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type metal oxide is formed. Using the oxygen-deficient type metal oxide for the transistor in the channel formation region can have a higher field-effect mobility.

[0429] When forming a metal oxide by sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) when forming the metal oxide, a metal oxide with high crystallinity can sometimes be formed. When forming a metal oxide by sputtering method, the temperature for heating the substrate is preferably 100°C or more and 400°C or less, more preferably 200°C or more and 300°C or less.

[0430] By adopting the above manufacturing method, the thickness of the mixed layer at the interface between the layer formed on the formation surface and the metal oxide can be reduced, or the alloying region at the interface between the layer formed on the formation surface and the metal oxide can be thinned to an undetectable level. For example, the thickness of the alloying region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm.

[0431] In addition, the thickness of the alloying region can sometimes be calculated by performing a line analysis of the composition of this region and its periphery using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0432] For example, with the direction perpendicular to the formation surface of the first layer as the depth direction, line analysis of the alloyed region and its surroundings is performed by EDX. Next, in the distribution of the quantitative values of each element with respect to the depth direction obtained by this analysis, the depth at which the quantitative value of the metal that is the main component of the first layer rather than the main component of the layer to be the formation surface (In when the first layer contains In) reaches half value is defined as the depth (position) of the interface between the above region and the first layer. In addition, the depth at which the quantitative value of the element (such as Si) that is the main component of the layer to be the formation surface rather than the main component of the first layer reaches half value is defined as the depth (position) of the interface between the above region and the layer to be the formation surface. By the above steps, the thickness of the alloyed region can be calculated.

[0433] When observing the thickness of the alloyed region in the oxide semiconductor layer of one aspect of the present invention by EDX analysis, for example, the thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm.

[0434] In addition, for example, when performing SIMS analysis on an oxide semiconductor layer formed on a silicon oxide film on the formation surface, the depth at which the silicon concentration reaches 50% of the maximum value of the concentration of the silicon oxide film is taken as the interface, and the distance between the depth at which the silicon concentration decreases to 1.0×10 21 atoms / cm 3 , preferably decreases to 5.0×10 20 atoms / cm 3 , more preferably decreases to 1.0×10 20 atoms / cm 3 and the interface is defined as the thickness t. The thickness t is preferably 3 nm or less, more preferably 2 nm or less.

[0435] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0436] In addition, by reducing the alloyed region, a CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is greater than 0 nm and 3 nm or less, preferably greater than 0 nm and 2 nm or less, and more preferably 1 nm or more and 2 nm or less in the direction substantially perpendicular to the formation surface of the oxide semiconductor layer.

[0437] Note that sometimes the CAAC structure near the formation surface can be confirmed in the observation using TEM. For example, when observing the cross-section of the oxide semiconductor layer using high-resolution TEM, bright spots arranged in layers in the direction parallel to the formation surface are confirmed near the formation surface.

[0438] In addition, the oxide semiconductor layer of one embodiment of the present invention may have a three-layer structure including a first layer, a second layer on the first layer, and a third layer on the second layer.

[0439] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can be manufactured by the following steps: after forming the first layer on the formation surface using a first deposition method, forming the second layer using a second deposition method, and forming the third layer using the first deposition method.

[0440] In the above oxide semiconductor layer, even if a composition that is not easily formed into a CAAC structure by forming a single layer is used as the first layer and the third layer, since crystal growth occurs with the second layer as the nucleus, the entire oxide semiconductor layer including the first layer and the third layer can have a CAAC structure. Alternatively, a region including at least a part of each of the first layer and the third layer to a region including the second layer can have a CAAC structure.

[0441] In particular, even in a composition with a high In content rate in the first layer and the third layer, it can have crystallinity suitable for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, while increasing the In content rate to improve the on-state characteristics of the transistor, a highly crystalline CAAC structure can be adopted to improve reliability.

[0442] In addition, the first layer and the third layer may also use a metal oxide having the same composition as the second layer. By using the same composition, CAAC formation after heat treatment may sometimes be facilitated.

[0443] Since the second layer has high crystallinity, the third layer can grow crystallographically with the crystal of the second layer as the nucleus or seed. Therefore, even when a deposition method that is not easily capable of imparting crystallinity is not used as the deposition method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a deposition method with a higher coverage ratio than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage over the entire layer.

[0444] In addition, by providing the first layer to reduce the influence of the formation surface, the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it can be expected that a layer with extremely excellent crystallinity is also formed in the third layer that crystallizes with the second layer as the nucleus or seed.

[0445] Note that when the oxide semiconductor layer is used as the semiconductor layer of a transistor, sometimes the third layer, which is the uppermost layer of the oxide semiconductor layer, contacts the gate insulating layer. By improving the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility of the transistor in the on state can be improved.

[0446] The crystallinity of the first layer and the third layer is improved with the second layer having high crystallinity as the nucleus or seed. Specifically, the crystallinity of the first layer may be improved by heat treatment during the deposition of the second layer or after the deposition of the third layer. In addition, the crystallinity of the third layer may be improved by heat treatment during the deposition of the third layer or after the deposition of the third layer. In addition, the above heat treatment plays an auxiliary role in improving the crystallinity.

[0447] Thus, in the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the metal oxides (i.e., CAAC) above and below the second layer containing a metal oxide with high crystallinity can be improved with the second layer as the nucleus or seed. Thereby, the crystallinity of the entire oxide semiconductor can be improved. In other words, with the second layer as the nucleus or seed, the metal oxides above and below it are solid-phase grown, so that an oxide semiconductor layer with high crystallinity can be formed. The oxide semiconductor layer formed by using the above deposition method, here the CAAC film can be referred to as axially grown (Axial Growth) CAAC (AG CAAC).

[0448] In the oxide semiconductor layer, regions having a CAAC structure are preferably widely present throughout the layer. The crystal of the region having a CAAC structure in the first layer is combined with the region having a CAAC structure in the second layer. The crystal of the region having a CAAC structure in the third layer is combined with the region having a CAAC structure in the second layer. Thus, the boundary between the first layer and the second layer may sometimes not be observed. In addition, the boundary between the second layer and the third layer may sometimes not be observed. It can sometimes be expressed that the oxide semiconductor layer is a layer in which a clear interface cannot be observed. It can sometimes be expressed that the oxide semiconductor layer is a single layer.

[0449] In each of the first to third layers, for example, when cross-sectional observation is performed using a high-resolution TEM, bright spots arranged parallel or substantially parallel to the formation surface are confirmed in the region having a CAAC structure. In addition, the c-axis of the CAAC structure possessed by each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the formation surface or the surface of the oxide semiconductor layer.

[0450] In addition, a part of the first layer or the third layer may sometimes not be crystallized.

[0451] In addition, in the case where the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can also be manufactured by the following steps: after forming the first layer on the formation surface using the first deposition method, forming the second layer using the first deposition method, and forming the third layer using the second deposition method.

[0452] As described above, by using a metal oxide with a high In content rate for a transistor, the field-effect mobility of the transistor can be increased. On the other hand, a metal oxide with a high In content rate tends to have a cubic crystal structure. Thus, by using a metal oxide with a high In content rate for the second layer in contact with the third layer, a crystal that reflects the orientation of the crystal included in the third layer can be formed.

[0453] In addition, the lattice mismatch degree between the crystal included in the third layer and the crystal included in the second layer is preferably small. Thereby, a crystal that reflects the orientation of the crystal included in the third layer can be formed in the second layer. At this time, for example, when observing a cross-section of the oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the second layer.

[0454] As long as the lattice mismatch degree between the crystal included in the third layer and the crystal included in the second layer is small, there is no particular limitation on the crystal structure of the second layer. The crystal structure of the second layer can be a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, or a trigonal system.

[0455] In the above structure, typically, the first layer can be a layer including a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it, or gallium oxide, the second layer can be a layer including the above metal oxide containing a trace amount of element M or indium oxide, and the third layer can be a layer including a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or near it. At this time, the first layer contains gallium. In addition, when the first layer includes a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it, the indium content rate in the first layer is lower than the gallium content rate. In addition, the indium content rate of the second layer is higher than the indium content rate of the third layer.

[0456] In the case of forming the first layer and the second layer by using the first deposition method, it is preferable to continuously deposit the first layer and the second layer in a manner not exposed to the atmosphere. By continuously depositing the first layer and the second layer in a manner not exposed to the atmosphere, the productivity can be improved. In addition, impurities (typically moisture, etc.) introduced into the interface between the first layer and the second layer and its vicinity can be reduced.

[0457] In addition, one or more of the first layer to the third layer may also be stacked to include a plurality of layers having different compositions. For example, the first layer can also be manufactured by the following steps: after forming a layer including a metal oxide with a high Ga content rate by using the first deposition method, forming a layer including a metal oxide with an In content rate higher than that of this layer by using the first deposition method.

[0458] It is preferable to perform microwave plasma treatment after forming a layer by using the first deposition method.

[0459] In the present specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma treatment refers to, for example, a treatment using a device including a power source that generates a high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0460] By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the oxide semiconductor layer 230 can be reduced. As impurities, hydrogen and carbon can be particularly mentioned. Note that the above shows a structure in which microwave plasma treatment is performed on a metal oxide in an oxygen-containing atmosphere, but it is not limited thereto. For example, microwave plasma treatment can also be performed on an insulating film provided near the metal oxide, more specifically, on a silicon oxide film, in an oxygen-containing atmosphere. In addition, sometimes the crystallinity of the oxide semiconductor layer is improved due to the heat in the microwave plasma treatment.

[0461] Microwave plasma treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 50 Pa or more and 700 Pa or less, and further preferably 100 Pa or more and 400 Pa or less. In addition, the treatment temperature is preferably room temperature (25 °C) or more and 750 °C or less, more preferably 300 °C or more and 500 °C or less, and may be 400 °C or more and 450 °C or less.

[0462] When performing microwave plasma treatment, the substrate can also be heated. The heating temperature of the substrate is preferably room temperature (for example, 25 °C) or more, 100 °C or more, 200 °C or more, 300 °C or more, or 400 °C or more and 500 °C or less or 450 °C or less. For example, the heating temperature of the substrate is preferably room temperature or more and 500 °C or less, more preferably 100 °C or more and 450 °C or less, further preferably 200 °C or more and 450 °C or less, still further preferably 300 °C or more and 450 °C or less, and yet further preferably 400 °C or more and 450 °C or less.

[0463] Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radicals may be triplet oxygen (O( 3 P j )), singlet oxygen (O( 1 D2)), and oxygen ions (O2 +The three states of ( ). In addition, when the hydrogen concentration in the oxide film is reduced by microwave plasma treatment, oxygen ions effectively play a role. In addition, the amount of oxygen radicals in each state varies according to the oxygen flow ratio or pressure in the microwave plasma treatment. For example, under the conditions of low oxygen flow ratio and low pressure, there is a tendency for the amount of oxygen ions to increase. On the other hand, when the oxygen flow ratio or pressure is too low, there are concerns such as unstable control of the oxygen flow and difficulty in stabilizing the discharge; the oxide film is etched, etc. Therefore, for example, the oxygen flow ratio (O2 / (O2+Ar)) in the microwave plasma treatment is preferably greater than 0% and 10% or less, more preferably 0.5% or more and 5% or less, further preferably 0.5% or more and 3% or less, and typically preferably 1%.

[0464] The shorter the treatment time of the microwave plasma treatment, the more the oxidation of the conductive layer 220 or the conductive layer 240, etc. can be suppressed. In addition, the productivity is improved. Thus, for example, the treatment time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and further preferably 1 minute or more and 10 minutes or less.

[0465] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using high frequencies such as microwaves or RF, and the oxygen radicals generated by plasmaizing the oxygen gas can act on the oxide semiconductor layer. Through the action of plasma, microwaves, or oxygen radicals, etc., the V O H in the oxide semiconductor layer can be divided into oxygen vacancies and hydrogen, and hydrogen as an impurity can be removed from the oxide semiconductor layer. In this way, the V O H contained in the oxide semiconductor layer can be reduced. At this time, carbon bonded to oxygen or hydrogen, etc. can sometimes also be removed. In this way, by performing microwave plasma treatment, impurities such as carbon or hydrogen can be reduced. In addition, by supplying the above-mentioned oxygen radicals to the oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0466] In addition, by performing microwave plasma treatment, the crystallinity of the layer formed by the first deposition method can be improved. Here, the principle of improving the crystallinity of the oxide semiconductor by microwave plasma treatment is described. First, active species such as oxygen radicals excited by microwaves reach the surface of the oxide semiconductor, and a substitution reaction between the active species and oxygen in the oxide semiconductor layer occurs. At this time, nuclei or seeds are formed. In addition, lateral growth of the nuclei or seeds is caused. In addition, when the active species excited by microwaves contain oxygen (typically oxygen ions) that is easily adsorbed to the sides of the nuclei or seeds, the above-mentioned lateral growth is promoted, so it is preferred. By performing microwave plasma treatment, the formation of nuclei or seeds and the lateral growth of the nuclei or seeds occur, and the crystallinity of the oxide semiconductor is improved.

[0467] On the other hand, when part of the oxygen in the oxide semiconductor layer existing before the microwave plasma treatment reacts with the hydrogen in the oxide semiconductor layer, that is, when the reaction of "2H + O → H2O↑" occurs, the hydrogen can be removed as H2O (also referred to as dehydration or dehydrogenation). Since H2O is one of the main reasons hindering the improvement of crystallinity, it is preferable to remove H2O from the oxide semiconductor layer. Removing the hydrogen in the oxide semiconductor layer as H2O to reduce the hydrogen concentration in the oxide semiconductor layer can thereby also promote the improvement of crystallinity. In addition, by increasing the temperature during the microwave plasma treatment, the hydrogen concentration in the oxide semiconductor layer can be further reduced.

[0468] In addition, a heat treatment may also be continuously performed in a manner not exposing to the atmosphere after the microwave plasma treatment. The temperature of the heat treatment is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and still more preferably 400°C or higher and 450°C or lower.

[0469] Note that a plasma treatment containing oxygen gas may also be performed instead of the microwave plasma treatment to improve crystallinity.

[0470] When the crystallinity of the layer formed by the first deposition method is improved, the crystallinity of the layer formed on this layer can be further improved. Therefore, the crystallinity of the entire oxide semiconductor layer can be improved.

[0471] As the oxygen supplied to the oxide semiconductor layer, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions containing unpaired electrons). The oxygen injected into the oxide semiconductor layer is preferably one or more of the above forms, and particularly preferably oxygen radicals.

[0472] In addition, a heat treatment is preferably performed after forming the oxide semiconductor layer. By performing the heat treatment, the crystallinity of the oxide semiconductor layer can be improved. Here, the heat treatment is not limited to heat treatment. For example, it may also be heat applied during the manufacturing process and the like.

[0473] The temperature of the heat treatment can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). In addition, the treatment time can be 10 hours or less, for example, 1 minute or longer and 5 hours or less, or 1 minute or longer and 2 hours or less. In addition, in the case of using an RTA apparatus, the treatment time can be, for example, 1 second or longer and 5 minutes or less. By this heat treatment, it is expected that the third layer formed by the first deposition method fills the gaps of the atomic-level crystal parts in the CAAC structure of the second layer formed by the second deposition method.

[0474] There is no particular limitation on the heating apparatus used for the heat treatment, and it can also be an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by the radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs a heat treatment using a high-temperature gas.

[0475] By this heat treatment process, sometimes the crystallinity of the region having the CAAC structure in the third layer formed by the first deposition method is improved. In addition, when this region is only formed below the above-mentioned third layer after deposition by the ALD method, sometimes this region expands upward by this heat treatment process. That is, by performing this heat treatment, a region having the CAAC structure is sometimes formed in the entire above-mentioned third layer.

[0476] In addition, it is preferable to make at least a part of the first layer or the second layer formed by the first deposition method CAAC by this heat treatment process. It can be expected that it is easy to cause CAAC to occur with the mixed layer formed in the above-mentioned first layer or second layer as a nucleus or a seed when forming a layer by the second deposition method. Preferably, the CAAC region in the above-mentioned first layer or second layer is large and expands to the vicinity of the formation surface.

[0477] In addition, CAAC conversion is performed from the upper part to the lower part of the first layer or the second layer described above. Therefore, it is not restricted by the material or crystallinity of the layer to be formed, and the vicinity of this layer can also be CAAC-converted. For example, even if this layer has an amorphous structure, the crystallinity of the first layer or the second layer described above can be improved. Therefore, the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer to be formed has an amorphous structure.

[0478] As described above, by performing one or both of microwave plasma treatment and heat treatment, the crystallinity of the entire oxide semiconductor layer can be improved. In addition, impurities in the oxide semiconductor layer can be reduced. By performing crystal growth in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0479] By improving the crystallinity of the oxide semiconductor layer, an increase in the resistance of the semiconductor layer of a transistor using the oxide semiconductor layer is suppressed, or the initial characteristics (especially the on-state current) of the transistor are improved. Thus, it is possible to expect to realize a transistor suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0480] In addition, one or both of microwave plasma treatment and heat treatment can be directly performed on the oxide semiconductor layer, or can be performed after forming an insulating film or the like on the oxide semiconductor layer.

[0481] Before depositing the first layer or after forming the first layer or the second layer using the first deposition method, a treatment of supplying oxygen to the first layer or the second layer can also be performed. Thus, oxygen can be supplied to the oxide semiconductor layer by heat or the like applied after this treatment.

[0482] As the treatment of supplying oxygen, for example, heat treatment in an oxygen-containing atmosphere or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere can be cited. Alternatively, oxygen can be supplied to the first layer or the second layer formed using the first deposition method by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film can be immediately removed or can remain. In the case where the deposited oxide film remains, this oxide film can be used as a layer (the second layer or the third layer) provided on the first layer or the second layer described above. In addition, as the oxygen-containing atmosphere, in addition to oxygen gas (O2), an atmosphere containing an oxygen-containing compound gas such as ozone (O3) or nitrous oxide (N2O) is included. In addition, the substrate temperature in the plasma treatment is 25°C or higher and 450°C or lower.

[0483] In one embodiment of the present invention, the oxide semiconductor layer has high crystallinity throughout the layer. Therefore, the boundary between the stacked films in the first to third layers may not be confirmed in the oxide semiconductor layer. In particular, after heat treatment, it may be difficult to confirm the boundary between the stacked films. For example, a cross-sectional TEM, a cross-sectional STEM (scanning transmission electron microscope), etc. can be used to confirm whether there is a boundary between the stacked films.

[0484] In addition, compared with the CAAC structure oxide semiconductor layer formed by one deposition method, one or more of the relative dielectric constant, film density, and film hardness of the film of the CAAC structure oxide semiconductor layer formed by the above two deposition methods may be higher.

[0485] By using the CAAC structure oxide semiconductor layer formed by the above two deposition methods for the channel formation region of a transistor, a transistor with excellent characteristics (for example, a transistor with a large on-state current, a high field-effect mobility, a small S value, a high frequency characteristic (also referred to as an f characteristic), a highly reliable transistor, etc.) can be realized.

[0486] In addition, an oxide semiconductor layer according to one embodiment of the present invention can sometimes be manufactured by using the first deposition method and one or both of microwave plasma treatment and heat treatment. In other words, an oxide semiconductor layer according to one embodiment of the present invention can sometimes be manufactured without using the second deposition method. For example, by performing one or both of microwave plasma treatment and heat treatment after forming the first layer by the first deposition method, the crystallinity of the first layer can be improved. Therefore, the crystallinity of the second layer formed on the first layer by the first deposition method can be improved with the first layer as a core or seed. In addition, by performing one or both of microwave plasma treatment and heat treatment after forming the second layer, the crystallinity of the oxide semiconductor layer can be improved. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0487] As described above, in a manufacturing method without using the second deposition method, the oxide semiconductor can also solid-phase grow upward with the first layer formed by the first deposition method as a core or seed to form a highly crystalline oxide semiconductor. The oxide semiconductor formed by the above deposition method can also be referred to as AG CAAC.

[0488] In addition, in the case where the oxide semiconductor layer has a stacked structure of two or more layers, the oxide semiconductor layer can also be manufactured by forming a metal oxide using a deposition method. In the case where the oxide semiconductor layer has a two-layer structure including a first layer and a second layer on the first layer, for example, the oxide semiconductor layer can be manufactured by sequentially forming the first layer and the second layer using a sputtering method. Since the deposition rate of the sputtering method is faster than that of the ALD method, the productivity can be improved. In addition, for example, when the oxide semiconductor layer has a three-layer structure including a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer to the third layer can also be formed using the sputtering method. Furthermore, a part of the first layer to the third layer can also be deposited using the ALD method. For example, one or both of the second layer and the third layer can be deposited using the ALD method.

[0489] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of the present embodiment can be used as the semiconductor layer of a transistor.

[0490] The oxide semiconductor layer of the present embodiment can be used as the oxide semiconductor layer 230 etc. included in each transistor described in Embodiment 1. In addition, the layer on the formation surface corresponds to the insulating layer 280 etc. described in Embodiment 1. For example, the first layer can be used as the oxide semiconductor layer 230_1, the second layer can be used as the oxide semiconductor layer 230_2, and the third layer can be used as the oxide semiconductor layer 230_3.

[0491] The oxide semiconductor layer of the present embodiment preferably has a CAAC structure. In the oxide semiconductor layer having a CAAC structure, metal atoms are arranged in layers in a direction parallel to or substantially parallel to the formation surface in the crystal part.

[0492] It can be speculated that the oxide semiconductor layer having a CAAC structure exhibits current anisotropy. For example, in IGZO crystals, current flows more easily in the a-axis direction than in the c-axis direction. In other words, it can be speculated that in the oxide semiconductor layer having a CAAC structure, current flows more easily in the lateral direction than in the longitudinal direction.

[0493] In the semiconductor device described in the above embodiment, metal atoms in the oxide semiconductor layer 230 are arranged in layers in a direction parallel to or substantially parallel to the formation surface. In addition, it can also be expressed that the a-b plane of the CAAC structure is provided in a direction parallel to or substantially parallel to the formation surface. By adopting such a structure, the a-b plane of the CAAC structure can be provided in the direction of current flow in the channel of the transistor. Thereby, the on-state current of the transistor can be increased.

[0494] When the oxide semiconductor layer of the present embodiment is used as the semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less. In addition, in a transistor for a more miniaturized semiconductor device, the thickness of the oxide semiconductor layer is preferably 1 nm or more and 20 nm or less, preferably 3 nm or more and 15 nm or less, preferably 5 nm or more and 12 nm or less, preferably 5 nm or more and 10 nm or less. In addition, the average thickness of the oxide semiconductor layer in the channel formation region of the transistor is, for example, preferably 2 nm or more and 15 nm or less.

[0495] The thickness of the first layer is, for example, preferably 0.5 nm or more and 50 nm or less, more preferably 0.5 nm or more and 30 nm or less, more preferably 0.5 nm or more and 20 nm or less, more preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 20 nm or less. In addition, the thickness of the first layer is more preferably 0.5 nm or more and 3 nm or less.

[0496] In addition, the first layer preferably has a region with a thickness of 0.1 nm or more and 3 nm or less, more preferably has a region with a thickness of 0.1 nm or more and 2 nm or less. Alternatively, it more preferably has a region with a thickness of 0.5 nm or more and 3 nm or less, and further preferably has a region with a thickness of 0.5 nm or more and 2 nm or less.

[0497] The thickness of the second layer is, for example, preferably 200 nm or less. In addition, when the second layer is in a layered form, the thickness is, for example, preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and further preferably 2 nm or more and 100 nm or less.

[0498] Alternatively, when the second layer can act as a nucleation site, the second layer sometimes does not exist in a layered form but becomes an aggregate of island regions. In this case, for example, the island regions included in the second layer are dispersed.

[0499] The preferred range of the thickness of the third layer can be referred to the description of the thickness of the first layer.

[0500] [Impurities in the oxide semiconductor layer] Here, the effects of various impurities in the oxide semiconductor layer are described.

[0501] As described in the above embodiments, in a transistor using an oxide semiconductor as a semiconductor layer, when oxygen vacancies (V O ) and impurities are present in the channel formation region of the oxide semiconductor layer, the electrical characteristics may easily vary and the reliability may decrease. Therefore, in order to stabilize the electrical characteristics of the OS transistor, it is effective to reduce the impurity concentration in the oxide semiconductor layer. In order to reduce the impurity concentration in the oxide semiconductor layer, it is preferable to also reduce the impurity concentration in the nearby film. Examples of the impurity include hydrogen, carbon, and nitrogen.

[0502] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Accordingly, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, still more preferably 1×10 19 atoms / cm 3 or less, still more preferably 3×10 18 atoms / cm 3 or less, and even more preferably 1×10 18 atoms / cm 3 or less. Further, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, still more preferably 1×10 19 atoms / cm 3 or less, still more preferably 3×10 18 atoms / cm 3 or less, and even more preferably 1×10 18 atoms / cm 3 or less.

[0503] In addition, when the oxide semiconductor contains nitrogen, electrons are generated as carriers, increasing the carrier concentration and making it easy to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen easily has a normally-on characteristic. Or, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Hereinafter, it is preferably 5×10 19 atoms / cm 3 Hereinafter, more preferably 1×10 19 atoms / cm 3 Hereinafter, more preferably 5×10 18 atoms / cm 3 Hereinafter, more preferably 1×10 18 atoms / cm 3 Hereinafter, further preferably 5×10 17 atoms / cm 3 Hereinafter.

[0504] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters this oxygen vacancy, electrons are sometimes generated as carriers. In addition, sometimes electrons are generated as carriers because a part of hydrogen bonds with oxygen bonded to metal atoms. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has a normally-on characteristic. Thus, it is preferable to minimize hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to be less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , further preferably less than 5×10 18 atoms / cm 3 , still further preferably less than 1×10 18 atoms / cm 3 , yet further preferably less than 1×10 17 atoms / cm 3 .

[0505] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Hereinafter, preferably 2×10 16 atoms / cm 3 or less.

[0506] By using an oxide semiconductor with sufficiently reduced impurities for the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0507] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0508] Embodiment 3 In this embodiment, a storage device according to one aspect of the present invention will be described with reference to ​ A storage device according to one aspect of the present invention includes a storage unit. In addition, the storage unit includes a transistor and a capacitor.

[0509] <Structural Example 1 of Storage Device> With reference to ​ The structure of a storage device including a transistor and a capacitor will be described. ​ is a plan view of a storage device including a storage unit. ​ is a cross-sectional view along the ​ indicated dash-dotted line A1 - A2. ​ is a cross-sectional view along the ​ indicated dash-dotted line A3 - A4.

[0510] ​ The storage device shown in includes: an insulating layer 140 on a substrate (not shown); a conductive layer 110 on the insulating layer 140; a storage unit 150 on the conductive layer 110; an insulating layer 180 on the conductive layer 110; an insulating layer 280 on the insulating layer 180; an insulating layer 284 on the insulating layer 280; an insulating layer 285 on the insulating layer 284; and a conductive layer 265 on the insulating layer 284, the insulating layer 285, and the storage unit 150. The insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 284, and the insulating layer 285 are used as interlayer films. The conductive layer 110 is used as a wiring.

[0511] The storage unit 150 includes a capacitor 100 on the conductive layer 110 and a transistor 200 on the capacitor 100.

[0512] The capacitor 100 includes a conductive layer 115 on a conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 220 on the insulating layer 130.

[0513] In the capacitor 100, the conductive layer 220 is used as one of a pair of electrodes (sometimes referred to as the upper electrode), the conductive layer 115 is used as the other of the pair of electrodes (sometimes referred to as the lower electrode), and the insulating layer 130 is used as the dielectric. That is, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0514] As ​ and ​ shown, the insulating layer 180 is provided with an opening 190 reaching the conductive layer 110. The conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190 and a region in contact with the side surface of the insulating layer 180 in the opening 190. The insulating layer 130 is disposed so as to be located in the opening 190. The conductive layer 220 is disposed so that at least a part thereof is located in the opening 190. Further, as ​ shown, the conductive layer 220 is preferably provided in a manner of being embedded in the opening 190. Further, the films provided inside the opening 190 are all preferably formed by the ALD method. Thereby, the films have good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220 are all preferably formed by the ALD method.

[0515] The capacitor 100 has a structure in which the upper electrode and the lower electrode face each other with a dielectric interposed therebetween not only on the bottom surface but also on the side surface in the opening 190, so that the capacitance per unit area can be increased. Thus, the deeper the depth of the opening 190, the greater the capacitance of the capacitor 100 can be. In this way, by increasing the capacitance per unit area of the capacitor 100, the read operation of the storage device can be made stable. Further, miniaturization or high integration of the storage device can be promoted.

[0516] As ​ shown, the shape of the opening 190 when viewed from the plane is preferably circular. By adopting a circular shape, the processing accuracy when forming the opening 190 can be improved, and thus a fine-sized opening 190 can be formed. Note that in this specification and the like, the circular shape is not limited to a perfect circle. Further, although an example in which the shape of the opening 190 when viewed from the plane is circular is shown in the present embodiment, the present invention is not limited thereto. The shape applicable to the opening 190 is the same as the shape applicable to the opening 270 described above.

[0517] ​An example is shown in which the side surface of the opening 190 is perpendicular to the top surface of the conductive layer 110. At this time, the opening 190 has a cylindrical shape. By adopting such a structure, miniaturization or high integration of the storage device can be achieved.

[0518] A conductive layer 115 is provided along the side surface of the opening 190 and the top surface of the conductive layer 110. In addition, an insulating layer 130 is provided on the conductive layer 115. In addition, a conductive layer 220 is provided on the insulating layer 130 in such a way as to be embedded in the opening 190. The capacitor 100 having such a structure can be referred to as a trench capacitor or a trench-type capacitor. Note that the structure of the capacitor 100 is not limited to this, and for example, a pillar-type capacitor, a parallel-plate capacitor, etc. can also be adopted.

[0519] The insulating layer 140 can use an insulating material that can be used for the insulating layer 210, etc.

[0520] Since the insulating layer 180 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulating layer 180, a single layer or a stack of insulating layers containing a material with a low relative dielectric constant can be used. Silicon oxide and silicon oxynitride have thermal stability, so they are preferred. In addition, the insulating layer 180 can use an insulating material that can be used for the insulating layer 280, etc.

[0521] An insulating layer 280 is disposed on the capacitor 100.

[0522] ​ The components of the transistor 200 are shown. Regarding the transistor 200, reference can be made to the description in Embodiment 1 ( ​ etc.), so the detailed description is omitted. In addition, the transistor included in the storage cell 150 is not limited to the transistor 200, and each transistor shown in Embodiment 1 can also be applied.

[0523] As ​ shown, the transistor 200 is disposed so as to overlap with the capacitor 100. In addition, the groove portion 290 provided with some components of the transistor 200 has an area overlapping with the opening 190 provided with some components of the capacitor 100. By adopting such a structure, the transistor 200 and the capacitor 100 can be disposed without significantly increasing the occupied area when viewed from the plane. As a result, the occupied area of the storage cell 150 can be reduced, and thus the storage cells 150 can be arranged in a high density to increase the storage capacity of the storage device. In other words, high integration of the storage device can be achieved.

[0524] ​An example is shown in which the width of the opening 190 in the X direction is the same as or substantially the same as the width of the groove 290. There is no particular limitation on the size relationship between the width of the opening 190 and the width of the groove 290. The width of the opening 190 may be smaller than the width of the groove 290. By making the width of the opening 190 in the X direction smaller than the width of the groove 290, the requirement for the positional alignment accuracy between the end portion of the conductive layer 220 and the opening 190 can be reduced, and thus it is relatively easy to process the conductive layer 220. In addition, miniaturization and high integration of the storage device can be achieved. In addition, the width of the opening 190 may be larger than the width of the groove 290 in the X direction. By making the width of the opening 190 larger than the width of the groove 290 in the X direction, the electrostatic capacitance of the capacitor 100 can be increased. In addition, for example, as ​ shown, the size relationship between the two widths in a semiconductor device according to one embodiment of the present invention can be confirmed based on a cross section parallel to the Z direction.

[0525] In addition, by disposing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the heat treatment during the manufacture of the capacitor 100. Therefore, deterioration of electrical characteristics of the transistor 200 such as threshold voltage variation and increase in parasitic resistance, and increase in electrical characteristic non-uniformity caused by such deterioration of electrical characteristics can be suppressed.

[0526] Here, ​ is a plan view showing an example of a storage device in which a plurality of ​ shown memory cells 150 are arranged. ​ An example is shown in which two × two memory cells 150 are arranged in the X direction and the Y direction. In addition, ​ shown the X direction is parallel to ​ shown A1 - A2 direction, ​ shown the Y direction is parallel to ​ shown B1 - B2 direction.

[0527] In addition, ​ shows ​ shown a perspective schematic view of the storage device. ​ is a perspective schematic view of a storage device including four memory cells. In addition, regarding ​ partial components (interlayer insulating layer, etc.) in, only the outline represented by a dashed line is shown.

[0528] As described in Embodiment 1, by connecting the conductive layer 240a and the conductive layer 240b, the conductive layer 240a and the conductive layer 240b can be used as the other of the source electrode and the drain electrode of the transistor 200 included in the memory cell 150.

[0529] As a method for connecting the conductive layer 240a and the conductive layer 240b, there can be cited a method of using one conductive layer as both the conductive layer 240a and the conductive layer 240b, a method of connecting the conductive layer 240a and the conductive layer 240b through a conductive layer, a method of applying the same potential to the conductive layer 240a and the conductive layer 240b, etc.

[0530] ​ An example of a structure in which one conductive layer is used as both the conductive layer 240a and the conductive layer 240b is shown. As ​ shown, a groove portion can be provided in the region of the one conductive layer where the memory cell 150 is disposed. By adopting such a structure, the conductive layer in the region where the memory cell 150 is disposed can be used as the conductive layer 240a or the conductive layer 240b. The above-mentioned groove portion can be formed, for example, so as to overlap with the groove portion 290 described in the first embodiment. Thereby, the groove portion can be formed without adding processes.

[0531] ​ An example of a structure in which the conductive layer 240a and the conductive layer 240b are connected through a conductive layer is shown. As ​ shown, the conductive layer 240a and the conductive layer 240b can be connected through the conductive layer 241a, the conductive layer 241b, and the conductive layer 242. The conductive layer 241a and the conductive layer 241b are used as plugs, and the conductive layer 242 is used as a wiring.

[0532] ​ Shown in ​ is a circuit diagram when the conductive layer 240a and the conductive layer 240b are connected in the memory device shown.

[0533] One of the source and drain of the transistor 200 is connected to one of the pair of electrodes of the capacitor 100, the other of the source and drain of the transistor 200 is connected to the wiring BIL, and the gate of the transistor 200 is connected to the wiring WOL. The other of the pair of electrodes of the capacitor 100 is connected to the wiring CAL.

[0534] Here, the wiring BIL corresponds to the conductive layer 240a and the conductive layer 240b, the wiring WOL corresponds to the conductive layer 265, and the wiring CAL corresponds to the conductive layer 110.

[0535] As ​ shown, preferably, the conductive layer 265 extends in the X direction, and the conductive layer 240a and the conductive layer 240b extend in the Y direction. By adopting such a structure, the wiring BIL and the wiring WOL cross each other. In addition, in ​ , the wiring CAL is parallel to the wiring WOL. Note that the present invention is not limited to this. The wiring CAL can also be parallel to the wiring BIL, for example.

[0536] Note that the storage unit will be described in detail in the following embodiments.

[0537] [Capacitor 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 220. In addition, a conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0538] The conductive layer 110 is used as a wiring CAL and can be formed, for example, in a strip shape. Note that the strip shape means a shape having a region extending in a certain direction (e.g., the X direction, the Y direction, or the Z direction).

[0539] The conductive layer 110 has a concave portion in the region overlapping with the opening 190.

[0540] As the conductive layer 110, a single layer or a stacked layer of the conductive materials described in [Conductive layer] of Embodiment 1 can be used. As the conductive layer 110, for example, a highly conductive material such as tungsten can be used. By using such a highly conductive material, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can fully function as a wiring CAL.

[0541] The conductive layer 115 has a region 101 with a bent corner within the concave portion of the conductive layer 110. Thus, for example, compared with the case where the region 101 has a right angle or an acute angle (has a corner), the electric field concentration near the insulating layer 130 in the region 101 can be suppressed. In addition, when starting from a reference plane, the height of the end portion 103 of the conductive layer 115 is lower than the top surface height of the insulating layer 180. Thus, compared with the case where the end portion 103 is located on the insulating layer 180, the electric field concentration near the insulating layer 130 at the end portion 103 can be suppressed. In this way, by suppressing the electric field concentration on the insulating layer 130, the dielectric breakdown of the insulating layer 130 can be suppressed, and a highly reliable storage device can be provided. Note that the reference plane refers to the top surface of the substrate, the top surface of the insulating layer 140, etc.

[0542] As the conductive layer 115, a single layer or a stacked layer of the conductive materials described in [Conductive layer] of Embodiment 1 can be used. As the conductive layer 115, it is preferable to use, as a single layer or a stacked layer, a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion. For example, titanium nitride or ITSO can also be used. Alternatively, for example, it can have a structure in which tantalum nitride is laminated on tungsten. Alternatively, for example, it can have a structure in which a first titanium nitride, tungsten, and a second titanium nitride are laminated in sequence. By adopting such a structure, oxidation of the conductive layer 115 due to the insulating layer 130 when the insulating layer 130 is made of an oxide can be suppressed. In addition, oxidation of the conductive layer 115 due to the insulating layer 180 when the insulating layer 180 is made of an oxide can be suppressed.

[0543] The insulating layer 130 is disposed on the conductive layer 115. The insulating layer 130 is disposed in contact with the top surface of the conductive layer 115. That is, the insulating layer 130 preferably covers the side ends of the conductive layer 115. Thereby, short circuits between the conductive layer 115 and the conductive layer 220 can be prevented.

[0544] Preferably, a material having a high relative permittivity is used as the insulating layer 130. By using a material having a high relative permittivity for the insulating layer 130, the thickness of the insulating layer 130 can be increased to an extent that can suppress leakage current and the capacitance of the capacitor 100 can be sufficiently ensured.

[0545] In addition, as the insulating layer 130, it is preferable to use a laminated insulating layer made of a material having a high relative permittivity, and a laminated structure of a material having a high relative permittivity and a material having a dielectric strength greater than that of the material having a high relative permittivity is preferably used. For example, as the insulating layer 130, an insulating film in which zirconia, alumina, and zirconia are laminated in sequence can be used. In addition, for example, an insulating film in which zirconia, alumina, zirconia, and alumina are laminated in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are laminated in sequence can be used. By using an insulating layer having a relatively large dielectric strength such as alumina by lamination, the dielectric strength can be increased and electrostatic breakdown of the capacitor 100 can be suppressed.

[0546] In addition, as the insulating layer 130, a material that can have ferroelectricity can be used. For the details of the material that can have ferroelectricity, reference can also be made to the description of Embodiment 1.

[0547] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even in a thin film of several nm, so they are preferably used for the insulating layer 130. The thickness of the insulating layer 130 can be 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and still further preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). In addition, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device.

[0548] In addition, metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when their area is small, so they are preferably used for the insulating layer 130. For example, the ferroelectric layer can have ferroelectricity even when the area (occupied area) when viewed from the plane is 100 μm 2 or less, 10 μm 2 or less, 1 μm 2 or less, or 0.1 μm 2 or less. In addition, sometimes the ferroelectric layer can have ferroelectricity even when the area (occupied area) when viewed from the plane is 10000 nm2 or less than 1000 nm 2 also has ferroelectricity below this value. By making the area of the ferroelectric layer small, the occupied area of the capacitor 100 can be reduced.

[0549] In addition, yttrium can be added to a metal oxide containing one or both of hafnium and zirconium. For example, by adding yttrium to a hafnium-zirconium oxide, the ferroelectricity can be enhanced.

[0550] A ferroelectric material is an insulator that has the property of polarizing internally under the action of an externally applied electric field and maintaining the polarization even when the electric field is zero. Therefore, by using a capacitor that uses this material as a dielectric (hereinafter sometimes referred to as a ferroelectric capacitor), a non-volatile memory element can be formed. A non-volatile memory element using a ferroelectric capacitor is sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as the capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0551] The conductive layer 220 is provided so as to cover the insulating layer 130. The side end portion of the conductive layer 220 is preferably located outside the side end portion of the conductive layer 115. By adopting such a structure, the conductive layer 220 can be embedded in the opening 190. In addition, by increasing the area of the conductive layer 220 as viewed from the plane, the requirement for the alignment accuracy with the groove portion 290 can be reduced, and thus the groove portion 290 can be more easily processed.

[0552] Regarding the materials, structures, etc. that can be used for the conductive layer 220, reference can be made to the description of Embodiment 1.

[0553] ​ is a diagram showing ​ an example in which the end portion 103 shown is located on the insulating layer 180. In ​ the example shown, the region 102 from the top surface of the insulating layer 180 to the side surface in the opening 190 has a curved portion. In addition, in ​ the example shown, the end portion 103 has a tapered shape. Since the region 102 has a curved portion and the end portion 103 has a tapered shape, even when the end portion 103 is located on the insulating layer 180, the electric field concentration near the region 102 and near the end portion 103 of the insulating layer 130 can be suppressed. Thereby, the dielectric breakdown of the insulating layer 130 can be suppressed, and a highly reliable storage device can be provided.

[0554] ​ shows ​For example, in a region where the insulating layer 130 overlaps with the insulating layer 180, an insulating layer 187 is provided on the insulating layer 130 as shown. By providing the insulating layer 187, it is sometimes possible to appropriately suppress the concentration of the electric field on the insulating layer 130.

[0555] <Example of the structure of a storage device 2> In the above <Example of the structure of a storage device 1>, an example is described in which the transistor 200...

Claims

1. A semiconductor device, comprising: an oxide semiconductor layer; a first insulating layer; a second insulating layer; a third insulating layer; a first conductive layer; a second conductive layer; and a third conductive layer, wherein the first conductive layer and the second conductive layer are isolated from each other on the first insulating layer, the first insulating layer has a groove portion between the first conductive layer and the second conductive layer, the oxide semiconductor layer has a region in contact with a part of the top surface of the first conductive layer and a side surface on one side of the groove portion, a region in contact with a part of the top surface of the second conductive layer and a side surface on one side of the groove portion, and a region in contact with the side surface of the groove portion, the second insulating layer is on the oxide semiconductor layer, the third conductive layer is on the second insulating layer, the side surfaces of the third conductive layer, the second insulating layer, and the oxide semiconductor layer are aligned or substantially aligned, the third insulating layer has a region in contact with another part of the top surface of the first conductive layer, another part of the top surface of the second conductive layer, the side surface of the oxide semiconductor layer, the side surface of the second insulating layer, and the side surface of the third conductive layer outside the groove portion, and the third insulating layer has a region in contact with the side surface of the oxide semiconductor layer, the side surface of the second insulating layer, and the side surface of the third conductive layer inside the groove portion.

2. The semiconductor device according to claim 1, further comprising a fourth conductive layer, wherein the fourth conductive layer is in contact with the top surface of the third conductive layer, and the extending direction of the fourth conductive layer intersects with the extending direction of the groove portion.

3. The semiconductor device according to claim 1, further comprising a fifth conductive layer, wherein the fifth conductive layer has a region overlapping with the first conductive layer and the second conductive layer with the first insulating layer therebetween, the fifth conductive layer has a concave portion in a region overlapping with the groove portion, and the oxide semiconductor layer has a region in contact with the side surface and the bottom of the concave portion.

4. The semiconductor device according to claim 3, wherein the concave portion has a curved portion.

5. A storage device, comprising: a capacitor; a transistor on the capacitor; a first insulating layer; and a second insulating layer, wherein the transistor includes an oxide semiconductor layer, a third insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, the first insulating layer covers the first conductive layer, the second conductive layer and the third conductive layer are isolated from each other on the first insulating layer, the first insulating layer has a groove portion between the second conductive layer and the third conductive layer, the first conductive layer has a concave portion in a region overlapping with the groove portion, the oxide semiconductor layer has a region in contact with a part of the top surface of the second conductive layer and a side surface on one side of the groove portion, a region in contact with a part of the top surface of the third conductive layer and a side surface on one side of the groove portion, a region in contact with the side surface of the groove portion, and a region in contact with the side surface and the bottom of the concave portion, the third insulating layer is on the oxide semiconductor layer, the fourth conductive layer is on the third insulating layer, The fourth conductive layer, the third insulating layer, and the side surfaces of the oxide semiconductor layer are aligned or substantially aligned. The second insulating layer has a region in contact with another part of the top surface of the second conductive layer, another part of the top surface of the third conductive layer, the side surface of the oxide semiconductor layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer outside the groove portion. Moreover, the second insulating layer has a region in contact with the side surface of the oxide semiconductor layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer inside the groove portion.

6. The storage device according to claim 5, further comprising a fifth conductive layer. Wherein the fifth conductive layer is in contact with the top surface of the fourth conductive layer. And the extending direction of the fifth conductive layer intersects the extending direction of the groove portion.

7. The storage device according to claim 5. Wherein the concave portion has a bent portion.

8. The storage device according to claim 5. Wherein the capacitor includes a sixth conductive layer, a fourth insulating layer on the sixth conductive layer, and the first conductive layer on the fourth insulating layer.

9. The storage device according to claim 5. Wherein the third insulating layer includes a first layer. And the first layer contains an oxide of hafnium.

10. The storage device according to claim 9. Wherein the first layer contains hafnium zirconium oxide.

11. The storage device according to claim 10. Wherein the third insulating layer includes a second layer on the first layer. And the second layer contains silicon nitride.

12. A semiconductor device, comprising: A first insulating layer; A second insulating layer; A first transistor; And A second transistor. Wherein the first insulating layer has a groove portion. The first transistor includes a first oxide semiconductor layer having a channel formation region. The second transistor includes a second oxide semiconductor layer having a channel formation region. At least a part of the first oxide semiconductor layer and at least a part of the second oxide semiconductor layer are located in the groove portion. And, when viewed in plan, the first oxide semiconductor layer and the second oxide semiconductor layer face each other with the second insulating layer therebetween in a direction perpendicular to the extending direction of the groove portion.

13. The semiconductor device according to claim 12. Wherein the first transistor includes a first conductive layer, a second conductive layer, and a third conductive layer. The second conductive layer is on the first insulating layer. The first conductive layer has a region overlapping the second conductive layer with the first insulating layer therebetween. The first conductive layer has a concave portion in a region overlapping the groove portion. The first oxide semiconductor layer has a region in contact with the side surface and the bottom of the concave portion of the first conductive layer and a region in contact with the top surface and the side surface of the second conductive layer. And the third conductive layer is above the first oxide semiconductor layer.

14. The semiconductor device according to claim 13. Wherein the second insulating layer has a region in contact with the side surface of the first oxide semiconductor layer and the side surface of the second oxide semiconductor layer inside the groove portion.

15. The semiconductor device according to claim 13 further includes a fourth conductive layer, wherein the fourth conductive layer is connected to the gates of the first transistor and the second transistor, and an extending direction of the fourth conductive layer intersects an extending direction of the groove portion.

16. A storage device includes: the semiconductor device according to claim 13; and a capacitor, wherein the capacitor is located below the first transistor, and the first conductive layer has a region serving as one of a pair of electrodes of the capacitor.

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