Thin film transistor

Abstract

The thin film transistor comprises a semiconductor layer, a first grid electrode, a first grid insulating layer, a drain electrode, a source electrode, a second grid insulating layer and a second grid electrode, the semiconductor layer comprises a first doped region, a second doped region and a channel region, and the channel region is connected with the first doped region and the second doped region; the first gate is over the semiconductor layer, wherein the channel region overlaps the entire first gate. The first gate insulating layer is located between the first gate and the semiconductor layer; the drain electrode is electrically connected with the first doped region of the semiconductor layer; the source electrode is electrically connected with the second doped region of the semiconductor layer; the second gate insulating layer is located between the second gate and the semiconductor layer; the second grid electrode overlaps the whole channel region and part of the first doped region, and the size of the part, overlapped with the first doped region, of the second grid electrode is 40%-133% of the size of the first grid electrode in the direction from the source electrode to the drain electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor component, and more particularly to a thin film transistor. Background Art

[0002] Generally, many semiconductor components are included in an electronic device. For example, a display device often includes many thin film transistors, which are formed by depositing various different thin films (such as semiconductors, metals, dielectric layers, etc.) on a substrate.

[0003] With the increasing demand for low power consumption, the thin film transistor needs to introduce smaller feature sizes. For example, the feature size is reduced from more than 10 μm to less than 10 μm. However, the reduction of the feature size of the thin film transistor will cause the kink effect to be more serious. For example, when the drain voltage increases, the drain current increases rapidly. Therefore, how to prevent the kink effect from occurring while reducing the feature size is still one of the goals pursued by related industries for improvement. Summary of the Invention

[0004] An embodiment of the present invention provides a thin film transistor, including a semiconductor layer, a first gate, a first gate insulating layer, a drain, a source, a second gate insulating layer, and a second gate; the semiconductor layer includes a first doped region, a second doped region, and a channel region, the first doped region is separated from the second doped region, and the channel region connects the first doped region and the second doped region; the first gate is located above the semiconductor layer, wherein the channel region overlaps the entire first gate; the first gate insulating layer is located between the first gate and the semiconductor layer; the drain is electrically connected to the first doped region of the semiconductor layer; the source is electrically connected to the second doped region of the semiconductor layer; the semiconductor layer is located between the second gate insulating layer and the first gate insulating layer; the second gate insulating layer is located between the second gate and the semiconductor layer; the second gate overlaps the entire channel region and a part of the first doped region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the first doped region is 40% to 133% of the size of the first gate.

[0005] In an embodiment of the present invention, the size of the part of the second gate overlapping the first doped region is 2 μm to 4 μm.

[0006] In an embodiment of the present invention, the first doped region includes a first lightly doped region and a first heavily doped region, the first lightly doped region is located between the first heavily doped region and the channel region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the first heavily doped region is 2% to 120% of the size of the first gate.

[0007] In an embodiment of the present invention, the above-mentioned second gate also overlaps a part of the second doped region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the second doped region is 20% to 100% of the size of the first gate.

[0008] In an embodiment of the present invention, the size of the part of the above-mentioned second gate overlapping the second doped region is 1 μm to 3 μm.

[0009] In an embodiment of the present invention, the above-mentioned second doped region includes a second lightly doped region and a second heavily doped region. The second lightly doped region is located between the second heavily doped region and the channel region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the second heavily doped region is 0% to 90% of the size of the first gate.

[0010] In an embodiment of the present invention, the central axis of the above-mentioned semiconductor layer does not overlap the central axis of the second gate.

[0011] In an embodiment of the present invention, the orthographic projection of the above-mentioned second gate on the substrate overlaps the orthographic projection of the drain on the substrate, but does not overlap the orthographic projection of the source on the substrate.

[0012] In an embodiment of the present invention, the above-mentioned first gate and the second gate are electrically connected.

[0013] In an embodiment of the present invention, the drain current change rate, the off-state current after strain, and the on-state current decay after strain of the above-mentioned thin-film transistor decrease as the size of the part of the second gate overlapping the first doped region increases in the direction from the source to the drain.

[0014] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A is a top view schematic diagram of a thin-film transistor according to an embodiment of the present invention.

[0016] Figure 1B is a cross-sectional schematic diagram taken along Figure 1A section line A-A' of

[0017] Figure 2A is a graph showing the relationship between the on-current (Ion) and the drain current change rate (Id%) of a thin-film transistor according to an embodiment of the present invention varying with the size L1.

[0018] Figure 2B is a graph showing the relationship between the off-current (Ioff) of a thin-film transistor according to an embodiment of the present invention varying with the size L1.

[0019] Figure 3A It is a graph showing the relationship between Ion of a thin film transistor according to an embodiment of the present invention and the size L2.

[0020] Figure 3B It is a graph showing the relationship between Id% of a thin film transistor according to an embodiment of the present invention and the size L2.

[0021] Figure 4A It is a graph showing the relationship between Ion and Ion degradation of a thin film transistor according to an embodiment of the present invention at the initial operation (T0) and after 100 seconds of self-heating stress (T100) with respect to the size L1.

[0022] Figure 4B It is a graph showing the relationship between Ioff of a thin film transistor according to an embodiment of the present invention at the initial operation (T0) and after 100 seconds of self-heating stress (T100) with respect to the size L1.

[0023] Among them, reference numerals:

[0024] 10: Thin film transistor

[0025] 100: Substrate

[0026] 110, 120: Gate

[0027] 130: Semiconductor layer

[0028] 131, 132: Doped region

[0029] 133: Channel region

[0030] 134, 135: Lightly doped region

[0031] 136, 137: Heavily doped region

[0032] 140: Drain

[0033] 150: Source

[0034] 160, 170: Gate insulating layer

[0035] 180: Planarization layer

[0036] A - A’: Section line

[0037] C1, C2: Central axis

[0038] D1: Direction

[0039] L, L1, L2, L3, L4: Size

[0040] V0, V1, V2: via holes Detailed implementation manners

[0041] In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are enlarged. Throughout the specification, the same reference numerals denote the same components. It should be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component, or intervening components may also be present. Conversely, when a component is referred to as being "directly on" or "directly connected to" another component, no intervening component is present. As used herein, "connected" can refer to physical and / or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other components exist between two components.

[0042] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, region, layer, or portion from another. Thus, the first "component", "part", "region", "layer", or "portion" discussed below may be referred to as a second component, part, region, layer, or portion without departing from the teachings herein.

[0043] The terms used herein are for the purpose of describing particular embodiments only and are not limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one" or indicating "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, regions, wholes, steps, operations, components, and / or parts, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, components, parts, and / or their combinations.

[0044] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one component to another, as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is flipped, a component described as on the "lower" side of other components will be oriented on the "upper" side of the other components. Thus, the exemplary term "lower" can include both the "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one figure is flipped, a component described as "below" or "beneath" other components will be oriented "above" the other components. Thus, the exemplary terms "lower" or "beneath" can include both the upper and lower orientations.

[0045] Taking into account the specific amounts of the measurements discussed and the errors associated with the measurements (i.e., the limitations of the measurement system), "about", "approximate", or "substantially" as used herein includes the stated value and the average within an acceptable deviation range of the specific value determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Further, "about", "approximate", or "substantially" as used herein can be selected to have a more acceptable deviation range or standard deviation depending on optical properties, etching properties, or other properties, rather than applying a single standard deviation to all properties.

[0046] Figure 1A is a top view schematic diagram of a thin film transistor 10 according to an embodiment of the present invention. Figure 1B is along Figure 1A The cross-sectional schematic diagram taken along the section line A-A'. Please refer to Figure 1A and Figure 1B As shown, the thin film transistor 10 includes a gate 110, a gate 120, a semiconductor layer 130, a drain 140, and a source 150. In addition, the thin film transistor 10 may further include a gate insulating layer 160, a gate insulating layer 170, and a planarizing layer 180. Hereinafter, in conjunction with the drawings, the embodiments of each component of the thin film transistor 10 will be further described, but the present invention is not limited thereto.

[0047] In some embodiments, the thin film transistor 10 may be disposed on a substrate 100. The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, an organic polymer, or a light-blocking / reflective material (e.g., metal, wafer, or ceramic) or other applicable materials. However, the present invention is not limited thereto. In other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane (PU), or other suitable materials.

[0048] The semiconductor layer 130 of the thin film transistor 10 is located above the substrate 100. The material of the semiconductor layer 130 may include an oxide semiconductor material, a silicon-based semiconductor material (such as polysilicon, amorphous silicon, etc.), or an organic semiconductor material. For example, the oxide semiconductor material may include at least one of IGZO (InGaZnO), IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), GZO (GaZnO), ZTO (ZnSnO), and ITZO (InSnZnO), but is not limited thereto. The organic semiconductor material may, for example, include various fused heterocycles (such as perylene diimide and naphthalimide small molecules or polymers), polymers (such as polypyrrole, polyfuran), derivatives of the above materials, or other suitable materials, or combinations of the above materials. In some embodiments, the semiconductor layer 130 includes polysilicon.

[0049] The gate 110 (which may also be referred to as the top gate) and the gate 120 (which may also be referred to as the gate or the protrusion gate) of the thin film transistor 10 may be located on opposite sides of the semiconductor layer 130. For example, the gate 110 may be located above the semiconductor layer 130, i.e., on the side away from the substrate 100, and the gate 120 may be located on the lower side of the semiconductor layer 130, i.e., on the side close to the substrate 100. For example, the gate 120 is located between the semiconductor layer 130 and the substrate 100, but is not limited thereto. In some embodiments, the orthographic projections of the gate 110 and the gate 120 (gate) on the substrate 100 are both within the orthographic projection of the semiconductor layer 130 on the substrate 100.

[0050] The gate 110 and the gate 120 may be electrically connected or connected to the same voltage source. For example, the gate 110 is electrically connected to the gate 120 through a via hole V0, as Figure 1A shown. In some embodiments, the materials of the gate 110 and the gate 120 (gate) may include metals with good conductivity, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), or neodymium (Nd), or alloys of any combination of the above metals. In some embodiments, the gate 110 and the gate 120 may also use other conductive materials, such as: nitrides of metals, oxides of metals, oxynitrides of metals, stack layers of metals and other conductive materials, or other materials with conductive properties. In some embodiments, the gate 110 and the gate 120 each independently include a single-layer or multi-layer structure.

[0051] The gate insulating layer 170 is located between the gate 110 and the semiconductor layer 130, and electrically separates the gate 110 from the semiconductor layer 130. Similarly, the gate insulating layer 160 is located between the gate 120 and the semiconductor layer 130, and electrically separates the gate 120 from the semiconductor layer 130. The gate insulating layer 160 may cover the gate 120. In some embodiments, the thickness of the gate insulating layer 160 may be greater than the thickness of the gate insulating layer 170, but is not limited thereto. In some embodiments, the thicknesses of the gate 110 and the gate 120 may be the same, but is not limited thereto. Additionally, the materials of the gate insulating layer 160 and the gate insulating layer 170 (gate insulating layer) may include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), dielectric polymers, or other suitable materials or laminates of the above materials, but are not limited thereto.

[0052] In some embodiments, the semiconductor layer 130 is located between the gate insulating layer 160 and the gate insulating layer 170. The semiconductor layer 130 may include a doped region 131, a doped region 132, and a channel region 133, where the doped region 131 and the doped region 132 are separated, and the channel region 133 connects the doped region 131 and the doped region 132. The channel region 133 may overlap the entire gate 110, that is, in the direction D1 from the source 150 to the drain 140, the gate 110 and the channel region 133 may have the same size L. In some embodiments, the size L is about 5 μm to 7 μm. In some embodiments, the size L is about 3 μm to 5 μm. In some embodiments, the size L is about 1.2 μm to 3 μm.

[0053] In the direction D1 from the source 150 to the drain 140, the size of the gate 120 may be greater than the size L of the gate 110. For example, the gate 120 overlaps the entire channel region 133 and a part of the doped region 131. In some embodiments, in the direction D1 from the source 150 to the drain 140, the size L1 of the part of the gate 120 overlapping the doped region 131 is about 40% to 133% relative to the size L of the gate 110, that is, L1 = (40% - 133%)L. For example, when the size L is 3 μm to 5 μm, the size L1 may be about 2 μm to 4 μm. In some embodiments, the size L1 is about 50% to 90% or about 60% to 80% relative to the size L. By making the size L1 be about 40% to 133% relative to the size L, Ion can be increased and Id% can be reduced when the feature size L is less than 10 μm, thereby preventing the kink effect from occurring.

[0054] In some embodiments, the gate 120 also overlaps a part of the doped region 132. In some embodiments, in the direction D1 from the source 150 to the drain 140, the size L2 of the part of the gate 120 overlapping the doped region 132 is about 20% to 100% relative to the size L of the gate 110, that is, L2 = (20% - 100%)L. For example, when the size L is 3 μm to 5 μm, the size L2 may be about 1 μm to 3 μm. In some embodiments, the size L2 is about 30% to 90% or about 40% to 80% relative to the size L. By making the size L2 be about 20% to 100% relative to the size L, Ion can also be increased and Id% can be maintained in a relatively low range when the feature size L is less than 10 μm, thereby helping to prevent the kink effect from occurring.

[0055] In some embodiments, in the direction D1 from the source 150 to the drain 140, the size of the gate 120 is approximately equal to 80%, 90%, or 100% of the size of the semiconductor layer 130. In some embodiments, as in Figure 1BIn the cross-sectional view shown, the orthogonal projection of the central axis C1 of the semiconductor layer 130 onto the substrate 100 does not overlap with the orthogonal projection of the central axis C2 of the gate 120 onto the substrate 100. In some embodiments, in the top view as shown in Figure 1A the orthogonal projection of the gate 120 onto the substrate 100 overlaps with the orthogonal projection of the drain 140 onto the substrate 100, but does not overlap with the orthogonal projection of the source 150 onto the substrate 100.

[0056] The doped region 131 may include a lightly doped region 135 and a heavily doped region 137. In some embodiments, the lightly doped region 135 is located between the heavily doped region 137 and the channel region 133, and in the direction D1 from the source 150 to the drain 140, the dimension L3 of the portion of the gate 120 overlapping with the heavily doped region 137 may be about 2% to 120% relative to the dimension L of the gate 110, that is, L3 = (2% - 120%)L. For example, when the dimension L is 3 μm to 5 μm, the dimension L3 may be about 0.1 μm to 3.6 μm. In some embodiments, the dimension L3 is about 5% to 30% or about 10% to 20% relative to the dimension L.

[0057] The doped region 132 may include a lightly doped region 134 and a heavily doped region 136. In some embodiments, the lightly doped region 134 is located between the heavily doped region 136 and the channel region 133, and in the direction D1 from the source 150 to the drain 140, the dimension L4 of the portion of the gate 120 overlapping with the heavily doped region 136 may be about 0% to 90% relative to the dimension L of the gate 110, that is, L4 = (0% - 90%)L. For example, when the dimension L is 3 μm to 5 μm, the dimension L2 may be about 0 μm to 2.6 μm. In some embodiments, the dimension L4 is about 3% to 15% or about 5% to 10% relative to the dimension L.

[0058] The drain 140 of the thin film transistor 10 may be electrically connected to the doped region 131 of the semiconductor layer 130, and the source 150 of the thin film transistor 10 may be electrically connected to the doped region 132 of the semiconductor layer 130. For example, the drain 140 may be electrically connected to the doped region 131 of the semiconductor layer 130 through a via hole V1 in the planarization layer 180, and the source 150 may be electrically connected to the doped region 132 of the semiconductor layer 130 through a via hole V2 in the planarization layer 180. In some embodiments, the doped region 131 and the doped region 132 of the semiconductor layer 130 may further contain dopants as needed, such as hydrogen, boron, or phosphorus.

[0059] In some embodiments, the materials of the drain 140 and the source 150 may each include a metal, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or an alloy of any combination of the above metals or a stack of the above metals and / or alloys, but the present invention is not limited thereto. The drain 140 and the source 150 may also use other conductive materials, such as: nitrides of metals, oxides of metals, oxynitrides of metals, stack layers of metals and other conductive materials, or other materials having conductive properties. In some embodiments, the drain 140 and the source 150 each have a single-layer structure or a multi-layer structure. In some embodiments, the drain 140 and the source 150 each include a stack layer of tungsten-nickel alloy (WNi) and copper.

[0060] In some embodiments, the thin-film transistor 10 may further include a planarization layer 180, and the planarization layer 180 may cover the gate 110 to be in contact with the gate insulating layer 170 (gate insulation layer). The material of the planarization layer 180 may include a transparent insulating material, such as acrylic, siloxane polymer, polyimide, epoxy resin, etc., but is not limited thereto.

[0061] Figure 2A is a graph showing the relationship between the on current (Ion) and the drain current change rate (Id%) of the thin-film transistor 10 according to an embodiment of the present invention as a function of the dimension L1. From Figure 2A it can be seen that the Id% of the thin-film transistor 10 decreases as the dimension L1 increases, and when the dimension L1 is from about 2 μm to 4 μm, the thin-film transistor 10 has a relatively high Ion. For example, the Ion can be maintained at about 4.0E-04 or more.

[0062] Figure 2B is a graph showing the relationship between the off current (Ioff) of the thin-film transistor 10 according to an embodiment of the present invention as a function of the dimension L1. From Figure 2B it can be seen that the Ioff of the thin-film transistor 10 decreases as the dimension L1 increases. When the dimension L1 is from about 2 μm to 4 μm, the Ioff of the thin-film transistor 10 can be maintained at about 5E-13 or less.

[0063] Figure 3A is a graph showing the relationship between the Ion of the thin-film transistor 10 according to an embodiment of the present invention as a function of the dimension L2. From Figure 3A it can be seen that when the dimension L2 is from about 1 μm to 3 μm, the Ion of the thin-film transistor 10 can be maintained at about 4.04E-4 or more.

[0064] Figure 3Bis a graph showing the relationship between the Id% of the thin film transistor 10 according to an embodiment of the present invention and the size L2. From Figure 3B it can be seen that when the size L2 is from about 1 μm to 3 μm, the Id% of the thin film transistor 10 can be maintained below about 1.7%. In addition, it is worth noting that the lower Id% of the thin film transistor 10 when the size L2 is from about -1 μm to 1 μm should be due to the size L1 being between about 2 μm and 4 μm.

[0065] Figure 4A is a graph showing the relationship between Ion and the Ion degradation after strain of the thin film transistor 10 according to an embodiment of the present invention at the initial operation (T0) and after experiencing 100 seconds of self-heating stress (T100) with respect to the size L1. The self-heating stress is carried out at a gate voltage (Vg) of -15 V, a drain voltage (Vd) of -25 V, and a temperature of 60 °C. From Figure 4A it can be seen that the Ion degradation after strain of the thin film transistor 10 generally decreases as the size L1 increases.

[0066] Figure 4B is a graph showing the relationship between Ioff of the thin film transistor 10 according to an embodiment of the present invention at the initial operation (T0) and after experiencing 100 seconds of self-heating stress (T100) with respect to the size L1. From Figure 4B it can be seen that the Ioff after strain of the thin film transistor 10 generally decreases as the size L1 increases.

[0067] In summary, the thin film transistor of the present invention can increase Ion, reduce Id% and Ioff, and also reduce the Ion degradation after strain and the Ioff after strain by making the protruding gate protrude from the top gate toward the drain by about 40% to 133% of the size of the top gate, so as to improve the electrical properties of the thin film transistor and prevent the kink effect from occurring when the feature size L is less than 10 μm. In addition, the thin film transistor of the present invention can also increase Ion and maintain Id% in a relatively low range by making the protruding gate protrude from the top gate toward the source by about 20% to 100% of the size of the top gate when the feature size L is less than 10 μm.

[0068] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field to which the present invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

Claims

1. A thin film transistor, characterized in that, Comprising: A semiconductor layer including a first doped region, a second doped region, and a channel region, wherein the first doped region and the second doped region are separated, and the channel region connects the first doped region and the second doped region; A first gate located above the semiconductor layer, wherein the channel region overlaps the entire first gate; A first gate insulating layer located between the first gate and the semiconductor layer; A drain electrically connected to the first doped region of the semiconductor layer; A source electrically connected to the second doped region of the semiconductor layer; A second gate insulating layer, wherein the semiconductor layer is located between the second gate insulating layer and the first gate insulating layer; And A second gate, wherein the second gate insulating layer is located between the second gate and the semiconductor layer, the second gate overlaps the entire channel region and a part of the first doped region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the first doped region is 40% to 133% of the size of the first gate.

2. The thin film transistor according to claim 1, wherein The size of the part of the second gate overlapping the first doped region is 2 μm to 4 μm.

3. The thin film transistor according to claim 1, characterized in that, The first doped region includes a first lightly doped region and a first heavily doped region, the first lightly doped region is located between the first heavily doped region and the channel region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the first heavily doped region is 2% to 120% of the size of the first gate.

4. The thin film transistor according to claim 1, wherein, The second gate also overlaps a part of the second doped region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the second doped region is 20% to 100% of the size of the first gate.

5. The thin film transistor according to claim 4, wherein The size of the part of the second gate overlapping the second doped region is 1 μm to 3 μm.

6. The thin film transistor according to claim 4, wherein, The second doped region includes a second lightly doped region and a second heavily doped region, the second lightly doped region is located between the second heavily doped region and the channel region, and in the direction from the source to the drain, the size of the part of the second gate overlapping the second heavily doped region is 0% to 90% of the size of the first gate.

7. The thin film transistor according to claim 1, characterized in that, The central axis of the semiconductor layer does not overlap the central axis of the second gate.

8. The thin film transistor according to claim 1, wherein The orthographic projection of the second gate on the substrate overlaps the orthographic projection of the drain on the substrate, but does not overlap the orthographic projection of the source on the substrate.

9. The thin film transistor according to claim 1, characterized in that, The first gate and the second gate are electrically connected.

10. The thin film transistor according to claim 1, characterized in that, The drain current change rate, the off-state current after strain, and the on-state current decay after strain of the thin film transistor decrease as the size of the part of the second gate overlapping the first doped region increases in the direction from the source to the drain.

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