Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same, belonging to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, forming a gate structure on the substrate; forming a repair oxide layer on the substrate and the sidewalls of the gate structure and performing vertical etching, retaining the repair oxide layer on the sidewalls of the gate structure; sequentially forming a lightly doped region, a transition region, and a heavily doped region from bottom to top in the substrate on both sides of the gate structure; forming a fully covered first etch stop layer on the substrate and etching to form an opening; forming a compensating epitaxial layer in the opening; removing the first etch stop layer, metallizing at least the compensating epitaxial layer and the substrate to form a metal silicide layer; then forming a second etch stop layer and an interlayer dielectric layer, and etching to the metal silicide layer to form a connection hole; forming a conductive plug in the connection hole. The present invention can simplify the manufacturing process, improve manufacturing efficiency, and simultaneously improve the performance and yield of semiconductor devices.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, integrated circuit chips are moving towards higher semiconductor device density and higher integration. As the feature size of semiconductor devices continues to shrink, the distance between adjacent gate structures decreases. During the manufacturing process, this leads to insufficient etching windows for metal silicide and contact holes (CTs), which can damage the lightly doped regions, resulting in high horizontal resistance and semiconductor device failure under high voltage. Alternatively, during the formation of conductive plugs, the contact holes may not be etched, causing CT short circuits and affecting the yield of semiconductor devices. Furthermore, as the physical gate length drops below 30nm, the parasitic resistance of the source and drain becomes non-negligible relative to the channel resistance, and ion implantation cannot reduce the source-drain parasitic resistance. Summary of the Invention

[0003] The present invention aims to provide a semiconductor device and a method for manufacturing the same. The semiconductor device and method provided by the present invention can simplify the manufacturing process and improve manufacturing efficiency while ensuring device performance. Furthermore, the distance between gate structures is increased, the etching window for connection holes is widened, the difficulty of etching the connection holes is reduced, and the quality of the connection holes is improved. Furthermore, the method can reduce costs, prevent hot carrier effects, change the trajectory of device carriers, and improve the yield of semiconductor devices.

[0004] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising at least the following steps:

[0005] providing a substrate, and forming a gate structure on the substrate;

[0006] forming a repair oxide layer on the substrate and the sidewalls of the gate structure;

[0007] vertically etching the repair oxide layer to retain the repair oxide layer on the sidewall of the gate structure;

[0008] forming a lightly doped region, a transition region and a heavily doped region in the substrate on both sides of the gate structure in sequence from bottom to top;

[0009] forming a fully covering first etch stop layer on the substrate and etching to form an opening, wherein the opening exposes a portion of the heavily doped region and at least a portion of the gate structure;

[0010] forming a compensation epitaxial layer in the opening;

[0011] removing the first etch stop layer, and metallizing at least the compensation epitaxial layer and the substrate to form a metal silicide layer;

[0012] forming a second etch stop layer and an interlayer dielectric layer on the substrate and the metal silicide layer;

[0013] Etching the interlayer dielectric layer to the metal silicide layer to form a connection hole;

[0014] A conductive plug is formed in the connection hole.

[0015] In one embodiment of the present invention, the manufacturing method further comprises the following steps:

[0016] forming a gate dielectric layer, a gate material layer, a multi-layer hard mask layer and a first photoresist layer in sequence on the substrate;

[0017] Using the first photoresist layer as a mask, etching the multi-layer hard mask layer, the gate material layer, and the gate dielectric layer to form a gate structure, wherein the first hard mask layer exists on the gate structure; and

[0018] The repair oxide layer is formed by thermal oxidation or in-situ water vapor growth, and the thickness of the repair oxide layer on the substrate is less than the thickness on the sidewall of the gate structure.

[0019] In one embodiment of the present invention, the manufacturing method further includes:

[0020] After etching the repair oxide layer, forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer exposes an area of ​​the substrate;

[0021] Using the patterned photoresist layer as a mask, ion implantation is performed perpendicular to the substrate to form lightly doped regions on both sides of the gate structure;

[0022] Adjusting the ion implantation angle to perform tilted ion implantation to form transition regions on both sides of the gate structure; and

[0023] Ion implantation is performed again perpendicular to the substrate to form heavily doped regions on both sides of the gate structure. In the same region, the lightly doped region, the transition region, and the heavily doped region have the same doping type.

[0024] In one embodiment of the present invention, when performing tilted ion implantation, the tilted implantation angle is the angle between the implantation direction and the substrate, and the implantation angle is 60° to 85°.

[0025] In one embodiment of the present invention, the doping concentration of the lightly doped region is less than the doping concentration of the transition region, the doping concentration of the transition region is less than the doping concentration of the heavily doped region, and the doping depth of the lightly doped region is greater than the doping depth of the transition region, and the doping depth of the transition region is greater than the doping depth of the heavily doped region.

[0026] In one embodiment of the present invention, adjacent to a side of the gate structure, a boundary of the heavily doped region is aligned with a boundary of the lightly doped region, and a boundary of the transition region exceeds the boundary of the heavily doped region.

[0027] In one embodiment of the present invention, the manufacturing method further includes:

[0028] forming a bottom anti-reflection layer and a first photoresist layer on the first etch stop layer;

[0029] exposing and developing the first photoresist layer and the bottom anti-reflection layer through a mask to form a first opening, wherein the first opening exposes a portion of the first etch stop layer, and the mask is the same as the mask used to form the connecting hole;

[0030] dry-etching the first etch-stop layer at the bottom of the first opening to form a second opening;

[0031] Laterally etching the first etch-stop layer exposed by the second opening to form a third opening; and

[0032] The first photoresist layer and the bottom anti-reflection layer are removed to form a fourth opening, wherein the fourth opening at least exposes a portion of the gate structure and a portion of the heavily doped region.

[0033] In one embodiment of the present invention, the metal silicide layer on the heavily doped region includes a first portion and a second portion, the first portion is obtained by metallization treatment of the compensation epitaxial layer and is formed on the substrate, the second portion is obtained by metallization treatment of the substrate and extends from the surface of the substrate into the substrate, and the connection between the first portion and the second portion is arc-shaped.

[0034] In one embodiment of the present invention, a depth of the second portion in the substrate is smaller than a depth of the transition region.

[0035] The present invention also provides a semiconductor device, which is obtained by the above-mentioned manufacturing method and at least comprises

[0036] a substrate, on which a gate structure and a repair oxide layer on both sides of the gate structure are provided;

[0037] Lightly doped regions are provided in the substrate on both sides of the gate structure;

[0038] a transition region, disposed in the substrate on both sides of the gate structure and located on the lightly doped region;

[0039] a heavily doped region, disposed in the substrate on both sides of the gate structure and located on the transition region;

[0040] a metal silicide layer, disposed at least on the heavily doped region and the gate structure, and protruding from surfaces of the substrate and the gate structure;

[0041] a second etch stop layer, disposed at least on the substrate and the repair oxide layer;

[0042] an interlayer dielectric layer, disposed on the substrate and the metal silicide layer;

[0043] The conductive plug is arranged in the interlayer dielectric layer.

[0044] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. By improving the semiconductor device and its method for manufacturing, the unexpected technical effect of the present application is that it can ensure the morphology and structural integrity of the gate structure, repair etching damage during the formation of the gate structure, and improve the yield of the semiconductor device. While ensuring device performance, it can simplify the manufacturing process and improve manufacturing efficiency. At the same time, it can increase the distance between gate structures, increase the etching window of the connection hole, reduce the etching difficulty of the connection hole, and improve the quality of the connection hole. Different doping regions can be formed through the same photoresist layer, which can reduce the number of photoresists and reduce costs. The channel length of the semiconductor device can be increased without changing the width of the gate structure, thereby reducing the leakage current Ioff of the device. Stress can be better transferred to the channel, which can better improve the carrier mobility rate, thereby improving device performance. The metal silicide layer formed with a special structure can deplete the ion concentration near the channel in the heavily doped region, blocking the movement of electrons and holes. On the one hand, it can prevent hot carrier effects, and on the other hand, it can change the movement trajectory of the device carriers. This ensures that the range of the metal silicide layer formed is larger than the range of the contact hole. During contact hole formation, damage to the heavily and lightly doped regions can be avoided in the event of problems such as increased critical dimensions, overlay offset, or over-etching of the contact holes, thereby improving device quality. This prevents the height of the active region and gate structure from being consumed, effectively preventing the consumption of dopant ions in the heavily and lightly doped regions, reducing drain leakage current and ensuring device performance. It also reduces the contact hole etching height, thereby reducing the difficulty of contact hole etching, avoiding contact hole disconnection, and improving the performance and yield of semiconductor devices.

[0045] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 Schematic diagram of a gate dielectric layer, a gate material layer, a multi-layer hard mask layer and a first photoresist layer on a substrate in one embodiment of the present invention.

[0048] Figure 2 FIG. 1 is a schematic diagram of forming a gate structure according to an embodiment of the present invention.

[0049] Figure 3 FIG. 1 is a schematic diagram of removing the second hard mask layer and forming a repair oxide layer in one embodiment of the present invention.

[0050] Figure 4 This is a schematic diagram of etching and repairing the oxide layer in one embodiment of the present invention.

[0051] Figure 5 FIG. 1 is a schematic diagram of forming a lightly doped region, a transition region, and a heavily doped region in the second region in one embodiment of the present invention.

[0052] Figure 6 Schematic diagram of forming a lightly doped region, a transition region and a heavily doped region in a first region in one embodiment of the present invention.

[0053] Figure 7 FIG. 1 is a schematic diagram of forming a buffer layer and a first stress layer in one embodiment of the present invention.

[0054] Figure 8 FIG. 1 is a schematic diagram of forming a first etch stop layer, a bottom anti-reflective layer, and a first photoresist layer in accordance with an embodiment of the present invention.

[0055] Figure 9 FIG. 1 is a schematic diagram of forming a first opening in a bottom anti-reflective layer and a first photoresist layer according to an embodiment of the present invention.

[0056] Figure 10 FIG. 1 is a schematic diagram of etching the first etch stop layer at the bottom of the first opening to form a second opening in one embodiment of the present invention.

[0057] Figure 11 FIG. 1 is a schematic diagram of forming a third opening by laterally etching the first etch stop layer exposed by the second opening in one embodiment of the present invention.

[0058] Figure 12 FIG. 1 is a schematic diagram of removing the bottom anti-reflective layer and the first photoresist layer to form a fourth opening according to an embodiment of the present invention.

[0059] Figure 13 FIG. 1 is a schematic diagram of forming a compensation epitaxial layer in one embodiment of the present invention.

[0060] Figure 14 FIG. 1 is a schematic diagram of an embodiment of the present invention after the first etch stop layer is removed.

[0061] Figure 15 FIG. 4 is a schematic diagram of forming a metal silicide layer according to an embodiment of the present invention.

[0062] Figure 16 FIG. 1 is a schematic diagram of forming a second etch stop layer, an interlayer dielectric layer, a hard mask layer, and a photomask layer in accordance with an embodiment of the present invention.

[0063] Figure 17 FIG. 1 is a schematic diagram of a connection hole formed in one embodiment of the present invention.

[0064] Figure 18 FIG. 1 is a schematic diagram of a barrier layer and a conductive structure formed in one embodiment of the present invention.

[0065] Description of labels:

[0066] 10. Substrate; 100. First region; 200. Second region; 101. First well region; 102. Second well region; 11. Shallow trench isolation structure; 12. Gate dielectric layer; 13. Gate material layer; 14. Hard mask layer; 141. First hard mask layer; 142. Second hard mask layer; 143. Third hard mask layer; 144. Fourth hard mask layer; 145. Fifth hard mask layer; 146. Sixth hard mask layer; 15. Gate structure; 151. First photoresist layer; 16. Repair oxide layer; 17. First patterned photoresist layer; 18. First lightly doped region; 19. First transition region; 20. First heavily doped region; 21. Second patterned photoresist layer; 22. second lightly doped region; 23. second transition region; 24. second heavily doped region; 25. buffer layer; 26. first stress layer; 27. first etch stop layer; 28. bottom anti-reflection layer; 29. ​​first photoresist layer; 291. first opening; 292. second opening; 293. third opening; 294. fourth opening; 30. compensation epitaxial layer; 31. metal silicide layer; 311. first division; 312. second division; 32. second etch stop layer; 33. interlayer dielectric layer; 34. etch mask layer; 35. photomask layer; 351. recess; 352. connection hole; 36. barrier layer; 37. conductive structure; 38. conductive plug. DETAILED DESCRIPTION

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0069] In the description of this specification, it should be understood that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "front," "back," "left," and "right" are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this solution and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific direction, be constructed, or operate in a specific direction. Therefore, they should not be construed as limitations on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0070] The present invention provides a semiconductor device and a method for manufacturing the same, which can simplify the manufacturing process and improve manufacturing efficiency while ensuring device performance. The method also increases the distance between gate structures, increases the etching window for connection holes, reduces the difficulty of etching the connection holes, and improves the quality of the connection holes. Different doping regions can be formed through the same photoresist layer, which can reduce the number of photoresists and reduce costs. The channel length of the semiconductor device can be increased without changing the width of the gate structure, thereby reducing the leakage current Ioff of the device. When forming the connection holes, damage to the heavily doped and lightly doped regions can be avoided, effectively avoiding the consumption of doping ions in the heavily doped and lightly doped regions, reducing drain leakage current, and eliminating hot carrier effects. The potential barrier between the metal silicide layer and the substrate can be reduced, enabling bidirectional conduction in the channel. The etching height of the contact holes can be reduced, thereby reducing the difficulty of etching the contact holes, avoiding contact hole disconnection, and improving the performance and yield of the semiconductor device. The manufacturing method of the present invention can be widely applied to the preparation of different semiconductor devices, and the obtained semiconductor devices can be applied to various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, household appliances, and aerospace.

[0071] See also Figure 1As shown, a substrate 10 is provided. Substrate 10 can be any material suitable for forming a semiconductor device. Examples of substrate 10 include silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, a silicon wafer, or other semiconductor materials formed from III / V compounds. This also includes stacked structures composed of these semiconductor materials, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SLSI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). The present invention does not limit the type of substrate 10; it can be flexibly configured based on requirements and can be configured based on the type of semiconductor device. In this embodiment, substrate 10 is, for example, a doped silicon wafer, and the doping type can be either P-type or N-type.

[0072] See also Figure 1As shown, in one embodiment of the present invention, a plurality of semiconductor devices are formed on a substrate 10 , and the present invention does not limit the types of semiconductor devices. The semiconductor device may be, for example, a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a thyristor, a charge coupled device (CCD image sensor), a constant voltage diode, a high frequency diode, a light-emitting diode (LED), a gate turn off thyristor (GTO), a digital signal processor (DSP), a fast recovery diode (FRD), a high-speed and high-efficiency rectifier diode (HED), a light triggered thyristor (LTT), a photo relay or a microprocessor, and the specific selection may be made during the manufacturing process. In this embodiment, the substrate 10 includes a first region 100 and a second region 200 , wherein the first region 100 is used to form an NMOS transistor, and the second region 200 is used to form a PMOS transistor. The NMOS transistor and the PMOS transistor are isolated by a shallow trench isolation structure 11 .

[0073] See also Figure 1 As shown, in one embodiment of the present invention, a first well region 101 and a second well region 102 are provided within substrate 10. First well region 101 is provided within first region 100 and is doped with P-type dopant ions, such as boron (B) or gallium (Ga). Second well region 102 is provided within second region 200 and is doped with N-type dopant ions, such as phosphorus (P) or arsenic (As). In this embodiment, the implantation depths of first well region 101 and second well region 102 are, for example, equal, or less than or equal to the depth of shallow trench isolation structure 11.

[0074] See also Figure 1As shown, in one embodiment of the present invention, after forming the well region, a gate dielectric layer 12, a gate material layer 13, a hard mask layer 14, and a first photoresist layer 151 are sequentially formed on the substrate 10. The gate dielectric layer 12 is, for example, silicon dioxide or a high-k dielectric layer, and is formed, for example, by thermal oxidation, in-situ steam generation (ISSG), or chemical vapor deposition (CVD). The thickness of the gate dielectric layer 12 is, for example, 8Å to 50Å, or, for example, 8Å to 15Å. The gate material layer 13 is, for example, polysilicon, and is formed, for example, by chemical vapor deposition. The thickness of the gate material layer 13 is, for example, 50nm to 200nm, and is selected based on the type of semiconductor device and manufacturing requirements. The hard mask layer 14 may have a multi-layer structure. In this embodiment, the hard mask layer 14 may include, for example, a first hard mask layer 141, a second hard mask layer 142, a third hard mask layer 143, a fourth hard mask layer 144, a fifth hard mask layer 145, and a sixth hard mask layer 146. The first hard mask layer 141 and the third hard mask layer 143 may be, for example, silicon oxide layers, the second hard mask layer 142 may be a silicon nitride layer, the fourth hard mask layer 144 may be an amorphous carbon layer, the fifth hard mask layer 145 may be a mixed material of silicon oxynitride and silicon oxide to serve as an anti-reflective layer, and the sixth hard mask layer 146 may be a resin-based composite material to serve as a bottom anti-reflective layer (BARC). The present application does not limit the formation method and thickness of each layer, which may be selected based on specific manufacturing requirements. A first photoresist layer 151 is disposed on the hard mask layer 14 to position the gate structure. By providing the multi-layer hard mask layer 14 , accurate etching can be performed during the manufacturing process to ensure the morphology and structural integrity of the gate structure, thereby improving the performance of the semiconductor device.

[0075] See also Figures 1 to 2 As shown, in one embodiment of the present invention, after forming a first photoresist layer 151, a multi-step etching process is performed using the first photoresist layer 151 as a mask, sequentially etching the hard mask layer 14, the gate material layer 13, and the gate dielectric layer 12 to form a gate structure 15. In this embodiment, the etching is performed, for example, by dry etching, and the etching gas includes, for example, chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a mixture thereof, or a mixture thereof with oxygen (O2). During the etching process, the etching gas is changed when different materials are etched. After the first photoresist layer 151 is removed during the etching process, etching continues using the hard mask layer 14 as a mask until the etching is complete. In this embodiment, after the gate structure 15 is formed, for example, the first hard mask layer 141 and the second hard mask layer 142 remain on the gate structure 15.

[0076] See also Figures 2 to 3 As shown, in one embodiment of the present invention, after the gate structure 15 is formed, the second hard mask layer 142 is removed, for example, by wet etching. The wet etching solution is, for example, phosphoric acid, and the mass fraction of phosphoric acid is 80% to 95%, and the etching temperature is 155°C to 165°C. After removing the second hard mask layer 142, a repair oxide layer 16 is formed on the substrate 10 and the sidewalls of the gate structure 15, for example, by thermal oxidation or in-situ water vapor growth. The repair oxide layer 16 is, for example, a silicon oxide layer, and since the oxidation rate of polycrystalline silicon is greater than that of single crystal silicon, the thickness of the repair oxide layer 16 on the substrate 10 is less than the thickness of the repair oxide layer 16 on the sidewalls of the gate structure 15. By forming the repair oxide layer 16, the etching damage in the process of forming the gate structure 15 can be repaired, thereby improving the yield of the semiconductor device.

[0077] See also Figures 3 and 4 As shown, in one embodiment of the present invention, after forming the repair oxide layer 16, vertical etching is performed, and the vertical etching is, for example, dry etching. During the etching process, for example, the substrate 10 is used as an etching stop layer to remove the etched repair oxide layer 16 and the first hard mask layer 141 in the horizontal direction. Since the thickness of the repair oxide layer 16 on the gate structure 15 is large, after etching, the remaining repair oxide layer 16 on both sides of the gate structure 15 serves as a sidewall structure of the gate structure, which can simplify the manufacturing process and improve manufacturing efficiency while ensuring device performance. At the same time, the thickness of the repair oxide layer 16 is relatively small. As a sidewall structure, it can increase the distance between gate structures, increase the etching window of the connection hole, reduce the etching difficulty of the connection hole, and improve the quality of the connection hole.

[0078] See also Figures 4 and 5 As shown, in one embodiment of the present invention, after etching and repairing the oxide layer 16, a first patterned photoresist layer 17 is formed on the substrate 10. The first patterned photoresist layer 17 exposes the second region 200. Using the first patterned photoresist layer 17 as a mask, multiple ion implantations are performed to form a first lightly doped region 18, a first transition region 19, and a first heavily doped region 20 from bottom to top. The doping ion type in the first lightly doped region 18, the first transition region 19, and the first heavily doped region 20 is opposite to the doping ion type in the second well region 102. In this embodiment, the doping ions are, for example, boron or boron fluoride ions (BF2 + ) and other P-type ions.

[0079] See also Figures 4 and 5As shown, in one embodiment of the present invention, after forming the first patterned photoresist layer 17, ion implantation is first performed perpendicular to the substrate to form a first lightly doped region 18 in the substrate 10 on both sides of the gate structure 15 in the second region 200. The ion implantation angle is then adjusted to perform tilted ion implantation to form a first transition region 19 on both sides of the gate structure 15. The tilted implantation angle is, for example, the angle between the implantation direction and the substrate. In this embodiment, the implantation angle is, for example, 60° to 85°, or 70° to 75°. Finally, ion implantation is performed perpendicular to the substrate to form a first heavily doped region 20 on both sides of the gate structure 15. On the side adjacent to the gate structure 15, the boundary of the first heavily doped region 20 is aligned with the boundary of the first lightly doped region 18, and the boundary of the first transition region 19 exceeds the boundary of the first heavily doped region 20, i.e., the first transition region 19 surrounds the first heavily doped region 20. In one embodiment of the present invention, the edge of the first transition region 19 is located below and partially overlaps the gate structure 15. The boundary of the first lightly doped region 18 is aligned with the side of the repaired oxide layer 16 away from the gate structure 15. The doping concentration of the first lightly doped region 18 is lower than that of the first transition region 19, which in turn is lower than that of the first heavily doped region 20. During ion implantation, the ion implantation energy in the first lightly doped region 18 is higher than that in the first transition region 19, which in turn is higher than that in the first heavily doped region 20. Therefore, the doping depth of the first lightly doped region 18 is higher than that in the first transition region 19, which in turn is higher than that in the first heavily doped region 20. Multiple ion implantations allow different doping regions to be formed within the same photoresist layer, reducing the number of photoresists and lowering costs. Forming the first transition region 19 prevents hot carrier effects and improves channel conductivity.

[0080] See also Figures 5 and 6 As shown, in one embodiment of the present invention, after forming the first heavily doped region 20, the first patterned photoresist layer 17 is removed, for example, by ashing or wet etching, to form a second patterned photoresist layer 21 on the substrate 10. The second patterned photoresist layer 21 exposes the first region 100. Using the first patterned photoresist layer 17 as a mask, multiple ion implantations are performed to form, from bottom to top, a second lightly doped region 22, a second transition region 23, and a second heavily doped region 24. The doping ion type in the second lightly doped region 22, the second transition region 23, and the second heavily doped region 24 is opposite to the doping ion type in the first well region 101. In this embodiment, the doping ions are, for example, N-type ions such as phosphorus or arsenic.

[0081] See also Figures 5 and 6As shown, in one embodiment of the present invention, after forming the second patterned photoresist layer 21, ion implantation is first performed perpendicular to the substrate to form a second lightly doped region 22 within the substrate 10 on both sides of the gate structure 15 in the first region 100. The ion implantation angle is then adjusted to perform tilted ion implantation to form a second transition region 23 on both sides of the gate structure 15. The implantation angle is, for example, 60° to 85°, or 70° to 75°, depending on the overlap between the second transition region 23 and the gate structure 15. Finally, ion implantation is performed perpendicular to the substrate to form a second heavily doped region 24 on both sides of the gate structure 15. On the side adjacent to the gate structure 15, the edge of the second heavily doped region 24 is aligned with the edge of the second lightly doped region 22, and the boundary of the second transition region 23 exceeds the boundary of the second heavily doped region 24, i.e., the second transition region 23 surrounds the second heavily doped region 24. In a specific embodiment of the present invention, the edge of the second transition region 23 is located below the gate structure 15 and partially overlaps with the gate structure 15. The boundary of the second lightly doped region 22 is aligned with the side of the repaired oxide layer 16 away from the gate structure 15. The doping concentration of the second lightly doped region 22 is lower than the doping concentration of the second transition region 23, which is lower than the doping concentration of the second heavily doped region 24. During ion implantation, the ion implantation energy of the second lightly doped region 22 is higher than the ion implantation energy of the second transition region 23, which is higher than the ion implantation energy of the second transition region 23. Therefore, the doping depth of the second lightly doped region 22 is higher than the doping depth of the second transition region 23, which is higher than the doping depth of the second heavily doped region 24. In this application, the relationship between the doping concentration and doping depth among the lightly doped regions, transition regions, and heavily doped regions in different regions is not limited, and the design and fabrication are specifically based on the requirements of the semiconductor devices in different regions. Through multiple ion implantations, different doped regions can be formed within the same photoresist layer, reducing the amount of photoresist and lowering costs. Forming the second transition region 23 prevents hot carrier effects and improves channel conductivity. By controlling the implantation angle of the transition region, the overlap between the transition region and the gate structure can be controlled. This increases the channel length of the semiconductor device without changing the gate structure width, thereby reducing the device's leakage current, Ioff.

[0082] See also Figures 6 and 7As shown, in one embodiment of the present invention, after forming the second heavily doped region 24, a fully covering buffer layer 25 and a first stress layer 26 are sequentially formed on the substrate 10, and then the first stress layer 26 on the second region 200 is removed. The buffer layer 25 is, for example, a silicon oxide layer, and the thickness of the buffer layer 25 is, for example, 5 nm to 15 nm. The first stress layer 26 is, for example, a silicon nitride layer, and the thickness of the first stress layer 26 is, for example, 10 nm to 25 nm. The first stress layer 26 has tensile stress. Spike annealing, for example, annealing at 1050°C to 1070°C, is used to activate the dopant ions in the doped region. Laser annealing is then performed at 1000°C to 1300°C to transfer the stress of the first stress layer 26 to the channel in the first region 100. After annealing is completed on the first region 100, the first stress layer 26 is removed, and a second stress layer (not shown) is formed on the second region 200. The second stress layer is a silicon nitride layer with compressive stress. Annealing is then performed to transfer stress to the channel in the second region 200. After annealing, the second stress layer and buffer layer 25 are removed. In this application, a multi-layer sidewall structure is not provided, which can better transfer stress to the channel, better improve the carrier mobility rate, and thus enhance device performance.

[0083] See also Figures 7 and 8 As shown, in one embodiment of the present invention, after removing the stress layer and the buffer layer, a first etch stop layer 27 is formed on the substrate 10. The first etch stop layer 27, for example, covers the repair oxide layer 16, the gate structure 15, the substrate 10, and the shallow trench isolation structure 11. The first etch stop layer 27 is, for example, a silicon nitride layer. The first etch stop layer 27 is obtained by, for example, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition. The thickness of the first etch stop layer 27 is, for example, 25 nm to 40 nm.

[0084] See also Figures 8 and 9 As shown, in one embodiment of the present invention, after forming the first etch stop layer 27, a bottom anti-reflective layer (BARC) 28 and a first photoresist layer 29 are formed on the first etch stop layer 27. The BARC 28 and the first photoresist layer 29 are formed, for example, by spin coating or doctor blade coating, and have smooth surfaces. The BARC 28 and the first photoresist layer 29 are composed of a resin-based composite material. A mask for forming connection holes is subsequently used, followed by exposure and development processes to form a first opening 291 in the first photoresist layer 29 and the BARC 28. The first opening 291 is located above the heavily doped region and the gate structure 15 and exposes a portion of the first etch stop layer 27.

[0085] See also Figures 9 to 11 As shown, in one embodiment of the present invention, after forming the first opening 291, the first etch-stop layer 27 at the bottom of the first opening 291 is removed, for example, by dry etching, to form a second opening 292. After forming the second opening 292, the first etch-stop layer 27 exposed by the second opening 292 is laterally etched, for example, by wet etching, to form a third opening 293. The wet etching solution is, for example, phosphoric acid with a mass fraction of 80% to 95%, and the etching temperature is 155°C to 165°C. The amount of lateral etching of the first etch-stop layer 27 is controlled by controlling the concentration of phosphoric acid, the etching temperature, and the etching time. In this embodiment, for example, the first etch-stop layer 27 on the gate structure 15 is removed, leaving a portion of the first etch-stop layer 27 on the heavily doped region. Forming the first opening through development can reduce the difficulty of etching. Furthermore, by using a mask for subsequently forming the connection hole to etch the first etch-stop layer, mask development can be reduced, lowering costs.

[0086] See also Figures 11 to 12 As shown, in one embodiment of the present invention, after lateral etching, the first photoresist layer 29 and the bottom anti-reflective layer 28 are removed, and a fourth opening 294 is formed on the gate structure 15 and the heavily doped region. The fourth opening 294 exposes a portion of the heavily doped region and at least a portion of the gate structure 15. In this embodiment, the fourth opening 294 exposes the entire gate structure 15 and a portion of the heavily doped region. The first photoresist layer 29 and the bottom anti-reflective layer 28 are removed, for example, by an asher process and wet etching. The asher process involves plasma treatment at 200°C to 300°C using oxygen or a mixture of oxygen, nitrogen, and hydrogen. The oxygen plasma removes the first photoresist layer 29 and the bottom anti-reflective layer 28, followed by wet etching using an organic solvent such as isopropyl alcohol. This ensures that no photoresist or bottom anti-reflective layer residue remains, thereby improving the yield of the semiconductor process. After forming the third opening 293 on the basis of a mask plate for subsequently forming a connection hole, etching is performed on both sides to form a fourth opening 294 for the subsequent formation of a compensation epitaxial layer and a metal silicide layer, ensuring that the range for forming the metal silicide layer is larger than the range for forming the connection hole. When the mask plate is subsequently used to form the connection hole, when problems such as the critical dimension (CD) of the connection hole becomes larger, overlay shift, or over-etching of the connection hole occur, damage to the heavily doped and lightly doped regions can be avoided, thereby improving device quality.

[0087] See also Figures 12 to 13As shown, in one embodiment of the present invention, after forming the fourth opening 294, a compensation epitaxial layer 30 is formed within the fourth opening 294. The compensation epitaxial layer 30 is, for example, a single crystal silicon layer, and its thickness is, for example, equal to the thickness of the first etch stop layer 27. Specifically, the compensation epitaxial layer 30 is formed, for example, by selective epitaxial growth, wherein the epitaxial growth gas source is, for example, silicon tetrachloride (SiCl4), trichlorosilane (SiHCl3), or dichlorosilane (SiH2Cl2), or a mixture thereof, and further, dichlorosilane, with a dichlorosilane flow rate of, for example, 200 sccm to 400 sccm, and the epitaxial growth temperature is, for example, 700°C to 900°C. During the formation of the compensation epitaxial layer 30, due to the presence of the first etch stop layer 27, the compensation epitaxial layer 30 is formed only on the substrate 10 and gate structure 15 exposed by the fourth opening 294.

[0088] See also Figures 13 and 14 As shown, in one embodiment of the present invention, after forming the compensation epitaxial layer 30, the first etch stop layer 27 is removed. In this embodiment, the first etch stop layer 27 is removed by, for example, wet etching, and the wet etching solution is, for example, phosphoric acid with a mass fraction of 80% to 95%, and the etching temperature is 155°C to 165°C.

[0089] See also Figures 14 and 15 As shown, in one embodiment of the present invention, after removing the first etch stop layer 27, at least the compensation epitaxial layer 30 and a portion of the substrate are metallized to form a metal silicide layer 31 to reduce subsequent contact resistance with the conductive plug. Specifically, a silicon oxide layer and a silicon nitride layer (not shown) are deposited on the substrate 10, the shallow trench isolation structure 11, the compensation epitaxial layer 30, and the repair oxide layer 16. The area where the metal silicide layer 31 is to be formed is then exposed by etching. A SiCoNi pre-cleaning process is performed to remove possible contaminants on the substrate 10 to improve the quality of the formed metal silicide layer 31. A layer of metal material (not shown) is then deposited, such as at least one of titanium, cobalt, or nickel. In this embodiment, a mixture of nickel and titanium is deposited, with a thickness of, for example, 10 nm to 15 nm. A titanium nitride layer (not shown) is formed on the metal material, with a thickness of, for example, 3 nm to 8 nm, to prevent oxidation of the metal material. The exposed substrate 10 and the compensation epitaxial layer 30 are metallized by rapid annealing, such as annealing at 260°C to 300°C for 30s to 40s, to form a high-resistance metal silicide Ni2PtSi, and then annealed at 400°C to 900°C for 30s to 40s to form a low-resistance NiPtSi2, i.e., a metal silicide layer 31. Finally, the unreacted metal material is removed.

[0090] See also Figure 15As shown, in one embodiment of the present invention, the metal silicide layer 31 on the heavily doped region includes a first subsection 311 and a second subsection 312. The first subsection 311 is formed by the reaction between the compensation epitaxial layer 30 and the metal material, and is formed protruding from the substrate 10. The second subsection 312 is formed by the reaction between the substrate 10 outside the compensation epitaxial layer 30 and the metal material, and extends from the surface of the substrate 10 into the substrate 10. The connection between the first subsection 311 and the second subsection 312 is arc-shaped. The depth of the second subsection 312 within the substrate is, for example, less than the depth of the transition region, so that a barrier layer is formed around the second subsection 312, which can reduce the potential barrier between the second subsection 312 and the substrate 10 and enable bidirectional conduction in the channel. The metal silicide layer with a special structure can consume the ion concentration near the channel in the heavily doped area and block the movement of electrons and holes. This is because the metal silicide is in contact with the substrate silicon, so that there are potential barriers on its left and right sides. Therefore, the second division 312 is equivalent to the role of the lightly doped area. On the one hand, it can prevent the hot carrier effect, and on the other hand, it can change the movement trajectory of the device carriers.

[0091] See also Figure 15 As shown, in one embodiment of the present invention, the width of the compensation epitaxial layer 30 is consistent with that of the gate structure 15. Therefore, the metal silicide layer 31 on the gate structure 15 protrudes from the surface of the gate structure 15. In other embodiments, if the width of the compensation epitaxial layer 30 on the gate structure 15 is smaller than the width of the gate structure 15, that is, when the fourth opening is formed, the opening width of the fourth opening on the gate structure 15 is smaller than the width of the gate structure 15, part of the gate structure will be metallized. At this time, the shape of the metal silicide layer 31 on the gate structure 15 is consistent with that on the heavily doped area. This application does not elaborate on this. By forming the compensation epitaxial layer 30, when forming the metal silicide layer 31, the height of the active area and the gate structure can be avoided from being consumed. At the same time, the consumption of doping ions in the heavily doped area and the lightly doped area can be effectively avoided, thereby reducing the source-drain parasitic resistance and ensuring device performance.

[0092] See also Figures 15 and 16 As shown, in one embodiment of the present invention, after forming the metal silicide layer 31, a second etch stop layer 32 is formed on the substrate 10. The second etch stop layer 32, for example, covers the metal silicide layer 31, the repair oxide layer 16, the substrate 10, and the shallow trench isolation structure 11. The second etch stop layer 32 is, for example, a silicon nitride layer. The second etch stop layer 32 is obtained, for example, by low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition. The thickness of the second etch stop layer 32 is, for example, 15 nm to 25 nm.

[0093] See also Figure 16As shown, in one embodiment of the present invention, after forming the second etch stop layer 32, an interlayer dielectric layer 33 is formed on the second etch stop layer 32. The interlayer dielectric layer 33 is, for example, a silicon oxide layer. For example, a silicon oxide layer is first formed covering the metal silicide layer 31 by high aspect ratio chemical vapor deposition (HARP-CVD) until the region between adjacent gate structures 15 is completely filled. For example, the silicon oxide layer is planarized by chemical mechanical polishing (CMP) to increase the filling energy of the interlayer dielectric layer, prevent voids that affect the fabrication yield of the conductive plug, and obtain a planarized surface that facilitates subsequent operations. A silicon oxide layer is then formed sequentially by plasma-enhanced chemical vapor deposition and chemical vapor deposition to obtain the interlayer dielectric layer 33. The present application does not limit the thickness of the silicon oxide layer formed by various deposition methods. In this embodiment, the thickness of the interlayer dielectric layer 33 on the substrate 10 is, for example, 250 nm to 280 nm. The interlayer dielectric layer 33 is formed by combining different methods to improve the deposition quality of the interlayer dielectric layer 33 and reduce the deposition cost.

[0094] See also Figure 16 As shown, in one embodiment of the present invention, an etching mask layer 34 is formed on the interlayer dielectric layer 33 to protect the interlayer dielectric layer 33, improve the etching selectivity, reduce the micro-groove effect, and improve the quality of the subsequent formation of the connection hole. In this embodiment, the etching mask layer 34 includes, for example, an amorphous carbon layer, a silicon oxynitride layer, and a silicon oxide layer, which are sequentially arranged on the interlayer dielectric layer 33. The thickness of each layer, such as the amorphous carbon layer, the silicon oxynitride layer, and the silicon oxide layer, is not limited in this application and is selected according to the manufacturing requirements. In a specific embodiment of the present invention, the thickness of the amorphous carbon layer is, for example, 160nm to 240nm, the thickness of the silicon oxynitride layer is, for example, 30nm to 40nm, and the thickness of the silicon oxide layer is, for example, 5nm to 10nm. By providing an etching mask layer with a multi-layer structure, the quality of the subsequent formation of the connection hole is improved.

[0095] See also Figure 16As shown, in one embodiment of the present invention, a photomask layer 35 is formed on the etching mask layer 34. In this embodiment, the photomask layer 35 includes, for example, an anti-reflection layer and a photoresist layer, which are sequentially arranged on the etching mask layer 34. The anti-reflection layer is a resin-based composite material. The thickness of each layer, such as the anti-reflection layer and the photoresist layer, is not limited in this application and is selected according to manufacturing requirements. In a specific embodiment of the present invention, the thickness of the anti-reflection layer is, for example, 20nm to 30nm, and the thickness of the photoresist layer is, for example, 90nm to 110nm. By forming a mask plate for forming a connection hole, exposure, development and other processes are performed to form a recess 351 in the photomask layer 35. The recess 351 is located on the heavily doped region and the gate structure 15 and exposes the bottom of the etching mask layer 34 to locate the position of the connection hole.

[0096] See also Figures 16 and 17 As shown, in one embodiment of the present invention, the mask layer 34, the interlayer dielectric layer 33, the second etch stop layer 32, and a portion of the metal silicide layer 31 are etched using a dry etching, wet etching, or a combination of dry etching and wet etching processes using a photomask layer 35 as a mask to form a connection hole 352. In this embodiment, dry etching is used, for example, and during the etching process, the second etch stop layer 32 is used sequentially as an etch stop layer depending on the material being etched. After etching to the same material at different locations, the etching gas is replaced to form the connection hole 352, and the connection hole 352 stops at the same depth within the metal silicide layer 31. During the etching process, since the metal silicide layer 31 protrudes from the surface of the substrate 10 or the gate structure 15, the etching height of the connection hole 352 is reduced. Therefore, the etching difficulty of the connection hole 352 can be reduced, thereby avoiding disconnection of the connection hole 352 and improving the yield of the semiconductor device.

[0097] See also Figures 17 and 18As shown, in one embodiment of the present invention, after forming the connection hole 352, a conductive plug 38 is formed within the connection hole 352. The conductive plug 38 includes a barrier layer 36 and a conductive structure 37. Specifically, the barrier layer 36 is formed on the sidewalls and bottom of the connection hole 352. The barrier layer 36 is formed, for example, by electroplating or physical vapor deposition. The barrier layer 36 is made of a material with good adhesion, such as tantalum, tantalum nitride, or titanium nitride. The thickness of the barrier layer 36 is, for example, 5 nm to 15 nm. Metal is deposited on the barrier layer 36 to form the conductive structure 37. The metal material is deposited, for example, by physical vapor deposition or electroplating. The metal material is made of copper, aluminum, or tungsten. Deposition is stopped until the metal material completely fills the connection hole 352. The metal is then planarized by chemical mechanical polishing to make the conductive structure 37 flush with the interlayer dielectric layer 33 on both sides. In this embodiment, the conductive structure 37 is made of, for example, tungsten, and the barrier layer 36 is, for example, a combination of a titanium layer and a titanium nitride layer. The titanium layer is disposed on the sidewalls and bottom of the connection hole 352, and the titanium nitride layer is disposed on the titanium layer. The thickness of the titanium layer is, for example, 8 nm to 10 nm, and the thickness of the titanium nitride layer is, for example, 3 nm to 5 nm. The combination of the titanium layer and the titanium nitride layer can prevent the raw material from reacting with the titanium layer during the deposition of the conductive structure 37, thereby preventing the conductive structure 37 from falling off. Furthermore, the stress of the titanium nitride layer can be alleviated, and the bonding strength between the titanium nitride layer and the interlayer dielectric layer 33 can be improved. The barrier layer 36 enhances the adhesion of the metal material to the sidewalls of the connection hole 352, blocks the diffusion of metal ions, reduces electromigration, and improves the reliability of the semiconductor device.

[0098] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. By improving the semiconductor device and its method for manufacturing, the unexpected technical effect of the present application is that it can ensure the morphology and structural integrity of the gate structure, repair etching damage during the formation of the gate structure, and improve the yield of the semiconductor device. While ensuring device performance, it can simplify the manufacturing process and improve manufacturing efficiency. At the same time, it can increase the distance between gate structures, increase the etching window of the connection hole, reduce the etching difficulty of the connection hole, and improve the quality of the connection hole. Different doping regions can be formed through the same photoresist layer, which can reduce the number of photoresists and reduce costs. The channel length of the semiconductor device can be increased without changing the width of the gate structure, thereby reducing the leakage current Ioff of the device. Stress can be better transferred to the channel, which can better improve the carrier mobility rate, thereby improving device performance. The metal silicide layer formed with a special structure can deplete the ion concentration near the channel in the heavily doped region, blocking the movement of electrons and holes. On the one hand, it can prevent hot carrier effects, and on the other hand, it can change the movement trajectory of the device carriers. This method ensures that the range of the metal silicide layer formed is larger than the range of the contact hole. This prevents damage to the heavily doped and lightly doped regions when forming the contact hole, resulting in problems such as increased critical dimensions, overlay offset, or over-etching of the contact hole, thereby improving device quality. By forming a compensating epitaxial layer, the height of the active region and gate structure can be prevented from being consumed during the formation of the metal silicide layer. This method also effectively prevents the consumption of dopant ions in the heavily doped and lightly doped regions, reducing drain leakage current and ensuring device performance. This method also reduces the contact hole etching height, thereby reducing the difficulty of contact hole etching, avoiding contact hole disconnection, and improving the performance and yield of semiconductor devices.

[0099] The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as those skilled in the art will recognize and appreciate, various equivalent modifications are possible within the spirit and scope of the present invention. As noted, modifications may be made to the present invention in light of the above description of the illustrated embodiments of the present invention, and such modifications will be within the spirit and scope of the present invention.

[0100] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application. In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be repeated here.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: At least the following steps are included: providing a substrate, and forming a gate structure on the substrate; forming a repair oxide layer on the substrate and the sidewalls of the gate structure; Etching the repair oxide layer to retain the repair oxide layer on the sidewall of the gate structure; A lightly doped region, a transition region, and a heavily doped region are sequentially formed in the substrate on both sides of the gate structure from bottom to top; ion implantation is performed perpendicularly to the substrate to form the lightly doped regions on both sides of the gate structure; the ion implantation angle is adjusted to perform tilted ion implantation to form transition regions on both sides of the gate structure; and ion implantation is performed again perpendicularly to the substrate to form heavily doped regions on both sides of the gate structure. forming a fully covering first etch stop layer on the substrate and etching to form an opening, wherein the opening exposes a portion of the heavily doped region and at least a portion of the gate structure; forming a compensation epitaxial layer in the opening; removing the first etch stop layer, and metallizing at least the compensation epitaxial layer and a portion of the substrate to form a metal silicide layer; forming a second etch stop layer and an interlayer dielectric layer on the substrate and the metal silicide layer; Etching the interlayer dielectric layer to the metal silicide layer to form a connection hole; A conductive plug is formed in the connection hole.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The production method further comprises the following steps: forming a gate dielectric layer, a gate material layer, a multi-layer hard mask layer and a first photoresist layer in sequence on the substrate; Using the first photoresist layer as a mask, etching the multi-layer hard mask layer, the gate material layer, and the gate dielectric layer to form a gate structure, wherein the first hard mask layer exists on the gate structure; and The repair oxide layer is formed by thermal oxidation or in-situ water vapor growth, and the thickness of the repair oxide layer on the substrate is less than the thickness on the sidewall of the gate structure.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The production method further comprises: After etching the repair oxide layer, forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer exposes an area of ​​the substrate; Using the patterned photoresist layer as a mask, ion implantation is performed perpendicular to the substrate to form lightly doped regions on both sides of the gate structure; Adjusting the ion implantation angle to perform tilted ion implantation to form transition regions on both sides of the gate structure; and Ion implantation is performed again perpendicular to the substrate to form heavily doped regions on both sides of the gate structure. In the same region, the lightly doped region, the transition region, and the heavily doped region have the same doping type.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: When performing tilted ion implantation, the tilted implantation angle is the angle between the implantation direction and the substrate, and the implantation angle is 60° to 85°.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The doping concentration of the lightly doped region is less than the doping concentration of the transition region, the doping concentration of the transition region is less than the doping concentration of the heavily doped region, and the doping depth of the lightly doped region is greater than the doping depth of the transition region, the doping depth of the transition region is greater than the doping depth of the heavily doped region.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: On a side adjacent to the gate structure, a boundary of the heavily doped region is aligned with a boundary of the lightly doped region, and a boundary of the transition region exceeds the boundary of the heavily doped region.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The production method further comprises: forming a bottom anti-reflection layer and a first photoresist layer on the first etch stop layer; exposing and developing the first photoresist layer and the bottom anti-reflection layer through a mask to form a first opening, wherein the first opening exposes a portion of the first etch stop layer, and the mask is the same as the mask used to form the connecting hole; dry-etching the first etch-stop layer at the bottom of the first opening to form a second opening; Laterally etching the first etch-stop layer exposed by the second opening to form a third opening; and The first photoresist layer and the bottom anti-reflection layer are removed to form a fourth opening, wherein the fourth opening at least exposes a portion of the gate structure and a portion of the heavily doped region.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The metal silicide layer on the heavily doped region includes a first section and a second section. The first section is obtained by metallization treatment of the compensation epitaxial layer and is formed on the substrate. The second section is obtained by metallization treatment of the substrate and extends from the surface of the substrate into the substrate. The connection between the first section and the second section is in an arc shape.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: A depth of the second portion in the substrate is smaller than a depth of the transition region.

10. A semiconductor device, characterized in that: Obtained by the production method according to any one of claims 1 to 9, comprising at least a substrate, on which a gate structure and a repair oxide layer on both sides of the gate structure are provided; Lightly doped regions are provided in the substrate on both sides of the gate structure; a transition region, disposed in the substrate on both sides of the gate structure and located on the lightly doped region; a heavily doped region, disposed in the substrate on both sides of the gate structure and located on the transition region; a metal silicide layer, disposed at least on the heavily doped region and the gate structure, and protruding from surfaces of the substrate and the gate structure; a second etch stop layer, disposed at least on the substrate and the repair oxide layer; an interlayer dielectric layer, disposed on the substrate and the metal silicide layer; The conductive plug is arranged in the interlayer dielectric layer.

Images