Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a method of forming the same. The device includes a high voltage junction termination element, a high voltage region within a ring of the high voltage junction termination element, a low voltage region outside the ring of the high voltage junction termination element, and a guard ring extending along an inner side of the ring of the high voltage junction termination element. The guard ring laterally surrounds the high voltage region.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to using a guard ring to improve the efficiency of electrostatic discharge (ESD). Background Art

[0002] Integrated circuits can be severely damaged due to various electrostatic discharge events. One of the main electrostatic discharge mechanisms comes from the human body and is called the human-body model (HBM). The human body can generate a tip current of several amperes to the integrated circuit in about 100 nanoseconds and burn it out. The second electrostatic discharge mechanism comes from metal objects and is called the machine model (MM), which has a higher rise time and current peak compared to the human-body model. The third electrostatic discharge mechanism comes from the integrated circuit itself and is called the charged-device model (CDM), which discharges the accumulated charge to the ground terminal in a time with a rise time of less than 0.5 nanoseconds. Therefore, an effective electrostatic protection device is needed to protect the integrated circuit from the harm of electrostatic discharge. Summary of the Invention

[0003] A semiconductor device includes: a high-voltage junction terminal element; a high-voltage region located inside the ring of the high-voltage junction terminal element; a low-voltage region located outside the ring of the high-voltage junction terminal element; and a guard ring extending along the inner side of the ring of the high-voltage junction terminal element. The guard ring laterally surrounds the high-voltage region.

[0004] A method for forming a semiconductor device includes: providing a substrate; forming an epitaxial layer on the substrate; forming a first high-voltage well in the epitaxial layer; forming a first deep well in the epitaxial layer; and forming a second high-voltage well in the epitaxial layer. The first deep well laterally surrounds the first high-voltage well. The second high-voltage well is adjacent to the first deep well and laterally surrounds the first high-voltage well. The second high-voltage well is located between the first high-voltage well and the first deep well.

[0005] The semiconductor device of the present invention incorporates a guard ring closely adjacent to the inner side of the ring of the high-voltage junction terminal element. During the operation of the semiconductor device, an unwanted parasitic bipolar junction path may be generated. When the voltage applied by the electrostatic discharge is too high, the high-voltage well of the parasitic bipolar junction path may be burned out, causing the semiconductor device to fail. The guard ring can attract the current flowing to the parasitic bipolar junction path, thereby replacing the unwanted parasitic bipolar junction as an alternative electrostatic discharge path. When the parasitic bipolar junction path is not turned on, the electrostatic discharge protection of the overall semiconductor device can be improved. Brief Description of the Drawings

[0006] The following will elaborate on various aspects of the embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale. In fact, the dimensions of the various elements can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0007] Figure 1 and Figure 2 are a top view and a cross-sectional schematic view of a semiconductor device according to some embodiments of the present invention.

[0008] Figure 3 is a top view of a semiconductor device according to some embodiments of the present invention.

[0009] Figure 4 is a top view of a semiconductor device according to other embodiments of the present invention.

[0010] Figure 5 and Figure 6 are a top view and a cross-sectional schematic view of a semiconductor device according to other embodiments of the present invention.

[0011] Symbol Description

[0012] 10: Semiconductor device

[0013] 10A: High-voltage junction termination element

[0014] 10A-1: High-voltage region

[0015] 10A-2: Low-voltage region

[0016] 10B: Protection ring

[0017] 10C: Level shifter

[0018] 20: Semiconductor device

[0019] 20A: High-voltage junction termination element

[0020] 20A-1: High-voltage region

[0021] 20A-2: Low-voltage region

[0022] 20B: Protection ring

[0023] 20C: Level shifter

[0024] 30: Semiconductor device

[0025] 30A: High-voltage junction termination element

[0026] 30A-1: High-voltage region

[0027] 30A-2: Low-voltage region

[0028] 30B: Protection ring

[0029] 30C: Level shifter

[0030] 30D: Resistor

[0031] 40: Semiconductor device

[0032] 40A: High-voltage junction termination element

[0033] 40A-1: High-voltage region

[0034] 40A-2: Low-voltage region

[0035] 40B: Protection ring

[0036] 40C: Level shifter

[0037] 100: Substrate

[0038] 200: Buried layer

[0039] 300: Epitaxial layer

[0040] 302: Well

[0041] 304: Well

[0042] 320: High-voltage well

[0043] 322: Well

[0044] 324: Well

[0045] 326: Well

[0046] 340: High-voltage well

[0047] 342: Well

[0048] 360: Deep well

[0049] 362: Well

[0050] 410: Doped region

[0051] 420: Doped region

[0052] 430: Doped region

[0053] 440: Doped region

[0054] 450: Doped region

[0055] 460: Doped region

[0056] 470: Doped region

[0057] 480: Doped region

[0058] 500a: Isolation structure

[0059] 500b: Isolation structure

[0060] 600: Interlayer dielectric layer

[0061] 610: Via hole

[0062] 620: Via hole

[0063] 630: Via hole

[0064] 640: Via hole

[0065] 650: Via hole

[0066] 660: Via hole

[0067] 680: Via hole

[0068] 710: Metal layer

[0069] 720: Metal layer

[0070] 730: Metal layer

[0071] 740: Metal layer

[0072] 750: Metal layer

[0073] 760: Metal layer

[0074] 780: Metal layer

[0075] A - A’: Line segment

[0076] B - B’: Line segment Detailed implementation manners

[0077] The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description that the first component is formed on the second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the present invention may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dominate the relationship between the various embodiments and / or configurations being discussed.

[0078] In addition, in some embodiments of the present invention, terms related to joining and connection, such as "connected" and "interconnected", unless specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures disposed between these two structures.

[0079] Furthermore, spatially relative terms, such as "under", "below", "lower", "above", "upper", and the like may be used herein to describe a relationship between one element or component and other elements or components as shown in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientation shown in the figures. When the device is rotated to another orientation (rotated 90° or other orientations), the spatially relative descriptions used herein may be interpreted accordingly with respect to the rotated orientation.

[0080] The terms "about", "approximately", "substantially" as used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or ±3%, or ±2%, or ±1%, or 0.5% of the given value. The given value is an approximate value, that is, in the case where there is no specific indication of "about", "approximately", "substantially", the given value may still imply the meaning of "about", "approximately", "substantially".

[0081] Some embodiments of the present invention are described below. Additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Components may be added to the semiconductor device structure. Some of these components may be replaced or omitted in different embodiments. Although some of the steps discussed in the embodiments are performed in a specific order, these steps may still be performed in another logical order.

[0082] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention belongs. It is understood that these terms, such as those defined in a general dictionary, should be interpreted to have a meaning consistent with the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0083] As the miniaturization of components to improve operating efficiency, the electrostatic breakdown tolerance of semiconductor devices also decreases. In the prior art, metal-oxide semiconductor (MOS) transistors with parasitic diode junctions are usually used as electrostatic discharge (ESD) components. In industry practice, a machine for measuring electrostatic discharge using transmission line pulse (TLP) can be used and set to the human body discharge mode.

[0084] The present invention includes embodiments for electrostatic discharge of semiconductor devices having high voltage junction termination (HVJT) elements. The electrostatic discharge can flow from the high voltage (highside) region to the low voltage (low side) region of the high voltage junction termination element. For example, when the high voltage junction termination element breaks down, the potential gradually decreases from the high voltage region to the low voltage region, causing current to flow from the high voltage region to the low voltage region. As a result, the electrostatic discharge can be obtained by utilizing the breakdown mechanism of the diode. Since the bias voltage of the electrostatic discharge generally reaches 1000V to 2000V, the breakdown of the diode will necessarily occur. For example, when the applied voltage exceeds 500V, breakdown occurs, causing the interface of the diode to conduct, and thus the current of the electrostatic discharge flows. During the operation of the semiconductor device, current can flow from the high voltage region through the high voltage junction termination element to the low voltage region (as the first path), and can also flow from the high voltage region through a level shifter to the low voltage region (as the second path). In other words, the electrostatic discharge can be carried out from the high voltage region to the low voltage region through different components.

[0085] In addition to the above two expected electrostatic discharge paths, it is possible to generate an additional unwanted parasitic bipolar junction path. Although the conduction voltage of the first path is lower than that of the unwanted parasitic bipolar junction path (indicating that the first path conducts earlier), the conduction voltages of the two are actually very close. However, the first path and the unwanted parasitic bipolar junction path have different electrostatic current withstand capabilities. When the applied voltage is too high and the current of the electrostatic discharge exceeds 0.5A, the components of the parasitic bipolar junction path may burn out, causing the semiconductor device to fail. The inventors have found that a guard ring can be incorporated to attract the current flowing to the parasitic bipolar junction path. It should be understood that the guard ring can also be referred to as a victim guard ring (VGR). When the parasitic bipolar junction path is not conducting, the electrostatic discharge protection of the overall semiconductor device can be enhanced.

[0086] Figure 1 and Figure 2 are a top view and a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments of the present invention. It should be noted that, Figure 2 For Figure 1A cross-sectional schematic diagram obtained from the line segment A-A'. In some embodiments, a semiconductor device generally may include any number of active components and passive components. Active components include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, laterally diffused metal-oxide semiconductor (LDMOS) transistors, bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistors, bipolar junction transistors (BJTs), planar transistors, fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA FETs), other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures.

[0087] Referring to Figure 1 and Figure 2 , the semiconductor device 10 may include a high-voltage junction terminal element 10A, a guard ring 10B, and a plurality of level shifters 10C. For simplicity, Figure 1 only the layout of all active regions (e.g., doped regions) of the high-voltage junction terminal element 10A, the guard ring 10B, and the plurality of level shifters 10C is illustrated. The line segment A-A' traverses the high-voltage junction terminal element 10A and the guard ring 10B. In some embodiments, the high-voltage junction terminal element 10A may be designed in a ring shape. A high-voltage region 10A-1 may be defined within the ring of the high-voltage junction terminal element 10A, and a low-voltage region 10A-2 may be defined outside the ring of the high-voltage junction terminal element 10A. Furthermore, the guard ring 10B may extend along the inner side of the ring of the high-voltage junction terminal element 10A. The plurality of level shifters 10C may be integrated into the ring of the high-voltage junction terminal element 10A, thus effectively saving the overall area of the semiconductor device 10. In addition, the integrated configuration electrically couples the high-voltage junction terminal element 10A, the guard ring 10B, and the plurality of level shifters 10C to each other, thus omitting wire bonding and via formation, resulting in improved reliability.

[0088] Continuing to refer to Figure 1 and Figure 2 , although the high-voltage junction terminal element 10A is shown as a rectangular ring, the embodiments of the present invention are not limited thereto. For example, the high-voltage junction terminal element 10A can be a circular ring, an oval ring, a square ring, a triangular ring, or any suitable closed geometric ring. The ring configuration makes the integration of the high-voltage junction terminal element 10A with the guard ring 10B and the plurality of level shifters 10C more efficient and does not occupy additional wafer area. It should be understood that the magnitude of the electrostatic discharge is positively correlated with the size of the high-voltage junction terminal element 10A. The high-voltage junction terminal element 10A can be designed to have a relatively large size to reduce the on-resistance of the semiconductor device 10, thereby inducing the electrostatic discharge current to flow through the high-voltage junction terminal element 10A. The high-voltage junction terminal element 10A physically and electrically separates the high-voltage region 10A-1 and the low-voltage region 10A-2. The high-voltage region 10A-1 can accommodate components operating at a high-voltage level, while the low-voltage region 10A-2 can accommodate components operating at a low-voltage level. Generally, "high voltage" generally refers to a voltage above 100V, such as between 100V and 1200V, between 100V and 750V, or between 750V and 1200V. "Low voltage" generally refers to a voltage below 20V, such as between 1V and 20V, between 1V and 10V, or between 10V and 20V. In a specific embodiment of the present invention, the high-voltage region 10A-1 and the low-voltage region 10A-2 operate at voltages of 600V and 5V, respectively.

[0089] In some embodiments, the high-voltage region 10A-1 can include a potential for supplying an absolute voltage (VB) at a high-voltage floating and a potential for supplying an offset voltage (VS) at a high-voltage floating, while the low-voltage region 10A-2 can include a potential for supplying a fixed voltage (VCC) at a low voltage. The voltage difference between the high-voltage floating supply absolute voltage (VB) and the high-voltage floating supply offset voltage (VS) can be between 0V and 20V. The potential of the high-voltage floating supply absolute voltage (VB) and the potential of the high-voltage floating supply offset voltage (VS) can be maintained with a stable voltage difference by the placement of capacitors. According to some embodiments of the present invention, the high-voltage floating supply offset voltage can be used to increase the overall operating voltage of the high-voltage region 10A-1.

[0090] To enhance the protection against electrostatic discharge, an electrostatic discharge clamp may be provided between the high-voltage floating supply absolute voltage terminal and the high-voltage floating supply offset voltage terminal in the high-voltage region 10A-1, and an electrostatic discharge clamp may also be provided between the low-voltage fixed supply voltage terminal and the electrical ground terminal (such as the control logic circuit) in the low-voltage region 10A-2. According to some embodiments of the present invention, electrostatic discharge may be carried out from the high-voltage region 10A-1 to the low-voltage region 10A-2 through the loop of the high-voltage junction terminal element 10A. More specifically, discharging the electrostatic charge from the high-voltage floating supply absolute voltage (VB) terminal in the high-voltage region 10A-1 to the electrical ground terminal in the low-voltage region 10A-2 may be the desired path, while discharging the electrostatic charge from the high-voltage floating supply offset voltage (VS) terminal in the high-voltage region 10A-1 to the electrical ground terminal in the low-voltage region 10A-2 may be the unwanted path. This is because the high-voltage floating supply absolute voltage terminal may form a diode (PN) junction path, while the high-voltage floating supply offset voltage terminal may form a parasitic bipolar (PNP) junction path, the details of which will be described in detail below. When the electrostatic discharge causes the potential of the high-voltage floating supply absolute voltage (VB) terminal to rise, the high-voltage floating supply offset voltage (VS) terminal will also rise accordingly. After breakdown occurs in the high-voltage junction terminal element 10A, the diode (PN) junction path will conduct, and the parasitic bipolar (PNP) junction path may also conduct subsequently.

[0091] Referring to Figure 1 and Figure 2 , a protection ring 10B may be provided in the high-voltage region 10A-1. In some embodiments, the protection ring 10B may be a complete loop and adjacent to the high-voltage junction terminal element 10A. As previously mentioned, the protection ring 10B may be incorporated to prevent the conduction of the parasitic bipolar junction path. It should be understood that since the parasitic bipolar junction path is likely to occur in the active region closest to the high-voltage junction terminal element 10A in the high-voltage region 10A-1, the protection ring 10B needs to be provided adjacent to the loop of the high-voltage junction terminal element 10A. In other words, the protection ring 10B needs to be closer to the high-voltage junction terminal element 10A than any active region in the high-voltage region 10A-1, thereby replacing any electrostatic discharge through the potential parasitic bipolar junction path.

[0092] Continuing to refer to Figure 1 and Figure 2 , a plurality of level shifters 10C may be integrated into the loop of the high-voltage junction terminal element 10A. From another perspective, a plurality of level shifters 10C may be located on the loop of the high-voltage junction terminal element 10A. It is worth noting that the plurality of level shifters 10C are spaced apart from each other. Although Figure 1Two level shifters 10C are illustrated, but the embodiments of the present invention are not limited thereto. For example, any number of level shifters 10C can be configured, depending on the application and design requirements. According to some embodiments of the present invention, the level shifter 10C can convert signals between the high voltage region 10A-1 and the low voltage region 10A-2. For example, the level shifter 10C can receive signals from control logic (not shown) to perform voltage switching between the high voltage region 10A-1 and the low voltage region 10A-2, or between the low voltage region 10A-2 and the high voltage region 10A-1. As previously mentioned, current can flow from the high voltage region through the level shifter 10C to the low voltage region, which is the second path for electrostatic discharge. However, existing semiconductor designs have effectively avoided electrostatic discharge through the second path. Therefore, the current mainly flows from the high voltage region through the high voltage junction termination element (including the diode (PN) junction) to the low voltage region, which is the first path for electrostatic discharge.

[0093] According to some embodiments of the present invention, the guard ring 10B can have a first conductivity type, and the high voltage junction termination element 10A and the level shifter 10C can have the same second conductivity type, where the first conductivity type is different from the second conductivity type. In the following embodiments, the first conductivity type and the second conductivity type can represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) can be doped with appropriate dopants (or impurities) individually. P-type dopants can include boron (B), indium (In), aluminum (Al), or gallium (Ga), while N-type dopants can include phosphorus (P) or arsenic (As).

[0094] Referring to Figure 1 and Figure 2 , the structure of the semiconductor device 10 can include a substrate 100, a buried layer 200, an epitaxial layer 300, isolation structures 500a, isolation structures 500b, an interlayer dielectric (ILD) layer 600, via holes 610, via holes 620, via holes 630, via holes 640, via holes 650, via holes 660, via holes 680, metal layers 710, metal layers 720, metal layers 730, metal layers 740, metal layers 750, metal layers 760, and metal layers 780.

[0095] In some embodiments, the epitaxial layer 300 may include wells 302, 304, high-voltage wells 320, 340, and deep well 360. The high-voltage well 320 may include wells 322, 324, and 326. The high-voltage well 340 may include well 342. The deep well 360 may include well 362. Well 322 may include doped region 410. Well 324 may include doped region 420. Well 326 may include doped region 430. Well 302 may include doped region 440. Well 304 may include doped region 450. Well 342 may include doped region 460. Well 362 may include doped region 480. It is noted that the substrate 100, the buried layer 200, the epitaxial layer 300, and the interlayer dielectric layer 600 may be disposed across the high-voltage junction terminal element 10A, the guard ring 10B, and the plurality of level shifters 10C.

[0096] In some embodiments, the substrate 100 may be, for example, a wafer or a chip, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. Additionally, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and / or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

[0097] In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a bottom substrate, a buried oxide (BOX) layer disposed on the bottom substrate, and a semiconductor layer disposed on the buried oxide layer. In a specific embodiment of the present invention, the substrate 100 may be of a first conductivity type (P-type), and its doping concentration is between 1×10 14 cm -3 and 3×10 14 cm -3 therebetween.

[0098] In other embodiments, the substrate 100 may include isolation structures (not shown) to define active regions and electrically isolate active region components within or on the substrate 100, but the embodiments of the present invention are not limited thereto. The isolation structures may include deep trench isolation (DTI) structures, shallow trench isolation (STI) structures, or local oxidation of silicon (LOCOS) structures. In some embodiments, forming the isolation structures may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form trenches extending from the top surface of the substrate 100 to a position within the substrate 100, where the trenches are located between adjacent active regions. Then, forming the isolation structures may include growing a liner layer rich in nitrogen (such as silicon oxynitride (SiON) or other similar materials) along the trenches, and then filling the trenches with an insulating material (such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. After that, an annealing process is performed on the insulating material in the trenches, and a planarization process (such as chemical mechanical polish (CMP)) is performed on the substrate 100 to remove the excess insulating material, so that the insulating material in the trenches is flush with the top surface of the substrate 100.

[0099] Continuing to refer to [[ID=_15]] Figure 1 and Figure 2 , an epitaxial layer 300 is formed on the substrate 100. According to some embodiments of the present invention, the epitaxial layer 300 may be of a second conductivity type (N-type), and its doping concentration is between 5×10 14 cm -3 and 5×10 15 cm -3Therebetween. In a specific embodiment of the present invention, the substrate 100 and the epitaxial layer 300 may have different conductivity types, and the doping concentration of the substrate 100 is less than that of the epitaxial layer 300. The material of the epitaxial layer 300 may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer 300 may be between 3 μm and 7 μm. The epitaxial layer 300 can be formed by an epitaxial process, which may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

[0100] Refer to Figure 1 and Figure 2 , the semiconductor device 10 includes a buried layer 200 disposed in the substrate 100. The buried layer 200 can directly contact the high-voltage wells 320, 340, and the deep well 360 of the epitaxial layer 300. According to some embodiments of the present invention, the buried layer 200 and the substrate 100 can form a diode junction, thereby providing an effective electrostatic discharge path. The buried layer 200 has a second conductivity type (N-type). It should be noted that the substrate 100 and the buried layer 200 have opposite conductivity types, and thus can form a diode (PN) junction path. The diode junction path inevitably exists. The doping concentration of the buried layer 200 may be between 6×10 15 cm -3 and 6×10 16 cm -3 Therebetween. The vertical dimension of the buried layer 200 may be between 1 μm and 2 μm. The lateral dimension of the buried layer 200 can traverse the entire high-voltage region 10A-1 and annularly overlap with the high-voltage junction terminal element 10A. It should be understood that since the buried layer 200 can form a diode (PN) junction path with the substrate 100, the area and perimeter of the buried layer 200 directly affect the magnitude of the electrostatic discharge. The buried layer 200 should cover the entire electrostatic discharge area.

[0101] The method for forming the buried layer 200 may include implanting an N-type dopant (such as phosphorus or arsenic) into the substrate 100 before forming the epitaxial layer 300, performing a heat treatment to drive the implanted ions into the substrate 100, and then forming the epitaxial layer 300 on the substrate 100. In some embodiments, since the epitaxial layer 300 is formed under high-temperature conditions, the implanted ions will diffuse into the epitaxial layer 300. As Figure 1 and Figure 2As shown, the buried layer 200 is located near the interface (marked by a dashed line) between the substrate 100 and the epitaxial layer 300, and has a part within the substrate 100 and another part within the epitaxial layer 300. In other words, the buried layer 200 can extend upward from the interface between the substrate 100 and the epitaxial layer 300.

[0102] Continuing to refer to Figure 1 and Figure 2 , a high-voltage well 320, a high-voltage well 340, and a deep well 360 can be formed in the epitaxial layer 300. In some embodiments, the high-voltage well 320 can be located in the high-voltage region 10A-1 of the high-voltage junction terminal element 10A, the high-voltage well 340 can be located in the guard ring 10B, and the deep well 360 can be located in the ring of the high-voltage junction terminal element 10A. From another perspective, the high-voltage well 340 and the deep well 360 can respectively define the guard ring 10B and the high-voltage junction terminal element 10A. It should be understood that, from a top view, the high-voltage well 340 surrounds the high-voltage well 320, so the high-voltage well 340 in the cross-sectional schematic diagram is disposed on both sides of the high-voltage well 320. Similarly, from a top view, the deep well 360 surrounds and abuts the high-voltage well 340, so the deep well 360 in the cross-sectional schematic diagram is disposed on the outer sides of the high-voltage well 340. From a top view, the high-voltage well 340 is located between the high-voltage well 320 and the deep well 360. The high-voltage well 320, the high-voltage well 340, and the deep well 360 can extend vertically from the upper surface of the epitaxial layer 300 to the interface between the epitaxial layer 300 and the buried layer 200. According to some embodiments of the present invention, the high-voltage well 320 and the high-voltage well 340 can be of the first conductive type (P-type), and the deep well 360 can be of the second conductive type (N-type).

[0103] Since the high-voltage well 320 (P-type), the buried layer 200 (N-type), and the substrate 100 (P-type) form a parasitic bipolar (PNP) junction, the active region in the high-voltage well 320 can cause an electrostatic discharge path of the unwanted parasitic bipolar junction. The high-voltage well 320 in the high-voltage region 10A-1 is connected to the high-voltage floating supply offset voltage (VS). When the high-voltage well 320 is disposed close to the high-voltage junction terminal element 10A, an electrostatic discharge path can be generated. In addition, the buried layer 200 and the deep well 360 can be regarded together as a "container" for setting the high-voltage region 10A-1, while the low-voltage region 10A-2 is located outside the "container". The configuration of the buried layer 200 and the deep well 360 can drive the application of the overall circuit in the high-voltage region 10A-1 to more than 100V.

[0104] The high-voltage wells 320, 340, and deep well 360 can be formed by, for example, ion implantation and / or diffusion processes. In alternative embodiments, instead of using ion implantation and / or diffusion processes, the high-voltage wells 320, 340, and deep well 360 can be doped in situ during the growth of the epitaxial layer 300. In other embodiments, in-situ and implant doping can be used together.

[0105] In some embodiments, the high-voltage well 320 can be located above the buried layer 200. More specifically, the high-voltage well 320 can be in direct contact with the buried layer 200 in the vertical direction. The doping concentration of the high-voltage well 320 can be between 5×10 15 cm -3 and 5×10 16 cm -3 . As previously mentioned, the high-voltage well 320 can include wells 322, 324, and 326. Well 322 is located between wells 324 and 326.

[0106] In some embodiments, the high-voltage well 340 can laterally surround the high-voltage well 320 and can be located above the buried layer 200. More specifically, the high-voltage well 340 can be in direct contact with the buried layer 200 in the vertical direction, and the high-voltage well 340 can be between the high-voltage well 320 and the deep well 360 in the horizontal direction. The doping concentration of the high-voltage well 340 can be between 5×10 15 cm -3 and 5×10 16 cm -3 . As previously mentioned, the high-voltage well 340 can include well 342. It should be understood that, from a top view, well 342 surrounds wells 322, 324, and 326, so well 342 in the cross-sectional schematic is disposed on the outer sides of wells 324 and 326 respectively.

[0107] In some embodiments, the deep well 360 can laterally surround the high-voltage well 340 (and the high-voltage well 320) and can be located above the buried layer 200. More specifically, the deep well 360 can be in direct contact with the buried layer 200 in the vertical direction. Furthermore, the deep well 360 can serve as a ring of the high-voltage junction terminal element 10A. The doping concentration of the deep well 360 can be between 5×10 15 cm -3 and 5×10 16 cm -3 . As previously mentioned, the deep well 360 can include well 362. It should be understood that, from a top view, well 362 surrounds well 342, so well 362 in the cross-sectional schematic is disposed on the outer sides of well 342.

[0108] Referring to Figure 1 andFigure 2 , wells 302 and 304 can be formed in the epitaxial layer 300. In some embodiments, wells 302 and 304 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300 and can overlap with the buried layer 200. Wells 302 and 304 can be located in the high-voltage region 10A-1 and outside the high-voltage well 320. According to some embodiments of the present invention, wells 302 and 304 can be of the second conductivity type (N-type). The formation method of wells 302 and 304 can be similar to that of the high-voltage well 320, the high-voltage well 340, and the deep well 360, and the details will not be repeated here.

[0109] In some embodiments, well 302 can be laterally located between the high-voltage well 320 and the high-voltage well 340. According to some embodiments of the present invention, well 302 can serve as an electrostatic discharge path desired to flow from the high-voltage region 10A-1 to the low-voltage region 10A-2. The doping concentration of well 302 can be between 5×10 16 cm -3 and 5×10 17 cm -3 . The thickness of well 302 can be between 0.2 μm and 0.6 μm. The lateral dimension of well 302 can be between 18 μm and 22 μm.

[0110] In some embodiments, well 304 can be laterally located between the high-voltage well 320 and the high-voltage well 340. According to some embodiments of the present invention, well 304 can serve as an electrostatic discharge path desired to flow from the high-voltage region 10A-1 to the low-voltage region 10A-2. The doping concentration of well 304 can be between 5×10 16 cm -3 and 5×10[[ID=2O]] 17 cm U -3 . The thickness of well 304 can be between 0.2 μm and 0.6 μm. The lateral dimension of well 304 can be between 18 μm and 22 μm.

[0111] Continuing to refer to Figure 1 and Figure 2 , wells 322, 324, and 32ó can be provided in the high-voltage well 320. In some embodiments, wells 322, 324, and 326 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. Well 322 can be laterally located between well 324 and well 326. Wells 324 and 326 can be adjacent to well 322. According to some embodiments of the present invention, well 322 can be of the second conductivity type (N-type), while wells 324 and 326 can be of the first conductivity type (P-type). The formation method of wells 322, 324, and 326 can be similar to that of the high-voltage well 320, the high-voltage well 340, and the deep well 360, and the details will not be repeated here.

[0112] Reference Figure 1 and Figure 2 , a well 342 can be formed in the high-voltage well 340. The well 342 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300 and can overlap with the buried layer 200. The well 342 can be of the first conduction type (P-type). According to some embodiments of the present invention, the well 342 can reduce the impedance of the discharge path. The doping concentration of the well 342 can be between 5×10 16 cm -3 and 5×10 17 cm -3 . The thickness of the well 342 can be between 0.2 μm and 0.6 μm. The lateral dimension of the well 342 can be between 1 μm and 2 μm. The method of forming the well 342 can be similar to the methods of forming the high-voltage well 320, the high-voltage well 340, and the deep well 360, and the details will not be repeated here.

[0113] Continuing to refer to Figure 1 and Figure 2 , a well 362 can be formed in the deep well 360. The well 362 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300 and can overlap with the buried layer 200. The well 362 can be of the second conduction type (N-type). According to some embodiments of the present invention, the well 362 can reduce the impedance of the discharge path. The doping concentration of the well 362 can be between 5×10 16 cm -3 and 5×10 17 cm -3 . The thickness of the well 362 can be between 0.2 μm and 0.6 μm. The lateral dimension of the well 362 can be between 1 μm and 2 μm. The method of forming the well 362 can be similar to the methods of forming the high-voltage well 320, the high-voltage well 340, and the deep well 360, and the details will not be repeated here.

[0114] Referring to Figure 1 and Figure 2 , a doping region 410 can be formed in the well 322. The doping region 410 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doping region 410 can be of the second conduction type (N-type). According to some embodiments of the present invention, the doping region 410 can reduce the contact impedance. The doping concentration of the doping region 410 can be between 5.0×10 19 cm -3 and 1.0×10 21 cm -3 . The thickness of the doping region 410 can be between 0.09 μm and 0.11 μm. The method of forming the doping region 410 can be similar to the methods of forming the high-voltage well 320, the high-voltage well 340, and the deep well 360, and the details will not be repeated here.

[0115] Continuing to refer toFigure 1 and Figure 2 , a doped region 420 can be formed in the well 324. The doped region 420 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 420 can be of a first conductivity type (P-type). According to some embodiments of the present invention, the doped region 420 can reduce the contact resistance. The doping concentration of the doped region 420 can be between 5.0×10 19 cm -3 and 1.0×10 21 cm -3 . The thickness of the doped region 420 can be between 0.18 μm and 0.22 μm. The method of forming the doped region 420 can be similar to the methods of forming the high-voltage wells 320, 340, and the deep well 360, and the details thereof will not be repeated here.

[0116] Referring to Figure 1 and Figure 2 , a doped region 430 can be formed in the well 326. The doped region 430 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 430 can be of a first conductivity type (P-type). According to some embodiments of the present invention, the doped region 430 can reduce the contact resistance. The doping concentration of the doped region 430 can be between 5.0×10 19 cm -3 and 1.0×10 21 cm -3 . The thickness of the doped region 430 can be between 0.18 μm and 0.22 μm. The method of forming the doped region 430 can be similar to the methods of forming the high-voltage wells 320, 340, and the deep well 360, and the details thereof will not be repeated here.

[0117] In some embodiments, the doped region 420 and the doped region 430 can serve as the high-voltage floating supply offset voltage (VS) terminals. The doped region 420 and the doped region 430, the wells 324 and 326, and the high-voltage well 320 are of the first conductivity type (P-type), the buried layer 200 is of the second conductivity type (N-type), and the substrate 100 is of the first conductivity type (P-type). The doped region 420 or the doped region 430, the buried layer 200, and the substrate 100 form a parasitic bipolar (PNP) junction. When the distance between the doped region 420 and / or the doped region 430 and the high-voltage junction terminal element 10A is too small, the electrostatic discharge path of the unwanted parasitic bipolar junction can be turned on. When the voltage applied by the electrostatic discharge is too high, the high-voltage well 320 of the parasitic bipolar junction path may be burned out, causing the semiconductor device 10 to fail.

[0118] According to some embodiments of the present invention, the guard ring 10B can attract the current flowing to the parasitic bipolar junction path. The electrostatic discharge path from the guard ring 10B in the high-voltage region 10A-1 to the low-voltage region 10A-2 is shorter than the electrostatic discharge path from the doped region 420 or the doped region 430 in the high-voltage region 10A-1 to the low-voltage region 10A-2. The doped region 460 of the guard ring 10B and the doped region 420 and / or the doped region 430 of the high-voltage well 320 can have the same potential, so the doped region 460 can replace the doped region 420 and / or the doped region 430 as an alternative electrostatic discharge path. In other words, the doped region 460 of the guard ring 10B can be turned on earlier than the doped region 420 and / or the doped region 430 of the high-voltage well 320. When the parasitic bipolar junction path is not turned on, the electrostatic discharge protection of the overall semiconductor device 10 can be improved.

[0119] Continuing to refer to Figure 1 and Figure 2 , a doped region 440 can be provided in the well 302. The doped region 440 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 440 can be of the second conductive type (N-type). According to some embodiments of the present invention, the doped region 440 can reduce the contact impedance. The doping concentration of the doped region 440 can be between 5.0×10 19 cm -3 and 1.0×10 21 cm -3 . The thickness of the doped region 440 can be between 0.09 μm and 0.11 μm. The formation method of the doped region 440 can be similar to the formation methods of the high-voltage well 320, the high-voltage well 340, and the deep well 360, and the details will not be repeated here.

[0120] Referring to Figure 1 and Figure 2 , a doped region 450 can be provided in the well 304. The doped region 450 can extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 450 can be of the second conductive type (N-type). According to some embodiments of the present invention, the doped region 450 can reduce the contact impedance. The doping concentration of the doped region 450 can be between 5.0×10 19 cm -3 and 1.0×10 21 cm -3 . The thickness of the doped region 450 can be between 0.09 μm and 0.11 μm. The formation method of the doped region 450 can be similar to the formation methods of the high-voltage well 320, the high-voltage well 340, and the deep well 360, and the details will not be repeated here.

[0121] In some embodiments, the doped regions 440 and 450 can serve as the high-voltage floating supply absolute voltage (VB) terminals. The doped regions 440 and 450, the wells 302 and 304, the epitaxial layer 300, and the buried layer 200 are all of the second conduction type (N-type), while the substrate 100 is of the first conduction type (P-type). The doped region 440 or 450, the buried layer 200, and the substrate 100 form a diode junction. During the operation of the semiconductor device 10, the doped region 440 or 450 can serve as an ideal electrostatic discharge path from the high-voltage region 10A-1 to the low-voltage region 10A-2.

[0122] Continuing to refer to Figure 1 and Figure 2 , a doped region 460 can be disposed in the well 342. The doped region 460 can be formed in the high-voltage well 340. In some embodiments, the doped region 460 laterally surrounds the doped regions 410, 420, 430, 440, and 450. The doped region 460 can vertically extend from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 460 can be of the first conduction type (P-type). According to some embodiments of the present invention, the doped region 460 can reduce the contact impedance. The doping concentration of the doped region 460 can be between 5.0×10 19 cm -3 and 1.0×10 21 cm -3 . The thickness of the doped region 460 can be between 0.18 μm and 0.22 μm. The formation method of the doped region 460 can be similar to the formation methods of the high-voltage wells 320, 340, and the deep well 360, and the details will not be repeated here.

[0123] Referring to Figure 1 and Figure 2 , a doped region 480 can be disposed in the well 362. The doped region 480 can be formed in the deep well 360. In some embodiments, the doped region 480 laterally surrounds the doped region 460 (and the doped regions 410, 420, 430, 440, and 450). The doped region 480 can vertically extend from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 480 can be of the second conduction type (N-type). According to some embodiments of the present invention, the doped region 480 can reduce the contact impedance. It should be noted that the deep well 360, the well 362, and the doped region 480 can together form a ring of the high-voltage junction terminal element 10A. The doping concentration of the doped region 480 can be between 5.0×10 19 cm -3 and 1.0×10 21 cm -3Therebetween. The thickness of the doped region 480 can be between 0.09 μm and 0.11 μm. The method of forming the doped region 480 can be similar to the methods of forming the high-voltage wells 320, 340, and the deep well 360, and the details thereof will not be repeated here.

[0124] Continuing to refer to Figure 1 and Figure 2 , isolation structures 500a and 500b can be formed on the epitaxial layer 300. Specifically, since their manufacturing processes involve high-temperature treatment, the isolation structures 500a and 500b are partially embedded in the epitaxial layer 300. According to some embodiments of the present invention, the isolation structures 500a and 500b can be drift oxides (DOX) used to isolate various conductive components to prevent short circuits in the semiconductor device 10 during operation. As Figure 2 shown, the doped region 480 can be laterally located between the isolation structure 500a and the isolation structure 500b. The isolation structure 500a can laterally isolate the doped region 480 from the doped region 460. The isolation structures 500a and 500b can be formed of silicon oxide (SiO), and can be local oxidation of silicon isolation structures formed by thermal oxidation. In other embodiments, the isolation structures 500a and 500b can be shallow trench isolation structures formed by etching, oxidation, and deposition processes.

[0125] Referring to Figure 1 and Figure 2 , after forming the isolation structures 500a and 500b, an interlayer dielectric layer 600 can be formed on the epitaxial layer 300. In some embodiments, the interlayer dielectric layer 600 can cover the epitaxial layer 300, the isolation structure 500a, and the isolation structure 500b. The interlayer dielectric layer 600 can not only provide mechanical protection and insulation for the underlying components, but also isolate different levels of conductive materials. The material of the interlayer dielectric layer 600 can include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiO x N y C 1-x-y, where x and y range from 0 to 1), tetraethyl orthosilicate (TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low-k dielectric materials, or other suitable dielectric materials.

[0126] The thickness of the interlayer dielectric layer 600 can be between 1000 μm and 1200 μm. The interlayer dielectric layer 600 can be formed by spin-on coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Then, a planarization process (such as chemical mechanical polishing) can be performed on the interlayer dielectric layer 600 to make the interlayer dielectric layer 600 have a flat top surface.

[0127] Continue to refer to Figure 1 and Figure 2, via holes 610, 620, 630, 640, 650, 660, and 680 can be formed to penetrate the interlayer dielectric layer 600. The via holes 610, 620, 630, 640, 650, 660, and 680 can physically contact the doped regions 410, 420, 430, 440, 450, 460, and 480 respectively. In addition, metal layers 710, 720, 730, 740, 750, 760, and 780 can be formed on the interlayer dielectric layer 600. In some embodiments, the metal layer 710 can be electrically coupled to the doped region 410 through the via hole 610, the metal layer 720 can be electrically coupled to the doped region 420 through the via hole 620, the metal layer 730 can be electrically coupled to the doped region 430 through the via hole 630, the metal layer 740 can be electrically coupled to the doped region 440 through the via hole 640, the metal layer 750 can be electrically coupled to the doped region 450 through the via hole 650, the metal layer 760 can be electrically coupled to the doped region 460 through the via hole 660, and the metal layer 780 can be electrically coupled to the doped region 480 through the via hole 680. According to some embodiments of the present invention, the metal layers 710, 720, 730, 740, 750, 760, and 780 can connect the high-voltage floating supply absolute voltage (VB) and the high-voltage floating supply offset voltage (VS). More specifically, the metal layers 720 and 760 are connected to the high-voltage floating supply offset voltage (VS), while the metal layers 740 and 780 are connected to the high-voltage floating supply absolute voltage (VB). The via holes 610, 620, 630, 640, 650, 660, 680, the metal layers 710, 720, 730, 740, 750, 760, and 780 can be integrally formed and thus include the same material.

[0128] The materials of via holes 610, 620, 630, 640, 650, 660, 680, metal layers 710, 720, 730, 740, 750, 760, and metal layer 780 may include amorphous silicon, polysilicon, poly - SiGe, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, and metals. The metals may include cobalt (Co), ruthenium (Ru), aluminum, palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, combinations thereof, or multi - layer films thereof. Via holes 610, 620, 630, 640, 650, 660, 680, metal layers 710, 720, 730, 740, 750, 760, and metal layer 780 may be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), plating, other suitable processes, or combinations thereof.

[0129] Figure 3 is a top - view of a semiconductor device 20 according to some embodiments of the present invention. The semiconductor device 20 includes a high - voltage junction terminal element 20A, a protection ring 20B, and a plurality of level shifters 20C. Compared with Figure 1The semiconductor device 10, and the guard ring 20B of the semiconductor device 20 includes a plurality of segments separated from each other. For simplicity, the features of the doped regions 410, 420, 430, 440, 450, 460, and 480 are similar to those Figure 1 shown, and the details will not be repeated herein.

[0130] Referring to Figure 3 , the semiconductor device 20 can be electrostatically discharged by the high-voltage regions 20A-1 to the low-voltage region 20A-2. In some embodiments, the high-voltage wells 340, 342, and the doped region 460 of the guard ring 20B can be patterned into a plurality of segments separated from each other, and the length of each segment is greater than 50 μm. For example, a patterned photoresist or hard mask can be formed on the epitaxial layer 300 before the ion implantation and / or diffusion process, and then the segments of the separated guard ring 20B are formed through the patterned photoresist or hard mask. Depending on the application and design requirements, the segments of the guard ring 20B can be disposed at the required positions, such as in the region where more active regions are concentrated in the high-voltage region 20A-1, or near the active regions closer to the ring of the high-voltage junction terminal element 20A. In other regions far from the active regions, the segments of the guard ring 20B can be selectively not provided. In other words, the guard ring 20B of the semiconductor device 20 does not need to be configured as a complete loop (such as the guard ring 10B of the semiconductor device 10). According to some embodiments of the present invention, the guard ring 20B can attract the current flowing to the parasitic bipolar junction path. The doped region 460 of the guard ring 20B and the doped regions 420 and / or 430 of the high-voltage well 320 can have the same potential, so the doped region 460 can replace the doped regions 420 and / or 430 as an alternative electrostatic discharge path. When the parasitic bipolar junction path is not turned on, the electrostatic discharge protection of the overall semiconductor device 20 can be improved.

[0131] Figure 4 is a top view of a semiconductor device 30 according to other embodiments of the present invention. The semiconductor device 30 includes a high-voltage junction terminal element 30A, a guard ring 30B, and a plurality of level shifters 30C. Compared with Figure 1 the semiconductor device 10, the semiconductor device 30 can further include a plurality of resistors 30D. For simplicity, the features of the doped regions 410, 420, 430, 440, 450, 460, and 480 are similar to those Figure 1 shown, and the details will not be repeated herein.

[0132] Referring to Figure 4, the semiconductor device 30 can be subjected to electrostatic discharge by the high-voltage regions 30A-1 to the low-voltage regions 30A-2. To increase the probability of electrostatic discharge through the doped region 440 and / or the doped region 450 as the desired path from the high-voltage region 30A-1 to the low-voltage region 30A-2, resistors 30D can be disposed between the doped region 420 and the doped region 460 of the guard ring 30B, and / or between the doped region 430 and the doped region 460 of the guard ring 30B. The resistance of each resistor 30D can be 15 ohms. That is, the guard ring 30B can be electrically coupled to the doped region 420 and / or the doped region 430 of the high-voltage well 320 by the resistor 30D to increase the impedance in the unwanted parasitic bipolar junction path to limit the current, thereby forcing the electrostatic discharge current to flow along the path of the doped region 440 and / or the doped region 450. It should be understood that the resistor 30D and the guard ring 30B are interdependent. That is, the resistor 30D can only be incorporated into the semiconductor device 30 having the guard ring 30B. According to some embodiments of the present invention, the guard ring 30B can attract the current flowing into the parasitic bipolar junction path. The doped region 460 of the guard ring 30B and the doped region 420 and / or the doped region 430 of the high-voltage well 320 can have the same potential, so that the doped region 460 can replace the doped region 420 and / or the doped region 430 as an alternative electrostatic discharge path. When the parasitic bipolar junction path is not turned on, the electrostatic discharge protection of the overall semiconductor device 30 can be enhanced.

[0133] Figure 5 and Figure 6 are a top view and a cross-sectional schematic view of a semiconductor device 40 according to other embodiments of the present invention. It should be noted that, Figure 6 is Figure 5 the cross-sectional schematic view obtained by the line B-B' of. The semiconductor device 40 includes a high-voltage junction terminal element 40A, a guard ring 40B, and a plurality of level shifters 40C. Compared with Figure 1 the semiconductor device 10 of, the semiconductor device 40 can further include a doped region 470 in the guard ring 40B. For simplicity, the characteristics of the doped region 410, the doped region 420, the doped region 430, the doped region 440, the doped region 450, the doped region 460, and the doped region 480 are similar to those shown in Figure 1 , and the details will not be repeated here.

[0134] Referring to Figure 5 and Figure 6, the semiconductor device 40 can be subjected to electrostatic discharge by the high-voltage regions 40A-1 to the low-voltage regions 40A-2. The doped region 460 and the doped region 470 can be simultaneously provided in the well 342. As previously mentioned, the doped region 460 has a first conductivity type (P-type). The doped region 470 can be configured to have a second conductivity type (N-type). As previously mentioned, the doped region 460, the buried layer 200, and the substrate 100 can form a parasitic bipolar (PNP) junction. In the case where the doped region 470 is added, the doped region 470 (N-type) of the guard ring 40B, the doped region 460 (P-type), the buried layer 200 (N-type), and the substrate 100 (P-type) can form a new parasitic bipolar (NPNP) junction. When the current of the electrostatic discharge is directed towards the path of the guard ring 40B, the new parasitic bipolar (NPNP) junction can further enhance the conduction ability. According to some embodiments of the present invention, the guard ring 40B can attract the current flowing towards the parasitic bipolar junction path. The doped region 460 of the guard ring 40B and the doped region 420 and / or the doped region 430 of the high-voltage well 320 can have the same potential, so the doped region 460 can replace the doped region 420 and / or the doped region 430 as an alternative electrostatic discharge path. When the parasitic bipolar junction path is not conducting, the electrostatic discharge protection of the overall semiconductor device 40 can be enhanced.

[0135] Continue to refer to Figure 5 and Figure 6 , the doped region 460 and the doped region 470 can be laterally adjacent to each other. In this embodiment, the metal layer 760 can be electrically coupled to the doped region 460 and the doped region 470 through the via hole 660. It should be understood that when the guard ring 40B is patterned into a plurality of mutually separated line segments (for example, applying Figure 3 's design), the doped region 470 should also be conformally patterned into a plurality of mutually separated line segments. As previously mentioned, the length of each line segment of the guard ring 40B is greater than 50 μm. It is worth noting that both the guard ring 40B and the doped region 470 of the guard ring 40B can be fabricated through existing masks, so the manufacturing cost or cycle will not be significantly increased.

[0136] In other embodiments, the doped region 470 can replace the doped region 460. In other words, only the doped region 470 is provided in the well 342, and the doped region 460 is not provided. The doped region 470 (N-type) of the guard ring 40B, the high-voltage well 340 (P-type), the buried layer 200 (N-type), and the substrate 100 (P-type) can still form a parasitic bipolar (NPNP) junction. When the electrostatic discharge current flows towards the path of the guard ring 40B, the parasitic bipolar (NPNP) junction can further enhance the discharge ability.

[0137] The semiconductor device of the present invention incorporates a guard ring adjacent to the inner side of the ring of the high-voltage junction terminal element. During the operation of the semiconductor device, unwanted parasitic bipolar junction paths may be generated. When the voltage applied by electrostatic discharge is too high, the high-voltage well of the parasitic bipolar junction path may be burned out, causing the semiconductor device to fail. The guard ring can attract the current flowing to the parasitic bipolar junction path, thus replacing the unwanted parasitic bipolar junction as an alternative electrostatic discharge path. When the parasitic bipolar junction path is not conducting, the electrostatic discharge protection of the overall semiconductor device can be enhanced.

[0138] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A high-voltage junction terminal element; A high-voltage region located within an annulus of the high-voltage junction terminal element; A low-voltage region located outside the annulus of the high-voltage junction terminal element; and A guard ring extending along the inner side of the annulus of the high-voltage junction terminal element, wherein the guard ring laterally surrounds the high-voltage region.

2. The semiconductor device according to claim 1, wherein, Further comprising a plurality of level shifters located on the annulus of the high-voltage junction terminal element.

3. The semiconductor device according to claim 2, wherein The plurality of level shifters are spaced apart from each other.

4. The semiconductor device according to claim 1, wherein, The guard ring is a complete loop.

5. The semiconductor device according to claim 1, characterized in that, The guard ring includes a plurality of mutually separated line segments, wherein the length of each line segment is greater than 50 μm.

6. The semiconductor device according to claim 1, wherein Further comprising: A substrate disposed across the high-voltage junction terminal element and having a first conductivity type; And An epitaxial layer disposed across the high-voltage junction terminal element and on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type.

7. The semiconductor device according to claim 6, wherein The high-voltage region includes a first high-voltage well disposed in the epitaxial layer and having the first conductivity type.

8. The semiconductor device according to claim 7, wherein, The first high-voltage well includes a first doped region having the first conductivity type.

9. The semiconductor device according to claim 8, wherein Further comprising a resistor electrically coupling the guard ring and the first doped region.

10. The semiconductor device according to claim 6, wherein The guard ring includes a second high-voltage well disposed in the epitaxial layer and having the first conductivity type.

11. The semiconductor device according to claim 10, wherein, The second high-voltage well includes a second doped region having the first conductivity type.

12. The semiconductor device according to claim 10, wherein, The second high-voltage well includes a second doped region and a third doped region having the first conductivity type and the second conductivity type respectively.

13. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate; Forming an epitaxial layer on the substrate; Forming a first high-voltage well in the epitaxial layer; Forming a first deep well in the epitaxial layer, wherein the first deep well laterally surrounds the first high-voltage well; and Forming a second high-voltage well in the epitaxial layer, wherein the second high-voltage well is adjacent to the first deep well and laterally surrounds the first high-voltage well, wherein the second high-voltage well is located between the first high-voltage well and the first deep well.

14. The method for forming a semiconductor device according to claim 13, wherein, The second high-voltage well and the first deep well respectively define a guard ring and a high-voltage junction terminal element.

15. The method for forming a semiconductor device according to claim 13, wherein, Further comprising forming a buried layer in the substrate, the buried layer directly contacting the first high-voltage well, the second high-voltage well, and the first deep well.

16. The method for forming a semiconductor device according to claim 13, wherein The first high-voltage well and the second high-voltage well have a first conductivity type, while the first deep well has a second conductivity type different from the first conductivity type.

17. The method for forming a semiconductor device according to claim 16, wherein, Forming a first doped region, a second doped region, and a third doped region in the first high-voltage well, the second high-voltage well, and the first deep well respectively.

18. The method for forming a semiconductor device according to claim 17, wherein, The first doped region and the second doped region have the first conductivity type, while the third doped region has the second conductivity type.

19. The method for forming a semiconductor device according to claim 18, wherein, Further comprising forming a fourth doped region in the second high-voltage well adjacent to the second doped region, wherein the fourth doped region has the second conductivity type.

20. The method for forming a semiconductor device according to claim 18, wherein, Patternizing the second high-voltage well and the second doped region into a plurality of mutually separated line segments, wherein the length of each line segment is greater than 50 μm.

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