Image sensor with tunable floating diffusion structure

Abstract

Image sensors with tunable floating diffusion (FD) structures for applications such as inspection and metrology are provided. One image sensor includes a sense node electrically connected to a circuit of the image sensor, formed on a first side of a silicon layer adjacent to the circuit, and formed of a voltage controlled variable floating diffusion (VCVFD) structure. The VCVFD structure includes a gate electrode configured to control a variable capacitance of the VCVFD structure via a voltage applied to the gate electrode through an electrical connection to the gate electrode. The VCVFD structure converts charge accumulated in response to electrons in a channel of the circuit to a voltage that is proportional to the amount of charge and depends on the variable capacitance. The VCVFD may also be implemented in an electronic sensor pixel configured for detecting electrons or x-rays, as further described herein.

Description

Technical Field

[0001] The present invention generally relates to an image sensor having a tunable floating diffusion structure (also referred to herein as a sensing node) that is particularly suitable for use in a charge coupled device (CCD) for applications such as inspection and metrology. Background Art

[0002] The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.

[0003] Semiconductor devices that fabricate (e.g.) logic and memory devices typically involve processing a substrate (e.g., a semiconductor wafer) using a large number of semiconductor manufacturing processes to form various features and multiple levels of the semiconductor device. For example, lithography is a semiconductor manufacturing process that involves transferring a pattern from a photomask to a resist disposed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include (but are not limited to) chemical mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices can be fabricated on a single semiconductor wafer in a certain arrangement and then divided into individual semiconductor devices.

[0004] The integrated circuit industry needs to provide inspection tools with increasingly high sensitivity to detect smaller defects and particles while maintaining high throughput for lower cost of ownership. The semiconductor industry is currently fabricating semiconductor devices having feature sizes of about 20 nanometers (nm) and smaller. In a few years, the industry will fabricate devices having a feature size of about 5 nm. Particles and defects that are only a few nm in size can reduce wafer yield and must be captured to ensure high yield production. In addition, efforts have been made to accelerate inspection to address a possible future transition from today's 300 mm diameter wafers to 450 mm diameter wafers. Thus, the semiconductor industry is driven by an increasing need for inspection tools that can achieve substantially high sensitivity at substantially high speed.

[0005] Image sensors are key components of semiconductor inspection tools. They play an important role in determining defect detection sensitivity and inspection speed. Considering their image quality, light sensitivity, and readout noise performance, charge coupled devices (CCDs) are widely used as image sensors for semiconductor inspection applications. Signal-to-noise ratio (SNR) and dynamic range (DR) are important figure of merits for CCD image sensors. SNR describes the ability of the sensor to detect a light signal on a particular noise-limited background, while DR quantifies the ability of the sensor to image both high-light and low-light scenarios adequately.

[0006] An image sensor typically includes a reverse-biased pn junction that operates as a capacitor to convert collected charge generated by incident radiation or electrons into a voltage, which can then be buffered and / or amplified and converted into a digital signal. This reverse-biased pn junction is referred to herein as a floating diffusion (FD) region. The capacitance of the FD region of an image sensor defines the upper and lower limits of the optical signal that can be detected, and thus the dynamic range of a subsequent CCD image sensor. Having a relatively small FD capacitance reduces the lower limit of the optical signal detection level (due to a higher signal voltage per collected unit of charge resulting from the smaller capacitance), enabling smaller signals to be detected; however, this comes at the cost of reducing the maximum detectable signal. Using a larger FD capacitance increases the maximum detectable signal but reduces the sensitivity of the image sensor to low-level optical signals. Accordingly, there is a need for a CCD image sensor that implements a tunable FD, which facilitates a relatively high dynamic range to improve inspection systems and overcomes all of the limitations described above.

[0007] Accordingly, it would be advantageous to develop an image sensor that does not have one or more of the disadvantages described above. SUMMARY OF THE INVENTION

[0008] The following description of the various embodiments should in no way be construed as limiting the subject matter of the appended claims.

[0009] One embodiment relates to an image sensor that includes a silicon layer configured to generate electron-hole pairs when light is incident on a photosensitive region of the silicon layer. The image sensor further includes circuitry formed on a first side of the silicon layer. The circuitry includes a channel and a first gate electrode configured to control electron accumulation in the channel in response to photo-induced generation of the electron-hole pairs.

[0010] The image sensor further includes a sense node electrically connected to the circuitry, formed on the first side of the silicon layer adjacent to the circuitry and outside the photosensitive region, and formed by a voltage-controlled variable floating diffusion (VCVFD) structure. The VCVFD structure includes a source region and a channel region. The source region of the VCVFD structure is connected to the channel of the circuitry and to an output circuit of the image sensor. The VCVFD structure further includes a second gate electrode adjacent to the source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the second gate electrode through an electrical connection to the second gate electrode.

[0011] The VCVFD structure is configured to convert charge responsive to the electron accumulation into a voltage proportional to the amount of the charge and dependent on the variable capacitance. The output circuit is configured to generate an output in response to the voltage output by the VCVFD structure. The image sensor may be further configured as described herein.

[0012] Another embodiment relates to a system configured to determine information about a sample. The system includes an illumination subsystem configured to direct light generated by a light source to the sample. The system also includes an image sensor positioned in the path of light from the sample and configured as described above. The light incident on the photosensitive region of the silicon layer is the light from the sample. The system further includes a computer subsystem configured to determine information about the sample based on the output generated by the output circuitry of the image sensor. The system may be further configured as described herein.

[0013] Another embodiment relates to a computer-implemented method for determining information about a sample. The method includes: directing light generated by a light source to the sample; and detecting light from the sample using an image sensor configured as further described above. The light from the sample is incident on the photosensitive region of the image sensor. The method also includes determining information about the sample based on the output generated by the output circuitry of the image sensor.

[0014] The steps of the method may be performed as further described herein. The method may include any other steps of any other method described herein. The method may be performed by any system described herein.

[0015] A further embodiment relates to a non-transitory computer-readable medium storing program instructions that may be executed on a computer system to perform a computer-implemented method for determining information about a sample. The computer-implemented method includes the steps of the method described above. The computer-readable medium may be further configured as described herein. The steps of the computer-implemented method may be performed as further described herein. Additionally, the computer-implemented method for which the program instructions are executed may include any other steps of any other method described herein.

[0016] Some embodiments relate to an electronic sensor pixel comprising a silicon layer that includes: an n-type buried channel layer that forms a first surface of the silicon layer; and a p-type electron-sensitive layer disposed between the buried channel layer and an opposing second surface of the silicon layer. The silicon layer further includes a floating diffusion disposed in the buried channel layer adjacent a central region of the pixel. The floating diffusion includes a sensing node formed by a VCVFD structure. The VCVFD structure includes a VCVFD source region and a VCVFD channel region. The VCVFD source region is connected to the channel of the pixel and an output circuit of the pixel. The VCVFD structure further includes a VCVFD gate electrode that is adjacent the VCVFD source region and configured to control a variable capacitance of the VCVFD structure via a voltage applied to the VCVFD gate electrode through an electrical connection to the VCVFD gate electrode. The VCVFD structure is configured to convert charge responsive to electrons moving in the n-type buried channel layer toward the floating diffusion into a voltage proportional to the amount of the charge and dependent on the variable capacitance.

[0017] The electronic sensor pixel further includes a resistive gate that includes at least one gate structure disposed above the first surface and configured such that an outer peripheral edge of the gate structure is substantially aligned with an outer peripheral edge of the buried channel layer. The gate structure defines a central opening such that an inner peripheral edge of the gate structure substantially surrounds and is spaced from the central region. The buried channel layer and the p-type electron-sensitive layer are configured such that the p-type electron-sensitive layer generates a plurality of electrons in response to each incident electron or X-ray photon and such that the generated plurality of electrons are driven into the buried channel layer. The resistive gate is configured such that when a reduced potential difference is applied between the inner peripheral edge and the outer peripheral edge of the gate structure, the resistive gate generates a first electric field that causes electrons in the n-type buried channel layer to move toward the floating diffusion. The electronic sensor pixel may be further configured as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other objects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings, in which:

[0019] Figure 1A is a schematic side cross-sectional view illustrating an embodiment of a voltage-controlled variable floating diffusion (VCVFD) structure;

[0020] Figure 1B is a schematic top view illustrating Figure 1A the VCVFD structure of

[0021] Figure 2AIs a schematic side cross-sectional view illustrating another embodiment of a VCVFD structure including a field effect transistor (FET) type structure having connected source and drain sections;

[0022] Figure 2B Is illustrative of Figure 2A A schematic top view of the VCVFD structure of;

[0023] Figure 3 Including a profile of the potential across the gate of the VCVFD structure and the distance into the semiconductor layer below the gate; Figure 1A A schematic of;

[0024] Figure 4 Is a schematic side cross-sectional view illustrating an additional embodiment of an image sensor including a back-illuminated charge coupled device (CCD) configured to include a VCVFD structure;

[0025] Figure 5 Is a schematic side view illustrating an embodiment of a system configured to determine information about a sample including a sensor configured as described herein;

[0026] Figures 6A to 6C Is a schematic plan view illustrating an embodiment of an image sensor in which a VCVFD is electrically connected to a different number of pixel columns;

[0027] Figure 7 Is a block diagram illustrating an embodiment of a non-transitory computer-readable medium storing program instructions that can be executed on a computer system to perform one or more of the computer-implemented methods described herein;

[0028] Figure 8 Illustrates an exemplary SEM incorporating a backscattered electron detector and a secondary electron detector according to an embodiment of the present invention;

[0029] Figure 9 Illustrates an exemplary method of inspecting or reinspecting a sample;

[0030] Figure 10A 、 10B And 10C illustrate key aspects of an exemplary solid-state electron detector including a plurality of pixels according to an embodiment of the present invention, wherein each pixel has one output;

[0031] Figure 11A And 11B Illustrate a single-pixel electron sensor according to an exemplary specific embodiment of the present invention in exploded and assembled front / top perspective views;

[0032] Figure 12A And 12B Is a display of during operationFigure 11B Simplified cross-sectional view of a pixel;

[0033] Figure 13 is a simplified plan view showing an exemplary layout of an amplifier utilized by a pixel according to an alternative embodiment of the present invention; and

[0034] Figure 14 is a simplified plan view showing a pixel layout according to another alternative embodiment of the present invention.

[0035] While the present invention is susceptible to various modifications and alternative forms, specific embodiments of the invention are shown by way of example in the figures and will be described in detail herein. However, it should be understood that the figures and their detailed description are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. Detailed Description

[0036] Referring now to the figures, it should be noted that the figures are not drawn to scale. In particular, the scale of some elements of the figures is greatly exaggerated to emphasize the characteristics of the elements. It should also be noted that the figures are not drawn to the same scale. Elements having similar configurations shown in more than one figure have been indicated by the same reference numerals. Unless otherwise mentioned herein, any element described and shown may comprise any suitable commercially available element.

[0037] The embodiments described herein generally relate to image sensors having a tunable floating diffusion (FD) structure for applications such as inspection and metrology, such as charge-coupled devices (CCDs). More specifically, the embodiments relate to the FD capacitance of an image sensor such as a CCD, and more particularly to a voltage-tunable FD capacitance. Additionally, the embodiments described herein provide improvements to CCD image sensors for semiconductor inspection systems to achieve a relatively high dynamic range using a voltage-controlled variable floating diffusion (VCVFD) structure. The terms "floating diffusion" and "sensing node" may be used interchangeably herein.

[0038] Currently, the FD region is formed as an n+ implant in the semiconductor layer. This configuration enables the implementation of standard transistors adjacent to the FD, such as transfer transistors and reset transistors. Using an n+ implant to form the FD also provides good ohmic contact between the contact plug and the FD. However, this configuration only provides a fixed pn junction capacitance that cannot be changed after the manufacture of the CCD image sensor.

[0039] A variable FD can be made by including a number of parallel fixed FD regions on an image sensor chip. An array of switch or transfer transistors can selectively couple the parallel fixed FD regions to the sensor output circuit. An electronic signal can be applied to the gates of a subset or all of the transfer transistors to electronically connect the selected fixed FD regions to the sensor output. Other electronic signals can turn off the other transfer transistors, thus disconnecting their fixed FD regions from the sensor output. As more parallel fixed FD regions are connected to the sensor output, the capacitance increases. Thus, the total capacitance attached to the sensor output can be electronically selected. One drawback of this method is that at least one switch must be directly connected to the sensor output. The capacitance of this switch and its connection to the sensor output will add to the capacitance of the FD connected to the sensor output, thus limiting the minimum FD capacitance that can be achieved and thus limiting the sensitivity of this CCD to essentially low light levels.

[0040] Although this switch-controlled variable FD can be useful in situations where sensitivity to essentially low light levels is not required, a variable FD controlled by an analog voltage can be a more compact and desirable choice for CCD image sensors in semiconductor inspection systems. A variable FD that changes its capacitance value based on the applied voltage can allow a wider range of capacitances, rather than the limited quanta of capacitances selected by binary control signals. An analog voltage-controlled variable capacitor that can be integrated into a CCD image sensor fabricated in a common CCD process is desired.

[0041] One embodiment of an image sensor includes a silicon layer configured to generate electron-hole pairs when light is incident on a photosensitive region of the silicon layer. Figure 4 Describe some aspects of the design, fabrication, and operation of an image sensor 400 that is a back-illuminated CCD image sensor configured to implement a VCVFD structure 450. When light 499 is absorbed in silicon, electron-hole pairs are generated. In this way, light 499 is incident on the back side (also referred to herein as the "second side") of the image sensor 400, which is opposite the front side (also referred to herein as the "first side") of the image sensor where the circuit of the image sensor is formed. The photosensitive region of the sensor can include, for example, the entire region of the sensor where the image sensor circuit (or pixel) is formed. The silicon layer can be configured to generate electron-hole pairs in any suitable manner known in the art.

[0042] In one embodiment, the silicon layer is a silicon epitaxial layer. In one such embodiment, the silicon epitaxial layer includes intrinsic or p-type doped silicon having a dopant concentration of less than 10 14 cm -3 . For example, the epitaxial layer can be fabricated on a highly p-type doped silicon substrate having a dopant concentration greater than about 10 15 cm -3 . As Figure 4As shown in [description], the sensor is fabricated in an intrinsic or lightly p-type doped epitaxial layer 401 having a thickness between a few microns and several tens of microns.

[0043] In another embodiment, the image sensor includes a thin p-type layer having a dopant concentration at least ten times higher than that of the silicon epitaxial layer, and the thin p-type layer is disposed on a second side of the silicon epitaxial layer opposite to a first side of the silicon layer. In a backside-illuminated image sensor, the backside (photosensitive) surface of the epitaxial layer 401 is where light 499 is incident. A substantially highly doped p+ layer 403 can be formed at the surface by ion implantation or driving in of boron atoms from a thin boron layer deposited on the backside surface of the epitaxial layer 401. The backside p+ layer 403 is "thin", where it can be substantially shallow (from a few nanometers to several tens of nanometers) to ensure suitable sensitivity to ultraviolet (UV), deep UV (DUV), and vacuum UV (VUV) light. Under long-term exposure to DUV or VUV light, charges and traps can accumulate in the silicon dioxide at the backside surface of the epitaxial layer 401 and can degrade sensor performance. The shallow p+ layer 403 introduces fixed negative charges on the sensor backside, which prevents photo-generated charges from being trapped at defects and maintains sensitivity to UV, DUV, and VUV light. An optional electrical connection 411 can be made to the backside p+ layer 403 and used to apply a bias voltage to the sensor backside (e.g., connect it to ground).

[0044] In an additional embodiment, the image sensor includes an anti-reflection layer disposed on a second side of the silicon layer opposite to the first side. For example, the anti-reflection layer can include a backside coating 480 deposited on the back surface of the epitaxial layer 401. Depending on the wavelength of interest, the backside coating 480 can be a substantially thin layer of pure boron or silicon dioxide or one or more anti-reflection layers (e.g., made of aluminum oxide) to reduce sensor reflectivity and improve sensitivity at that wavelength. For example, in addition to the doping level ranges described herein, the backside optical coating can also be custom-engineered to be highly sensitive to the wavelengths of interest of the systems in which the sensor can be used as further described herein.

[0045] The image sensor also includes circuitry formed on the first side of the silicon layer. The circuitry includes a channel and a first gate electrode configured to control the accumulation of electrons in the channel in response to the photo-induced generation of electron-hole pairs. For example, when light 499 is absorbed in silicon, electron-hole pairs are generated. The holes move to the backside surface where they recombine, while the electrons are accelerated towards the channel formed by the n-type layer 404 by an electric field generated across the sensor by a voltage applied to the gate electrodes (e.g., gates 420, 422, 424, and 426, which form photosensitive pixel columns) on the front side of the sensor. Although only four gates are shown for clarity purposes, in a preferred embodiment, far more gates are used to form a substantially large number of light-collecting pixels, from one pixel per column (e.g., a line sensor) to thousands of pixels.

[0046] A potential difference is applied to these gates via electrical connections 421, 423, 425, and 427 to control where (under which gate) the collected photo-generated electrons accumulate in the n-type layer 404. The electrons will accumulate under the gate with the maximum potential thereunder. For example, if the contact 427 connected to the gate 426 is at a voltage of +5V and the contact 425 connected to the gate 424 is at a voltage of -5V, then the electrons will accumulate under the gate electrode 426.

[0047] In addition to controlling the storage of charge, the gates are also used to transfer the stored charge from one pixel to another. For example, if electrons are stored under the gate 426, then raising the voltage applied to the gate 424 by the contact 425 to a voltage more positive than the voltage applied to the gate 426, and / or lowering the voltage applied to the gate 426 by the contact 427 to a voltage smaller (more negative) than the voltage applied to the gate 424 will cause the electrons to move from under the gate 426 to under the gate 424. Subsequently, the electrons can be made to move from the gate 424 to 422, from the gate 422 to the gate 420, etc. by appropriately changing the voltages applied to the electrodes 425, 423, and 421.

[0048] As in CCD technology, the gates can be configured as two-phase, three-phase, or four-phase clocks (i.e., there are two, three, or four gates per pixel, respectively). Additionally, in sensors applicable to semiconductor inspection (such as time delay integration (TDI) sensors), the gates are timed at a rate that causes the charge to be transferred in synchronization with a moving image falling on the sensor (e.g., in synchronization with the movement of a stage on which the sample to be inspected is held).

[0049] At one end of the photosensitive pixel gate, for example, when electrons are under the gate 420, the electrons are made to move to a first buffer gate (such as 430) by applying a voltage higher than the voltage applied to the contact 421 connected to the gate 420 to the contact 431 connected to the gate 430. Then, a voltage more positive (e.g., several volts more positive) than the voltage applied to the gate 430 is applied to the second buffer gate 435 via the contact 436, thereby causing the electrons to move under the second buffer gate 435. After this transfer, lowering the first buffer gate 430 to a voltage smaller than the voltage applied to the pixel gate 420 by the contact 421 stops the transfer of electrons to the region under the buffer gate 435 and allows the accumulation of electrons from the next image pixel under the buffer gate 430.

[0050] In a preferred embodiment, the sensor 400 may include additional gates similar to 440, each gate having an electrical connection (e.g., 441) to form a readout register that transfers an image signal from a circuit (e.g., a CCD pixel) to a VCVFD sensing node (e.g., 450) for charge-to-voltage conversion. Depending on the application in which the sensor will be used, the number of additional gates may vary from a few to dozens (typically from 2 to 32). Electrons are transferred from one gate of the readout register to another by appropriately sequencing the voltages applied to the gates, as is done in a CCD. In another embodiment, there may be no readout register and gate 440 may be omitted, and electrons may be transferred directly to the VCVFD structure, which may be configured as further described herein.

[0051] In one embodiment, the channel of the circuit includes an n-type doped buried channel. For example, an n-type layer 404 having a dopant concentration of about 10 16 cm -3 may be formed directly beneath the top (front) surface of the epitaxial layer 401. When the sensor is appropriately biased, layer 404 forms a buried channel for collecting and transferring electrons, as described above. p+-type layers 405 may be at both ends of the n-type layer 404, and the p+-type layers 405 have a dopant concentration that is greater than or equal to about 2 times the dopant concentration of the n-type layer. The p+ layer 405 is connected to ground through one or more electrical contacts (e.g., 412), and it may be connected to ground at multiple locations.

[0052] A dielectric layer 408 is formed (e.g., grown) on the front surface of the epitaxial layer. The dielectric layer may include: a single dielectric material, such as silicon dioxide; multiple dielectric material layers, such as a silicon nitride layer on top of a silicon dioxide layer; or a three-layer stack, such as silicon dioxide on silicon nitride on silicon dioxide. A suitable dielectric thickness is in the range from about 50 nm to about 200 nm. The dielectric layer 408 may optionally have openings etched therein to allow electrical contact to the underlying silicon when needed. Multiple gate electrodes (e.g., 420, 422, 424, 426, 430, 435, and 440), which may be made of polysilicon, are formed (e.g., deposited and patterned) on top of the dielectric layer 408. The gate electrodes are separated from each other by a dielectric material (not shown). Electrical connections (e.g., 421, 423, 425, 427, 431, 436, and 441) may be made to the gate electrodes. In a preferred embodiment, the gate electrodes overlap each other (as shown, for example, at 432) to control the edge electric field near the edges of the electrodes.

[0053] In one embodiment, the image sensor is configured as a CCD. In another embodiment, the image sensor is configured as a back-illuminated CCD. In some embodiments, the circuit is configured as a CCD circuit. In additional embodiments, the circuit is configured as a metal-oxide semiconductor field-effect transistor (MOSFET). For example, the image sensor described herein may be configured as a back-illuminated CCD image sensor implementing a VCVFD structure. As further described above, the image sensor may include CCD pixels and circuitry on the front side of an intrinsic or lightly p-type doped silicon epitaxial layer and may incorporate a pure boron layer on its back (illuminated) surface. Electrons generated by light at near-infrared (near-IR), visible, UV, DUV, VUV, extreme UV (EUV), and / or X-ray wavelengths are detected in the epitaxial layer and collected by the CCD pixels on the front side of the epitaxial layer due to an electric field generated across the epitaxial layer by an appropriate voltage applied to the CCD pixels. The electrons collected by the CCD pixels are transferred to a VCVFD structure configured to perform charge-to-voltage conversion and connected to a CCD readout circuit. As further described herein, sensor embodiments may be configured as CCD sensors for semiconductor wafer, photomask, and printed circuit board (PCB) inspection.

[0054] In additional embodiments, the image sensor is configured as a CCD, the CCD being configured to function as a time delay integration (TDI) sensor. For example, sensor embodiments described herein may be CCD sensors that function as TDI sensors for inspection of wafers, photomasks, PCBs, etc. This image sensor may be configured such that the gates are timed at a rate that causes charge to be transferred in synchronization with a moving image falling on the sensor (e.g., in synchronization with the movement of a stage on which the sample to be inspected is held). This embodiment of the sensor and the system in which the sensor may be used may be further configured as described in U.S. Patent No. 9,620,547, issued to Chuang et al. on April 11, 2017, which is incorporated herein by reference in its entirety as if fully set forth herein. For example, the sensor described herein may be configured as a CCD sensor having internal avalanche multiplication, as described in this patent.

[0055] The image sensor further includes a sensing node electrically connected to the circuitry. For example, as Figure 4 shown, the image sensor includes a sensing node 450 connected to the circuitry (e.g., formed by gate electrodes 420, 422, 424, 426, 430, 435, and 440). The sensing node may be electrically connected to the circuitry, as further described herein.

[0056] The sense node adjacent circuitry is formed on a first side of the silicon layer and outside the photosensitive region. In this way, the sense node is adjacent to one or more gate electrodes (e.g., CCD gate electrodes such as gate electrodes 420, 422, 424, 426, 430, 435, and 440) and receives signal charge from them. Thus, the embodiments described herein are different from complementary metal oxide semiconductor (CMOS) image sensor pixels, where the VCVFD structure would have to be embedded in each pixel. In other words, in a CMOS device, the VCVFD structure would have to be formed in the photosensitive region of the device, while in many of the embodiments described herein, the VCVFD structure can advantageously be formed outside the photosensitive region, as Figure 4 shown.

[0057] The sense node 450 is formed by the VCVFD structure. Figure 1A and 1B show a side view and a top view, respectively, of a basic VCVFD structure implemented on a silicon layer. The VCVFD structure includes a source region 104 and a channel region 108. As Figure 1A and 1B shown, one end of the silicon layer 100 under the polysilicon gate is doped with an n-type impurity having a concentration that is several orders of magnitude higher than the p-type doping 102 of the silicon layer (e.g., in the range from 10 18 to 10 20 atoms per cubic centimeter) to form the pn junction of the source 104 of the VCVFD structure. The source of the VCVFD structure (e.g., via electrical connection 106) is electrically connected to a sense amplifier that buffers a voltage signal corresponding to the charge stored in the VCVFD capacitor to the image sensor output.

[0058] The source region of the VCVFD structure is connected to the channel of a circuit (not shown in Figure 1A and 1B ) and the output circuit of the image sensor (not shown in Figure 1A and 1B ). The source region of the VCVFD structure can be connected to the channel, as further described herein and shown in Figure 4 . As further described herein, the source 104 can be connected to the channel of the circuit such that the VCVFD structure receives charge 120 from the sensor circuit.

[0059] In one embodiment, the source region of the VCVFD structure is connected to a charge reset structure in the image sensor. For example, the source 104 can be connected to Figure 1BThe adjacent reset structure 122 shown in [description], the reset structure 122 is formed by a polysilicon gate 124 (to which the reset gate (RG) voltage is applied via an electrical connection 126) and an n-type drain 128 (to which a fixed reset drain (RD) voltage is applied by an electrical connection 130). After the voltage signal at the VCVFD source is read out by a sense amplifier, the RG gate is biased to connect the VCVFD source to the RD voltage which is typically higher than the VCVFD source voltage, such that charge is discharged from the VCVFD source. Thus, the VCVFD structure is reset to the RD voltage. When the reset is complete, the VCVFD source is disconnected from the RD voltage, such that it can receive the next charge signal from the circuitry of the image sensor.

[0060] In one embodiment, the source region of the VCVFD structure and the channel of the circuitry are doped with the same polarity, and the source region of the VCVFD structure has a dopant concentration equal to or higher than that in the channel of the circuitry. For example, as Figure 4 shown in [description], the VCVFD structure 450 may include a source 451 formed by an n+-type silicon region implanted and / or diffused into an epitaxial layer 401. The dopant concentration of the source 451 is typically several orders of magnitude higher than that of the n-type layer 404, for example, in the range from 10 18 cm -3 to 10 21 cm -3 range.

[0061] In another embodiment, the channel region of the VCVFD structure and the channel of the circuitry are doped with the same polarity. For example, both the channel region of the VCVFD structure and the channel of the circuitry may be n-type channels. The VCVFD channel and the channel of the circuitry can be formed in the same step and can have the same or different dopant concentrations. Thus, in the same manner as the circuitry, the VCVFD structure can be either a surface channel type or a buried channel type. For example, in some embodiments, the channel region of the VCVFD structure is configured as an n-type buried channel. In another embodiment, the channel region of the VCVFD structure is configured as an n-type surface channel. In this way, the gate electrode of the VCVFD structure can be either an n-type buried channel or an n-type surface channel.

[0062] The VCVFD structure further includes a VCVFD gate electrode (also referred to herein as the "second gate electrode") adjacent to the source region. For example, Figure 4 the VCVFD gate electrode 452 shown in [description] can be formed using the same polysilicon material as the CCD pixel gates (e.g., gates 420, 422, 424, and 426) and using the same dielectric layer 408 or using different electrode and dielectric materials. As Figure 4 illustrated in [description] (and in Figure 1Aclearer in [reference] and further described herein), the VCVFD gate 452 is typically adjacent to the source 451 and may slightly overlap it. Similarly to the CCD, the VCVFD structure 450 may include a reset transistor adjacent to the VCVFD source and connected to a fixed reset voltage ( Figure 4 not shown in [reference]). The reset transistor may be used to reset the VCVFD structure before transferring electrons from the pixel, as further described herein. Figure 4 The VCVFD structure shown in [reference] may be connected to a charge reset structure, as Figure 1B and Figure 2B further shown and described in [reference].

[0063] The VCVFD gate electrode is configured to control the variable capacitance of the VCVFD structure by applying a voltage to the VCVFD gate electrode via an electrical connection to the VCVFD gate electrode. For example, the gate 452 has an electrical connection 453 via which the voltage applied to the VCVFD gate can be controlled. In this way, the VCVFD structure can be configured as an analog VCVFD structure for an image sensor (e.g., a CCD image sensor using a metal oxide semiconductor (MOS) structure including a gate and a source). When the gate-to-source voltage (V G ) of the MOS structure is higher than the threshold voltage (V T ), charges can be stored in the MOS inversion layer and in the source-bulk pn junction capacitor. The total capacitance of this FD structure can be controlled via an analog gate voltage.

[0064] As Figure 1A shown in [reference], the VCVFD gate electrode of the VCVFD structure may include a polysilicon gate 112 separated from a silicon layer 100 by a relatively thin layer of oxide dielectric (i.e., gate oxide) 110. The polysilicon gate has an electrical connection 114 through which the voltage V G is applied to the VCVFD gate, thus forming a MOS structure. Depending on the desired VCVFD capacitance, the lateral dimension of this polysilicon gate can vary from a few micrometers to dozens of micrometers. The thickness of the oxide dielectric layer can vary from a few nanometers to dozens of nanometers and can be determined by the CCD image sensor manufacturing process and the desired VCVFD capacitance.

[0065] Figure 1A The p+ ohmic contact 116 shown in [reference] can be formed by locally implanting a higher density of p-type impurities at the surface of the silicon layer. The p+ ohmic contact may have an electrical connection 118 to connect the silicon layer to the ground potential.

[0066] Figure 3 shows the electrostatic potential across Figure 1AThe profile 302 of the distance of the polysilicon gate, oxide dielectric of the VCVFD structure embodiment, and the line 300 (from point A to point B) into the semiconductor layer under the gate. The total capacitance of the VCVFD structure is

[0067] C VCVFD (V G ) = C S + C Gate (V G )

[0068] where C S is the capacitance of the VCVFD source representing the minimum C VCVFD , which is typically determined by the capacitance of the pn junction forming the VCVFD source and its parasitic capacitances (e.g., due to the overlap of the nearby CCD gate with the VCVFD source and the interconnection between the VCVFD source and the CCD sense amplifier), and C Gate is the additional capacitance due to the VCVFD gate, which is controlled by the voltage V G applied to the gate itself. Referring to Figure 3 , and using the analysis performed in "A Tradeoff Analysis of Transfer Speed Versus Charge-Handling Capacity for CCD’s" by Barbe et al. (Technology and Applications of CCDs Workshop, Edinburgh, Scotland, 1974, which is incorporated herein by reference as if fully set forth), in the case where it is assumed that the charge in the buried channel is depleted by applying a relatively large positive voltage, it has been shown that for a VCVFD based on a buried-channel field-effect transistor (FET), C Gate is determined by

[0069]

[0070] where

[0071]

[0072] and d, ε OX , ε S and t are the thickness of the oxide layer, the oxide dielectric constant, the silicon dielectric constant, and the thickness of the buried-channel layer, respectively. N is the minority carrier density collected under the gate, where N A and N D are the acceptor and donor concentrations in the silicon layer, respectively, and

[0073] φmin = φ c + φ j = φ min (V G )

[0074] is the minimum value of the potential of the buried channel layer that depends on the voltage V applied to the gate of the VCVFD. The above equation can also be used for a VCVFD structure based on a surface channel FET by setting t to zero, such that G where is the gate oxide capacitance per unit area, and where N is replaced by the gate surface potential φ D / (N D + N A )φ min For a VCVFD structure based on a surface channel FET, the C S capacitance is proportional to the gate voltage swing. It increases as the gate voltage increases, but at relatively high gate voltages, it can ultimately be limited by surface avalanche breakdown or oxide breakdown effects. For a VCVFD based on a buried channel FET, the capacitance can be limited by the gate voltage swing or by the doping characteristics of the buried channel. Gate

[0075] The VCVFD structure is configured to convert the charge responsive to electron accumulation into a voltage that is proportional to the amount of charge and depends on the variable capacitance. For example, the VCVFD structure converts the charge of electrons into a voltage that is proportional to the amount of charge and depends on the total capacitance of the VCVFD structure, which is determined by the sum of the fixed capacitance of the VCVFD source and the variable capacitance of the VCVFD gate, and is controlled by the voltage applied to Figure 4 the electrode 453 shown in. In this way, during operation, the charge collected from an (e.g., CCD) imaging element (pixel) is transferred to the VCVFD structure and stored in its source - bulk pn - junction capacitor. When the polysilicon gate voltage V Figure 4 G is lower than the threshold voltage V T of the MOS structure formed by its oxide dielectric and the silicon layer, the charge stored in the channel 108 under the polysilicon gate is substantially small. On the other hand, when the polysilicon gate voltage V G is higher than the threshold voltage V T of the MOS structure, in addition to the source - bulk pn - junction capacitor, charge is also stored in the channel under the polysilicon gate.

[0076] As shown in Figure 1A and 1BThe VCVFD structure described in Figure 1A and 1B can also be formed by the source and gate of a "partial" FET device lacking a drain. The partial FET structure can be of either an enhancement mode (surface channel) type or a depletion mode (buried channel) type. In a preferred embodiment, the CCD gate and the partial FET structure used to form the VCVFD structure are of the buried channel type, which is a better choice for use in a CCD image sensor to avoid the charge transfer and noise performance problems typical of surface channel devices.

[0077] In another embodiment, the VCVFD structure includes a drain region connected to the channel region of the VCVFD structure, and the source region and the drain region of the VCVFD structure are electrically connected. Figure 2A and 2B Side and top views respectively show alternative embodiments of the VCVFD structure formed by the n-type source 204 and drain 206 of an FET on a p-type 202 silicon layer 200. The source region 204 and the drain region 206 are formed on either side of a channel 208 on which a polysilicon gate 214 is formed. Depending on the desired VCVFD capacitance, the lateral dimension of the polysilicon gate 214 can vary from a few microns to dozens of microns. The polysilicon gate is separated from the silicon layer 200 by a relatively thin layer of oxide dielectric 212 (i.e., gate oxide). The thickness of the oxide dielectric layer can vary from a few nanometers to dozens of nanometers and can be determined by the CCD image sensor manufacturing process and the desired VCVFD capacitance. The polysilicon gate has an electrical connection 216 through which a voltage V G is applied to the VCVFD gate.

[0078] As in the FET manufacturing process, the impurity concentration of the source and drain regions is typically from 10 16 to 10 20within the range of a few atoms and several orders of magnitude higher than in the silicon layer. The FET structure can be either an enhancement mode (surface channel) type or a depletion mode (buried channel) type. In a preferred embodiment, the FET structure is of the depletion mode (buried channel) type, which is a better choice for charge transfer and noise performance of a CCD image sensor, as mentioned above. Thus, in most of the embodiments described herein, the VCVFD structure is configured to have only a source (or a connected source and drain) and a gate with a buried channel thereunder. Additionally, an n-type source region (or a connected n-type source and drain region) in the p-type silicon layer is used for most of the VCVFD embodiments described herein, but the concepts described herein are equally applicable to a p-type source (or a connected p-type source and drain region) in an n-type silicon layer.

[0079] In Figure 2A and 2B the embodiments shown, the FET source and drain regions are electrically connected and can be considered two VCVFD structures connected in parallel to a sense amplifier through an electrical connection 210. The source region of the VCVFD structure is also connected to the channel of the circuit and the output circuit of the image sensor (not shown in Figure 2A and 2B ). As further described herein, the source 204 can be connected to the channel of the circuit such that the VCVFD structure receives charge 222 from the sensor circuit.

[0080] In one embodiment, the source region of the VCVFD structure is connected to a charge reset structure in the image sensor. For example, Figure 2B the adjacent reset structure 224 shown in Figure 2B can be connected to both the source region and the drain region such that charge can be discharged from both regions during a reset operation that occurs between successive charge signal readout operations.

[0081] Figure 2A and 2B the VCVFD structures shown can be further configured as described herein. For example, a p+ ohmic contact 218 can be formed by locally implanting a higher density of p-type impurities at the surface of the silicon layer. The p+ ohmic contact can have an electrical connection 220 to connect the silicon layer to a ground potential.

[0082] The output circuit of the image sensor is configured to produce an output in response to the voltage output by the VCVFD structure. The output circuit may be included in (or be one of) a plurality of circuits configured to amplify and / or process signals generated by the sensor and to control the sensor, and these circuits may be fabricated inside or adjacent to the photosensitive region. In Figure 4 , the source 451 has an electrical connection 454 to connect it to a CCD readout circuit typically formed by MOSFET transistors (such as the MOSFET transistors described above). In Figure 4 The VCVFD output voltage on the connection 454 in may be connected to a buffer or amplifier before being connected to the CCD output or an analog-to-digital converter (ADC).

[0083] This circuit is illustrated in Figure 4 by MOSFET transistors formed by source and drain implants 406, channel implant 407, gate dielectric 409, and gate electrode 410. Electrical connections (such as 415, 416, and 417) can be made to the gate, source, and drain of the MOSFET transistors, respectively. The gate dielectric 409 may be substantially similar to the dielectric layer 408 and may be formed simultaneously, or depending on, for example, the desired transistor characteristics, the gate dielectric 409 may be formed of a different material and / or a different thickness than the dielectric layer 408. Although only one such transistor is illustrated in Figure 4 for clarity purposes only, typically such circuits include many transistors. In a preferred embodiment, MOSFET transistors with n-type channels are fabricated in a p+ doped well 405 to electrically isolate them from dark current and photocurrent in the epitaxial material 401.

[0084] The structure 408a may also be substantially similar to the dielectric layer 408 and may be formed simultaneously as, for example, a single dielectric layer, which is then patterned to create a gap between the dielectric layer 408 and the structure 408a. Alternatively, depending on, for example, the desired characteristics of the structure 408a, the structure 408a may be formed of a different material and / or a different thickness than the dielectric layer 408 and / or the gate dielectric 409. The structure 408a may be an optional isolation structure formed between the VCVFD structure 450 and the output circuit and may be formed above the p-well 405. In this way, the isolation structure can separate the readout circuit from the sensor active region and the VCVFD structure.

[0085] In some embodiments, the circuit is configured as a two-dimensional (2D) pixel array. For example, in a CCD image sensor suitable for a semiconductor inspection system, multiple pixel columns (such as in Figure 4The pixel columns described in [reference] are arranged to form a 2D photosensitive pixel array. A clock signal is connected across the entire array and is used to simultaneously transfer charge from one pixel within all columns or a group of columns to the next pixel. However, the sensor pixels may be arranged in a configuration different from the one shown and may include more or fewer pixels than the pixels shown.

[0086] In another embodiment, the circuit is configured to include a plurality of pixel columns including at least first and second pixel columns, the at least first and second pixel columns each including one or more pixels, the sensing node is one of a plurality of sensing nodes in an image sensor, the plurality of sensing nodes including at least first and second sensing nodes, and the first and second sensing nodes are each electrically connected to all of one or more pixels in the first and second pixel columns, respectively. More specifically, each sensing node may be electrically connected only to the first (or last) pixel in each column. If a column includes more than one pixel, then the first pixel is connected to the second pixel, the second pixel is connected to the third pixel, and so on. Thus, a sensing node can be directly connected to one pixel in a column and connected to other pixels in the same column via that one pixel. In this way, the sensor can include a VCVFD structure for each pixel column. More specifically, a first VCVFD structure can be electrically connected to all pixels in only the first pixel column, a second VCVFD structure can be electrically connected to all pixels in only the second pixel column different from the first pixel column, and so on. Each VCVFD structure can be configured as described herein. In this way, Figure 4 the structure shown in [reference] can form a pixel column electrically connected to one VCVFD structure, and the image sensor can include multiple sets of these structures arranged side by side on the sensor.

[0087] In Figure 6A a more detailed view of this image sensor is shown. Image sensor 600 includes four pixel columns 601-1, 601-2, 601-3, and 601-4. Although four pixel columns are shown in this figure, the sensor may include one or more of these pixel columns. Additionally, although Figure 6A each column shown in [reference] includes five pixels, each column may include one or more pixels. As in Figure 6AAs shown, the VCVFD 602-1 is electrically connected to the first or last pixel in column 601-1 and thus to all the pixels in that column and not to the pixels in any other column. In a similar manner, the VCVFD 602-2 is only electrically connected to all the pixels in column 601-2, the VCVFD 602-3 is only electrically connected to all the pixels in column 601-3, and the VCVFD 602-4 is only electrically connected to all the pixels in column 601-4. Each VCVFD structure can have the same configuration as every other VCVFD structure. Thus, the image sensor can include many more pixel circuits than VCVFD structures. For example, in each column of transistors or circuits, there can be one or more pixel circuits (even dozens or hundreds of pixel circuits) and only one VCVFD structure. This configuration provides the advantages further described herein.

[0088] In another embodiment, the circuit is configured to include a plurality of pixel columns including at least first and second pixel columns, at least first and second pixel column rows include one or more pixels, and the sense node is electrically connected to one or more pixels in the first and second pixel columns. In other words, the sensor can include a VCVFD structure that is common to a group of two or more pixel columns. In Figure 6B shows one such embodiment of an image sensor. In this embodiment, the image sensor 610 includes four columns each including five pixels. The number of columns and the number of pixels in each column can vary as described above. In this embodiment, the VCVFD 613-1 is electrically connected to all the pixels in only columns 611-1 and 611-2, and the VCVFD 613-2 is electrically connected to all the pixels in only columns 611-3 and 611-4. The VCVFDs 613-1 and 613-2 can have the same configuration as each other and can be configured as described herein. The image sensor can also include elements 612-1 and 612-2, which can include buffer gates, readout registers, etc. (such as Figure 4 the buffer gates 430 and 435 and the readout register gate 440 shown in). Thus, the VCVFD can be electrically connected to these elements and thereby to each of the pixels to which it is connected. In this way, a VCVFD structure can be provided to a group of columns that are read out simultaneously.

[0089] In addition, a single VCVFD structure can be electrically connected to the pixels in more than two columns. For example, a first VCVFD structure can be electrically connected to all the pixels in the first, second, and third columns, and a second VCVFD structure can be electrically connected to all the pixels in the fourth, fifth, and sixth columns. In this way, Figure 4 the structure shown in can form one of the multiple pixel columns electrically connected to one VCVFD structure, and the image sensor can include multiple combinations of such structures arranged side by side on the sensor. In Figure 6COne such embodiment of an image sensor is shown herein. In this embodiment, the image sensor 620 includes four columns each including five pixels. The number of columns and the number of pixels in each column may vary as described above. In this embodiment, the VCVFD 623 is electrically connected to all the pixels in only columns 621-1, 621-2, 621-3, and 621-4, which may be all the pixel columns in the image sensor or only a portion of the pixel columns in the sensor (in which case, the image sensor may include Figure 6C more than one of the configurations shown in Figure 4 ). The VCVFD 623 may be further configured as described herein. The image sensor may also include elements 622-1, 622-2, 622-3, and 622-4, which may include buffer gates, readout registers, etc. (such as

[0090] the buffer gates 430 and 435 and the readout register gate 440 shown in Figure 6A ). Thus, the VCVFD may be electrically connected to these elements and thereby to each of the pixels connected thereto. Figure 6B and 6C The image sensors shown in may include many more pixel circuits than VCVFD structures. For example, in every two or more transistor or circuit columns, there may be one or more pixel circuits (even dozens or hundreds of pixel circuits) and only one VCVFD structure. These configurations also provide the advantages further described herein.

[0091] In some embodiments, only one or two VCVFD structures connected to an output circuit may be used. For example, in a preferred embodiment applicable to substantially high-speed inspection systems (such as high-speed inspection systems used in the semiconductor industry), multiple VCVFD structures and their corresponding outputs (such as dozens of outputs, hundreds of outputs, one output per column, or one output per two columns) may be used to output multiple pixels simultaneously in order to achieve a substantially high data output rate. Such sensors may include a 2D array of about 1000 or thousands of columns, with lengths between hundreds and thousands of pixels. Such sensors may be configured as further described herein.

[0092] In some embodiments, a circuit is configured to include pixels of at least a first and a second pixel, a sense node is electrically connected to the first and second pixels, and an image sensor or a computer subsystem is configured to calibrate the sense node, thereby calibrating the first and second pixels. In this way, the embodiments described herein can be configured such that calibration of the pixels can be accomplished by calibrating each sense node rather than the pixels. In other words, by calibrating the sense node, each pixel electrically connected to the sense node can be effectively calibrated. For example, if a sense node is coupled to all pixels in a column, then the calibration response or sensitivity in that one column should all be the same. Thus, since the image sensors described herein will most likely include substantially fewer sense nodes than pixels (e.g., thousands of sense nodes versus millions of pixels), the embodiments described herein can calibrate each pixel faster and more easily by calibrating the sense node rather than the pixel itself. In addition to calibrating the sense node rather than the pixel itself, the calibration can be performed in any suitable manner known in the art by the image sensor or the computer subsystem. The computer subsystem can be further configured as described herein.

[0093] Compared to some of the embodiments described above in which each column includes multiple pixels, the image sensor embodiments described herein can include a single pixel in each column. Thus, this image sensor can include a single pixel line, where each column pixel circuit includes only a single pixel circuit. Each single pixel circuit can be formed by only one CCD gate, although it can have multiple electrodes connected to it to control the voltage applied across the gate and the potential in the CCD channel under the gate. Examples of this sensor pixel configuration are described in the following patents: U.S. Patent No. 9,620,547, issued April 11, 2017, to Chuang et al.; and U.S. Patent No. 10,194,108, issued January 29, 2019, to Chuang et al., which are hereby incorporated by reference as if fully set forth herein. The image sensors described herein can be further configured as described in these patents.

[0094] In another embodiment, the image sensor is positioned in an inspection system such that the light incident on the photosensitive region is light from a sample being inspected by the inspection system, and the inspection system is configured to detect a defect on the sample based on an output generated by an output circuit of the image sensor. This embodiment can be configured as further described herein and as shown in Figure 5 shown.

[0095] Another embodiment relates to a system configured to determine information about a sample. Figure 5 FIG. 500 shows an exemplary inspection system 500 configured to inspect or make measurements on a sample 508 in accordance with one or more embodiments described herein. The inspection system 500 can be configured as an inspection system or a metrology system configured to inspect or make measurements on a sample 508.

[0096] The sample 508 can be a wafer. The wafer can include any wafer known in the semiconductor field. The embodiments are also not limited to the samples on which they can be used. For example, the embodiments described herein can be used for samples such as photomasks, reticles, flats, printed circuit boards (PCBs), and other semiconductor samples.

[0097] The sample 508 can be disposed on a stage assembly 512 to facilitate movement of the sample 508. The stage assembly 512 can include any stage assembly known in the art, including but not limited to X-Y stages, R-θ stages, and the like. In another embodiment, the stage assembly 512 is capable of adjusting the height of the sample 508 during inspection to maintain focus on the sample 508. In yet another embodiment, a lens (such as the objective lens 550) can be moved up and down during inspection to maintain focus on the sample 508.

[0098] The system includes an illumination subsystem configured to direct light generated by a light source to the sample. The illumination subsystem can include an illumination source 502 that generates output light L having a wavelength in a range such as between about 120 nm and about 2000 nm. OUT The illumination source 502 can be a light source such as a laser or a broadband light source. Additionally, the illumination source 502 can include any other suitable light source known in the art.

[0099] The illumination subsystem can include one or more optical components, such as beam splitters, mirrors, lenses, apertures, and wave plates, which are configured to condition the light L OUT and direct the light L OUT to the sample 508. The optical components can be configured to illuminate an area, line, or spot on the sample 508. In one embodiment of the illumination subsystem, the beam splitter or mirror 534, mirrors 537 and 538, and lens 552 are configured to illuminate the sample 508 from below so as to effect inspection or measurement of the sample 508 by transmitting the light L INT through the sample. The illumination subsystem can also or alternatively include the beam splitter or mirrors 534 and 535, mirror 536, and lens 551, which are configured to illuminate the sample 508 with the light at an oblique angle of incidence L Obl (e.g., an angle of incidence greater than 60° relative to the normal of the sample surface). In this embodiment, the specularly reflected light L Spec can be blocked or discarded rather than collected.

[0100] The illumination subsystem can also or alternatively include a combination that is configured to direct the illumination light L INOptical device 503 that directs to the top surface of sample 508. For example, the illumination subsystem may include lens 533, illumination pupil aperture 531, illumination tube lens 532, beam splitter 540, and objective lens 550 of optical device 503 that together direct light from a light source to the sample at an incident angle, which may be, for example, a normal or substantially normal incident angle. Illumination tube lens 532 may be configured to image illumination pupil aperture 531 into the pupil within objective lens 550. For example, illumination tube lens 532 may be configured such that illumination pupil aperture 531 and the pupil within objective lens 550 are conjugate to each other. Illumination pupil aperture 531 may be configured by switching different apertures into the position of illumination pupil aperture 531 and / or by adjusting the diameter or shape of the opening of illumination pupil aperture 531. In this regard, sample 508 may be illuminated by different angular ranges depending on the characterization (e.g., measurement or inspection) performed under the control of computing system 514. Illumination pupil aperture 531 may also include a polarization element (not shown) to control the polarization state of illumination light L IN of the illumination light L.

[0101] The system also includes sensor 506 positioned in the path of light from the sample. The sensor is configured as further described herein. Light from the sample is incident on the photosensitive area of the image sensor. For example, when illuminating sample 508 in one or more of the above-described modes, optical device 503 is also configured to collect light L R / S / T that is reflected, scattered, diffracted, transmitted, and / or emitted from sample 508, and direct and focus light L R / S / T to sensor 506 of detector assembly 504. Sensor 506 and detector assembly 504 may include any sensor embodiments further described herein. Detector assembly 504 is communicatively coupled to computing system 514.

[0102] Computing system 514 is configured to store and / or analyze data from detector assembly 504 under the control of program instructions 518 stored on carrier medium 516. Computing system 514 may be configured to control other components of inspection system 500, such as stage 512, illumination source 502, and optical device 503.

[0103] The optical device 503 may include a condenser tube lens 522. The condenser tube lens 522 may be configured to image a pupil within the objective lens 550 onto a condenser pupil aperture 521. For example, the condenser tube lens 522 may be configured such that the condenser pupil aperture 521 and the pupil within the objective lens 550 are conjugate to each other. The condenser pupil aperture 521 may be configured by switching different apertures into the position of the condenser pupil aperture 521 and / or by adjusting the diameter or shape of the opening of the condenser pupil aperture 521. In this regard, illumination of different angular ranges reflected or scattered from the sample 508 may be directed to the detector assembly 504 under the control of the computing system 514. The condenser pupil aperture 521 may also include a polarization element (not shown) such that a specific polarization of the light L R / S / T transmitted to the sensor 506 can be selected.

[0104] The illumination pupil aperture 531 and / or the condenser pupil aperture 521 may include programmable apertures. Programmable apertures are generally discussed in the following patents: U.S. Patent No. 9,255,887, issued to Brunner on February 9, 2016, and U.S. Patent No. 9,645,287, issued to Brunner on May 9, 2017, the entire texts of both U.S. patents are incorporated herein by reference. Methods for selecting aperture configurations for inspection are generally described in the following patents: U.S. Patent No. 9,709,510, issued to Kolchin et al. on July 18, 2017, and U.S. Patent No. 9,726,617, issued to Kolchin et al. on August 8, 2017, the entire texts of both U.S. patents are incorporated herein by reference. The embodiments described herein may be further configured as described in these patents.

[0105] Figure 5 The various optical elements and operating modes depicted in Figure 5 are only used to illustrate how the sensor 506 may be used in the inspection system 500 and are not intended to limit the scope of the present disclosure. The actual inspection system 500 may implement

[0106] a subset or superset of the modes and optical devices depicted in Figure 5The computing system 514 shown in [description]. The computing system 514 can be coupled to the sensor 506 in any suitable manner (e.g., via one or more transmission media, which may include "wired" and / or "wireless" transmission media), such that the computing system can receive the output, images, etc. generated by the sensor 506. The computing system 514 can be configured to perform several functions described herein using the output of the sensor and any other functions further described herein. This computing system can be further configured as described herein.

[0107] The computing system can include one or more computer subsystems (not shown) configured to perform one or more functions (e.g., determining information about a sample based on the output of an image sensor). The computer subsystems of the computing system (and other computer subsystems described herein) may also be referred to herein as computer systems. Each of the computing systems and computer subsystems or systems described herein can take various forms, including personal computer systems, image computers, main computer systems, workstations, network appliances, Internet appliances, or other devices. Generally, the term "computer system" can be broadly defined to encompass any device having one or more processors that execute instructions from a memory medium. The computing systems and computer subsystems or systems can also include any suitable processors known in the art (e.g., parallel processors). Additionally, the computing systems and the computer subsystems or the systems can include computer platforms with high-speed processing and software (as standalone tools or networked tools).

[0108] If the system includes more than one computer subsystem, the different computer subsystems can be coupled to each other such that images, data, information, instructions, etc. can be sent between the computer subsystems, as further described herein. For example, two or more computer subsystems can be coupled to each other by any suitable transmission medium (not shown), which may include any suitable wired and / or wireless transmission media known in the art. Two or more such computer subsystems can also be effectively coupled by sharing a computer-readable storage medium (not shown).

[0109] Provided herein Figure 5To generally illustrate some configurations of a system that may include sensor embodiments described herein. Obviously, the system configurations described herein can be changed to optimize the performance of the system as is typically done when designing a commercial system. Additionally, the systems described herein can be implemented using existing systems (e.g., by adding the image sensor embodiments and other functionality described herein to an existing system), such as systems commercially available from KLA-Tencor Corporation of Milpitas, California. For some such systems, the embodiments described herein can be provided as optional functionality of an existing system (e.g., in addition to other functionality of the system). Alternatively, the systems described herein can be designed "from scratch" to provide a brand-new system.

[0110] The computer subsystem can be configured to determine information in several different ways depending on, for example, the sample, the optical system configuration, and the information determined for the sample. For example, in one embodiment, the system is configured as an inspection system, and the information about the sample includes information based on defects detected on the sample in the output. In one such instance, the computing system 514 can be configured to detect defects on the sample 508 by applying a defect detection method to the output generated by the sensor 506. The computing system 514 can be coupled to the sensor 506 as further described herein such that it can receive the output generated by the sensor. Detecting defects on the sample can be performed using any suitable defect detection method and / or algorithm in any suitable manner known in the art (e.g., applying a defect detection threshold to the output and determining that any output having a value higher than the threshold corresponds to a defect (or potential defect)).

[0111] In another embodiment, the system is configured as a metrology system. In additional embodiments, the system is configured as a defect re-inspection system. For example, Figure 5 The embodiments of the system shown herein can be modified in one or more parameters to provide different imaging capabilities depending on the application for which it will be used. In one such instance, the system can be configured to have a higher resolution in cases where it will be used for metrology rather than for inspection. In other words, Figure 5 The embodiments of the system shown herein describe some general and various configurations of the system, which can be customized in several ways that will be obvious to those skilled in the art to produce systems with different imaging capabilities that are more or less suitable for different applications.

[0112] In this manner, the system can be configured in the case of a defect re-inspection system to produce an output suitable for re-inspecting defects on a sample, and in the case of a metrology system to measure one or more characteristics of the sample. In a defect re-inspection system embodiment, the computing system 514 can be configured to re-inspect defects on the sample 508 by applying a defect re-inspection method to the output generated by the sensor 506 and possibly using the output generated by the sensor to determine additional information about the re-inspected defects. In a metrology system embodiment, the computing system 514 can be configured to use the output generated by the sensor to determine one or more characteristics of the sample 508.

[0113] Defect re-inspection typically involves re-inspecting defects that are themselves detected by an inspection process and generating additional information about the defects at a higher resolution, for example, in a high magnification mode using the systems described herein. Thus, defect re-inspection is performed at discrete locations on the sample where defects have been detected by inspection. The higher resolution data of the defects generated by defect re-inspection is generally more suitable for determining the attributes of the defects, such as profile, roughness, more accurate size information, etc. The computing system 514 can be configured to determine this information about the defects on the sample in any suitable manner known in the art.

[0114] Metrology processes are used to monitor and control the process during various steps in a semiconductor manufacturing process. A metrology process differs from an inspection process in that, unlike an inspection process where defects are detected on a sample, a metrology process is used to measure one or more characteristics of the sample that cannot be determined using currently available inspection tools. For example, a metrology process is used to measure one or more characteristics of the sample (such as the dimensions of features formed on the sample during the process (e.g., line width, thickness, etc.)) such that the performance of the process can be determined from the one or more characteristics. Additionally, if one or more characteristics of the sample are unacceptable (e.g., outside a predetermined range of the characteristics), then the measurement of the one or more characteristics of the sample can be used to change one or more parameters of the process such that additional samples manufactured by the process have acceptable characteristics.

[0115] The metrology process also differs from the defect reinspection process in that, unlike the defect reinspection process in which defects detected through inspection are revisited, the metrology process can be performed at locations where no defects are detected. In other words, unlike defect reinspection, the location where the metrology process is performed on a sample can be independent of the results of the inspection process performed on the sample. Specifically, the location where the metrology process is performed can be selected independently of the inspection results. Additionally, since the location where metrology is performed on a sample can be selected independently of the inspection results, unlike defect reinspection where the location for defect reinspection to be performed on a sample cannot be determined until the inspection results of the sample are generated and available, the location for performing the metrology process can be determined before the inspection process has been performed on the sample. The computing system 514 can be configured to determine any suitable characteristic of the sample in any suitable manner known in the art.

[0116] In any system embodiment described herein, Figure 5 the computing system 514 shown therein can be configured to generate results based on outputs that may be generated by an image sensor using any other output generated by the computing system, the results including at least information determined for the sample. The results can be in any suitable format (e.g., a KLARF file, an exclusive file format used by tools commercially available from KLA; a result file generated by Klarity, which is a tool commercially available from KLA; batch results, etc.). Additionally, all embodiments described herein can be configured to store the results of one or more steps of the embodiment in a computer-readable storage medium. The results can include any results described herein and can be stored in any manner known in the art. The storage medium can include any storage medium described herein or any other suitable storage medium known in the art. After the results are stored, the results can be accessed in the storage medium and used by any method or system embodiment described herein, formatted for display to a user, used by another software module, method, or system, etc. to perform one or more functions on the sample or another sample.

[0117] Such functions include (but are not limited to) change processes, such as manufacturing processes or steps that have been or will be performed on the sample in a feedback, feedforward, in-situ manner, etc. For example, the computer subsystem can be configured to determine one or more changes to a process that has been or will be performed on the sample based on detected defects and / or other determined information. The change to the process can include any suitable change to one or more parameters of the process. For example, if the determined information is a defect detected on the sample, the computer subsystem preferably determines the change such that defects on other samples on which the revised process is to be performed can be reduced or prevented, the defect on the sample can be corrected or eliminated in another process performed on the sample, the defect can be compensated for in another process performed on the sample, etc. The computer subsystem can determine such changes in any suitable manner known in the art.

[0118] Next, the changes can be sent to a semiconductor manufacturing system (not shown) or a storage medium accessible to both the computer subsystem and the semiconductor manufacturing system ( Figure 5 not shown). The semiconductor manufacturing system may or may not be part of the system embodiments described herein. For example, the systems described herein can be coupled to a semiconductor manufacturing system, e.g., via one or more common elements such as a housing, a power supply, a sample handling device or mechanism, etc. The semiconductor manufacturing system can include any semiconductor manufacturing system known in the art, such as a lithography tool, an etching tool, a chemical-mechanical polishing (CMP) tool, a deposition tool, and the like.

[0119] Each of the embodiments of the systems described above can be further configured according to any other embodiment described herein.

[0120] Another embodiment relates to a computer-implemented method for determining information about a sample. The method includes directing light generated by a light source onto the sample. The method also includes using an image sensor to detect light from the sample. The image sensor is configured as further described herein. For example, light from the sample is incident on a photosensitive region of a silicon layer of the image sensor. The method further includes determining information about the sample based on an output generated by an output circuit of the image sensor.

[0121] Each of the steps of the method can be performed as further described herein. The method can also include any other steps that can be performed by the systems described herein. The steps of the method can be performed by the systems described herein that can be configured according to any of the embodiments described herein.

[0122] An additional embodiment relates to a non-transitory computer-readable medium storing program instructions that can be executed on a computer system to perform a computer-implemented method for determining information about a sample. One such embodiment is shown in Figure 7 . Specifically, as shown in ​ , the non-transitory computer-readable medium 700 includes program instructions 702 that can be executed on a computer system 704. The computer-implemented method can include any of the steps of any of the methods described herein.

[0123] The program instructions 702 for implementing a method such as the methods described herein can be stored on the computer-readable medium 700. The computer-readable medium can be a storage medium such as a magnetic disk or an optical disk, a magnetic tape, or any other suitable non-transitory computer-readable medium known in the art.

[0124] The program instructions can be implemented in any of a variety of ways, including process-based techniques, component-based techniques, and / or object-oriented techniques, etc. For example, the program instructions can be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (“MFC”), SSE (Streaming SIMD Extensions), or other techniques or methodologies as needed.

[0125] The computer system 704 can be configured according to any of the embodiments described herein.

[0126] The VCVFD structure described above is particularly applicable in an optical-based system (such as the optical-based system described above), but can also be an exemplary sensing node for a sensor configured for other applications, such as an electronic sensor or an X-ray sensor. For example, the VCVFD structure described above can be incorporated into an electronic sensor pixel and an electronic sensor, as described below.

[0127] The resistive gate in the individual electronic sensor pixels described below is an important difference from the pixels of a conventional CMOS image sensor. The electronic sensor pixels are sensitive to light (unless coated with an opaque coating), but their relatively large size means that they will not be useful in an optical-based inspection system. The electric field generated by the resistive gate (when an appropriate operating voltage is applied) enables the pixel to be relatively fast (~100MHz readout rate) while being relatively large. Otherwise, the time for electrons to drift from one corner of the pixel to the sensing node would be too long for high-speed operation.

[0128] For electronic sensor applications, such as integrating into a sensor in an electron beam system similar to the electron beam system depicted in ​ (described below), the sensor can be configured to detect electrons or X-rays. Compared to an inspection system using light, there are typically fewer incident signal electrons or X-ray photons per unit time, and each incident electron or X-ray photon generates many (usually dozens to thousands) electron-hole pairs when absorbed in silicon.

[0129] In one mode, individual arriving high-energy electrons (say, with an energy of about 1 keV or higher) or X-ray photons (with an energy of several hundred eV to about 20 keV to 30 keV) are counted, and their energy is determined (approximately) from the number of the generated electron-hole pairs (i.e., the collected signal). In this mode, the floating diffusion capacitance is preferably relatively small, ideally only a few femtofarads (fF), so that a small signal can be measured with as little noise as possible.

[0130] In another mode, signals from secondary electrons (energies typically 20 eV to 50 eV) are collected. Secondary electrons are more numerous than higher energy electrons and X-ray photons, but produce only about 10 or fewer electron-hole pairs per incident electron. Depending on the operating mode, a higher floating diffusion capacitance may be preferred if relatively large signals are to be detected. The VCVFD allows the floating diffusion capacitance to be changed according to the system operating mode.

[0131] In one embodiment of an electronic sensor pixel, the pixel includes a silicon layer that includes: an n-type buried channel layer that forms a first surface of the silicon layer; and a p-type electron-sensitive layer that is disposed between the buried channel layer and an opposite second surface of the silicon layer. Each of these elements may be configured as described below.

[0132] The silicon layer also includes a floating diffusion disposed in the buried channel layer adjacent a central region of the pixel. The floating diffusion includes a sensing node formed by a VCVFD structure. The VCVFD structure includes a VCVFD source region and a VCVFD channel region. The VCVFD source region is connected to the channel of the pixel and the output circuit of the pixel. The VCVFD structure also includes a VCVFD gate electrode that is adjacent the VCVFD source region and is configured to control the variable capacitance of the VCVFD structure by a voltage applied to the VCVFD gate electrode via an electrical connection to the VCVFD gate electrode. The VCVFD structure is configured to convert charge responsive to electrons moving in the n-type buried channel layer toward the floating diffusion into a voltage that is proportional to the amount of charge and depends on the variable capacitance. This VCVFD structure may be configured as further described herein and is shown in, for example ​ , 1B , 2A and 2B. The VCVFD structure may be connected to a pixel as shown in ​ . Additionally, the VCVFD structure may be formed in a floating diffusion FD as shown in ​ , 10B and 11A.

[0133] The electronic sensor pixel further includes a resistive gate including at least one gate structure disposed above a first surface and configured such that an outer peripheral edge of the gate structure is substantially aligned with an outer peripheral edge of the buried channel layer. The gate structure defines a central opening such that an inner peripheral edge of the gate structure substantially surrounds and is spaced from a central region. The buried channel layer and the p-type electron sensitive layer are configured such that the p-type electron sensitive layer generates a plurality of electrons in response to each incident electron and such that the generated plurality of electrons are driven into the buried channel layer. The resistive gate is configured such that when a reduced potential difference is applied between an inner peripheral edge and an outer peripheral edge of the gate structure, the resistive gate generates a first electric field that causes electrons in the n-type buried channel layer to move toward a floating diffusion. The electronic sensor pixel may be further configured as described herein. These elements may also be configured as described herein.

[0134] The following description, from co-owned U.S. Patent Application Publication No. 2016 / 0064184, published Mar. 3, 2016, by Brown et al., is incorporated herein by reference in its entirety as if fully set forth herein. The embodiments of electronic sensor pixels, electronic sensors, and electron beam systems described in this disclosure are exemplary types of pixels, sensors, and systems into which the VCVFD structures described herein may be incorporated. However, it will be apparent that the VCVFD structures described herein may be used in electronic sensor pixels, electronic sensors, and electron beam systems having other configurations known in the art. The embodiments described herein may be further configured as described in the above-cited patent disclosure.

[0135] ​ An exemplary scanning electron microscope (SEM) 800 is illustrated, which is also referred to as an inspection or re-inspection system configured to inspect or re-inspect a sample 831, such as a semiconductor wafer, a reticle, or a photomask. The SEM 800 generally includes an electron gun (source) 840, electron optics including an upper column 841 and a lower column 842, a stage 830 for supporting and positioning the sample 831, and a system computer 860.

[0136] In one embodiment, the electron gun 840 includes a cathode 801 (such as a thermal field emission or Schottky cathode, a single crystal tungsten cathode, or a LaB6 cathode) and extraction and focusing electrodes 802. The electron gun 840 may further include a magnetic lens (not shown). The electron gun 840 generates a primary electron beam 850 having a desired beam energy and beam current.

[0137] The upper column 841 of the electron optical device includes one or more condenser lenses 807 that reduce the primary beam to produce a small spot on the sample 831. Generally, a spot size of about 1 to several nm is preferred for producing a high-resolution image for reinspecting the sample. The inspection of the sample can use a larger spot size to scan the sample 831 more quickly. When the spot size is on the order of 100 nm or greater, a single condenser lens 807 may be sufficient, but for a spot size of several tens of nm or less, two or more condenser lenses are typically required. The condenser lens 807 can include a magnetic lens, an electrostatic lens, or both. The upper column 841 may also include one or more deflectors 805 that scan the primary electron beam across the region of the sample 831. The deflector 805 can be placed on either side of the condenser lens 807 as shown, or within the condenser lens 807 (not shown) or behind the condenser lens 807. The deflector 805 can include an electrostatic deflector or a combination of magnetic and electrostatic deflectors. In one embodiment, there may be no deflector in the upper column 841. Alternatively, all deflectors can be included in the lower column 842.

[0138] The lower column 842 includes a final (immersion) lens 810 for focusing the primary electron beam onto a small spot on the sample 831. The final lens 810 can include a magnetic lens (as shown) or a combination of a magnetic lens and an electrostatic lens (not shown). To achieve a small spot size at the sample 831, the final lens 810 is placed close to the sample 831 such that the sample is immersed in the magnetic field of the lens. This can reduce the aberration in the electron spot on the sample 831. The lower column 842 also includes a deflector 809 that works in combination with the deflector 805 (if present) to scan the primary electron beam across the region of the sample 831.

[0139] The sample 831 is placed on a stage 830 to facilitate movement of different regions of the sample 831 under the electron column. The stage 830 can include an X-Y stage or an R-θ stage, and in one embodiment, is configured to support and position multiple sample types (e.g., unpatterned semiconductor wafers, patterned semiconductor wafers, photomasks or reticles) typically reinspected by the integrated circuit industry. In a preferred embodiment, the stage 830 can adjust the height of the sample 831 during inspection to maintain focus. In other embodiments, the final lens 810 can be adjusted to maintain focus. In some embodiments, a focus or height sensor (not shown) can be mounted on or near the final lens 810 to provide a signal to adjust the height of the sample 831 or adjust the focus of the final lens 810. In one embodiment, the focus sensor or height sensor can be an optical sensor.

[0140] When an electron optical device scans a primary electron beam 850 across a region of a sample 831, secondary electrons and backscattered electrons are emitted from the region. The secondary electrons can be collected and accelerated by an electrode 820 and directed to a secondary electron detector 821. Electron optical devices for collecting, accelerating, and / or focusing secondary electrons are described in U.S. Patent No. 7,141,791 to Masnaghetti et al. entitled "Apparatus and method for e-beam dark-field imaging". This patent is incorporated herein by reference. As described in the '791 patent, the electron optical device for the secondary electron detector can include de-scanning optics for at least partially eliminating the effect of the deflector 809 on the trajectory of the secondary electrons. In some embodiments of the present invention, de-scanning electron optics are not required and can be omitted because de-scanning can be approximately achieved by an ASIC included in the secondary electron detector, as described herein. The secondary electron detector 821 is preferably a solid-state electron detector (e.g., one of the solid-state electron detectors described herein) and is configured to generate an image data signal ID2 based on the detected secondary electrons, where the image data signal ID2 is transmitted to a computer 860 and used to generate an image of the associated scanned sample region, thereby facilitating visual inspection of the defect D. Other electron optical devices and detector configurations and methods for detecting and analyzing secondary electrons that can be used in conjunction with the systems and methods described herein are described in U.S. Patent No. 7,838,833 to Lent et al. entitled "Apparatus and method for e-beam dark imaging with perspective control"; and U.S. Patent No. 7,714,287 to James et al. entitled "Apparatus and method for obtaining topographical dark-field images in a scanning electron microscope". These two U.S. patents are incorporated herein by reference.

[0141] Backscattered electrons can be detected by a backscattered electron detector (such as the backscattered electron detectors shown at 822a and 822b), which is implemented by one of the solid-state electron detectors described herein and is configured to generate an image data signal ID1 based on the detected backscattered electrons, where the data signal ID1 is transmitted to a computer 860 and is also used to generate an image of the associated scanned sample area. Preferably, the backscattered electron detector is placed as close as possible to the sample 831, such as at position 822a (i.e., between the final lens 810 and the sample 831). However, the gap between the sample 831 and the final lens 810 can be small (e.g., about 2 mm or less), and for example, for a focus or height sensor, a gap may be required, and thus, placing the backscattered electron detector at position 822a may not be practical. Alternatively, the backscattered electron detector can be placed at a position such as 822b on the opposite side of the pole piece of the final lens 810 relative to the sample 831. It should be noted that the backscattered electron detector cannot block the primary electron beam 850. The backscattered electron detector can have a hole in the middle or can include multiple detectors (e.g., two, three, or four individual detectors), which are arranged around the path of the primary electron beam 850 so as not to block the path while effectively capturing the backscattered electrons.

[0142] The landing energy of the primary electron beam 850 on the sample 831 depends on the potential difference between the cathode 801 and the sample 831. In one embodiment, the stage 830 and the sample 831 may be maintained near ground potential, and the landing energy is adjusted by changing the potential of the cathode 801. In another embodiment, the landing energy on the sample 831 may be adjusted by changing the potential of the stage 830 and the sample 831 relative to ground. In any embodiment, the final lens 810 and the backscattered electron detectors 822a and / or 822b must all be at a potential that is close to each other and close to the potential of the sample 831 and the stage 830 (e.g., less than about 1000 V relative to the sample 831 and the stage 830) in order to avoid arcing to the sample 831. Due to this small potential difference, backscattered electrons from the sample 831 will be only slightly accelerated or not accelerated at all from the sample to the backscattered electron detectors 822a and / or 822b. Since the landing energy on the sample 831 can be quite low for some semiconductor samples (e.g., between about 500 eV and 2 keV) in order to avoid damaging the sample, the energy of the backscattered electrons when they land on the backscattered electron detectors 822a and / or 822b will be quite low. Therefore, for the sensitivity of the SEM, it is important that the backscattered electron detectors 822a and 822b generate many electron-hole pairs from a single low-energy backscattered electron (e.g., an electron having an energy of about 2 keV or less). Conventional silicon detectors inevitably have a thin oxide (e.g., native oxide) coating on the surface of the silicon that blocks most electrons having an energy below about 2 keV from reaching the silicon, or alternatively have a thin metal (e.g., Al) coating on the surface that scatters and absorbs a significant portion of the incident low-energy electrons. In a preferred embodiment, the solid-state electron detector described herein has a pinhole-free pure boron coating on its surface. The pinhole-free pure boron coating prevents oxidation of the silicon and allows for effective detection of low-energy electrons (including electrons having an energy less than 1 keV). A method for manufacturing a silicon detector having a pinhole-free pure boron coating and the design of such a detector are described in U.S. Patent Application Publication 2013 / 0264481, titled "Back-illuminated Sensor With Boron Layer," filed on March 10, 2013, by Chern et al. This patent application is incorporated herein by reference.

[0143] Positioned at ​ The bubble in the lower left portion of INCIDENTA simplified solid-state sensor 823 that converts to measurable charge entirely within a single monolithic semiconductor (e.g., epitaxial silicon) structure 824. The sensor 823 includes: a p-type electron-sensitive layer 827 configured to generate a plurality of electrons e INCIDENT (or X-ray photons) in response to each incident electron e 827 entering through the front surface 827-F; an n-type buried channel layer 825 configured to transfer electrons e 825 representing at least some of the generated electrons e 825 to the n+ floating diffusion FD; an amplifier 829 that generates an output signal OS based on the charge (voltage) V FD collected on the floating diffusion FD. The buried channel layer 825 is disposed on the top surface 827-B of the electron-sensitive layer 827 to facilitate the efficient collection of electrons e 827 generated by the electron-sensitive layer 827, and the floating diffusion FD is disposed within the buried channel layer 825 to facilitate the reception of electrons e 825 , thereby making the measured charge (voltage) V FD proportional to the number of electrons e FD captured by the floating diffusion FD. According to aspects of the present invention, the p-type electron-sensitive layer 827, the n-type buried channel layer 825, the n+ floating diffusion FD, and the amplifier 829 are co-fabricated by diffused dopants on the monolithic semiconductor structure 824, whereby the entire incident photon-to-readout conversion occurs entirely within the semiconductor structure 824. An optional pure boron layer 828 is formed on the bottom surface 827-F of the electron-sensitive layer 827 such that incident electrons e INCIDENT travel through the pure boron layer 828 before entering the electron-sensitive layer 827. As discussed in additional detail below, in addition to the sensor 823, each solid-state electron detector further includes at least one analog-to-digital converter 826 that converts the output signal OS to digital form for transmission to a computer 860 as a digital image data signal IDx (i.e., as signal ID1 in the case of the backscattered electron detector 822a or 822b, or as signal ID2 in the case of the secondary electron detector 821).

[0144] For simplicity, the various circuits and systems of the SEM 800 are described above in a simplified form, and it should be understood that these circuits and systems include additional features and perform additional functions. For example, although the backscattered electron detectors 822a / 822b and the secondary electron detector 821 of the SEM 800 are described above as including simplified sensors 823 to succinctly introduce certain key features of the present invention, it should be understood that the backscattered electron detectors 822a / 822 and the secondary electron detector 821 are preferably implemented using the multi-pixel electron detectors described below. Furthermore, in addition to generating an image of the scanned sample area, the computer 860 can also be configured to perform additional functions, such as determining the presence and / or type of defects using the methods described below based on the incident electron energy values indicated by the image data signals.

[0145] ​ An exemplary method 900 for inspecting or re-inspecting a sample, such as a semiconductor wafer, a reticle, or a photomask, is described. The method illustrated in ​ can be repeated for each area of the sample to be inspected or re-inspected. In a re-inspection SEM, the areas to be re-inspected may have been previously identified as potentially containing defects or particles by optical or SEM inspection.

[0146] For each area of the sample to be inspected or re-inspected, the exemplary method 900 begins at step 901. A master clock signal for controlling the timing of scanning the primary electron beam and acquiring image data is generated at step 902.

[0147] A beam deflection scan pattern is generated at step 904. This beam deflection scan pattern generates voltages and / or currents that travel to beam deflectors (such as shown at ​ 805 and 809). The pattern can be a raster scan, a serpentine pattern, a square spiral, or other pattern that covers the area of the sample. The scan pattern can also include, for example, delays and dummy scans where data is not collected to control charging of the sample surface.

[0148] A first pixel clock signal is generated at step 906. The first pixel clock signal is synchronized with the master clock signal. The first pixel clock signal can be at the same frequency as the master clock signal, a multiple of the master clock signal frequency, a factor of the master clock signal (i.e., the master clock signal frequency divided by an integer), or a rational multiple of the master clock signal frequency.

[0149] At step 908, on each cycle of the first pixel clock signal, the signals collected in the backscattered electron detector are read out and digitized.

[0150] In step 910, a second pixel clock signal synchronized with the master clock signal is generated. The second pixel clock signal can be at the same frequency as the master clock signal, a multiple of the master clock signal frequency, a factor of the master clock signal (i.e., the master clock signal frequency divided by an integer), or a rational multiple of the master clock signal frequency. The second pixel clock signal can be at the same frequency as the first pixel clock signal. In one embodiment, the first pixel clock signal is used for both the first and second pixel clock signals and no separate second pixel clock signal is generated.

[0151] In step 912, on each cycle of the second pixel clock signal (or if no second pixel clock signal is used, then the first pixel clock signal), the signal collected in the secondary electron detector is read out and digitized.

[0152] In step 914, the digitized backscattered and secondary electron signals are used to determine the presence of one or more defects in the scanned area. Defects can include the presence of materials (such as particles) that should not be present, the absence of materials that should be present (such as can occur under over-etching conditions), or deformed patterns.

[0153] In optional step 916, for each defect found in step 914, the defect type or the material type of the defect can be determined. For example, elements with a high atomic number typically scatter a larger portion of the incident electrons than elements with a low atomic number. The backscattered electron signal can be used to infer the presence or absence of elements with a high atomic number (such as metals). In step 916, when re-inspecting an area that has been previously inspected, the previously inspected data (optical and / or electron beam) can be used in combination with the digitized backscattered and secondary electron signals to better determine the defect or material type. In one embodiment, steps 914 and 916 can be combined into a single step that simultaneously determines the presence and type of the defect.

[0154] The method 900 can be repeated from the start for each area to be re-inspected or inspected on the sample.

[0155] ​ Describes an exemplary simplified multi-pixel electron detector 1000 for use in re-inspecting an SEM or other SEM system (such as ​ the SEM 800 shown in). The electron detector 1000 generally includes a sensor circuit 1010 and a signal processing circuit 1020. In ​ the preferred embodiment shown in, for reasons that will become clearer below, the sensor circuit 1010 is fabricated on a silicon structure (chip) 1011, and the signal processing circuit 1020 is fabricated on a separate silicon structure (chip) 1021. In an alternative embodiment (not shown), both the sensor and signal processing circuits are fabricated on the same silicon chip.

[0156] Refer to​ In the lower part of, sensor 1010 includes sixteen pixels 1015-11 to 1015-44 arranged in a four-row, four-column (4×4) array. For descriptive purposes, the "rows" of pixels are aligned in the arbitrarily assigned X-axis direction in ​ , whereby pixels 1015-11 to 1015-14 form the first row, pixels 1015-21 to 1015-24 form the second row, pixels 1015-31 to 1015-34 form the third row, and pixels 1015-41 to 1015-44 form the fourth row. Similarly, the "columns" of pixels are aligned in the Y-axis direction shown in ​ , whereby pixels 1015-11 to 1015-41 form the first column, pixels 1015-12 to 1015-42 form the second column, pixels 1015-13 to 1015-43 form the third column, and pixels 1015-14 to 1015-44 form the fourth column. In practical applications, it is expected that the sensor circuit includes an array of 16×16, 32×32, 64×64, or more pixels, where the pixels of these larger arrays include features similar to those of the simplified 4×4 array described below. Furthermore, the number of pixels in each row / column of the array does not need to be a power of 2, nor does the number of pixels in each row need to be equal to the number of pixels in each column. In one embodiment (e.g., in the case of the backscattered electron detectors 822a or 822b shown in ​ ), sensor 1010 includes a hole (not shown) in the middle of the sensor to allow the primary electron beam to travel through the sensor. Although pixels 1015-11 to 1015-44 are depicted as having a square shape, the pixels can also be rectangular or hexagonal.

[0157] According to aspects of the present invention, each pixel of sensor circuit 1010 includes an electron-sensitive, buried-channel, floating-diffusion, and amplifier circuit structure similar to that described above with reference to ​ . By way of example, referring to pixel 1015-41 in ​ , each pixel generally includes a p-type electron-sensitive region 1012A, an n-type buried-channel layer 1016, a floating diffusion FD, and an amplifier 1017. The p-type electron-sensitive region 1012A is formed by an epitaxial layer 1012 located below pixel 1015-41 and as described above with reference to ​The described manner functions to generate a plurality of electrons in response to incident electrons. The buried channel layer 1016 is formed above the electron-sensitive region 1012A by n-type dopants diffused into the epitaxial layer 1012, and is used to transfer the electrons generated by the electron-sensitive region 1012A to the floating diffusion FD. The floating diffusion FD, illustrated using a schematic capacitor symbol for descriptive purposes, is formed by n+ dopants diffused into the buried channel layer 1016, and is used to collect at least some of the plurality of electrons generated by the electron-sensitive region 1012A, whereby a corresponding charge (voltage) is generated in the manner described above with reference to ​ The amplifier 1017 includes transistors M1, M2, and M3, and is used to generate an associated output signal OS41 whose voltage level is determined by the number of electrons collected on the floating diffusion FD during any given readout operation. Each pixel also includes a reset transistor RT for resetting the voltage level of the pixel floating diffusion FD after each readout operation.

[0158] In ​The sensor circuit 1010 is depicted in cross-section to illustrate a preferred embodiment in which pixels 1015-11 to 1015-44 are fabricated on a thin film structure including an epitaxial (epi) layer 1012 and a boron layer 1013. In one embodiment, the substrate 1011 is a p+ (i.e., highly p-doped) substrate and the epitaxial layer 1012 is a p-epitaxial layer (i.e., a layer having a low concentration of p-dopant). Preferably, the thickness T of the epitaxial layer 1012 is between about 40 micrometers (μm) and 100 μm so as to keep the time it takes for electrons to drift from the electron-sensitive region to the buried channel layer limited to less than about 10 ns while providing good mechanical strength. Depending on the mechanical support provided by the substrate 1011, the epitaxial layer 1012 can be made thinner than 40 μm, e.g., between about 10 μm and 40 μm. After forming the epitaxial layer 1012, one or more additional layers (not shown) (e.g., a gate oxide layer, a silicon nitride gate layer, and one or more dielectric layers) are formed over the epitaxial layer 1012, and one or more doped regions (e.g., an n-type buried channel portion 1016, an n+ floating diffusion FD, channel regions associated with the reset transistor RT and the amplifier 1017, and doped regions associated with front-side circuit elements (not shown) forming the control circuit 1018 disposed in the peripheral region of the pixel array) are formed in the epitaxial layer 1012. Forming the various pixel transistors and front-side circuit elements involves implanting or doping portions of the front side of the epitaxial layer and can involve patterning the gate layer. The portion of the substrate 1011 disposed under pixels 1015-11 to 1015-44 is then removed (thinned) to expose the electron-sensitive (front-side) surface 1012-ES, and then the boron layer 1013 is formed on the electron-sensitive surface 1012-ES. For example, additional details related to the formation of the thin film structure depicted in ​ are provided in the co-owned and co-pending U.S. Patent Application Publication 2013 / 0264481, titled “Back-illuminated Sensor With Boron Layer,” filed Mar. 10, 2013, by Chern et al., the entire text of which is incorporated herein by reference.

[0159] ​ is shown in additional detail ​Simplified diagram of exemplary pixel 1015-41. Specifically, amplifier 1017 includes a first NMOS transistor M1 having a drain terminal connected to a voltage source VOD, a gate terminal connected to a floating diffusion FD and controlled by the charge stored on the floating diffusion FD, and a source terminal connected to the drain terminal of a second NMOS transistor M2 and the gate terminal of a third NMOS transistor M3. The gate and source terminals of transistor M2 are connected to ground, and the drain terminal of transistor M3 is connected to the voltage source VOD, whereby the output terminal of amplifier 1017 is formed by the source terminal of transistor M3. Pixel 1015-41 also includes an NMOS reset transistor RT having a source terminal connected to the floating diffusion FD, a gate terminal controlled by a reset control signal RG, and a drain terminal connected to a reset voltage RD. During operation of pixel 1015-41, each detection / readout cycle begins by resetting the floating diffusion FD to voltage RD by toggling the reset transistor RT, then waiting for a predetermined detection period, and then sampling the output signal OS41. If zero incident (i.e., backscattered or secondary) electrons enter the electron-sensitive region of pixel 1015-41 during the detection period, the voltage levels on the floating diffusion FD and the output signal OS41 do not change significantly from the reset value at readout. If one or more incident (i.e., backscattered or secondary) electrons enter the electron-sensitive region of pixel 1015-41 during the detection period, the voltage level on the floating diffusion FD changes (becomes more negative) by an amount proportional to the number and energy of the incident electrons (which is indicated by the number of electrons accumulated in the floating diffusion FD), whereby the voltage level of the output signal OS41 at readout provides an approximate energy level of the incident electrons detected during the detection / readout cycle (or the sum of the energies if multiple electrons are incident during the detection / readout cycle). When operating at an operating speed of 100 MHz, 100 million detection / readout cycles are performed per second on each pixel.

[0160] According to ​ the preferred embodiment of the present invention depicted in, the floating diffusion of each pixel is located in the central region of its pixel, and the nominal lateral size dimension of each pixel is about 250 μm or less to facilitate the transfer of electrons to the floating diffusion during each detection / readout cycle. Briefly referring to ​ , the lateral size dimension is measured in the X-Y plane horizontal to the silicon structure 1011 and represents the area occupied by each pixel. Referring to ​ , the floating diffusion FD is located in the central region C of the area occupied by pixel 1015-41 ( ​) wherein the width of pixel 1015-41 is indicated by width dimension X1, and the length of pixel 1015-41 is indicated by dimension Y1. According to the present preferred embodiment, both dimensions X1 and Y1 are about 250 μm or less to facilitate high-speed readout operations. Due to the drift velocity of electrons in silicon, when it is desired to read out pixel 1015-41 at a data rate of about 100 MHz or higher, the lateral dimension of each pixel is preferably not more than about 250 μm, such that electrons can be driven to the centrally located floating diffusion FD in about 10 nanoseconds (ns) or less. For lower speed operations, pixels larger than 250 μm may be acceptable. For operations at speeds much higher than 100 MHz, a pixel size less than 250 μm is preferred.

[0161] Referring ​ to the upper portion of, according to known techniques, analog-to-digital converters 1025-11 to 1025-44 and optional signal processing circuitry 1028-1 and optional signal transmission circuitry 1028-2 are fabricated on semiconductor substrate 1021. In one embodiment, to facilitate a one-to-one signal connection between pixels 1015-11 to 1015-44 and analog-to-digital converters 1025-11 to 1025-44 discussed below, analog-to-digital converters 1025-11 to 1025-44 are arranged in a pattern that generally mirrors the array pattern (matrix) formed by pixels 1015-11 to 1015-44. Digital values generated by analog-to-digital converters 1025-11 to 1025-44 are transmitted by conductors 1029 to processing circuitry 1028-1, which is configured, for example, to calculate an approximate energy of incident electrons based on digitized output signals (image data) received from associated pixels of the sensor circuit. For example, optional high-speed data transmission circuitry 1028-2 is used to transmit image data signal ID to an external processing system (e.g., a computer).

[0162] In one embodiment, in addition to the array of analog-to-digital converters 1025-11 to 1025-44, signal processing circuit 1020 further includes processing circuitry 1028-1 configured, for example, to calculate an approximate energy of incident electrons based on digitized output signals (image data) received from associated pixels of the sensor circuit. In another embodiment, signal processing circuit 1020 further includes high-speed data transmission circuitry 1028-2 for transmitting image data signal ID to an external processing system (e.g., a computer).

[0163] Referring again ​In the lower part, each output signal OS11 to OS44 generated by pixels 1015-11 to 1015-44 is transmitted through an associated conductive path (indicated by the dashed line) to the associated analog-to-digital converters 1025-11 to 1025-44 disposed on the signal processing circuit 1020. For example, pixel 1015-11 transmits output signal OS11 to analog-to-digital converter 1025-11 through a dedicated conductive path, pixel 1015-12 transmits output signal OS12 directly to analog-to-digital converter 1025-12, and so on. In the preferred embodiment described below with reference to ​ The output signals OS11 to OS44 may be transmitted through metal pads, solder balls / bumps, or a similar structure that provides an individual signal path between each pixel and its associated analog-to-digital converter.

[0164] As explained herein, each pixel has multiple signal or electrical connections, such as a gate, control signals, a power supply, and a ground. For a practical and cost-effective assembly for individually connecting each of these signals to each pixel, the interconnect density would be too high. Preferably, most or all of these signals are connected together between adjacent pixels and brought to a convenient location, such as near the edge of the sensor where external electrical connections can be made. For example, as indicated in ​ Signals RD, RG, and VOD are transmitted from the control circuit area 1018 to the pixels in each row through metal conductors (signal lines) 1019. In an actual device, there may be more than three signals connected together between the pixels, but three signals are shown here to illustrate the principle. External connections to signals such as RD, RG, and VOD can be made using bonding wires, solder balls, or bumps (as described below with reference to ​ Description) or other techniques. As ​ Shown in, the connections between the signals can be made mainly or exclusively in one direction (such as the horizontal direction shown), in order to simplify the interconnections and allow the use of only a single metal layer. For example, using a large enough area outside the active area of the sensor, or using two or more metal layers, if the additional cost can be justified, the interconnections can be easily made in two dimensions.

[0165] Compared with the shared signal lines of the sensor circuit 1010, as indicated in the upper part of ​ Each analog-to-digital converter 1025-11 to 1025-44 of the signal processing circuit 1020 is coupled to the processing circuit 1028-1 through an individual conductor (signal line) 1029 to maximize data transfer and processing.

[0166] ​A description is given of an exemplary electronic detector 1000A including an electronic sensor 1010A, an ASIC (signal processing circuitry) 1020A, and a substrate 1001. The substrate 1001 provides mechanical support for the electronic detector 1000A and allows external electrical connections (not shown) to the electronic detector 1000A. The substrate 1001 may include silicon or ceramic materials. The electronic sensor 1010A and the ASIC 1020A are fabricated on separate silicon substrates (die or chips) that are then stacked on top of each other. Alternatively, the electronic sensor 1010A and the ASIC 1020A may be placed on opposite sides of the substrate 1001, or side by side on the substrate 1001 (not shown). The electronic sensor 1010A is preferably similar to ​ and 10B the multi-pixel electronic sensors described in, and even more preferably includes pixels, such as the pixels described below, for example, with reference to ​ and 11B . During operation, the electronic detector 1000A is positioned such that the electron-sensitive surface 1012-ES faces the sample or other electron source, whereby detected electrons impinge on the electron-sensitive surface 1012-ES and are detected as described herein.

[0167] The electronic sensor 1010A is electrically connected to the ASIC 1020A by solder balls or bumps 1006. In a preferred embodiment, the output signal generated by each pixel 1015 of the electronic sensor 1010A is transmitted to the associated analog-to-digital converter 1025 of the ASIC 1020A through the associated solder ball / bump 1006. For example, the output signal OS11 generated by pixel 1015-11 is transmitted through an associated conductor to a first pad 1009 disposed on the lower surface of the sensor 1010A, and from the first pad 1009 through the associated solder ball / bump 1006-11 to a second pad disposed on the ASIC 1020A, and the output signal OS11 is transmitted from the second pad to the input terminal of the associated analog-to-digital converter 1025-11. One or more solder balls / bumps 1006 may also be used to transmit signals from the ASIC 1020A (e.g., from circuit 1028) to the control circuit 1018 of the sensor 1010A. These balls or bumps also provide mechanical support for the electronic sensor 1010A and provide thermal conductivity to the electronic sensor 1010A. The solder balls or bumps may alternatively be used to directly mount the electronic sensor 1010A to the substrate 1001 (not shown). Metal pads may also be provided on the electronic sensor 1010A to enable wire bonding to provide electrical connection to the electronic sensor 1010A (e.g., to the surface 1012-ES of the electronic sensor 1010A).

[0168] ASIC 1020A can be directly mounted onto substrate 1001 as shown, or can be mounted and electrically connected to substrate 1001 through solder balls or bumps (not shown). If ASIC 1020A includes through-silicon vias, solder balls or bumps can be used on both sides of ASIC 1020A. Metal pads 1007 and 1027 and / or wire bonds 1039 can be used to make the electrical connection between ASIC 1020A and substrate 1001. A similar wire bond connection can be made between sensor 1010A and substrate 1001, or all connections between substrate 1001 and sensor 1010A are made through ASIC 1020A. ASIC 1020A can include a single ASIC or two or more ASICs. For example, in one embodiment, ASIC 1020A can include two ASICs, one ASIC mainly containing analog functions and the other ASIC mainly containing digital functions. Additional integrated circuits (such as fiber optic transmitters or fiber optic receivers (not shown)) can also be mounted on substrate 1001.

[0169] ASIC 1020A preferably includes an analog-to-digital converter 1025 configured to digitize the output signal of pixels 1015 from electronic sensor 1010A. In one embodiment, ASIC 1020A includes one analog-to-digital converter 1025 for each pixel 1015, such that all pixels 1015 can be digitized in parallel at a high speed (e.g., at a speed of 100 MHz or higher). Using a high digitization rate (e.g., 100 MHz or higher), each pixel 1015 can detect up to a plurality of electrons per clock cycle, and thus, each analog-to-digital converter 1025 may only need 8, 6 or fewer bits. Designing converters with a smaller number of bits to operate at high speed is easier. Analog-to-digital converters with a smaller number of bits can occupy a small area of silicon, making it feasible to have a large number (e.g., 1024 or more) of bits on one ASIC.

[0170] ASIC 1020A preferably implements ​ part of the method shown. For example, when electron detector 1000A is used as a backscattered electron detector, ASIC 1020A can implement step 908, or when the electron detector is used as a secondary electron detector, ASIC 1020A can implement step 912. ASIC 1020A can further incorporate circuitry to generate ​ the first pixel clock signal or the second pixel clock signal described, or can receive a pixel clock signal from an external circuit.

[0171] When the electron detector 1000A is used as a secondary electron detector, the ASIC 1020A can perform unscanning of secondary electrons, and the result is similar to the unscanning performed by the electron optics in the '791 patent cited above. The ASIC 1020A can sum signals from groups of pixels corresponding to secondary electrons emitted from the sample into an angular range and output the sum as one signal. As the beam deflection changes, the ASIC 1020A can sum different groups of pixels at the changed deflections corresponding to approximately the same angular range. Since the same master clock is used to generate or synchronize the beam deflection and to generate or synchronize the first and second pixel clocks, the ASIC 1020A has the required timing information to adjust which groups of pixels are summed together in synchronization with the beam deflection scan.

[0172] When the electron current is low and the pixel clock rate is high enough such that the average number of electrons per pixel is much less than 1, then the charge collected in a single pixel in a single cycle of the pixel clock can be used to determine whether an electron is detected in the pixel during that clock cycle, and if so, to determine the approximate energy of the electron. A boron coating on the electron sensor surface is necessary to achieve this capability. In the absence of a boron coating, when the incident electron energy is less than about 1 keV, few or no electrons are generated per incident electron. With a boron coating of about 5 nm thickness, about 100 electrons are generated per incident 1 keV electron. If the floating diffusion capacitance is small enough to generate more than about 10 microvolts (μV) per electron, then this signal can be detected above the noise level. In one embodiment, the floating diffusion capacitance is small enough such that the floating diffusion generates greater than about 20 μV per electron. For such low-level signals, it is important to couple each pixel to the corresponding analog-to-digital converter by the shortest possible path to keep the noise level low and the stray capacitance low. Attaching the electron sensor directly to the ASIC allows the path from each pixel to the corresponding analog-to-digital converter to be very short.

[0173] When individual electrons can be detected, the ASIC 1020A can use the signal level to determine the approximate energy of the electron. The ASIC 1020A can further set thresholds, count, or grade the electrons according to the energy of the incident electrons in order to detect or classify one or more types of defects or materials on the sample.

[0174] ​ and 11B are respectively a disassembled and assembled perspective view showing a simplified pixel 1100 of an electron sensor (e.g., the sensor 1010 described above with reference to ​ ). Similar to the pixels described above, the pixel 1100 preferably has a size (nominal lateral dimension) between about 200 μm and 250 μm.

[0175] Reference ​ , similar to the pixel features mentioned above, pixel 1100 includes a p-type electron-sensitive layer 1157A, an n-type buried channel layer 1155 disposed above the p-type electron-sensitive layer 1157A, an n+ floating diffusion FD formed in the n-type buried channel layer 1155, an amplifier 1110, and an optional pure boron layer 1160 disposed below the p-type electron-sensitive layer 1157A.

[0176] The buried channel layer 1155 and the electron-sensitive layer 1157A are disposed in the epitaxial silicon layer 1157 such that the upper extent of the buried channel layer 1155 coincides with the top (first) surface 1157-S1 of the epitaxial silicon layer 1157 (forming the top (first) surface 1157-S1), and the electron-sensitive layer 1157A includes a portion of the epitaxial silicon layer 1157 disposed between the buried channel layer 1155 and the bottom (electron-sensitive) surface 1157-S2 of the epitaxial silicon layer 1157. The epitaxial silicon layer 1157 has a thickness preferably between about 10 μm and 100 μm and is lightly p-doped such that in one embodiment, the resistivity is between about 10 and 2000 Ωcm. A thicker epitaxial layer provides greater mechanical strength but may generate more dark current. Layers thicker than about 20 μm or 30 μm may require a lower doping level (higher resistivity) to maintain a fully depleted state in the bulk of the silicon. Too low a doping level is not preferred because it will result in a higher dark current.

[0177] The buried channel layer 1155 is generated by n-type doping diffused using known techniques below the top surface 1157-S1 of the epitaxial silicon layer 1157. The doping concentration of the buried channel layer 1155 must be several orders of magnitude greater than the doping concentration in the epitaxial silicon layer 1157 such that the epitaxial silicon layer 1157 is fully depleted during operation. In a preferred embodiment, the concentration of the n-type dopant in the buried channel layer 1155 is between about 10 16 and 5×10 16 cm -3 -3.

[0178] The floating diffusion FD includes a relatively small n+ doped region disposed in the buried channel layer 1155 configured to collect electrons generated in the pixel 1100 in response to incident backscattered or secondary electrons. In a preferred embodiment, the floating diffusion FD has a nominal lateral size between about 1 and 5 μm, and the concentration of the n-type dopant in the floating diffusion FD is between about 10 19 and 10 21 cm -3 -3. The connection for transferring the stored charge to the amplifier 1110 is made to the floating diffusion FD using known techniques.

[0179] The pure boron layer 1160 is preferably deposited after the epitaxial silicon layer 1157 or on the bottom surface 1157-S2. The thickness of the boron layer 1160 is preferably between about 2 nm and 10 nm, for example, a thickness of about 5 nm. As explained in U.S. Patent Application Publication No. 2013 / 0264481, titled "Back-illuminated Sensor With Boron Layer" and filed on March 10, 2013 by Chern et al. (which is incorporated herein by reference above), during the boron deposition process, some boron diffuses several nm into the epitaxial silicon layer 1157 to form a thin, very highly doped p+ layer adjacent to the pure boron layer 1160. This p+ layer is important for the optimal operation of the sensor. This p+ layer generates an electric field that drives electrons towards the buried channel 1155, reduces the dark current from the back surface of the epitaxial silicon layer 1157, and increases the conductivity of the silicon surface, thereby allowing the sensor to operate at high incident electron currents as well as low currents. In one embodiment, during the deposition of the pure boron layer 1160, additional boron is allowed to diffuse into the silicon. This can be accomplished by one of several methods. In one exemplary method, a boron layer thicker than the final desired thickness is deposited (e.g., when a 5 nm final thickness is required, a 6 nm to 8 nm layer can be deposited) and then the boron is allowed to diffuse into the silicon epitaxial layer 1157 by holding the sensor at the deposition temperature or higher (e.g., between about 800 °C and 950 °C) for several minutes. In another exemplary embodiment, a boron layer several nm thick can be deposited on the silicon, then the boron can be driven in at the deposition temperature or higher, and then the final desired thickness (e.g., 5 nm) of boron can be deposited.

[0180] According to aspects of this embodiment, the amplifier 1110 is formed in and above an elongated p-type well region 1159 that extends vertically from the top surface 1157-S1 into the electron-sensitive layer 1157A and extends outward from a point adjacent to the central region C of the pixel (i.e., towards the peripheral outer edge 1155-OPE of the n-type buried channel layer 1155). It should be noted that for descriptive purposes, in ​The p-type well region 1159 is shown as being separated from the silicon epitaxial layer 1157, but in fact, the p-type well region 1159 includes a p-type doped region of the silicon epitaxial layer 1157. In an alternative embodiment, the p-well 1159 is completely contained within the square perimeter boundary of the pixel 1100 or extends beyond the perimeter boundary (e.g., into an adjacent pixel). In one embodiment, the p-well 1159 is formed by implanting boron at a concentration substantially higher than the dopant concentration in the silicon epitaxial layer 1157, and then n-type channel regions 1112 of various transistors of the amplifier 1110 are formed in the p-well 1159, whereby the p-well 1159 is used to prevent electrons from directly migrating from the epitaxial silicon layer into the channel region 1112. In one embodiment, the p-well extends beneath the floating diffusion and the channel region of the reset transistor of the pixel (discussed below with reference to ​ to prevent electrons from directly migrating from the epitaxial silicon layer into the floating diffusion.

[0181] As ​ indicated, one or more dielectric layers 1154 overlie the buried channel. The dielectric layer 1154 may include a single silicon dioxide layer or a silicon nitride layer on top of the silicon dioxide layer or a silicon oxide layer on top of the silicon nitride layer on top of the silicon dioxide layer. The individual layer thicknesses may be between about 20 nm and 50 nm.

[0182] According to another aspect, the pixel 1100 further includes a resistive gate 1151, the resistive gate 1151 including one or more polysilicon or amorphous silicon gate structures 1170 disposed on the dielectric layer 1154 and configured to cover most of the upper surface 1157-S1. As ​ indicated, the resistive gate 1151 includes an outer peripheral edge 1151-OPE that is substantially aligned with the perimeter of the pixel 1100 (i.e., is generally aligned with the outer peripheral edge 1155-OPE of the buried channel layer 1155), and defines a central opening 1151-CO such that the inner peripheral edge 1151-IPE of the resistive gate 1151 (i.e., the inner edge of the gate structure 1170) substantially surrounds the central pixel region C and is laterally spaced from the central pixel region C (e.g., as ​ indicated). In one embodiment, the gate structure 1170 includes polysilicon having a relatively lightly doped level (e.g., having a resistivity greater than about 30 Ω / cm), such that when a reduced potential difference is applied between the inner peripheral edge 1151-IPE and the outer peripheral edge 1151-OPE, the resistive gate 1151 generates as discussed below with reference to ​ and 12BThe described manner biases the electrons in the buried channel layer 1155 toward the associated electric field of the central region C of the pixel. To facilitate operation of the resistive gate 1151 such that electrons from all of the peripheral lateral regions of the pixel 1100 are biased toward the central region C for collection by the floating diffusion FD, the resistive gate 1151 further includes elongated conductors (e.g., metal lines) 1171 and 1172 disposed on the gate structure 1170 along and adjacent to the outer peripheral edge 1151 - OPE and the inner peripheral edge 1151 - IPE, respectively. As described below, a negative electric potential (e.g., a voltage of - 5V) relative to the elongated conductor 1172 is applied to the elongated conductor 1171. The resulting potential difference between the conductors 1171 and 1172 creates a decreasing electric potential in the gate structure 1170 (i.e., between the inner peripheral edge 1151 - IPE and the outer peripheral edge 1151 - OPE) in a substantially radial direction, which drives the electrons in the buried channel (see ​ ) toward the floating diffusion FD. Additional connections to the gate structure 1170 can be provided between the conductors 1171 and 1172 and maintained at an electric potential intermediate the electric potentials applied to the conductors 1171 and 1172 to modify the electric potential gradient in the resistive gate 1151. Additional details regarding the composition of the resistive gate 1151 can be found in U.S. Patent Application No. 11 / 805,907, filed May 25, 2007, by Armstrong et al. (published as U.S. Patent Application Publication 2011 / 0073982 on Mar. 31, 2011), titled "Inspection System Using BackSide Illuminated Linear Sensor". The entire text of this patent application is incorporated herein by reference.

[0183] According to another aspect, the pixel 1100 further includes one or more optional additional gate structures disposed between the resistive gate 1151 and the floating diffusion FD to further drive electrons onto the floating diffusion FD or to control when electrons are collected / accumulated on the floating diffusion FD. For example, the pixel 1100 includes a C - shaped highly doped polysilicon gate structure 1153 disposed on the dielectric layer 1154 and inside the inner peripheral edge 1151 - IPE of the resistive gate 1151. A constant or switched voltage can be applied to the gate structure 1153 to control and ensure effective charge transfer from the portion of the buried channel layer 1155 under the resistive gate 1151 to the floating diffusion FD. In the following reference ​ and 12BIn one described embodiment, the gate structure 1153 is used as a summing gate to which a low voltage (e.g., 0 V (relative to the bottom surface 1157 - S2 or the boron layer 1160)) is applied during reset and a high voltage (e.g., 10 V) is applied during readout. In addition to the summing gate 1153, one or more additional gates (e.g., buffer gates, transfer gates, and output gates) can also be formed by associated additional gate structures placed between the resistive gate 1151 and the floating diffusion FD. Such gates are well known in CCD technology and can operate in a similar manner in this electronic sensor. See, for example, J.R. Janesick, "Scientific Charge - Coupled Devices", SPIE Press, 2001, pages 156 - 165.

[0184] ​ Shows the simplified pixel 1100 in a partially assembled state. As indicated, most of the pixel 1100 (i.e., most of the top surface 1157 - S1) is covered by an amorphous or polycrystalline silicon gate structure 1170 that forms the resistive gate 1151. The exposed area (indicated by the dashed box) above the p - well region 1159 is indicated as empty for illustrative purposes but in fact contains various connection structures and gates associated with the transistors that form the amplifier 1110 and the reset transistor RT. The following references ​ Provide an exemplary layout of these structures and gates. In one embodiment (not shown), the summing gate 1153 overlaps with the inner peripheral edge 1151 - IPE of the resistive gate 1151 (see ​ ), i.e., extends above the inner peripheral edge 1151 - IPE and is separated by a suitable insulator to keep it electrically isolated. This overlapping configuration prevents edge electric fields in the silicon below the gap between the two gate structures. These edge electric fields can trap electrons in the buried channel or cause them to move in an unintended direction.

[0185] ​ And 12B Are simplified cross - sectional views of the pixel 1100 during an exemplary detection / readout cycle (operation), where ​ Depicts the pixel 1100 at time T0 during or immediately after the floating diffusion FD is reset to the reset voltage (i.e., OS 400 Equals the reset voltage level V RST ), and ​ Depicts the pixel 1100 when the output signal OS 400 Is read out in the manner described above (i.e., at OS 400is equal to the voltage level V determined by the number of electrons accumulated on the floating diffusion FD between times T0 and T1 FD at a subsequent time T1 (when). It should be noted that ​ and 12B the individual layers shown in are not drawn to scale but are enlarged to show them more clearly.

[0186] Reference ​ , the back surface coated with the pure boron layer 1160 is preferably maintained at a potential similar to the outer edge of the resistive gate (in the example, for example, 0 V). Since boron is conductive and since the silicon directly below the pure boron layer 1160 is highly doped with boron, the back surface can be made sufficiently conductive such that connection to it at one or several locations provides a sufficiently low impedance path for the operation of the sensor at high incident currents (for example, currents of about 10 to 50 nanoamperes (nA)). The electric field formed by these potential differences drives electrons (such as E1160) generated in the epitaxial silicon (electron-sensitive) region 1157A by backscattered or secondary electrons incident on the sensor through the pure boron layer 1160 towards the buried channel 1155, as illustrated by the arrows on the electrons. The potential difference is applied to the resistive gate 1151 between the outer edge of the pixel 1100 and the inner edge of the gate structure 1170 through conductors 1171 and 1172. In one example, 0 V is applied to the outer edge through conductor 1171 and 5 V is applied to the inner edge through conductor 1172, as shown. The resulting potential difference in the gate structure 1170 creates an electric field that drives electrons (such as E1151) placed in the buried channel 1155 towards the center of the pixel 1100 (i.e., causes these electrons to move towards the floating diffusion FD).

[0187] In ​ and 12B the example depicted in, the summing gate 1153 is used to control electrons and drive them into the floating diffusion FD. For example, as indicated in ​ , when (for example, during reset) the transfer of electrons to the floating diffusion FD is blocked, the voltage applied to the summing gate 1153 is significantly lower than the voltage applied to conductor 1172, whereby the electric field prevents electrons from flowing easily into the floating diffusion FD and causes them to accumulate in the buried channel 1155 below 1172 (as indicated by electron E1151). Conversely, as indicated in ​ , when electrons are to be transferred to the floating diffusion FD (for example, just before readout), the summing gate 1153 receives a relatively high positive potential (relative to the voltage applied to conductor 1172, for example, 10 V relative to the 5 V applied to conductor 1172, as shown), thereby causing electrons (such as E1153) below conductor 1172 to move towards the floating diffusion FD. Since the floating diffusion FD acts as a capacitor, the voltage V on the floating diffusion FD at readoutFD Becomes more negative as more charge (electrons) accumulates. For small signals, the change in voltage V FD is proportional to the accumulated charge (i.e., the capacitance of the floating diffusion FD is substantially constant), but as the amount of charge increases, the capacitance changes and the voltage increase is no longer linear. Although operation in the linear regime is generally preferred, in one embodiment, operation in the non-linear regime can be used to compress high dynamic range signals. Since the sensitivity (charge-to-voltage conversion ratio) and speed depend on the capacitance of the floating diffusion FD being small, it is generally preferred to keep the floating diffusion FD as small as possible and to minimize the size (and thus capacitance) of the structures connected to the floating diffusion FD, including the channel of the reset transistor and the connection to the gate of transistor M1. By implementing the FD as a VCVFD, depending on the system operating mode and the expected signal level, an appropriate floating diffusion capacitance can be selected by applying a control voltage to the VCVFD, as described above. In this way, the VCVFD can be used to handle both small signals (minimum capacitance) and large signals (higher capacitance depending on the tuning of the VCVFD gate) in a way that achieves a high dynamic range.

[0188] It should be noted that the voltage values cited in the examples above are only examples. Different values can be used, and the optimal value depends on many factors, including the desired operating speed of the sensor, the geometry of one or more gates, the doping profile and thickness of the dielectric layer 1154. It should also be noted that it is generally convenient to define the back side of the sensor (i.e., the electron-sensitive side) as 0V (note that if the electron detector floats at a potential other than ground, this voltage can be away from the ground potential), and the conductor 1171 is preferably connected to a similar potential.

[0189] In an alternative embodiment, instead of switching the voltages on the reset transistor and the various gates of each pixel, the reset transistor and the various gates are held at a fixed potential such that electrons generated in the epitaxial silicon (electron-sensitive) region 1157A can flow continuously to the floating diffusion FD. In this mode, the voltage on the reset gate RG( ​ ) must be held at a voltage that causes the reset transistor RT to be in a high-resistance, partially-conducting state (e.g., a channel resistance between about 500 kΩ and several MΩ) rather than "off" (which corresponds to a channel resistance of several hundred MΩ or higher) or "on" (which corresponds to a channel resistance of several kΩ or lower).

[0190] In this embodiment, the gates between the inner peripheral edge of the resistive gate 1170 and the floating diffusion FD must each be maintained at a continuously higher voltage (all higher than the voltage of the conductor 1172) such that electrons in the buried channel 1155 will be driven toward the floating diffusion FD. For example, if the conductor 1172 is at a potential of 5V, then the sum gate 1153 can be maintained at a voltage of 6V. If there is another gate (not shown) between the inner peripheral edge of the resistive gate 1170 and the sum gate 1153, then the other gate can be maintained, for example, at 6V and the sum gate 1153 at 7V. The reset drain RD ( ​ ) must be maintained at a voltage significantly more positive than the innermost gate (e.g., the sum gate 1153) in order to hold the floating diffusion FD at a sufficiently high potential relative to all the gates to attract electrons in the buried channel. For example, the reset drain RD can be maintained at 15V.

[0191] As will be readily appreciated, the channel of the reset transistor RT and the capacitance of the floating diffusion FD form an RC time constant that determines how quickly the voltage on the floating diffusion FD decays back to the reset drain RD voltage after electrons arrive at the floating diffusion FD. For example, if the analog-to-digital converter samples each pixel at 100 MHz (i.e., once every 10 ns), then an RC time constant of about 20 ns or 30 ns can be appropriate. In this example, if the capacitance of the floating diffusion is about 10 fF, then the reset gate RG voltage should be set such that the resistance of the channel of the reset transistor RT is about 2.5 MΩ to give a time constant of about 25 ns.

[0192] This embodiment is made feasible by the sensors disclosed herein because each pixel is connected to its own analog-to-digital converter. In conventional two-dimensional CCD or CMOS image sensors, because the number of analog-to-digital converters is less than the number of pixels, charge needs to be stored and read out continuously. In addition, conventional CMOS image sensors use transistors and gates with surface channels rather than buried channels. Compared to buried channels, surface channels generate noise and cannot transfer small charges without loss.

[0193] ​ is a simplified plan view showing a portion of the pixel 1100A, and in particular, shows an exemplary layout utilized by the pixel 1100A according to an exemplary specific embodiment of the present invention, including the floating diffusion FD, the amplifier 1110A, and the reset transistor RT. In one embodiment, the pixel 1100A is substantially the same as the pixel 1100 described above (i.e., where the floating diffusion FD is located in the central region of the pixel 1100A), and thus the unillustrated portions of the pixel 1100A are omitted for the sake of brevity. In ​In [the figure], the doped region (e.g., the floating diffusion FD) is indicated by the dotted shaded region, the conductive structure (e.g., polysilicon or metal) is indicated by the slanted region, and the vertical metal vias are indicated by the boxes containing the "X" symbol. It should be noted that the various amplifier polysilicon or metal structures are separated (i.e., discontinuous), and are patterned and interconnected using standard techniques. In this example, the reset transistor RT is placed directly below the floating diffusion FD, and the amplifier 1110A includes transistors M1, M2, and M3 that are connected and operate in a manner similar to that described above with reference to ​ For clarity, the additional connections and vias associated with the structure shown in ​ are omitted.

[0194] Reference ​ to the upper part, the floating diffusion FD is disposed adjacent to the p-well region 1159A, which is formed in the manner described above and includes various n-channel regions associated with the reset transistor RT and the transistors M1 to M3 of the amplifier 1110A. For example, the reset transistor RT includes an n-channel region 1112A disposed in the p-well region 1159A directly below the floating diffusion FD and connected to the floating diffusion FD and receiving the reset voltage RD RT and includes a gate structure controlled by the reset gate signal RG. The transistor M1 includes an n-channel region 1112A disposed in the p-well region 1159A directly below the reset transistor RT M1 and includes a gate structure connected to the floating diffusion FD, a drain structure connected to the system voltage VOD, and a source structure connected to the drain structure of the transistor M2 and the gate structure of the transistor M3. The transistor M2 includes an n-channel region 1112A disposed in the p-well region 1159A directly below the transistor M1 M2 and includes a gate structure and a source structure connected to ground. The transistor M3 includes an n-channel region 1112A disposed in the p-well region 1159A directly below the transistor M2 M3 and includes a drain structure connected to the system voltage VOD and a source structure for transmitting the output signal OS of the pixel 1100A to the associated analog / digital converter through a metal pad or solder ball / bump 1106 in an arrangement similar to that shown and described in reference ​ It should be noted that the metal pad for OS may be located at a position away from the center of the pixel 1100A, and in one embodiment, may overlay portions of one or more adjacent pixels. 1100A In one embodiment, the reset transistor RT is controlled to discharge the floating diffusion FD to the reset voltage RD using a reset gate voltage RG that is positive enough to turn on the reset transistor RT. RD should be lower than the voltages applied to the various pixel gates (e.g., as described above with reference to

[0195] and ​ and 11BVoltage correction of the described resistive gate 1151 and summing gate 1153). For example, referring to ​ In the example shown in which the summing gate 1153 uses 10V control, the reset drain voltage RD can have a voltage value between approximately 15V and 20V. The reset transistor RT must be turned on periodically to discharge the electrons that have accumulated in the floating diffusion FD. When the incident electron current hitting the pixel is small, it may not be necessary to discharge (reset) the floating diffusion every time a pixel is read out. When the incident current is high, it may be necessary to reset the floating diffusion FD every pixel clock cycle.

[0196] ​ Figure 14 shows a partially simplified exemplary sensor 1400 arranged according to another embodiment of the present invention, and illustrates an alternative layout pattern, in which the p-well region 1459-1 of pixel 1440-1 extends into the space otherwise occupied by adjacent pixel 1440-2, and at least one control signal utilized by pixel 1440-1 is connected to signal line 1419-21 passing through adjacent pixel 1440-2. The p-well regions and signal lines discussed in this example are formed and function in a manner similar to the p-well region 1159 and signal line 1019 discussed in detail above with reference to ​ and 10A It should be noted that the metal wire bundles 1419-1 and 1419-2 extend over all other structures, are separated from the underlying polysilicon structures (e.g., resistive gate 1470-1 or resistive gate 1470-2) by a borophosphosilicate glass layer or other dielectric material, and are connected to the underlying structures through metal vias (not shown). It should also be noted that several structures of pixels 1440-1 and 1440-2 described above are omitted in ​ for clarity and brevity.

[0197] As mentioned above, the amorphous or polysilicon gate structure for generating the resistive gate (and any additional gates, such as the summing gate 1153 discussed above) in each pixel substantially completely covers the pixel area, except for the central region (i.e., allowing access to the floating diffusion) and the region in which the p-well is formed. In the examples described above with reference to ​ and 11B the p-well region 1159 is completely disposed within the square boundary of each pixel, so the resistive and summing gates completely extend around the remaining perimeter of pixel 1100. However, in some cases, the M3 amplifier transistor requires a width that extends beyond the lower pixel boundary.

[0198] To accommodate the extended M3 transistor shape, the pixels of sensor 1400 are configured to share portions of their space with neighboring pixels. Specifically, to provide space for both portions of its own elongated p-well regions 1459-1 and 1459-0 that extend downward from the pixels (not shown) above, the resistive gate structure 1470-1 of pixel 1440-1 is formed in a generally "H" shaped pattern. Similarly, the resistive gate structure 1470-2 of pixel 1440-2 is formed in the same "H" shaped pattern to accommodate the lower portion of p-well 1459-1 and the upper portion of p-well region 1459-2.

[0199] As discussed above, the pixels in each row of sensor 1400 share common signal lines that extend along the entire row to a peripheral located control circuit (not shown). In ​ the case shown, signal harness 1419-1 extends above the row containing pixel 1440-1, and signal harness 1419-2 extends above the row containing pixel 1440-2. Since the p-well regions extend into neighboring pixels, in some cases it becomes effective to provide signal connections from signal harnesses that extend above neighboring pixels. For example, signal line 1419-21 is connected through conductor 1419-21A to a transistor structure (not shown) disposed in p-well region 1459-1, whereby a signal (e.g., 0V / ground) is provided from signal beam 1419-2 through neighboring pixel 1440-2 to pixel 1440-1. Similarly, signal line 1419-11 of signal beam 1419-1 provides a signal to a transistor structure (not shown) disposed in p-well region 1459-0.

[0200] ​ Also depicted are the preferred locations of solder bumps / balls 1406-1 and 1406-2 in pixels 1440-1 and 1440-2 (i.e., in the lower left quarter of each pixel area). It should be noted that the depicted sizes of solder bumps / balls 1406-1 and 1406-2 in pixels 1440-1 and 1440-2 are typically accurate for a 250μm nominal lateral (e.g., diagonal) pixel size and standard solder bumps / balls. In alternative embodiments with pixels of different sizes or different sized solder balls or bumps, the relative sizes of the pads and pixels can be significantly different from ​ that illustrated.

[0201] In an embodiment, the electronic detector described herein can also detect X-rays. If the X-rays emitted by a sample have sufficient energy (e.g., an energy of about 1 keV or higher), then the X-rays can generate sufficient electrons when absorbed in the electron sensor to be detected.

[0202] The systems and methods described herein can be used with any of the systems and methods described in the following patents: U.S. Published Patent Application 2014 / 0151552, titled "Tilt-Imaging Scanning Electron Microscope," filed Mar. 18, 2013, by Jiang et al.; U.S. Published Patent Application 2013 / 0341504, titled "Auger Elemental Identification Algorithm," filed Jun. 7, 2013, by Neill et al.; U.S. Published Patent Application 2011 / 0168886, titled "Charged-particle energy analyzer," filed Mar. 17, 2011, by Shadman et al.; and U.S. Published Patent Application 2010 / 0208979, titled "Use of design information and defect image information in defect classification," filed Feb. 16, 2009, by Abbott et al. All of these applications are incorporated herein by reference.

[0203] In one embodiment, the electron sensor pixel includes a boron layer disposed on a second surface of the epitaxial silicon layer. For example, in an embodiment where the floating diffusion (FD) is implemented by a VCVFD structure, the sensor may further include a boron coating (such as ​ and 11B the boron coating 1160 shown in ​ and 11B ), which may be important for electron detectors and for DUV, VUV, and EUV detectors. In another embodiment, the electron sensor pixel includes a beryllium coating disposed on a second surface of the epitaxial silicon layer to block most electrons from reaching the epitaxial silicon layer while allowing most X-rays to reach the layer. In additional embodiments, the electron sensor pixel includes a thin foil disposed in front of a second surface of the epitaxial silicon layer. For example, a beryllium coating or thin foil in front of the sensor (where "thin" may be defined in this context as being about 5 μm to 100 μm thick) will benefit the X-ray detector in blocking electrons. In some such embodiments,

[0204] The electronic sensor pixel, electronic sensor, and electron beam system embodiments described above can be further configured as described herein. For example, in one embodiment, the silicon layer is a silicon epitaxial layer. In one such embodiment, the silicon epitaxial layer comprises intrinsic or p-type doped silicon having a dopant concentration of less than 10 14 cm -3 .

[0205] In another embodiment of an electronic sensor pixel in which the floating diffusion (FD) is implemented as a VCVFD, the VCVFD source region and the n-type buried channel layer are doped with the same polarity, and the VCVFD source region has a dopant concentration equal to or higher than the dopant concentration in the n-type buried channel layer. In some embodiments, the VCVFD source region is connected to a charge reset structure. In additional embodiments, the VCVFD channel region and the n-type buried channel layer are doped with the same polarity. In additional embodiments, the silicon layer is a silicon epitaxial layer, and the p-type electron-sensitive layer has a dopant concentration that is at least ten times higher than the dopant concentration of the silicon epitaxial layer.

[0206] In some embodiments, the electronic sensor pixel is one of a plurality of electronic sensor pixels configured as a two-dimensional pixel array in an image sensor. This pixel array can be configured as shown in ​ , 6B and 6C, but instead of having a VCVFD located at one end of the pixel column, each pixel will contain its own VCVFD structure, as further described above.

[0207] [[ID=Id17]]In view of this description, those skilled in the art will appreciate further modifications and alternative embodiments of various aspects of the present invention. For example, an image sensor, a system including the image sensor, and a method for determining information about a sample are provided. Accordingly, this description should be construed only as illustrative and for the purpose of teaching those skilled in the art the general manner of carrying out the present invention. It is to be understood that the forms of the present invention shown and described herein are to be taken as the presently preferred embodiments. As will be apparent to those skilled in the art after benefiting from this description of the present invention, elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the present invention may be utilized independently. Changes may be made to the elements described herein without departing from the spirit and scope of the present invention as described in the appended claims.

Claims

1. An image sensor, comprising: a silicon layer configured to generate electron-hole pairs when light is incident on a photosensitive region of the silicon layer; a circuit formed on a first side of the silicon layer, wherein the circuit includes a channel and a first gate electrode configured to control electron accumulation in the channel in response to generation of the electron-hole pairs; and a sense node electrically connected to the circuit, formed on the first side of the silicon layer adjacent to the circuit and outside the photosensitive region, and formed of a voltage-controlled variable floating diffusion (VCVFD) structure, wherein the VCVFD structure includes: a source region and a channel region, wherein the source region of the VCVFD structure is connected to the channel of the circuit and an output circuit of the image sensor; and a second gate electrode adjacent to the source region and configured to control a variable capacitance of the VCVFD structure via a voltage applied to the second gate electrode through an electrical connection to the second gate electrode, wherein the VCVFD structure is configured to convert a charge responsive to the electron accumulation into a voltage proportional to the amount of the charge and depending on the variable capacitance, and wherein the output circuit is configured to generate an output in response to the voltage output by the VCVFD structure.

2. The sensor according to claim 1, wherein the image sensor is configured as a charge-coupled device.

3. The sensor according to claim 1, wherein the image sensor is configured as a backside-illuminated charge-coupled device.

4. The sensor according to claim 1, wherein the image sensor is configured as a charge-coupled device configured to function as a time-delay integration sensor.

5. The sensor according to claim 1, wherein the circuit is configured as a charge-coupled device circuit.

6. The sensor according to claim 1, wherein the circuit is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET).

7. The sensor according to claim 1, wherein the silicon layer is a silicon epitaxial layer.

8. The sensor of claim 1 , wherein the silicon layer is a silicon epitaxial layer, and wherein the silicon epitaxial layer comprises a silicon epitaxial layer having a thickness of less than 10 14 cm -3 The dopant concentration of intrinsically or p-type doped silicon.

9. The sensor according to claim 1, wherein the channel of the circuit includes an n-type doped buried channel.

10. The sensor according to claim 1, wherein the source region of the VCVFD structure and the channel of the circuit are doped with the same polarity, and wherein the source region of the VCVFD structure has a dopant concentration equal to or higher than that in the channel of the circuit.

11. The sensor according to claim 1, wherein the source region of the VCVFD structure is further connected to a charge reset structure in the image sensor.

12. The sensor according to claim 1, wherein the channel region of the VCVFD structure and the channel of the circuit are doped with the same polarity.

13. The sensor according to claim 1, wherein the silicon layer is an epitaxial silicon layer, wherein the image sensor further comprises a thin p-type layer having a dopant concentration that is at least ten times higher than the dopant concentration of the epitaxial silicon layer, and wherein the thin p-type layer is disposed on a second side of the epitaxial silicon layer opposite to the first side.

14. The sensor according to claim 1, wherein the image sensor further comprises an anti-reflection layer disposed on a second side of the silicon layer opposite to the first side.

15. The sensor according to claim 1, wherein the circuit is configured as a two-dimensional pixel array.

16. The sensor according to claim 1, wherein the circuit is configured to include a plurality of pixel columns including at least a first and a second pixel column, wherein the at least first and second pixel columns each include one or more pixels, wherein the sensing node is one of a plurality of sensing nodes in the image sensor, wherein the plurality of sensing nodes includes at least a first and a second sensing node, and wherein the first and second sensing nodes are electrically connected to all of the one or more pixels in the first and second pixel columns, respectively.

17. The sensor according to claim 1, wherein the circuit is configured to include a plurality of pixel columns including at least a first and a second pixel column, wherein the at least first and second pixel columns each include one or more pixels, and wherein the sensing node is electrically connected to the one or more pixels in the first and second pixel columns.

18. The sensor according to claim 1, wherein the channel region of the VCVFD structure is configured as an n-type buried channel.

19. The sensor according to claim 1, wherein the channel region of the VCVFD structure is configured as an n-type surface channel.

20. The sensor according to claim 1, wherein the VCVFD structure further comprises a drain region connected to the channel region of the VCVFD structure, and wherein the source region and the drain region of the VCVFD structure are electrically connected.

21. The sensor according to claim 1, wherein the circuit is configured to include pixels including at least a first and a second pixel, wherein the sensing node is electrically connected to the first and second pixels, and wherein the image sensor or the computer subsystem is configured to calibrate the sensing node, thereby calibrating the first and second pixels.

22. The sensor according to claim 1, wherein the image sensor is positioned in an inspection system such that the light incident on the photosensitive region is light from a sample inspected by the inspection system, and wherein the inspection system is configured to detect a defect on the sample based on the output generated by the output circuit of the image sensor.

23. A system configured to determine information about a sample, comprising: An illumination subsystem configured to direct light generated by a light source onto the sample; An image sensor positioned in a path of light from the sample and comprising: A silicon layer configured to generate electron-hole pairs when the light from the sample is incident on a photosensitive region of the silicon layer; A circuit formed on a first side of the silicon layer, wherein the circuit includes a channel and a first gate electrode configured to control electron accumulation in the channel in response to the generation of electron-hole pairs; and A sense node electrically connected to the circuit, formed on the first side of the silicon layer adjacent to the circuit and outside the photosensitive region, and formed by a voltage-controlled variable floating diffusion (VCVFD) structure, wherein the VCVFD structure includes: A source region and a channel region, wherein the source region of the VCVFD structure is connected to the channel of the circuit and the output circuit of the image sensor; and A second gate electrode adjacent to the source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the second gate electrode through an electrical connection to the second gate electrode, wherein the VCVFD structure is configured to convert the charge in response to the electron accumulation into a voltage proportional to the amount of the charge and depending on the variable capacitance, and wherein the output circuit is configured to generate an output in response to the voltage output by the VCVFD structure; and A computer subsystem configured to determine information about the sample based on the output.

24. The system according to claim 23, wherein the system is further configured as an inspection system, and wherein the information about the sample includes information about defects detected on the sample based on the output.

25. An electronic sensor pixel, comprising: A silicon layer including: An n-type buried channel layer forming a first surface of the silicon layer; A p-type electron-sensitive layer disposed between the buried channel layer and a relative second surface of the silicon layer; And A floating diffusion disposed in the buried channel layer adjacent to a central region of the pixel, wherein the floating diffusion includes a sense node formed by a voltage-controlled variable floating diffusion (VCVFD) structure, wherein the VCVFD structure includes: A VCVFD source region and a VCVFD channel region, wherein the VCVFD source region is connected to the channel of the pixel and the output circuit of the pixel; and A VCVFD gate electrode adjacent to the VCVFD source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the VCVFD gate electrode through an electrical connection to the VCVFD gate electrode, wherein the VCVFD structure is configured to convert the charge in response to electrons moving towards the floating diffusion in the n-type buried channel layer into a voltage proportional to the amount of the charge and depending on the variable capacitance; and A resistive gate including at least one gate structure disposed above the first surface and configured such that an outer peripheral edge of the gate structure is substantially aligned with an outer peripheral edge of the buried channel layer, the gate structure defining a central opening such that an inner peripheral edge of the gate structure substantially surrounds the central region and is spaced from the central region, wherein the buried channel layer and the p-type electron-sensitive layer are configured such that the p-type electron-sensitive layer generates a plurality of electrons in response to each incident electron or X-ray photon, and such that the plurality of generated electrons are driven into the buried channel layer, and wherein the resistive gate is configured such that when a reduced potential difference is applied between the inner peripheral edge and the outer peripheral edge of the gate structure, the resistive gate generates a first electric field that causes electrons in the n-type buried channel layer to move toward the floating diffusion.

26. The electronic sensor pixel according to claim 25, further comprising a boron layer disposed on the second surface of the epitaxial silicon layer.

27. The electronic sensor pixel according to claim 25, further comprising a beryllium coating disposed on the second surface of the epitaxial silicon layer.

28. The electronic sensor pixel according to claim 25, further comprising a thin foil disposed in front of the second surface of the epitaxial silicon layer.

29. The electronic sensor pixel according to claim 25, wherein the silicon layer is a silicon epitaxial layer.

30. The electronic sensor pixel according to claim 25, wherein the silicon layer is a silicon epitaxial layer, and wherein the silicon epitaxial layer comprises intrinsic or p-type doped silicon having a dopant concentration of less than 10 14 cm -3 .

31. The electronic sensor pixel according to claim 25, wherein the VCVFD source region and the n-type buried channel layer are doped with the same polarity, and wherein the VCVFD source region has a dopant concentration equal to or higher than the dopant concentration in the n-type buried channel layer.

32. The electronic sensor pixel according to claim 25, wherein the VCVFD source region is further connected to a charge reset structure.

33. The electronic sensor pixel according to claim 25, wherein the VCVFD channel region and the n-type buried channel layer are doped with the same polarity.

34. The electronic sensor pixel according to claim 25, wherein the silicon layer is a silicon epitaxial layer, and wherein the p-type electron-sensitive layer has a dopant concentration that is at least ten times higher than the dopant concentration of the silicon epitaxial layer.

35. The electronic sensor pixel according to claim 25, wherein the electronic sensor pixel is one of a plurality of electronic sensor pixels configured as a two-dimensional pixel array in an image sensor.

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