FPGA-based RBF neural network PID parameter setting method

Abstract

The invention provides an FPGA (Field Programmable Gate Array)-based RBF (Radial Basis Function) neural network PID (Proportion Integration Differentiation) parameter setting method, and relates to the field of intelligent control and FPGA embedded systems. A three-level assembly line structure design is adopted, an input layer collects error signals and differential of the error signals in real time, a hidden layer constructs six Gaussian kernel functions to calculate nonlinear mapping in parallel, and an output layer generates PID parameters through linear combination. The method is realized based on a Xilinx Zynq7020 development board, and a radial basis function of a hidden layer is calculated through a Taylor expansion. The problems that a traditional PID controller is fixed in parameter, good in local control effect and poor in overall control effect are solved, and self-adaptive adjustment of PID parameters is achieved through the RBF neural network. And the FPGA adopts a parallel processing mechanism, so that the calculation speed and the response speed are high, the flexibility is high, and the calculation operation speed of the neural network can be remarkably improved. The method can be widely applied to various industrial scenes needing accurate control, such as motor control and temperature control, and has practical reference significance for industrial process control.

Description

Technical Field

[0001] The invention belongs to the field of intelligent control and FPGA embedded systems, and particularly relates to a RBF neural network PID parameter tuning method based on FPGA. Background Art

[0002] PID Control Limitations Traditional PID controllers face challenges in parameter tuning and slow dynamic response in nonlinear, time-varying systems. Although neural network-based PID control methods have been proposed, existing solutions are mostly based on software simulation or general-purpose processor implementations, making them difficult to meet the real-time requirements of industrial scenarios.

[0003] FPGA Technology Advantages FPGA has the characteristics of parallel computing, low latency and hardware reconfiguration, and its efficiency has been verified in fields such as neural network acceleration, real-time signal processing and industrial control. Summary of the Invention

[0004] The purpose of the present invention is to propose a PID parameter tuning method based on RBF neural network of FPGA, and to deploy RBF neural network on FPGA using Verilog language to realize adaptive optimization of control system. It is implemented based on Xilinx Zynq platform, and the radial basis function of the hidden layer is calculated by Taylor expansion. Simulation experiments show that the deployment of RBF neural network is accurate and effective, which verifies the significant advantages of FPGA hardware acceleration in dynamic parameter tuning. The present invention solves the problem that the parameters of traditional PID controller are fixed, the local control effect is good, but the overall control effect is poor, and the adaptive adjustment of PID parameters is realized through RBF neural network. This design of multi-module collaborative work not only improves the computing efficiency, but also ensures the accuracy of the calculation, so that the hidden layer can quickly and accurately complete complex nonlinear mapping tasks.

[0005] To achieve the above objectives, the present invention adopts the following technical solutions and implementation steps: This system implements FPGA-based deployment of the RBF-PID neural network algorithm. It employs a three-stage pipeline design: the input layer acquires the error signal (e(k)) and its derivative (Δe(k)) in real time. The hidden layer constructs six Gaussian kernel functions to parallelly compute nonlinear mappings. The output layer generates PID parameters (Kp, Ki, Kd) through linear combination. Implemented on the Xilinx Zynq platform, the system uses Taylor expansion to fit the radial basis functions of the hidden layer and deploys them to the FPGA. The specific process includes the following steps: Step 1: Setting up the input layer. The specific process is as follows: 1-1: Input signal buffer Register the actual value and set value of the input to ensure the stability and synchronization of the data and prepare for subsequent error calculation; 1-2: Error calculation Calculate the error between the set value and the actual value in real time, that is, the error value at the current moment; 1-3: Error change rate calculation Calculate the rate of change of the error, that is, the difference between the error values at two adjacent moments, to reflect the dynamic changes of the error; 1-4: Enable signal processing By delaying the received enable signal, the module's output enable signal is generated to control the output timing of the data and ensure that the data is received by the subsequent module at the appropriate time.

[0006] Step 2: Setting up the exponential calculation preprocessing module mainly involves preprocessing the input error signal and error change rate signal, and calculating the exponential part of the radial basis function as shown in formula (1). The specific process includes the following submodules: in, is the radial basis function, , Is a one-dimensional vector representing the input of the two RBF networks, which are the error signal e(k) and its differential Δe(k), is the center value of the radial basis function, is the width of the radial basis function; 2-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 2-2: Error offset calculation When the input enable signal is valid, the difference between the error signal and the center value C in the radial basis function, as well as the difference between the error change rate and the center value C are calculated respectively; 2-3: Square calculation and denominator calculation When the enable delay signal is valid, the square values of the two differences in step 2-2 are calculated respectively and stored in the corresponding registers respectively; at the same time, the square of parameter b is calculated and multiplied by 2, and then the result is stored in the register. This value is used as the denominator of the subsequent division operation; 2-4: Molecular Computing When the delay signal of the enable signal is valid, the result of adding the square values of the two differences calculated in steps 2-3 is stored in the register, and this value is used as the numerator of the subsequent division; 2-5: Fast division calculation module, calculates the quotient and remainder of a given dividend and divisor. The submodules are as follows: 2-5-1: Status Definition Multiple states are defined to control the process of division operation, including idle (S0), shift (S1), judgment (S2), expansion (S3), calculation (S4), update (S5), error (S6) and success (S7); 2-5-2: Find the most significant bit function Define a function to find the most significant bit, which is used to find the position of the most significant bit of the given data. This is very important for determining the bit width of the data and performing unique operations. 2-5-3: Determine data distance function Define a data distance judgment function to determine the displacement distance between two data. This function determines the number of bits that need to be shifted by comparing the most significant bits of the two data. 2-5-4: Register initialization Initialize each register, including the dividend register, divisor register, divisor holding register, remainder register, shift register, judgment flag register, and quotient register; 2-5-5: State Machine Control Use a finite state machine to control the flow of division operations. The state machine determines the next state based on the current state and the judgment flag; In the idle state (S0), if the start division signal is valid, it enters the shift state (S1); In the shift state (S1), the displacement distance between the dividend and the divisor is calculated; In the judgment state (S2), the process decides to enter the error state (S6), success state (S7) or extension state (S3) according to the conditions such as whether the divisor is 0 or whether the dividend is less than the divisor. In the extended state (S3), the divisor is shifted left to expand the position; In the calculation state (S4), the remainder of the dividend minus the divisor is calculated; In the update state (S5), the values of the dividend and divisor are updated, and the quotient is accumulated; 2-5-6: Division operation execution If the division start signal is valid and the current state is idle, the dividend and divisor are stored in the corresponding registers respectively, and the displacement distance is calculated; according to the next state of the state machine, the corresponding operations are performed, including shifting, judging, expanding, calculating the remainder and updating the quotient; 2-5-7: Output results According to the current state of the state machine, the quotient, remainder, division completion signal and error flag are output; in the error state (S6), the error flag is output and the quotient and remainder are cleared; in the success state (S7), the quotient and remainder are output and the division completion signal is set; 2-6: Index result calculation The quotient's two's complement is inverted and added with 1, and then stored in the corresponding exponential result intermediate variable. The purpose is to make this value negative, because there is a minus sign in front of the radial basis function exponential part. 2-7: Index result output When the output enable signal is valid, the six exponential result intermediate variables are assigned to the six output exponential results respectively.

[0007] Step 3: Setting up the exponential judgment preprocessing module. The main function of this module is to judge the exponent output by the exponential calculation preprocessing module and provide the subsequent Taylor expansion module with the exponential value of the nearest expansion point and the required point. The specific process includes the following submodules: 3-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 3-2: Exponent negation The exponential result of the input is inverted and stored in the register. Because the exponential part of the radial basis function is negative, it is a positive value after inversion, which is convenient for subsequent calculations. 3-3: Determine the nearest expansion point The value obtained by adding one to the upper four bits of the exponential result in the register in step 3-2 is used to determine the nearest expansion point, and the corresponding expansion point exponent value is stored in the register. This step is to determine the vicinity of a predefined expansion point for Taylor expansion calculation, so as to improve calculation accuracy and efficiency. 3-4: Calculate the offset Subtract 4095 (4095 corresponds to all 1s in binary 12 bits) from the lower 12 bits of the exponent result of the register in step 3-2. The value of this register represents the offset of the point to be calculated relative to the nearest expansion point and is used for subsequent Taylor expansion calculations. The offset here is between 0 and 1. 3-5: Output enable signal control When the delay signal of the enable signal is valid, an output enable signal is generated to control the timing of the module output, which facilitates further processing by the subsequent Taylor expansion module. Step 4: Setting up the Taylor expansion module. This module uses the Taylor series expansion to calculate the approximate value of the exponential function based on the expansion value and offset provided by the exponential judgment preprocessing module. The specific process includes the following submodules: 4-1: Enable signal delay processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 4-2: Index value storage Store the input exponent value in the register to ensure that the exponent value used in subsequent calculations is the latest; 4-3: Initialize Taylor expansion calculation Set the initial term of Taylor expansion to 4095, because 4095 corresponds to all 12 bits in binary; 4-4: Calculations of Taylor expansion The calculation of the first to seventh terms of the Taylor expansion is completed through addition, multiplication and shift operations. Because the offset is between 0 and 1, the expansion is chosen at zero point; 4-5: Final result calculation Input the final calculation result into the register to obtain the final Taylor expansion approximation; 4-6: Output enable signal control When the delayed signal of the enable signal is valid, the output enable signal becomes valid, ensuring that the final result is stable and is output to the subsequent module for further processing at the appropriate time point.

[0008] Step 5: Set up the hidden layer output module. This module post-processes the exponential function approximation calculated by the Taylor expansion module and combines it with the exponential value of the nearest expansion point to obtain the final exponential calculation result. The specific process includes the following submodules: 5-1: Enable signal registration Put the input enable signal into the register. This step is used to synchronize the subsequent calculation process to ensure that data processing is performed within the time period when the enable signal is valid. 5-2: Calculation of intermediate results When the input enable signal is valid, the exponential value of the input nearest expansion point is multiplied by the Taylor expansion calculation result, and the result is stored in the register to obtain the complete exponential calculation result; 5-3: Final result output and enable signal control Shift the result in the register in step 5-2 right by 12 bits to output the final exponential calculation result, and adjust the numerical precision back to Q12: At the same time, set the output enable signal to ensure that the valid exponential calculation result is output only during the time period when the enable signal is valid, avoiding erroneous data transmission.

[0009] Step 6: Set up the output layer module. This module performs weighted summation on the six intermediate results calculated by the hidden layer, limits the summation result, and finally outputs the PID control parameters (Kp, Ki, Kd). Specifically, it consists of the following submodules: 6-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 6-2: Weighted Calculation When the input enable signal is valid, the six intermediate results of the input are multiplied by the corresponding weight parameters to obtain six weighted values; 6-3: Intermediate sum calculation When the delayed signal of the enable signal is valid, the first three weighted values are added together, and the last three weighted values are added together, in order to simplify the subsequent sum calculation.

[0010] 6-4: Total calculation and limit processing When the delay signal of the enable signal is valid, the two values in step 6-3 are added together to obtain the sum, and the amplitude is limited to ensure that the output value is within a reasonable range to prevent excessive or insufficient values from affecting the stability of the control system. 6-5: Result output and enable signal control The value in step 6-4 is shifted right by 12 bits as the final output value in order to adjust the numerical precision to Q12; at the same time, the output enable signal is set to ensure that valid results are output only during the period when the enable signal is valid.

[0011] The beneficial effects of the present invention are: (1) This invention utilizes a full FPGA architecture, fully leveraging the FPGA's parallel computing advantages. Through a three-stage pipeline design—the input layer acquires the error signal and its derivative in real time, the hidden layer computes radial basis functions in parallel, and the output layer linearly combines and generates PID parameters—this significantly improves the real-time performance and efficiency of PID parameter tuning.

[0012] (2) In implementing the hidden layer, the present invention employs a unique four-level modular design: an exponential calculation preprocessing module, an exponential judgment preprocessing module, a Taylor expansion module, and a hidden layer output module. This modular design not only improves computational efficiency but also enables precise calculation of exponential functions through Taylor expansion, avoiding the inaccuracy associated with traditional table lookup methods.

[0013] (3) The output layer of the present invention can generate PID parameters in real time based on the calculation results of the hidden layer and has adaptive adjustment capabilities. Through a feedback mechanism, the system can dynamically optimize the PID parameters output by the RBF neural network based on the control effect, thereby improving the control effect. This mechanism greatly improves the adaptability and robustness of the control system, enabling it to better cope with complex and changing industrial environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the RBF neural network structure based on FPGA; Figure 2 This is the overall simulation diagram of the RBF neural network input layer module based on FPGA; Figure 3This is a simulation diagram of the parameter verification of the RBF neural network input layer module based on FPGA; Figure 4 This is a simulation diagram of the RBF neural network hidden layer module index calculation based on FPGA; Figure 5 This is the simulation result diagram of radial basis output of hidden layer module of RBF neural network based on FPGA; Figure 6 This is a simulation diagram of the parameter input of the RBF neural network output layer module based on FPGA; Figure 7 This is a simulation diagram of the parameter output of the RBF neural network output layer module based on FPGA; Figure 8 This is the resource usage diagram of RBF neural network deployment implemented on FPGA; Figure 9 It is a flow chart of the present invention. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and key points of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and implementation examples. It should be understood that the specific implementation examples described herein are only used to explain the present invention and are not intended to limit the present invention.

[0016] This system implements an FPGA-based RBF-PID neural network algorithm. It employs a three-stage pipeline design: the input layer acquires the error signal (e(k)) and its derivative (Δe(k)) in real time. The hidden layer constructs six Gaussian kernel functions to parallelly compute nonlinear mappings. The output layer generates PID parameters (Kp, Ki, Kd) through linear combination. Implemented on the Xilinx Zynq platform, the system uses Taylor expansion to fit the radial basis functions of the hidden layer and deploys them to the FPGA. Figure 1 This is a schematic diagram of the FPGA-based RBF neural network structure, showing the structure and parameters of the deployed RBF neural network.

[0017] The system is implemented as follows: Step 1: Setting up the input layer. The specific process is as follows: 1-1: Input signal buffer Register the actual value and set value of the input to ensure the stability and synchronization of the data and prepare for subsequent error calculation; 1-2: Error calculation Calculate the error between the set value and the actual value in real time, that is, the error value at the current moment; 1-3: Error change rate calculation Calculate the rate of change of the error, that is, the difference between the error values at two adjacent moments, to reflect the dynamic changes of the error; 1-4: Enable signal processing By delaying the received enable signal, the module's output enable signal is generated to control the output timing of the data and ensure that the data is received by the subsequent module at the appropriate time point; according to Figure 2 and Figure 3 The simulation results of the input layer of the RBF neural network in the simulation show that the set target speed is 1000 rpm. The actual output speed can be seen from the simulation diagram, which can achieve a relatively good tracking effect on the set speed. Figure 3 As can be seen in the figure, at the location where the yellow solid line marks the set speed, the actual speed is 1013 rpm, and the error is the set value minus the actual value -13. The error output calculation at the current moment is correct. The error at the previous moment was 2, so the rate of change of the error at the current moment is -15, and the output is also correct. Therefore, the deployed RBF is correctly extended into the network input layer.

[0018] Step 2: Setting up the exponential calculation preprocessing module mainly involves preprocessing the input error signal and error change rate signal, and calculating the exponential part of the radial basis function as shown in formula (1). The specific process includes the following submodules: in, is the radial basis function, , Is a one-dimensional vector representing the input of the two RBF networks, which are the error signal e(k) and its differential Δe(k), is the center value of the radial basis function, is the width of the radial basis function; 2-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 2-2: Error offset calculation When the input enable signal is valid, the difference between the error signal and the center value C in the radial basis function, as well as the difference between the error change rate and the center value C are calculated respectively; 2-3: Square calculation and denominator calculation When the enable delay signal is valid, the square values of the two differences in step 2-2 are calculated respectively and stored in the corresponding registers respectively; at the same time, the square of parameter b is calculated and multiplied by 2, and then the result is stored in the register. This value is used as the denominator of the subsequent division operation; 2-4: Molecular Computing When the delay signal of the enable signal is valid, the result of adding the square values of the two differences calculated in steps 2-3 is stored in the register, and this value is used as the numerator of the subsequent division; 2-5: Fast division calculation module, calculates the quotient and remainder of a given dividend and divisor. The submodules are as follows: 2-5-1: Status Definition Multiple states are defined to control the process of division operation, including idle (S0), shift (S1), judgment (S2), expansion (S3), calculation (S4), update (S5), error (S6) and success (S7); 2-5-2: Find the most significant bit function Define a function to find the most significant bit, which is used to find the position of the most significant bit of the given data. This is very important for determining the bit width of the data and performing unique operations. 2-5-3: Determine data distance function Define a data distance judgment function to determine the displacement distance between two data. This function determines the number of bits that need to be shifted by comparing the most significant bits of the two data. 2-5-4: Register initialization Initialize each register, including the dividend register, divisor register, divisor holding register, remainder register, shift register, judgment flag register, and quotient register; 2-5-5: State Machine Control Use a finite state machine to control the flow of division operations. The state machine determines the next state based on the current state and the judgment flag; In the idle state (S0), if the start division signal is valid, it enters the shift state (S1); In the shift state (S1), the displacement distance between the dividend and the divisor is calculated; In the judgment state (S2), the process decides to enter the error state (S6), success state (S7) or extension state (S3) according to the conditions such as whether the divisor is 0 or whether the dividend is less than the divisor. In the extended state (S3), the divisor is shifted left to expand the position; In the calculation state (S4), the remainder of the dividend minus the divisor is calculated; In the update state (S5), the values of the dividend and divisor are updated, and the quotient is accumulated; 2-5-6: Division operation execution If the division start signal is valid and the current state is idle, the dividend and divisor are stored in the corresponding registers respectively, and the displacement distance is calculated; according to the next state of the state machine, the corresponding operations are performed, including shifting, judging, expanding, calculating the remainder and updating the quotient; 2-5-7: Output results According to the current state of the state machine, the quotient, remainder, division completion signal and error flag are output; in the error state (S6), the error flag is output and the quotient and remainder are cleared; in the success state (S7), the quotient and remainder are output and the division completion signal is set; 2-6: Index result calculation The quotient's two's complement is inverted and added with 1, and then stored in the corresponding exponential result intermediate variable. The purpose is to make this value negative, because there is a minus sign in front of the radial basis function exponential part. 2-7: Index result output When the output enable signal is valid, the six exponential result intermediate variables are assigned to the six output exponential results respectively.

[0019] Step 3: Setting up the exponential judgment preprocessing module. The main function of this module is to judge the exponent output by the exponential calculation preprocessing module and provide the subsequent Taylor expansion module with the exponential value of the nearest expansion point and the required point. The specific process includes the following submodules: 3-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 3-2: Exponent negation The exponential result of the input is inverted and stored in the register. Because the exponential part of the radial basis function is negative, it is a positive value after inversion, which is convenient for subsequent calculations. 3-3: Determine the nearest expansion point The value obtained by adding one to the upper four bits of the exponential result in the register in step 3-2 is used to determine the nearest expansion point, and the corresponding expansion point exponent value is stored in the register. This step is to determine the vicinity of a predefined expansion point for Taylor expansion calculation, so as to improve calculation accuracy and efficiency. 3-4: Calculate the offset Subtract 4095 (4095 corresponds to all 1s in binary 12 bits) from the lower 12 bits of the exponent result of the register in step 3-2. The value of this register represents the offset of the point to be calculated relative to the nearest expansion point and is used for subsequent Taylor expansion calculations. The offset here is between 0 and 1. 3-5: Output enable signal control When the delay signal of the enable signal is valid, an output enable signal is generated to control the timing of the module output, which facilitates further processing by the subsequent Taylor expansion module. Step 4: Setting up the Taylor expansion module. This module uses the Taylor series expansion to calculate the approximate value of the exponential function based on the expansion value and offset provided by the exponential judgment preprocessing module. The specific process includes the following submodules: 4-1: Enable signal delay processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 4-2: Index value storage Store the input exponent value in the register to ensure that the exponent value used in subsequent calculations is the latest; 4-3: Initialize Taylor expansion calculation Set the initial term of Taylor expansion to 4095, because 4095 corresponds to all 12 bits in binary; 4-4: Calculations of Taylor expansion The calculation of the first to seventh terms of the Taylor expansion is completed through addition, multiplication and shift operations. Because the offset is between 0 and 1, the expansion is chosen at zero point; 4-5: Final result calculation Input the final calculation result into the register to obtain the final Taylor expansion approximation; 4-6: Output enable signal control When the delay signal of the enable signal is valid, the output enable signal becomes valid, ensuring that the final result is stable and is output to the subsequent module for further processing at the appropriate time point; Step 5: Set up the hidden layer output module. This module post-processes the exponential function approximation calculated by the Taylor expansion module and combines it with the exponential value of the nearest expansion point to obtain the final exponential calculation result. The specific process includes the following submodules: 5-1: Enable signal registration Put the input enable signal into the register. This step is used to synchronize the subsequent calculation process to ensure that data processing is performed within the time period when the enable signal is valid. 5-2: Calculation of intermediate results When the input enable signal is valid, the exponential value of the input nearest expansion point is multiplied by the Taylor expansion calculation result, and the result is stored in the register to obtain the complete exponential calculation result; 5-3: Final result output and enable signal control Shift the result in the register in step 5-2 right by 12 bits to output the final exponential calculation result, and adjust the numerical precision back to Q12: At the same time, set the output enable signal to ensure that the valid exponential calculation result is output only during the time period when the enable signal is valid, avoiding erroneous data transmission.

[0020] Figure 4 and Figure 5 is the simulation result of the hidden layer of the RBF neural network, Figure 4 The yellow solid line marks the location where expont is displayed as -544, which is the output of the exponential part of the radial basis function. Figure 5 The yellow solid line marks the position where result1 is the output of the first neuron in the hidden layer. There are a total of 6 neurons in the hidden layer. We only need to verify the correctness of one of them. So we choose the output of the first neuron. According to the error and error change rate at the current moment, the center values C11, C12 and the width b1, we can use a calculator to get the exponential calculation result at this time as -0.13285. Then, the Q12 precision used in the FPGA needs to be multiplied by 2 to the 12th power, and the result is -544.1536, which is the same as Figure 4 The simulation result output of the exponential is consistent; then the output of the first neuron of the radial basis function is calculated to be 0.875596421722, and then multiplied by 2 to the power of 12 to be 3586.44294337, which is consistent with Figure 5 Compared with the simulation results of result1, the error is very small, which proves that the deployment of the hidden layer of the RBF neural network is correct.

[0021] Step 6: Set up the output layer module. This module performs weighted summation on the six intermediate results calculated by the hidden layer, limits the summation result, and finally outputs the PID control parameters (Kp, Ki, Kd). Specifically, it consists of the following submodules: 6-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 6-2: Weighted Calculation When the input enable signal is valid, the six intermediate results of the input are multiplied by the corresponding weight parameters to obtain six weighted values; 6-3: Intermediate sum calculation When the delayed signal of the enable signal is valid, the first three weighted values are added together, and the last three weighted values are added together, in order to simplify the subsequent sum calculation.

[0022] 6-4: Total calculation and limit processing When the delay signal of the enable signal is valid, the two values in step 6-3 are added together to obtain the sum, and the amplitude is limited to ensure that the output value is within a reasonable range to prevent excessive or insufficient values from affecting the stability of the control system. 6-5: Result output and enable signal control Shift the value in step 6-4 right by 12 bits as the final output value to adjust the numerical precision to Q12; at the same time, set the output enable signal to ensure that valid results are output only when the enable signal is valid; Figure 6 and Figure 7The simulation result diagram of the output layer of the RBF neural network is shown in Figure 2. Since the output of RBF is the three parameters of PID and is obtained by the linear combination of the hidden layer output and the weight, only the relevant signal of parameter P is pulled out in the simulation diagram for verification. Figure 7 It can be seen that the outputs of the six radial basis functions of the hidden layer are 3832, 3832, 3782, 3782, 3782 and 3782 respectively. The six weights of the parameter P are 100, 100, 10, 100, 100 and 10 respectively. The value of P output in the simulation diagram is 390. Now we perform theoretical calculation verification. The linear addition of the hidden layer output and the weight is 1598440, which is then divided by 2 to the 12th power and converted to Q12 precision format as 390.244140625. It can be seen that the output layer deployment of the RBF neural network is correct. Figure 8 Resource usage diagram for FPGA implementation of RBF neural network deployment.

[0023] This invention presents a novel solution for PID parameter tuning using an RBF neural network based on an FPGA. Through rational system architecture design and efficient hardware implementation, this method offers a novel solution for PID parameter tuning. This method boasts fast computational speed, high accuracy, and strong adaptability, significantly improving control system performance and stability. It holds broad application prospects in industrial automation.

Claims

1. A RBF neural network PID parameter tuning method based on FPGA, characterized in that: The steps include: A three-stage pipeline structure is adopted: the input layer collects the error signal e(k) and its differential Δe(k) in real time, the hidden layer constructs a Gaussian kernel function to parallelly calculate the nonlinear mapping, and the output layer generates PID parameters through linear combination. Based on the Xilinx Zyn7020 platform, the radial basis function of the hidden layer is fitted by Taylor expansion and deployed in the FPGA.

2. The FPGA-based RBF neural network PID parameter tuning method according to claim 1, wherein: There are two input layers, namely error and rate of change of error.

3. The RBF neural network PID parameter tuning method based on FPGA according to claim 1, characterized in that: The number of neurons in the hidden layer is 6, which is used to realize the calculation of RBF radial basis function. The hidden layer includes four modules: exponential calculation preprocessing module, exponential judgment preprocessing module, Taylor expansion module and hidden layer output module; The exponential calculation preprocessing module is used to perform preliminary processing of exponential operations on the input data. The exponential judgment preprocessing module judges the size range of the exponential part based on the data output by the exponential calculation preprocessing module, determines the most recently expanded data and the specific expansion position that needs to be calculated; the Taylor expansion module will perform precise Taylor expansion calculation on the radial basis function to obtain accurate nonlinear mapping results; finally, the final output result of the radial basis function is calculated through the hidden layer output module.

4. The RBF neural network PID parameter tuning method based on FPGA according to claim 1, characterized in that: There are three output layers, which are the three parameters of PID: Kp, Ki, and Kd. The output layer generates the final PID parameters through linear combination according to the calculation results of the hidden layer.

5. A RBF neural network PID parameter tuning method based on FPGA according to any one of claims 1 to 4, characterized in that: The input layer is set up as follows: 1-1: Input signal buffer Register the actual value and set value of the input; 1-2: Error calculation Calculate the error between the set value and the actual value in real time, that is, the error value at the current moment; 1-3: Error change rate calculation Calculate the rate of change of the error, that is, the difference between the error values at two adjacent moments, to reflect the dynamic changes of the error; 1-4: Enable signal processing By delaying the received enable signal, the module's output enable signal is generated to control the output timing of the data and ensure that the data is received by the subsequent module at the appropriate time.

6. The FPGA-based RBF neural network PID parameter tuning method according to claim 5, characterized in that: The exponential calculation preprocessing module is set up as follows: preprocess the input error signal and error change rate signal, and calculate the exponential part of the radial basis function as shown in formula (1): in, is the radial basis function, , Is a one-dimensional vector representing the input of the two RBF networks, which are the error signal e(k) and its differential Δe(k), is the center value of the radial basis function, is the width of the radial basis function; 2-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 2-2: Error offset calculation When the input enable signal is valid, the difference between the error signal and the center value C in the radial basis function, as well as the difference between the error change rate and the center value C are calculated respectively; 2-3: Square calculation and denominator calculation When the enable delay signal is valid, the square values of the two differences in step 2-2 are calculated respectively and stored in the corresponding registers respectively; at the same time, the square of parameter b is calculated and multiplied by 2, and then the result is stored in the register. This value is used as the denominator of the subsequent division operation; 2-4: Molecular Computing When the delay signal of the enable signal is valid, the result of adding the square values of the two differences calculated in steps 2-3 is stored in the register, and this value is used as the numerator of the subsequent division; 2-5: Fast division calculation module, calculates the quotient and remainder of a given dividend and divisor. The submodules are as follows: 2-5-1: Status Definition Define multiple states to control the process of division operation, including idle (S0), shift (S1), judgment (S2), expansion (S3), calculation (S4), update (S5), error (S6) and success (S7); 2-5-2: Find the most significant bit function Define a function to find the most significant bit, which is used to find the position of the most significant bit of the given data; 2-5-3: Determine data distance function Define a data distance judgment function to determine the displacement distance between two data. This function determines the number of bits that need to be shifted by comparing the most significant bits of the two data. 2-5-4: Register initialization Initialize each register, including the dividend register, divisor register, divisor holding register, remainder register, shift register, judgment flag register, and quotient register; 2-5-5: State Machine Control Use a finite state machine to control the process of division operation. The state machine determines the next state based on the current state and the judgment flag. In the idle state (S0), if the start division signal is valid, it enters the shift state (S1); In the shift state (S1), the displacement distance between the dividend and the divisor is calculated; In the judgment state (S2), the process decides to enter the error state (S6), success state (S7) or extension state (S3) according to the conditions such as whether the divisor is 0 or whether the dividend is less than the divisor. In the extended state (S3), the divisor is shifted left to expand the position; In the calculation state (S4), the remainder of the dividend minus the divisor is calculated; In the update state (S5), the values of the dividend and divisor are updated, and the quotient is accumulated; 2-5-6: Division operation execution If the division start signal is valid and the current state is idle, the dividend and divisor are stored in the corresponding registers respectively, and the displacement distance is calculated; according to the next state of the state machine, the corresponding operations are performed, including shifting, judging, expanding, calculating the remainder and updating the quotient; 2-5-7: Output results According to the current state of the state machine, the quotient, remainder, division completion signal and error flag are output; in the error state (S6), the error flag is output and the quotient and remainder are cleared; in the success state (S7), the quotient and remainder are output and the division completion signal is set; 2-6: Index result calculation Take the complement of the quotient and add 1 to it, then store it in the corresponding exponential result intermediate variable to make this value negative; 2-7: Index result output When the output enable signal is valid, the six exponential result intermediate variables are assigned to the six output exponential results respectively.

7. The FPGA-based RBF neural network PID parameter tuning method according to claim 6, characterized in that: The setting method of the index judgment preprocessing module is as follows: 3-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 3-2: Exponent negation The input exponential result is inverted and stored in the register; 3-3: Determine the nearest expansion point The value obtained by adding one to the upper four bits of the exponent result in the register in step 3-2 is used to determine the nearest expansion point, and the corresponding expansion point exponent value is stored in the register; 3-4: Calculate the offset Subtract 4095 from the lower 12 bits of the exponent result of the register in step 3-2, and store the result in the register. The value of this register represents the offset of the point to be calculated relative to the nearest expansion point, which is used for subsequent Taylor expansion calculations. The offset here is between 0 and 1. 3-5: Output enable signal control When the delay signal of the enable signal is valid, an output enable signal is generated to control the timing of module output.

8. The RBF neural network PID parameter tuning method based on FPGA according to claim 7, characterized in that: The Taylor expansion module is set up as follows: 4-1: Enable signal delay processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 4-2: Index value storage Store the input exponent value in the register; 4-3: Initialize Taylor expansion calculation Set the initial term of Taylor expansion to 4095; 4-4: Calculations of Taylor expansion The calculation of the first to seventh terms of Taylor expansion is completed through addition, multiplication and shift operations, and the expansion is selected at zero point; 4-5: Final result calculation Input the final calculation result into the register to obtain the final Taylor expansion approximation; 4-6: Output enable signal control When the delayed version of the enable signal is valid, the output enable signal becomes valid.

9. The FPGA-based RBF neural network PID parameter tuning method according to claim 8, characterized in that: The setting method of the hidden layer output module is as follows: 5-1: Enable signal registration Put the input enable signal into the register; 5-2: Calculation of intermediate results When the input enable signal is valid, the exponential value of the input nearest expansion point is multiplied by the Taylor expansion calculation result, and the result is stored in the register to obtain the complete exponential calculation result; 5-3: Final result output and enable signal control Shift the result in the register in step 5-2 right by 12 bits to output the final exponential calculation result, and adjust the numerical precision back to Q12: At the same time, set the output enable signal to ensure that the valid exponential calculation result is output only during the time period when the enable signal is valid.

10. The RBF neural network PID parameter tuning method based on FPGA according to claim 9, characterized in that: The output layer module is set up as follows: 6-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 6-2: Weighted Calculation When the input enable signal is valid, the six intermediate results of the input are multiplied by the corresponding weight parameters to obtain six weighted values; 6-3: Intermediate sum calculation When the delayed signal of the enable signal is valid, the first three weighted values are added together, and the last three weighted values are added together; 6-4: Sum calculation and limit processing When the delayed signal of the enable signal is valid, the two values in step 6-3 are added together to obtain a sum, and a limiting process is performed; 6-5: Result output and enable signal control Shift the value in step 6-4 right by 12 bits as the final output value, adjust the precision of the value to Q12; and set the output enable signal at the same time.

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