Data reading method and memory controller

Abstract

The invention provides a data reading method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a first reading instruction which does not contain a target memory address pointer from a host system; reading the target data from the memory module during the preparation of the target memory space by the host; after obtaining the target data, sending a data ready notification to the host system to request a target memory space; when the target memory space is ready, obtaining a second reading instruction containing a target memory address pointer; and transmitting the target data to the host system according to the target memory address pointer. By changing the data reading process of a traditional NVMe protocol, parallel processing of host memory allocation and read data preparation is achieved, the reading performance of the storage device under the condition that the host memory is insufficient is effectively improved, meanwhile, the memory requirement of a host system is obviously reduced, and the memory pressure of the host system is relieved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of storage devices, and in particular to a data reading method and a memory controller, which are applied to NVMe (Non-Volatile Memory Express) devices such as SSDs (Solid State Drives) configured with flash memory, and are used to improve the reading performance of NVMe devices when the host memory is tight. Background Art

[0002] With the development of computer technology, solid-state drives (SSDs) have become widely used due to their high read and write speeds. NVMe (Non-Volatile Memory Express) is a high-performance storage protocol designed specifically for SSDs and is widely used in modern computer systems.

[0003] According to the NVMe protocol, the host needs to allocate memory before issuing a read command. For example, when a read command requires reading 1MB of data, the host needs to allocate 1MB of memory space in advance. If the host is short of memory, it will need to wait for memory to be released until there is enough free memory before sending a read command. When sending a read command, the host will include a PRP (Physical Region Page) pointer in the command to point to the previously allocated memory. Subsequent data read from the flash memory will be transferred to the memory area pointed to by the PRP.

[0004] When the host sets a large queue depth, it must wait for the corresponding amount of free memory to be released at once before sending a read command. This mechanism of waiting for the host's memory to be released before issuing a read command can significantly affect the device's read performance, especially when the host's memory resources are limited. Summary of the Invention

[0005] In light of this, the present disclosure provides a data writing method and memory controller. This method allows a host system to issue a read command to a storage device without first preparing the corresponding memory. While the host is preparing the corresponding memory, the storage device can simultaneously read the corresponding data and notify the host system. Once the memory is ready, the read data can be transmitted to the host system. This method aims to address the prior art technical problem of limited read performance, where the host must wait for sufficient memory before issuing a read command.

[0006] One or more embodiments of the present disclosure provide a data reading method, which is applied to a storage device configured with a memory module. The method comprises: obtaining a first read instruction from a host system, wherein the first read instruction does not include a target memory address pointer corresponding to a target memory space, wherein the first read instruction is used to instruct to read target data stored in the memory module; while the host system is preparing the target memory space, reading the target data corresponding to the first read instruction from the memory module according to the first read instruction; after obtaining the target data, sending a data ready notification to the host system, wherein the data ready notification is used to notify the host system that the target data is ready and request the target memory space; when the target memory space is ready, obtaining a second read instruction from the host system, wherein the second read instruction includes the target memory address pointer corresponding to the target memory space; and transferring the target data to the target memory space of the host system according to the target memory address pointer.

[0007] In one or more embodiments of the present disclosure, obtaining the first read instruction from the host system includes: obtaining the first read instruction from a submission queue of the host system in response to a read instruction notification sent by the host system.

[0008] In one or more embodiments of the present disclosure, the sending of the data ready notification includes: writing a memory allocation request to a memory allocation completion queue of a host memory of the host system, wherein the memory allocation completion queue is a dedicated queue for applying for target memory space, and the memory allocation request includes submission queue identification information corresponding to the first read instruction; and sending a data ready notification to the host system to notify the host system to check the memory allocation request in the memory allocation completion queue.

[0009] In one or more embodiments of the present disclosure, the memory allocation request includes at least one of the following information: submission queue identification information, requested memory size information, a command identifier, and a status field, wherein the submission queue identification information is used to identify the submission queue where the first read instruction is located, and the command identifier is used to match the corresponding read instruction.

[0010] In one or more embodiments of the present disclosure, obtaining the second read instruction from the host system includes: obtaining the second read instruction from a submission queue of the host system in response to an address completion notification sent by the host system.

[0011] In one or more embodiments of the present disclosure, transferring the target data to the target memory space of the host system includes: obtaining the second read instruction and the target memory address pointer in the second read instruction; instructing the buffer memory to start data transmission; and transferring the target data from the buffer memory to the target memory space of the host system according to the target memory address pointer.

[0012] In one or more embodiments of the present disclosure, the method further includes: after transferring the target data to the target memory space of the host system, sending status information to a completion queue of the host system, wherein the status information is used to indicate the completion status of the read operation corresponding to the first read instruction and includes a command identifier corresponding to the first read instruction; sending an interrupt signal to the host system, wherein the interrupt signal enables the host system to read the status information; and receiving a completion notification sent by the host system, wherein the completion notification is used to indicate that the host system has processed the entry in the completion queue corresponding to the completion notification, and the space in the completion queue corresponding to the entry has been released.

[0013] In one or more embodiments of the present disclosure, the target memory address pointer is a physical region page pointer, which is used to indicate a physical memory location in the host system for receiving the target data.

[0014] In one or more embodiments of the present disclosure, after obtaining the target data, a data ready notification is sent to the host system so that the host system executes: obtaining available target memory space; setting the target memory address pointer to the first read instruction to form the second read instruction; and sending an address completion notification to indicate that the target memory address pointer has been set.

[0015] In one or more embodiments of the present disclosure, the method further includes: after the host system processes the memory allocation request in the memory allocation completion queue, receiving a memory allocation completion notification sent by the host system, wherein the memory allocation completion notification is used to indicate that the host system has processed the entry in the memory allocation completion queue corresponding to the memory allocation completion notification, and the space corresponding to the entry in the memory allocation completion queue has been released.

[0016] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device for electrically connecting to a host system. The processor is configured to: obtain a first read instruction from the host system, wherein the first read instruction does not include a target memory address pointer corresponding to a target memory space, and wherein the first read instruction is used to instruct to read target data stored in the memory module; while the host system is preparing the target memory space, read the target data corresponding to the first read instruction from the memory module according to the first read instruction; after obtaining the target data, send a data ready notification to the host system, wherein the data ready notification is used to notify the host system that the target data is ready and request the target memory space; when the target memory space is ready, obtain a second read instruction from the host system, wherein the second read instruction includes the target memory address pointer corresponding to the target memory space; and transfer the target data to the target memory space of the host system according to the target memory address pointer.

[0017] Based on the above, the data reading method and memory controller provided by the present disclosure alter the reading process when host memory is limited. This allows the storage device to first read data from the memory module based on a read instruction that does not contain a host memory address, without having to wait for the host system to allocate memory. Simultaneously, the host system can prepare the corresponding memory space. This approach parallelizes the time spent waiting for host memory allocation and the time spent reading data from the flash memory, effectively reducing the overall wait time for read operations and thereby improving the storage device's read performance.

[0018] In addition, the present disclosure introduces a new data-ready notification mechanism, which enables the storage device to actively request memory space from the host system after the data is ready, rather than passively waiting for the host system to allocate memory. On the other hand, the host system can also selectively instruct the storage device that the read data can be written to the prepared memory space depending on the size of the prepared memory space. This active request method optimizes the memory allocation strategy in the traditional NVMe protocol, allowing the host system to manage memory resources more flexibly. In particular, in the case of a large read data queue depth, the method disclosed in the present disclosure can significantly reduce the memory requirements of the host system, allowing the host system to use multiple smaller memory spaces in batches to complete the reading of large data, greatly reducing the memory pressure on the host side. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure;

[0020] Figure 2 is a flow chart of a data reading method according to an embodiment of the present disclosure;

[0021] Figure 3 is a timing diagram of a data reading method according to an embodiment of the present disclosure;

[0022] Figure 4 Schematic diagram of a process of obtaining and sending a first read instruction according to an embodiment of the present disclosure;

[0023] Figure 5 Schematic diagram of a process of data ready notification and memory allocation request according to an embodiment of the present disclosure;

[0024] Figure 6 1 is a schematic diagram of a flow chart of obtaining a second read instruction according to an embodiment of the present disclosure;

[0025] Figure 7 1 is a flow chart illustrating a process of transmitting and completing reading data according to an embodiment of the present disclosure;

[0026] Figure 8 FIG. 4 is a detailed timing diagram of a data reading method according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0028] Figure 1 FIG is a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Figure 1The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120 (also referred to as a host memory), and a data transfer interface circuit 130. In this embodiment, the second processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the second processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0029] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0030] In this embodiment, the host system 10 is electrically connected to the storage device 20 via the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0031] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless method. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), etc., based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a display, and a speaker via the system bus.

[0032] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0033] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0034] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the second processor 110. Specifically, the host memory 120 is used to store data structures such as a submission queue (SQ), a completion queue (CQ), and a memory allocation completion queue (ALLOC CQ), and provides target memory space for target data read from the storage device 20. The submission queue is used to store read instructions sent by the host system 10 to the storage device 20; the completion queue is used to store status information returned by the storage device 20 to the host system 10; and the memory allocation completion queue is a queue dedicated to applying for target memory space and is used to store memory allocation requests sent by the storage device 20 to the host system 10. For example, in this embodiment, the host memory 120 can be dynamic random access memory (DRAM), static random access memory (SRAM), etc. However, it should be understood that the present disclosure is not limited to this, and the host memory 120 can also be other suitable memories.

[0035] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading, and erasing data in the memory module 220 according to instructions from the host system 10 .

[0036] More specifically, the first processor 211 in the memory controller 210 is hardware with computing capabilities that controls the overall operation of the memory controller 210. Specifically, the first processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is operating, these control instructions / program codes are executed to perform operations such as writing, reading, and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform specific information management operations to implement the data reading method provided by the present disclosure. The control instructions / program codes corresponding to the data reading method can be further implemented as a circuit unit in the form of hardware to implement the data reading method provided by the present disclosure.

[0037] It is worth mentioning that in this embodiment, the second processor 110 and the first processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present disclosure is not limited thereto.

[0038] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 may also be considered as operations performed by the memory controller 210.

[0039] The data management circuit 212 is electrically connected to the first processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is configured to receive instructions from the first processor 211 to transmit data. For example, the data management circuit 212 reads data from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213 (e.g., performing corresponding write operations based on various write instructions from the host system 10). For another example, the data management circuit 212 performs a read operation based on a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 (the data may be read from one or more storage units in the one or more physical units) via the memory interface control circuit 213, and writes the read data to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230. In another embodiment, the data management circuit 212 may also be integrated into the first processor 211.

[0040] The memory interface control circuit 213 is configured to receive instructions from the first processor 211 and cooperate with the data management circuit 212 to perform a write (also known as programming) operation, a read operation, or an erase operation on the memory module 220 .

[0041] In addition, the data to be written to the memory module 220 will be converted into a format acceptable to the memory module 220 via the memory interface control circuit 213. Specifically, if the first processor 211 wants to access the memory module 220, the first processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence instructing to write data, a read instruction sequence instructing to read data, an erase instruction sequence instructing to erase data, and corresponding instruction sequences for instructing various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address will be included.

[0042] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationships between the logical addresses of the logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of the physical units (e.g., physical erase units / physical blocks, physical pages) configured in the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also referred to as the logical-to-physical mapping table) to look up the physical unit to which a logical unit is mapped (e.g., to look up the physical page to which a logical page is mapped; to look up the physical address to which a logical address is mapped). Furthermore, the memory controller 210 can use the physical-to-logical address mapping table (also referred to as the physical-to-logical mapping table) to look up the logical unit to which a physical unit is mapped (e.g., to look up the logical page to which a physical page is mapped; to look up the logical address to which a physical address is mapped).

[0043] The buffer memory 214 is electrically connected to the first processor 211 and is used to temporarily store data and instructions from the host system 10, data from the memory module 220, and various system data used to manage the storage device 20. In particular, when the first processor 211 reads target data from the memory module 220 in accordance with a first read instruction, the target data is temporarily stored in the buffer memory 214 until a target memory address pointer provided by the host system 10 is obtained. The target data is then transferred to the target memory space of the host system 10. This mechanism enables the storage device 20 to complete the data read operation from the memory module 220 in advance even if the host system 10 has not yet prepared the target memory space, thereby achieving parallel processing of data reading and memory allocation.

[0044] The memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store user data sent by the host system 10. The memory module 220 supports a multi-plane write mechanism through its multi-plane structure. Specifically, each chip of the memory module 220 has multiple planes (Plane), each plane has multiple physical blocks, and each physical block includes multiple physical pages. In this embodiment, each physical page has multiple storage units (also known as physical bytes or bytes), and each storage unit corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage unit. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0045] Figure 2 is a flow chart of a data reading method according to an embodiment of the present disclosure;

[0046] In one embodiment, referring to Figure 2 The present disclosure provides a data reading method, which is applied to a storage device configured with a memory module. The method comprises the following steps:

[0047] Step S210: Obtain a first read instruction from a host system, wherein the first read instruction does not include a target memory address pointer corresponding to a target memory space, and wherein the first read instruction is used to instruct to read target data stored in the memory module.

[0048] In this embodiment, the first processor 211 obtains a first read instruction from the host system 10. Unlike the traditional NVMe protocol, this first read instruction does not include a target memory address pointer such as a physical region page (PRP) pointer, which is used to indicate the physical address of the host memory unit that can store the target read data (referred to as target data). This means that when the host system 10 sends the read instruction, it has not yet allocated target memory space for receiving the target data. This mechanism allows the host system 10 to issue a read command without waiting for sufficient memory space, thereby improving reading efficiency when memory resources are tight.

[0049] Specifically, the first processor 211 may obtain the first read instruction in the following manner: the second processor 110 of the host system 10 writes the first read instruction to a submission queue in the host memory 120 and then sends a read instruction notification via a doorbell mechanism; the first processor 211 of the storage device 20 responds to the notification and obtains the first read instruction from the submission queue. The first read instruction includes necessary information, such as the logical address and data size of the target data to be read, but does not include the host memory address for storing the read data.

[0050] Step S220 : While the host system is preparing the target memory space, read the target data corresponding to the first read instruction from the memory module according to the first read instruction.

[0051] In this embodiment, while the host system 10 is preparing the target memory space, the first processor 211 instructs the memory interface control circuit 213 to read the target data from the memory module 220 according to the first read instruction. This parallel processing mechanism is a key innovation of the present disclosure, as it allows data reading operations on the storage device 20 and memory allocation operations on the host system 10 to be performed simultaneously without having to wait for each other.

[0052] Specifically, the first processor 211 parses the logical address information in the first read instruction, determines the physical address of the target data in the memory module 220 using the logical-to-physical address mapping table, and then instructs the memory interface control circuit 213 to read the target data from the corresponding physical address. The read data is temporarily stored in the buffer memory 214, awaiting subsequent transmission.

[0053] Step S230: After acquiring the target data, sending a data ready notification to the host system, wherein the data ready notification is used to notify the host system that the target data is ready and to request the target memory space.

[0054] In this embodiment, after the first processor 211 has read the target data from the memory module 220 and stored it in the buffer memory 214, it sends a data ready notification to the host system 10. The purpose of this notification is to inform the host system 10 that the target data is ready and to request the host system 10 to allocate the necessary target memory space to receive the data.

[0055] Specifically, the first processor 211 executes the sending of the data ready notification, including: writing a memory allocation request to the memory allocation completion queue of the host memory 120 of the host system 10, wherein the memory allocation completion queue is a dedicated queue for applying for target memory space, and the memory allocation request includes the submission queue identification information corresponding to the first read instruction; and sending a data ready notification to the second processor 110 (also referred to as the second processor) of the host system 10 to notify the second processor 110 to check the memory allocation request in the memory allocation completion queue. The memory allocation request may also include information such as the requested memory size information and a command identifier, wherein the command identifier is used to match the corresponding read instruction. This mechanism allows the storage device 20 to actively request memory resources instead of passively waiting for allocation from the host system 10.

[0056] In one embodiment, when the first processor 211 writes a memory allocation request to the memory allocation completion queue, the memory allocation request includes at least one of the following information: submission queue identification information, requested memory size information, a command identifier, and a status field. The submission queue identification information is used to identify the submission queue where the first read instruction is located, facilitating the host system 10 to quickly locate the corresponding original read instruction; the requested memory size information indicates the size of the target memory space to be allocated, ensuring that sufficient space is allocated to store the target data; the command identifier is used to match the corresponding read instruction to ensure that the data is correctly mapped to the corresponding request; and the status field is used to record the processing status, priority, or special requirements of the memory allocation request, such as the urgency of the request, the processing stage (e.g., "pending," "processing," or "completed"), the number of retries, or additional conditions related to a specific read operation. With this information, the host system 10 and the storage device 20 can effectively coordinate the memory allocation and data transfer processes to ensure the correct execution of the read operation.

[0057] Step S240: When the target memory space is ready, obtain a second read instruction from the host system, wherein the second read instruction includes the target memory address pointer corresponding to the target memory space.

[0058] In this embodiment, when the host system 10 receives the data ready notification, the second processor 110 allocates a target memory space for the target data and generates a second read instruction by updating the first read instruction. Unlike the first read instruction, the second read instruction includes a target memory address pointer (such as a PRP pointer) corresponding to the target memory space. For example, the first read instruction is updated to the second read instruction by filling in the target memory address pointer to the original first read instruction. The second read instruction is actually the first read instruction with the target memory address pointer filled in, and contains the same data request information as the first read instruction, but adds a target memory address pointer that can be used to store the target data.

[0059] At the same time, the second processor 110 can also process the corresponding memory allocation request in the memory allocation completion queue and clear the request entry, indicating that the memory allocation request has been processed, thereby freeing up the corresponding space in the memory allocation completion queue. This mechanism ensures the effective utilization of the memory allocation completion queue resources and prevents the queue from being full and affecting the processing of new memory allocation requests. The second processor 110 then sends an address completion notification and a memory allocation completion notification to the first processor 211 through a doorbell mechanism or direct notification, indicating that the target memory address pointer has been set.

[0060] Then, the second processor 110 sends an address completion notification to the first processor 211, notifying the first processor 211 that the physical address of the target memory space corresponding to the memory allocation request has been completed in the second read instruction. In response to the address completion notification sent by the host system 10, the first processor 211 obtains the second read instruction from the submission queue of the host system 10 to extract the target memory address pointer for storing the target data.

[0061] In one embodiment, after the host system 10 processes the memory allocation request in the memory allocation completion queue, the first processor 211 receives a memory allocation completion notification sent by the host system 10, and the memory allocation completion notification is used to indicate that the host system 10 has processed the entry in the memory allocation completion queue corresponding to the memory allocation completion notification, and the space corresponding to the entry in the memory allocation completion queue has been released.

[0062] For example, after the second processor 110 of the host system 10 allocates target memory space for target data and fills the target memory address pointer into the first read instruction to form a second read instruction, the second processor 110 will simultaneously process the corresponding memory allocation request in the memory allocation completion queue. After the processing is completed, the second processor 110 will clear the corresponding memory allocation request entry and send a memory allocation completion notification to the storage device 20, clearly indicating that the memory allocation request has been processed and the corresponding entry space in the memory allocation completion queue has been released.

[0063] After receiving the memory allocation completion notification, the first processor 211 updates its internal record to confirm that the memory allocation request has been successfully processed by the host system 10. This mechanism is very important for managing the resources of the memory allocation completion queue, especially in the scenario of processing a large number of concurrent read requests.

[0064] In one embodiment, the memory allocation completion notification can be sent together with the address completion notification or as a separate notification. Regardless of the method used, this notification mechanism ensures that the storage device 20 accurately understands the status of the memory allocation completion queue and can make appropriate processing decisions. For example, when the first processor 211 knows that a memory allocation request has been processed and the corresponding queue entry has been released, it can reuse the queue entry for a new data read operation when needed.

[0065] Furthermore, this queue space release mechanism prevents the memory allocation completion queue from becoming full. If the queue becomes full and is not released promptly, new memory allocation requests may be unable to be written, thereby affecting the efficiency of the entire data reading process. By using a clear memory allocation completion notification mechanism, the host system 10 and storage device 20 can work together to ensure efficient use of queue resources.

[0066] Step S250: Transferring the target data to the target memory space of the host system according to the target memory address pointer.

[0067] In this embodiment, after obtaining the target memory address pointer in the second read instruction, the first processor 211 instructs the data management circuit 212 to transfer the target data stored in the buffer memory 214 to the target memory space of the host system 10 .

[0068] Specifically, the first processor 211 parses the second read instruction to obtain a target memory address pointer, which indicates the physical memory address (e.g., the physical address of the target memory space) in the host memory 120 for receiving the target data. The first processor 211 then instructs the data management circuit 212 to transfer (write) the target data in the buffer memory 214 to the physical memory address in the host memory 120 via direct memory access (DMA). After the transfer is complete, the first processor 211 sends (writes) status information to the completion queue of the host system 10, indicating that the read operation has been completed. The status information indicates the completion status of the read operation corresponding to the first read instruction and includes a command identifier corresponding to the first read instruction.

[0069] More specifically, the first processor 211 writes the status information to the completion queue in the host memory 120. The status information includes not only a status flag indicating whether the read operation is successfully completed, but also a command identifier for the host system 10 to identify the original read instruction corresponding to the status information.

[0070] Subsequently, the first processor 211 sends an interrupt signal to the host system 10, which causes the host system 10 to read the status information. This interrupt mechanism enables the host system 10 to promptly know that the read operation has been completed without requiring the host system 10 to frequently poll the completion queue to query the operation status. Figure 7 In step A72, the second processor 110 of the host system 10 reads the status information in the completion queue to understand the completion status of the read operation. If the second processor 110 determines that no error occurred during the entire read process (normal read), the second processor 110 generates and sends a completion notification to the first processor 211.

[0071] Finally, first processor 211 receives a completion notification from host system 10. This completion notification indicates that host system 10 has processed the entry in the completion queue corresponding to the completion notification and that the space corresponding to the entry in the completion queue has been released. Furthermore, after processing the status information, host system 10 clears the corresponding status information and notifies storage device 20 that the corresponding status information entry in the completion queue has been processed. This mechanism ensures efficient utilization of completion queue resources, preventing queue space from being full and preventing the inability to write new completion status.

[0072] At the same time, if Figure 7 As shown in step A74, the host system 10 will also clear the corresponding second read instruction to further free up space in the submission queue. This entire process constitutes a complete resource management cycle, ensuring that system resources can be efficiently utilized to support continuous data read operations.

[0073] Through the above steps, the present disclosure implements parallel processing of host memory allocation and storage device data preparation, effectively improving the storage device's read performance when host memory is limited. Furthermore, in situations with high queue depths, the disclosed method can significantly reduce the host system's memory requirements, enabling the host system to read large amounts of data in batches using smaller memory spaces, thereby alleviating the host system's memory pressure.

[0074] Figure 3 FIG. 4 is a timing diagram of a data reading method according to an embodiment of the present disclosure.

[0075] In one embodiment, referring to Figure 3 This disclosure provides a timing diagram of a data reading method, detailing the interaction between the host system 10 and the various components of the storage device 20, including the flow of instructions and data between the second processor 110 of the host system 10, the host memory 120, the first processor 211 of the storage device 20, the buffer memory 214, and the memory module 220. The entire reading process can be divided into four main phases: the advance instruction sending phase, the parallel processing phase, the physical area page pointer completion phase, and the data transmission and completion phase.

[0076] In the advance instruction sending phase, the second processor 110 first writes a first read instruction to the host memory 120 in step S311. The first read instruction does not contain a target memory address pointer. This is a key innovation of the present disclosure, allowing the host system 10 to send a read request without allocating memory space. Subsequently, in step S312, the second processor 110 sends a read instruction notification (e.g., SQ tailDoorbell) corresponding to the first read instruction to notify the storage device 20 that there is a new read instruction. In step S313, the first processor 211 obtains the first read instruction from the submission queue (SQ) of the host memory 120, completing the advance instruction sending phase.

[0077] During the parallel processing phase, the system implements parallel execution of target memory space preparation and data reading. On the one hand, the second processor 110 begins preparing or releasing the target memory space in step S321. On the other hand, the first processor 211 issues a first read instruction in step S322 and executes a first read operation in step S323 to read data from the memory module 220. In step S324, the memory module 220 returns the successfully read target data to the buffer memory 214 for temporary storage. When the data is ready, the first processor 211 sends (writes) a memory allocation request to the host memory 120's memory allocation completion queue (CQ) in step S325 to request memory space. In step S326, it sends a data-ready notification (e.g., an Allocation CQ doorbell) corresponding to the target data, prompting the second processor 110 to read the memory allocation request, informing the second processor 110 that the target data is ready and requesting the target memory space. This parallel processing mechanism for preparing the target memory space and reading the target data significantly improves the efficiency of the read operation and reduces overall waiting time.

[0078] During the physical region page pointer completion phase, assuming that in step S331, the second processor 110 has already obtained the available target memory space and the corresponding target memory address pointer. Next, in step S332, the second processor 110 sets the target memory address pointer to the first read instruction in the SQ to form a second read instruction. Next, in step S333, the second processor 110 sends an address completion notification to inform the first processor 211 that the target memory address pointer has been set.

[0079] In practice, "address completion notification" can be implemented as follows: In the NVMe protocol, this notification mechanism is actually implemented through a "doorbell" mechanism. Specifically, after the second processor 110 completes setting the target memory address pointer (i.e., filling the PRP pointer into the read instruction in the submission queue), it writes to a specific doorbell register. This operation notifies the storage controller (i.e., the first processor 211) that the instructions in the submission queue have been updated and the submission queue needs to be rechecked.

[0080] The specific implementation can be:

[0081] 1. The second processor 110 writes a value to a specific control register (e.g., a doorbell register) of the storage device 20 to indicate the update position of the submission queue;

[0082] 2. This write operation triggers a hardware interrupt or notification mechanism;

[0083] 3. After receiving the interrupt or notification, the first processor 211 knows that it needs to recheck the instructions at a specific position in the submission queue.

[0084] In some implementations, this may also be a specially designed control command or status bit update specifically to indicate that the address pointer has been completed. The host system may set a specific status bit or send a specific control command to explicitly inform the storage device that the instruction has been updated.

[0085] Regardless of the specific form adopted, the core function of this "address completion notification" is to ensure that the first processor 211 can promptly detect the update of the instruction in the submission queue, thereby obtaining the second read instruction containing the target memory address pointer for subsequent data transfer operations.

[0086] Next, in response to the address completion notification, the first processor 211 obtains the second read instruction and the target memory address pointer therein from the SQ in step S334, and prepares to use the target memory address pointer to perform data transmission.

[0087] Entering the data transfer and completion phase, the first processor 211 performs direct memory access according to the target memory address pointer in step S341, transferring the target data in the buffer memory 214 to the host memory 120. Subsequently, the first processor 211 sends status information indicating the command completion status and related auxiliary information in step S342, and sends an interrupt signal in step S343.

[0088] In the NVMe protocol, this interrupt is usually implemented through the MSI (Message Signaled Interrupt) or MSI-X (Extended Message Signaled Interrupt) mechanism of the PCIe (Peripheral Component Interconnect Express) interface. These mechanisms allow devices to trigger interrupts by writing to a specific address in the host memory, rather than through traditional interrupt pins. When the second processor 110 receives the interrupt signal, it executes the corresponding interrupt handler. The program checks the completion queue, processes the status information in the completion queue, and takes corresponding subsequent actions, such as reading the status information.

[0089] In one or more embodiments, the status information may have one or more of the following details:

[0090] 1. Command completion status code: This is the core part of the status information, used to indicate the final result of the read operation. Examples include Success, Invalid Command, Internal Error, Data Transfer Error, and Insufficient Resources. These status codes follow the standard error code system defined in the NVMe specification, allowing the host system to accurately understand the operation results.

[0091] 2. Command identifier: This is used to match the original read command corresponding to this status information, ensuring that the host system can correctly associate the status information with the previously sent read request. This is especially important when handling multiple concurrent read operations.

[0092] 3. Phase Tag: This is the mechanism used in the NVMe protocol to distinguish between new and old completion entries. When the completion queue wraps around, the phase tag flips to help the host system determine which entries are newly written.

[0093] 4. Queue identifier: used to indicate the submission queue corresponding to the status information, especially when the system uses multiple queues.

[0094] 5. Processing time information: This may include the start time, completion time, or total processing time of the operation, which helps with performance monitoring and optimization.

[0095] 6. Amount of data transferred: The amount of data that was actually successfully transferred, especially in the case of partial completion. This information can help the host system understand how much data was actually read.

[0096] 7. Resource usage: This may include information such as buffer memory usage and internal resource allocation status, which helps the host system optimize subsequent operations.

[0097] 8. Error details: When an error occurs, it may contain more detailed error information, such as error location, error type, possible recovery suggestions, etc.

[0098] 9. Completion protection information: used to verify the integrity of the completion entry, such as a checksum or other integrity verification code.

[0099] 10. Extended status field: Provides additional status information for specific types of commands or operations that may not be suitable for standard status code representation.

[0100] Furthermore, in the embodiments of the present disclosure, due to the use of a dynamic memory allocation mechanism, the status information may also include specific information related to memory allocation, such as the memory allocation result, the actual allocated memory address, the memory release status, etc. This additional information enables the host system to better understand and manage memory resources and support subsequent read operations.

[0101] Next, in step S344, the second processor 110 reads the status information to determine the completion of the read operation. In step S345, the second processor 110 sends a completion notification to the first processor 211, indicating that the host system has acknowledged the completion of the entire read operation. The completion notification indicates that the host system 10 has processed the entry (e.g., status information) in the completion queue corresponding to the completion notification and that the space in the completion queue corresponding to the entry has been freed. Thus, a complete read operation is completed.

[0102] The above timing design embodies the core spirit of this disclosure: by allowing the host system 10 to first send a read instruction that does not contain a memory address, it enables parallel processing of memory allocation and data preparation, effectively improving the read performance of NVMe devices when host memory is limited. Furthermore, through a clear notification mechanism and queue management, the coordination of the entire read process and the proper utilization of resources are ensured.

[0103] The following is more utilized Figure 4-Figure 7 The details of each process of the data reading method will be described separately.

[0104] Figure 4 The figure is a schematic diagram of a process of obtaining and sending a first read instruction according to an embodiment of the present disclosure.

[0105] like Figure 4 As shown, three core components, namely the second processor 110 , the host memory 120 and the first processor 211 , participate in the interaction at this stage. Figure 4, three key queue structures, namely, a submission queue SQ, a completion queue CQ, and a memory allocation completion queue ACQ, are shown. These queues are located in the host memory 120 and are used to support command and data exchange between the host system 10 and the storage device 20.

[0106] At this stage, the second processor 110 first prepares a first read instruction CMD1, which is characterized by not containing a physical region page pointer (no PRP). As shown by arrow A41, the second processor 110 writes the first read instruction into the submission queue SQ of the host memory 120. This step corresponds to Figure 3 Step S311 in is the starting point of the entire reading process.

[0107] Then, as shown by arrow A42, the second processor 110 sends a read instruction notification to the first processor 211, informing the storage device 20 that there is a new read instruction waiting to be processed. This step corresponds to Figure 3 Step S312 in the embodiment ensures that the first processor 211 can promptly discover the new read instruction. This notification mechanism is usually implemented through the doorbell mechanism in the NVMe protocol, that is, the second processor 110 writes a value to a specific control register to trigger a hardware interrupt or notification mechanism.

[0108] Then, as shown by arrow A43, the first processor 211 obtains the first read instruction from the submission queue. This step corresponds to Figure 3 Step S313 in FIG. 1 is a sign that the first processor 211 starts processing the read request. The first read instruction obtained also does not include a physical region page pointer (no PRP), which indicates that the host system 10 has not yet allocated memory space for the data to be read.

[0109] Finally, as indicated by arrow A44, the first processor 211 issues a read instruction sequence to the memory module of the storage device 20 according to the first read instruction. This step initiates the data preparation process. The first processor 211 reads the corresponding target data from the memory module according to the logical address and other auxiliary information in the first read instruction.

[0110] Figure 4 The illustrated process fully demonstrates a key innovation of the present disclosure: the host system 10 can send a first read instruction, without a physical region page pointer, to the storage device 20 before allocating memory space. This mechanism overcomes the limitation of the traditional NVMe protocol that memory must be allocated before a read instruction can be sent, enabling the parallel processing of preparing memory space and reading target data.

[0111] Figure 5The figure is a flowchart of data ready notification and memory allocation request according to an embodiment of the present disclosure.

[0112] like Figure 5 As shown in FIG. 5 , as indicated by arrow A50, it is assumed that the first processor 211 has completed the read operation of the target data. At this point, the first processor 211 generates a memory allocation request ARQ, which contains key information such as the submission queue identification information corresponding to the first read instruction, the requested memory size information, the command identifier, and the status field. This information enables the host system 10 to accurately identify the original read instruction corresponding to the memory allocation request ARQ and understand the memory size to be allocated (the target data has been stored after the read operation).

[0113] Then, as shown by arrow A51, the first processor 211 writes the memory allocation request to the memory allocation completion queue ACQ of the host memory 120. The memory allocation completion queue ACQ is a dedicated queue introduced in the present disclosure, which is specifically used to apply for target memory space and is a key component of the dynamic memory allocation mechanism. This step corresponds to Figure 3 In step S325, the memory application process is started.

[0114] Next, as shown by arrow A52, the first processor 211 sends a data ready notification to the second processor 110. This data ready notification informs the host system 10 that the target data is ready and requests the host system 10 to check the memory allocation request in the memory allocation completion queue ACQ. This step corresponds to Figure 3 Step S326 in the process ensures that the host system 10 can timely discover the memory allocation request ARQ. This notification mechanism can also be implemented through an interrupt signal or other dedicated notification mechanisms to ensure that the host system 10 can respond quickly.

[0115] As shown by arrow A53, after receiving the data ready notification, the second processor 110 reads the memory allocation request ARQ from the memory allocation completion queue ACQ to understand the memory requirements of the storage device 20. Through this mechanism, the second processor 110 can know which data is ready and how much memory space is required, so as to perform the corresponding memory allocation operation.

[0116] Figure 5The illustrated process fully demonstrates another innovative aspect of the present disclosure: storage device 20 can proactively request memory space from host system 10 after data is ready, rather than passively waiting for memory allocation from host system 10. This "active request" mechanism enables more flexible management of memory resources. In particular, in memory-constrained situations, host system 10 can dynamically allocate memory resources based on actual conditions, prioritizing important or urgent requests. For example, second processor 110 can determine whether to consume already read target data in batches (allocating corresponding memory space) or consume all read target data all at once, based on the usage of host memory 120.

[0117] In the traditional NVMe protocol, the host system 10 must pre-allocate sufficient memory space before sending a read instruction, which can cause read operations to be delayed when memory is tight. However, the mechanism proposed in this disclosure decouples data preparation from memory allocation through the memory allocation completion queue ACQ and data ready notification, allowing the two to proceed in parallel, thereby improving overall read performance.

[0118] Furthermore, when the storage device 20 processes multiple read requests simultaneously, this mechanism allows the host system 10 to selectively prioritize memory allocation for certain requests based on their priority or other policies, rather than strictly following the order in which they are processed. This flexibility further optimizes overall system performance and resource utilization.

[0119] Figure 6 4 is a flow chart of obtaining a second read instruction according to an embodiment of the present disclosure.

[0120] like Figure 6 As shown by arrow A60, it is assumed that the second processor 110 has responded to the memory allocation request of the first processor 211 and successfully allocated the target memory space (corresponding to Figure 3 In step S331 of the embodiment, a physical region page pointer (PRP) corresponding to the physical memory address of the target memory space is obtained. The physical region page pointer (PRP) points to a memory location in the host system 10 allocated for receiving the target data.

[0121] Next, as indicated by arrow A61, the second processor 110 updates the second read instruction (CMD2) to the submission queue SQ of the host memory 120. For example, the second processor 110 directly writes a new second read instruction (the second read instruction includes the physical region page pointer (PRP)) or fills the physical region page pointer (PRP) into the original first read instruction to form a second read instruction (corresponding to Figure 3 Step S332 in the process).

[0122] At the same time, as shown by arrow A62, the second processor 110 sends an address completion notification to the first processor 211, clearly informing the storage device 20 that the target memory address pointer has been set. This notification mechanism ensures that the first processor 211 can promptly discover the update of the instruction in the submission queue, so that in response, it can obtain the second read instruction containing the target memory address pointer. This step corresponds to Figure 3 Step S333 in .

[0123] In addition, as shown by arrow A63, the second processor 110 also clears the corresponding memory allocation request, that is, removes the previous request entry from the memory allocation completion queue ACQ. This operation ensures that the resources of the memory allocation completion queue can be effectively managed and prevents the queue from being full and affecting the processing of new memory allocation requests.

[0124] Finally, as shown by arrow A64, the first processor 211 obtains the second read instruction from the submission queue SQ, including the target memory address pointer (PRP) contained therein. Through this mechanism, the first processor 211 obtains the necessary memory address information and can transfer the prepared target data to the specified memory location of the host system 10. This step corresponds to Figure 3 Step S334 in .

[0125] Figure 6 The illustrated process fully demonstrates another key mechanism of the present disclosure: the host system 10 dynamically adds target memory address pointers by updating the read instructions in the submission queue and sending address completion notifications. This mechanism enables the host system 10 to allocate memory space for prepared data as soon as memory resources become available, eliminating the need to wait for all memory resources to be ready before initiating read operations.

[0126] In the traditional NVMe protocol, read instructions must include complete memory address information when sent, which requires the host system to pre-allocate sufficient memory. However, the mechanism proposed in this disclosure decouples read requests from memory allocation by dividing read instructions into two phases (first read instruction and second read instruction), enabling the system to manage memory resources more flexibly.

[0127] It's worth noting that this mechanism also allows the host system 10 to selectively handle multiple memory allocation requests based on actual circumstances. For example, when receiving multiple data-ready notifications simultaneously, the host system 10 can decide which requests to allocate memory to first based on application priority, data importance, or other policies, thereby achieving more intelligent resource management.

[0128] Figure 7 1 is a flow chart illustrating the process of reading data transmission and reading completion according to an embodiment of the present disclosure.

[0129] like Figure 7 As shown by arrow A70, it is assumed that the first processor 211 has transferred the target data from the buffer memory 214 to the target memory space of the host system 10 according to the target memory address pointer in the second read instruction (this step corresponds to Figure 3 Step S341 in the process).

[0130] Next, as indicated by arrow A71, the first processor 211 writes the status information CS into the completion queue CQ of the host memory 120. The status information is used to indicate the completion status of the read operation corresponding to the first read instruction, and includes key information such as the command identifier, completion status code, and stage flag. This information enables the host system 10 to accurately understand the result of the read operation, including whether it is successfully completed or whether an error occurs. This step corresponds to Figure 3 Step S342 in .

[0131] Subsequently, as indicated by arrow A72, the first processor 211 sends an interrupt signal to the second processor 110. In practice, this interrupt signal is usually implemented through a mechanism such as MSI or MSI-X of the PCIe interface, which allows the device to trigger an interrupt by writing to a specific address in the host memory. This interrupt mechanism ensures that the host system 10 can promptly know that the read operation has been completed without the need to frequently poll the completion queue. This step corresponds to Figure 3 Step S343 in .

[0132] After receiving the interrupt signal, the second processor 110 reads the status information from the completion queue CQ as shown by arrow A73 to understand the completion status of the read operation. By parsing the status information, the second processor 110 can determine whether the read operation is successfully completed and whether error handling is required. This step corresponds to Figure 3 Step S344 in .

[0133] After completing the status check, as shown by arrow A74, the second processor 110 sends a completion notification (e.g., CQ Head Doorbell) to the first processor 211. This notification indicates that the host system 10 has processed the corresponding entry in the completion queue, and the space of the corresponding entry in the completion queue has been released and can be used to process new completion information. This step corresponds to Figure 3 Step S345 in .

[0134] At the same time, the host system 10 also needs to clear queue resources. As indicated by arrow A75, the second processor 110 clears the corresponding status information, removing the processed entry from the completion queue CQ. As indicated by arrow A76, the second processor 110 also clears the corresponding second read instruction, removing the completed instruction from the submission queue SQ. These operations ensure efficient utilization of queue resources and provide ample queue space for subsequent read operations.

[0135] Figure 7 The illustrated process fully demonstrates the complete read operation termination mechanism of the present disclosure: through various mechanisms such as status information, interrupt signals, and completion notifications, effective communication and collaboration between the storage device 20 and the host system 10 are achieved. This mechanism not only ensures the correct completion of data transmission but also supports the system in maintaining sufficient resources to process subsequent read requests by promptly releasing queue resources.

[0136] Figure 8 FIG. 4 is a detailed timing diagram of a data reading method according to another embodiment of the present disclosure.

[0137] In another embodiment, referring to Figure 8 , the present disclosure provides a detailed timing diagram of a data reading method, which comprehensively shows the complete interaction process between the second processor 110, the submission queue SQ, the memory allocation completion queue ACQ, the completion queue CQ, the target memory space 121 and the first processor 211. Figure 8 The entire data reading method is divided into five main phases: the pre-read instruction issuance phase, the parallel processing phase, the target memory address pointer completion phase, the data transmission and completion phase, and the queue space release phase. This detailed timing arrangement clearly demonstrates how the dynamic memory allocation mechanism proposed in this disclosure works in coordination between its various components.

[0138] During the pre-fetch instruction sending phase, as shown in step S811, the second processor 110 writes a first read instruction (excluding the target memory address pointer) to the submission queue SQ. Subsequently, in step S812, the second processor 110 sends a read instruction notification, notifying the storage device 20 of the new read instruction. In step S813, the first processor 211 retrieves the first read instruction from the submission queue SQ. This phase establishes the fundamental innovation of the present disclosure: allowing the host system 10 to send a read request before allocating memory space.

[0139] In the parallel processing stage, the host prepares the memory space and performs data reading in parallel. As shown in step S821, the second processor 110 prepares the target memory space 121; at the same time, as shown in step S822, the first processor 211 reads the target data from the memory module. When the data reading is completed, the first processor 211 writes a memory allocation request (including submission queue identification information) to the memory allocation completion queue ACQ in step S823, and sends a data ready notification in step S824 to notify that the target data is ready and request the target memory space. This parallel mechanism is the core advantage of the present disclosure and can effectively reduce the overall waiting time.

[0140] In the target memory address pointer completion phase, as shown in step S831, the second processor 110 obtains the available target memory space. In step S832, the second processor 110 sets the target memory address pointer to the first read instruction to form a second read instruction. Subsequently, in step S833, the second processor 110 updates the memory allocation completion queue ACQ (release memory allocation request) and clears the processed request entry. The second processor 110 sends an address completion notification in step S834, and the first processor 211 obtains the second read instruction containing the target memory address pointer in step S835. This stage realizes the dynamic addition of memory addresses, enabling the system to flexibly manage memory resources.

[0141] During the data transfer and completion phase, as shown in step S841, the first processor 211 transfers the target data to the target memory space 121 according to the target memory address pointer. After the data transfer is complete, the first processor 211 sends status information (e.g., including completion status and command identifier) to the completion queue CQ in step S842 and sends an interrupt signal to notify the host system 10 in step S843. The second processor 110 reads the status information in step S844 to understand the completion status of the operation and sends a completion notification in step S845. This phase ensures the accurate completion of data transfer and the correct transmission of status.

[0142] Finally, in the queue space release phase, the second processor 110 updates the completion queue CQ (releasing completion queue entry space) in step S851 and updates the submission queue SQ (releasing submission queue entry space) in step S852. This resource release ensures queue resource reuse and allows the system to continuously process new read requests.

[0143] Figure 8The complete timing flow illustrates the core advantages of the dynamic memory allocation mechanism proposed in this disclosure: by separating read instructions from memory allocation, data preparation and memory allocation can be processed in parallel. A dedicated memory allocation completion queue and associated notification mechanism enable collaborative reads between the storage device 20 and the host system 10. Comprehensive queue management and resource release mechanisms ensure efficient utilization of system resources. These mechanisms work together to significantly improve the read performance of NVMe storage devices when host memory is limited.

[0144] Of particular note is that the disclosed method allows the host system 10 to flexibly manage memory resources based on actual circumstances. For example, in a scenario where the queue depth is 32 and each read command requires 1MB of memory, conventional methods require pre-allocation of 32MB of memory. However, the disclosed method requires only a specific small unit (e.g., 1MB) of memory to begin processing read commands, significantly reducing the memory pressure on the host system 10. Furthermore, the host system 10 can selectively prioritize memory allocation for certain requests based on application priority or data importance, achieving more intelligent resource management.

[0145] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is executed in a processor, the processor performs the steps of the above-mentioned data reading method. The computer program product can be implemented in hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0146] Based on the above embodiments, the data reading method and memory controller provided by the present disclosure have the following significant technical effects:

[0147] First, by changing the traditional NVMe protocol's read process, the present disclosure enables the storage device to first read data from the memory module based on a read instruction that does not contain a host memory address, without having to wait for the host system to allocate memory. At the same time, the host system can prepare the corresponding memory space. This approach parallelizes the time spent waiting for host memory allocation and the time spent reading data from the memory module, effectively reducing the overall wait time for read operations and thereby improving the storage device's read performance.

[0148] Secondly, this disclosure introduces a new data-ready notification mechanism that enables the storage device to proactively request memory space from the host system once data is ready, rather than passively waiting for the host system to allocate memory. Furthermore, the host system can selectively indicate to the storage device which read data is ready to be written to the prepared memory space, depending on the size of the prepared memory space. This proactive request method optimizes the memory allocation strategy in the traditional NVMe protocol, enabling the host system to manage memory resources more flexibly.

[0149] Furthermore, the present disclosure significantly improves system resource utilization by coordinating memory allocation and data access. The coordinated operation of the memory allocation completion queue, submission queue, and completion queue, along with corresponding notification mechanisms, ensures efficient coordination between the host system and storage devices, supporting the parallel processing of multiple read requests.

[0150] Finally, in the case of a large read data queue depth, the method disclosed in the present invention can significantly reduce the memory requirements of the host system, allowing the host system to use multiple smaller memory spaces in batches to complete the reading of large data, thereby reducing the memory pressure on the host side.

[0151] In summary, the data reading method and memory controller provided by the present disclosure effectively solve the performance bottleneck problem of the traditional NVMe protocol under the condition of tight host memory through innovative read instruction settings and dynamic memory allocation mechanism, and optimize the reading efficiency of the storage device.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, applied to a storage device equipped with a memory module, characterized in that: The method comprises: Retrieve a first read instruction from a host system, wherein the first read instruction does not include a target memory address pointer corresponding to a target memory space, and wherein the first read instruction is used to instruct to read target data stored in the memory module; During the period when the host system prepares the target memory space, reading the target data corresponding to the first read instruction from the memory module according to the first read instruction; After acquiring the target data, sending a data ready notification to the host system, wherein the data ready notification is used to notify the host system that the target data is ready and to request the target memory space; When the target memory space is ready, obtaining a second read instruction from the host system, wherein the second read instruction includes the target memory address pointer corresponding to the target memory space; and The target data is transferred to the target memory space of the host system according to the target memory address pointer.

2. The data reading method according to claim 1, wherein: The acquiring of a first read instruction from the host system comprises: In response to the read instruction notification sent by the host system, the first read instruction is obtained from a submission queue of the host system.

3. The data reading method according to claim 1, wherein: The sending of the data ready notification includes: Writing a memory allocation request to a memory allocation completion queue of a host memory of the host system, wherein the memory allocation completion queue is a dedicated queue for applying for target memory space, and the memory allocation request includes submission queue identification information corresponding to the first read instruction; and A data ready notification is sent to the host system to notify the host system to check the memory allocation request in the memory allocation completion queue.

4. The data reading method according to claim 3, wherein: The memory allocation request includes at least one of the following information: submission queue identification information, requested memory size information, command identifier and status field, wherein the submission queue identification information is used to identify the submission queue where the first read instruction is located, and the command identifier is used to match the corresponding read instruction.

5. The data reading method according to claim 1, wherein: The acquiring a second read instruction from the host system comprises: In response to the address completion notification sent by the host system, the second read instruction is obtained from a submission queue of the host system.

6. The data reading method according to claim 1, wherein: The transferring the target data to the target memory space of the host system comprises: Obtaining the second read instruction and a target memory address pointer in the second read instruction; instructing the buffer memory of the storage device to start data transfer; and The target data is transferred from the buffer memory to the target memory space of the host system according to the target memory address pointer.

7. The data reading method according to claim 1, wherein: The method further comprises: After transferring the target data to the target memory space of the host system, sending status information to a completion queue of the host system, wherein the status information is used to indicate a completion status of the read operation corresponding to the first read instruction and includes a command identifier corresponding to the first read instruction; sending an interrupt signal to the host system, the interrupt signal causing the host system to read the status information; and A completion notification sent by the host system is received, where the completion notification is used to indicate that the host system has processed an entry in the completion queue corresponding to the completion notification, and space in the completion queue corresponding to the entry has been released.

8. The data reading method according to claim 1, wherein: The target memory address pointer is a physical region page pointer, which is used to indicate a physical memory location in the host system for receiving the target data.

9. The data reading method according to claim 1, wherein: After acquiring the target data, a data ready notification is sent to the host system so that the host system executes: Get available target memory space; Setting a target memory address pointer to the first read instruction to form the second read instruction; as well as An address completion notification is sent to indicate that the target memory address pointer has been set.

10. The data reading method according to claim 3, wherein: The method further comprises: After the host system processes the memory allocation request in the memory allocation completion queue, a memory allocation completion notification sent by the host system is received, where the memory allocation completion notification is used to indicate that the host system has processed the entry in the memory allocation completion queue corresponding to the memory allocation completion notification, and the space in the memory allocation completion queue corresponding to the entry has been released.

11. A memory controller for controlling a storage device equipped with a memory module, characterized in that: The memory controller comprises: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system, wherein the processor is configured to: Retrieve a first read instruction from the host system, wherein the first read instruction does not include a target memory address pointer corresponding to a target memory space, and wherein the first read instruction is used to instruct to read target data stored in the memory module; During the period when the host system prepares the target memory space, reading the target data corresponding to the first read instruction from the memory module according to the first read instruction; After acquiring the target data, sending a data ready notification to the host system, wherein the data ready notification is used to notify the host system that the target data is ready and to request the target memory space; When the target memory space is ready, obtaining a second read instruction from the host system, wherein the second read instruction includes the target memory address pointer corresponding to the target memory space; and The target data is transferred to the target memory space of the host system according to the target memory address pointer.

12. The memory controller according to claim 11, wherein: In the operation of obtaining the first read instruction from the host system: In response to the read instruction notification sent by the host system, the processor obtains the first read instruction from a submission queue of the host system.

13. The memory controller according to claim 11, wherein: In the operation of sending the data ready notification: The processor writes a memory allocation request to a memory allocation completion queue of a host memory of the host system, where the memory allocation completion queue is a dedicated queue for applying for target memory space, and the memory allocation request includes submission queue identification information corresponding to the first read instruction; as well as The processor sends a data ready notification to the host system to notify the host system to check the memory allocation request in the memory allocation completion queue.

14. The memory controller according to claim 13, wherein: The memory allocation request includes at least one of the following information: submission queue identification information, requested memory size information, command identifier and status field, wherein the submission queue identification information is used to identify the submission queue where the first read instruction is located, and the command identifier is used to match the corresponding read instruction.

15. The memory controller according to claim 11, wherein: In the operation of obtaining the second read instruction from the host system: In response to the address completion notification sent by the host system, the processor obtains the second read instruction from a submission queue of the host system.

16. The memory controller according to claim 11, wherein: The memory controller further includes a buffer memory, wherein in the operation of transferring the target data to the target memory space of the host system: The processor obtains the second read instruction and a target memory address pointer in the second read instruction; The processor instructs the buffer memory to start data transmission; as well as The processor transfers the target data from the buffer memory to the target memory space of the host system according to the target memory address pointer.

17. The memory controller according to claim 11, wherein: The processor is further configured to: After transferring the target data to the target memory space of the host system, sending status information to a completion queue of the host system, wherein the status information is used to indicate a completion status of the read operation corresponding to the first read instruction and includes a command identifier corresponding to the first read instruction; sending an interrupt signal to the host system, wherein the interrupt signal causes the host system to read the status information; as well as A completion notification sent by the host system is received, where the completion notification is used to indicate that the host system has processed an entry in the completion queue corresponding to the completion notification, and space in the completion queue corresponding to the entry has been released.

18. The memory controller according to claim 11, wherein: The target memory address pointer is a physical region page pointer, which is used to indicate a physical memory location in the host system for receiving the target data.

19. The memory controller according to claim 11, wherein: After acquiring the target data, a data ready notification is sent to the host system so that the host system executes: Get available target memory space; Setting a target memory address pointer to the first read instruction to form the second read instruction; as well as An address completion notification is sent to indicate that the target memory address pointer has been set.

20. The memory controller according to claim 13, wherein: The processor is further configured to: After the host system processes the memory allocation request in the memory allocation completion queue, a memory allocation completion notification sent by the host system is received, where the memory allocation completion notification is used to indicate that the host system has processed the entry in the memory allocation completion queue corresponding to the memory allocation completion notification, and the space in the memory allocation completion queue corresponding to the entry has been released.

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