A chip component layout optimization method, device, equipment and storage medium

Abstract

An embodiment of the present invention provides a method, apparatus, device and storage medium for optimizing the component layout of a chip. The method may include obtaining the operating parameters and spatial properties of each component in the chip; the operating parameters include at least one of thermal resistivity, operating current, and operating resistance; the spatial properties include at least one of maximum spacing, minimum spacing, position, and area; determining candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component; determining a target layout of each component in the chip based on the candidate layouts; the present invention can determine candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component in the chip, and then determine the target layout based on the candidate layouts, can accurately predict the impact of component layout on chip temperature distribution, can adapt to different process nodes and design requirements, and improve design flexibility and applicability.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip component layout optimization method, device, equipment and storage medium. Background Art

[0002] With the continuous improvement of the integration and power consumption of electronic devices, power management units (PMUs) play an increasingly important role in chip design. Especially in high-current application scenarios, PMUs need to take on the task of transmitting high current density, which will cause a large amount of heat to be generated inside the chip. If not effectively managed, the thermal effect will seriously affect the performance, reliability and service life of the chip. Currently, component layout optimization for chips usually relies on manual experience, and its flexibility and adaptability are not high. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a chip component layout optimization method, apparatus, device and storage medium that overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a method for optimizing component layout of a chip, the method comprising:

[0005] Obtaining operating parameters and spatial properties of each component in the chip; the operating parameters include at least one of thermal resistance coefficient, operating current, and operating resistance; the spatial properties include at least one of maximum spacing, minimum spacing, position, and area;

[0006] determining candidate layouts of the components in the chip based on the operating parameters and spatial properties of the components;

[0007] A target layout of each component in the chip is determined based on the candidate layout.

[0008] Optionally, determining a candidate layout of each component in the chip according to the operating parameters and spatial properties of each component includes:

[0009] Determine an initial population; the initial population includes a plurality of individuals, each of the plurality of individuals including position parameters of each component in the chip;

[0010] Determining the fitness value of each individual in the initial population according to the operating parameters and spatial properties of each component in each individual;

[0011] Select an individual with a larger fitness value in the initial population as a parent individual;

[0012] Generate a new population by performing crossover and mutation operations on the parent individuals;

[0013] The candidate layouts are generated within a neighborhood of the new population.

[0014] Optionally, determining the initial population includes:

[0015] Determine the population size N;

[0016] For each individual Pi, generate the position parameters Xi=(xi1, yi1, xi2, yi2, ..., xim, yim) of each element in the chip, where the position parameters are coordinate values ​​generated according to the specific positions of the elements, where m is the number of elements;

[0017] All generated individuals Pi are placed into the population P to form the initial population.

[0018] Optionally, determining the fitness value of each individual in the initial population according to the operating parameters and spatial attributes of each component in each individual includes:

[0019] determining a position score for each individual in the initial population based on the spatial attributes of each element in each individual;

[0020] determining a power consumption score of each individual in the initial population according to an operating parameter of each component in each individual;

[0021] Determining a vector score for each individual in the initial population based on the operating parameters and spatial attributes of each component in each individual;

[0022] Obtaining a first weight of the location score, a second weight of the power consumption score, and a third weight of the vector score;

[0023] The fitness value of each individual in the initial population is determined according to the position score, power consumption score and vector score of each individual in the initial population, and the first weight, the second weight and the third weight.

[0024] Optionally, determining the position score of each individual in the initial population according to the spatial attributes of each element in each individual includes:

[0025] Obtaining the center position coordinates in the chip;

[0026] The position score of each individual in the initial population is determined according to the position of each element in the individual and the center position coordinates in the chip.

[0027] Optionally, determining the power consumption score of each individual in the initial population according to the operating parameters of each component in each individual includes:

[0028] The power consumption score of each individual in the initial population is determined according to the operating current and the operating resistance of each component in the individual.

[0029] Optionally, determining the vector score of each individual in the initial population according to the operating parameters and spatial attributes of each component in each individual includes:

[0030] Obtain the offset of each component in a single entity in multiple vector directions respectively;

[0031] determining temperature values ​​of the respective elements in the plurality of vector directions according to offsets of the respective elements in the plurality of vector directions, operating parameters of the respective elements, and spatial properties;

[0032] determining a vector score for each component according to temperature values ​​of each component in a plurality of vector directions;

[0033] The vector score of each individual in the initial population is determined according to the vector scores of the respective elements.

[0034] Optionally, determining a target layout of each component in the chip based on the candidate layout includes:

[0035] Determine whether the preset termination conditions are met;

[0036] When the preset termination condition is met, a target layout of each component in the chip is determined according to the candidate layout.

[0037] Optionally, the preset termination condition includes reaching a preset number of iterations, or the temperature of the chip drops to a preset temperature.

[0038] Optionally, it also includes:

[0039] If the preset termination condition is not met, the process returns to the step of determining candidate layouts of the components in the chip according to the operating parameters and spatial properties of the components, until the preset termination condition is met and the candidate layout is determined as the target layout.

[0040] The present invention also discloses a device for optimizing chip component layout, the device comprising:

[0041] an acquisition module, configured to acquire operating parameters and spatial properties of each component in the chip; the operating parameters including at least one of thermal resistance coefficient, operating current, and operating resistance; and the spatial properties including at least one of maximum spacing, minimum spacing, position, and area;

[0042] A first determining module, configured to determine a candidate layout of each component in the chip based on the operating parameters and spatial properties of each component;

[0043] The second determining module is configured to determine a target layout of each component in the chip according to the candidate layout.

[0044] Optionally, the first determining module includes:

[0045] A first determination submodule is configured to determine an initial population; the initial population includes a plurality of individuals, each of the plurality of individuals including position parameters of each component in the chip;

[0046] a second determining submodule, configured to determine the fitness value of each individual in the initial population according to the operating parameters and spatial attributes of each component in each individual;

[0047] A selection submodule is used to select an individual with a larger fitness value in the initial population as a parent individual;

[0048] A first generation submodule is used to generate a new population by performing crossover and mutation operations on the parent individuals;

[0049] The second generation submodule is configured to generate the candidate layout within the neighborhood of the new population.

[0050] Optionally, the first determining submodule includes:

[0051] A first determining unit, configured to determine a population size N;

[0052] a generating unit, configured to generate, for each individual Pi, position parameters Xi = (xi1, yi1, xi2, yi2, ..., xim, yim) of each element in the chip, wherein the position parameters are coordinate values ​​generated according to the specific positions of the elements, where m is the number of elements;

[0053] A forming unit is used to put all generated individuals Pi into the population P to form the initial population.

[0054] Optionally, the second determining submodule includes:

[0055] a position score determining unit, configured to determine a position score of each individual in the initial population based on a spatial attribute of each element in each individual;

[0056] a power consumption score determining unit, configured to determine a power consumption score of each individual in the initial population based on an operating parameter of each component in each individual;

[0057] a vector score determination unit, configured to determine a vector score of each individual in the initial population based on the operating parameters and spatial properties of each component in each individual;

[0058] a weight acquiring unit, configured to acquire a first weight of the location score, a second weight of the power consumption score, and a third weight of the vector score;

[0059] The second determining unit is configured to determine the fitness value of each individual in the initial population according to the position score, power consumption score and vector score of each individual in the initial population, and the first weight, the second weight and the third weight.

[0060] Optionally, the location score determination unit includes:

[0061] A first acquisition subunit is used to acquire the center position coordinates of the chip;

[0062] The first determining subunit is configured to determine a position score of a single individual in the initial population according to the position of each element in the single individual and the center position coordinates in the chip.

[0063] Optionally, the power consumption score determining unit includes:

[0064] The second determining subunit is configured to determine the power consumption score of a single individual in the initial population according to the operating current and the operating resistance of each component in the single individual.

[0065] Optionally, the vector score determination unit includes:

[0066] The second acquisition subunit is used to respectively acquire the offset of each element in a single individual in multiple vector directions;

[0067] a third determining subunit, configured to determine the temperature values ​​of the respective elements in the plurality of vector directions according to the offsets of the respective elements in the plurality of vector directions, the operating parameters of the respective elements, and the spatial properties;

[0068] a fourth determining subunit, configured to determine a vector score of each component according to temperature values ​​of each component in a plurality of vector directions;

[0069] The fifth determining subunit is configured to determine the vector score of each individual in the initial population according to the vector scores of the respective elements.

[0070] Optionally, the second determining module includes:

[0071] The judgment submodule is used to judge whether the preset termination condition is met;

[0072] The third determining submodule is configured to determine a target layout of each component in the chip according to the candidate layout when the preset termination condition is met.

[0073] Optionally, the preset termination condition includes reaching a preset number of iterations, or the temperature of the chip drops to a preset temperature.

[0074] Optionally, it also includes:

[0075] The fourth determination submodule is configured to return to the step of determining a candidate layout of each component in the chip based on the operating parameters and spatial properties of each component if the preset termination condition is not met, until the preset termination condition is met and the candidate layout is determined as the target layout.

[0076] Accordingly, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various steps of the above-mentioned chip component layout optimization method embodiment are implemented.

[0077] Accordingly, an embodiment of the present invention discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various steps of the above-mentioned chip component layout optimization method embodiment are implemented.

[0078] The embodiments of the present invention include the following advantages:

[0079] The present invention can determine the candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component in the chip, and then determine the target layout based on the candidate layouts. It can accurately predict the impact of the component layout on the chip temperature distribution, adapt to different process nodes and design requirements, and improve the flexibility and applicability of the design; through multi-dimensional combination strategies, the target layout can achieve a balance in key indicators such as heat dissipation performance, signal integrity, and chip area, effectively improving the reliability and work efficiency of the chip and reducing labor costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 It is a flowchart of the steps of an embodiment of a chip component layout optimization method of the present invention;

[0081] Figure 2 It is a flow chart of an embodiment of a chip component layout optimization method of the present invention;

[0082] Figure 3 It is a structural block diagram of an embodiment of a chip component layout optimization device of the present invention. DETAILED DESCRIPTION

[0083] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0084] One of the core concepts of the embodiments of the present invention is that the present invention can determine the candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component in the chip, and then determine the target layout based on the candidate layouts. It can accurately predict the impact of various component layout schemes on the chip temperature distribution, adapt to different process nodes and design requirements, and improve the flexibility and applicability of the design; through a multi-dimensional combination strategy, the target layout can achieve a balance in key indicators such as heat dissipation performance, signal integrity, and chip area, effectively improving the reliability and work efficiency of the chip and reducing labor costs.

[0085] Reference Figure 1 , shows a flowchart of a chip component layout optimization method embodiment of the present invention, which may specifically include the following steps:

[0086] Step 101, obtaining the operating parameters and spatial properties of each component in the chip; the operating parameters include at least one of thermal resistivity, operating current, and operating resistance; the spatial properties include at least one of maximum spacing, minimum spacing, position, and area.

[0087] In the embodiment of the present invention, thermal resistance coefficient is a parameter reflecting the heat dissipation capability of a component. The lower the thermal resistance, the better the heat dissipation performance.

[0088] Operating current / resistance: A key parameter that determines component power consumption and directly affects heat generation.

[0089] Position refers to the coordinate position of each component in the chip, maximum spacing refers to the maximum distance between components, minimum spacing refers to the minimum distance between components, and area refers to the size of each component in the chip.

[0090] Parameters such as thermal resistance, operating current, and operating resistance can be obtained from component datasheets or through testing. For example, a chip includes a microprocessor component. The thermal resistance of the microprocessor may be 0.5°C / W, the operating current is 2A, and the operating resistance is 5Ω. Then, the spatial properties of each component in the current chip can be obtained, such as the position coordinates of the microprocessor are (0.1, 0.2) and the area is 0.01m 2 .

[0091] Step 102 : determining candidate layouts of components in the chip based on the operating parameters and spatial properties of the components.

[0092] In an embodiment of the present invention, after obtaining the operating parameters and spatial properties of each component, a plurality of candidate layouts can be generated under the condition that the constraints are satisfied through a preset algorithm. The preset algorithm can be one of simulated annealing, genetic algorithm or particle swarm optimization algorithm, which is not limited here. For example, a genetic algorithm is used to simulate the biological evolution process to continuously iterate and optimize the layout scheme.

[0093] Step 103 : Determine the target layout of each component in the chip based on the candidate layout.

[0094] In an embodiment of the present invention, after obtaining candidate layouts, different candidate layouts may be compared, and a component layout that best meets user requirements may be selected as a target layout, and then the target layout may be output.

[0095] The present invention discloses a component layout optimization method for a chip. The present invention can determine candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component in the chip, and then determine a target layout based on the candidate layouts. The method can accurately predict the impact of various component layout schemes on the chip temperature distribution, can adapt to different process nodes and design requirements, and improve the flexibility and applicability of the design; through a multi-dimensional combination strategy, the target layout can achieve a balance in key indicators such as heat dissipation performance, signal integrity, and chip area, effectively improving the reliability and work efficiency of the chip and reducing labor costs.

[0096] In one embodiment of the present invention, candidate layouts of components in a chip are determined based on operating parameters and spatial properties of each component, including: determining an initial population; the initial population includes multiple individuals, each of the multiple individuals includes position parameters of each component in the chip; determining the fitness value of each individual in the initial population based on the operating parameters and spatial properties of each component in each individual; selecting an individual with a larger fitness value in the initial population as a parent individual; generating a new population by performing crossover and mutation operations on the parent individuals; and generating candidate layouts within a neighborhood of the new population.

[0097] In the embodiment of the present invention, the initial population refers to a set including multiple layout schemes. For example, an initial population includes multiple layout schemes, and the positions of components in each layout scheme are different.

[0098] The initial population can be generated using either random or heuristic methods. Random generation involves randomly assigning component positions within the chip layout, subject to basic constraints such as minimum spacing. Heuristic generation involves using prior knowledge (such as placing high-power components closer to heat dissipation zones) to construct partial initial solutions and improve search efficiency.

[0099] Fitness Value: A quantitative indicator that measures the quality of a layout, usually calculated by weighting multiple optimization parameters. This solution can determine the fitness value of each individual in the initial population based on the operating parameters and spatial properties of each component in each individual.

[0100] After determining the fitness value of each individual, better individuals can be selected from the current population as parents to generate the next generation. Common methods include roulette selection method and tournament selection method.

[0101] Roulette Wheel Selection: Randomly select according to the fitness value ratio. The higher the fitness, the greater the probability of being selected.

[0102] Tournament Selection: Several individuals are randomly selected to compete, and the one with the highest fitness wins.

[0103] You can choose any method to determine the parent individuals based on your needs. In one example, assume that the initial population has 100 individuals, and select the top 30% of the fitness ranking individuals (30) as the parent individuals.

[0104] Furthermore, gene exchange in biological inheritance can be simulated, and new individuals can be generated by combining some layout parameters of two parent individuals.

[0105] For example: Randomly select the positions of some components to inherit from parent A, and the rest to inherit from parent B.

[0106] Mutation: Randomly adjust the positions of certain components to prevent the algorithm from falling into local optimality.

[0107] For example, the 30 selected parent individuals are crossed in pairs to generate 50 offspring individuals, and mutations are applied to the offspring individuals, such as randomly adjusting the coordinates of 5 elements, to eventually obtain 80 new individuals (30 parents + 50 offspring) to form a new population.

[0108] Finally, local optimization is performed on the basis of the new population to generate candidate layouts. Individuals with high fitness can be fine-tuned, such as moving a single component to check whether performance is improved. For example, the top 10% of individuals (8) are selected from the new population, and their component positions are perturbed in a small range (such as ±5μm). If the new layout has higher fitness, the original individual is replaced, and finally a set of candidate layouts is output. The present invention generates a diverse initial population through random initialization, combined with the crossover and mutation operation of the genetic algorithm, which can widely explore the layout space and effectively avoid falling into the local optimal solution.

[0109] In one embodiment of the present invention, determining the initial population includes:

[0110] Determine the population size N;

[0111] For each individual Pi, generate the position parameters Xi=(xi1, yi1, xi2, yi2, …, xim, yim) of each component in the chip. The position parameters are the coordinate values ​​generated according to the specific position of each component, where m is the number of components.

[0112] Put all generated individuals Pi into the population P to form the initial population.

[0113] In an embodiment of the present invention, when determining the initial population, the size of the population can be determined first. The population size N determines the diversity and computational complexity of the initial layout scheme. Usually, depending on the complexity of the chip and the available computing resources, the value range of N is between 50-200. For chips with a small number of components and relatively simple layout constraints, a smaller N value can be selected; while for high-end chips with a large number of components and complex constraints, a larger N value tends to be selected to ensure sufficient initial diversity to support subsequent optimization searches.

[0114] After determining the population size, for each individual Pi, it is necessary to generate position parameters Xi for each component in the chip. This process is based on the spatial property requirements of the components, such as minimum spacing, maximum spacing and other constraints, and reasonably allocates component positions within the physical area of ​​the chip. Specifically, the position parameters Xi are composed of a series of coordinate values ​​(xi1, yi1, xi2, yi2, ..., xim, yim), where m is the number of components in the chip, and each pair of coordinate values ​​(xij, yij) corresponds to the position of the jth component in the i-th individual on the chip plane. When generating coordinate values, it is first necessary to ensure that the distance between components meets the minimum spacing constraint to avoid electromagnetic interference, poor heat dissipation and other problems caused by components being too close; at the same time When generating coordinates, the component position cannot exceed the physical boundaries of the chip, and the impact of the maximum spacing constraint on performance such as signal transmission delay must be taken into account. For example, for two high-frequency signal components, the spacing between them must be no less than the specified minimum spacing to prevent mutual signal interference; for components with high heat dissipation requirements, they should be avoided from being placed in the corners of the chip where the heat dissipation conditions are poor. In order to generate coordinate values ​​that meet these conditions, a method of random generation combined with constraint checking and correction can be used. First, a set of coordinate values ​​are randomly generated within the physical area of ​​the chip, and then the constraints such as the distance between components are checked. If they are not met, the coordinate values ​​are adjusted until the generated position parameters meet all spatial attribute constraints, thereby obtaining a reasonable individual layout solution.

[0115] After generating a satisfactory position parameter Xi for each individual Pi, all these individuals Pi are integrated and placed into a population P. This completes the construction of the initial population, which contains N different chip component layout schemes. Each scheme is a reasonable layout hypothesis generated based on the component's operating parameters and spatial property requirements. These initial layout schemes form the basis for subsequent genetic algorithm optimization iterations. Subsequent operations such as calculating fitness values, selecting parent individuals, and crossover mutation will continuously evolve based on the initial population, gradually screening out better layout schemes until the optimal layout that meets the chip performance optimization goal is found. For example, in the initial population, some individual layouts may focus on reducing signal transmission delays between components, while others may focus more on overall heat dissipation. As the genetic algorithm iterates, these layout schemes with different focuses compete and merge with each other, driving the layout scheme towards the direction of optimal overall performance. The initial population determination process provides an efficient, flexible, and scalable basic framework for the optimization of chip component candidate layouts through a design with controllable scale, standardized coding, guaranteed diversity, and standardized processes, effectively supporting the subsequent iterative evolution of the genetic algorithm.

[0116] In one embodiment of the present invention, the fitness value of each individual in the initial population is determined based on the working parameters and spatial attributes of each component in each individual, including: determining the position score of each individual in the initial population based on the spatial attributes of each component in each individual; determining the power consumption score of each individual in the initial population based on the working parameters of each component in each individual; determining the vector score of each individual in the initial population based on the working parameters and spatial attributes of each component in each individual; obtaining a first weight for the position score, a second weight for the power consumption score, and a third weight for the vector score; and determining the fitness value of each individual in the initial population based on the position score, power consumption score, and vector score of each individual in the initial population, and the first weight, second weight, and third weight.

[0117] In the embodiment of the present invention, the position score is a quantitative evaluation of the rationality of the spatial layout of components in an individual, and the position score of each individual can be determined based on the spatial attributes of the components in each individual.

[0118] The power consumption score is a quantitative assessment of the power consumption of each component in an individual based on operating parameters.

[0119] Vector scoring is a quantitative evaluation of each element in an individual in the vector direction based on working parameters and spatial properties.

[0120] After calculating the location score, power consumption score, and vector score of each individual, the first weight can be assigned to the location score, the second weight to the power consumption score, and the third weight to the vector score, where the first weight + the second weight + the third weight = 1. Then, based on the location score, power consumption score, and vector score of each individual in the initial population, and the first weight, the second weight, and the third weight, the fitness value of each individual in the initial population is determined, as shown in formula (1):

[0121] Formula (1)

[0122] Among them, S refers to the fitness value of each individual. Refers to the first weight, refers to the position score, refers to the second weight, refers to the power consumption score, Refers to the third weight, Refers to vector scoring; the present invention forms a fitness value through weighted summation of a multi-dimensional scoring system, providing a clear quantitative standard for individual selection of the genetic algorithm.

[0123] In one embodiment of the present invention, the position score of each individual in the initial population is determined based on the spatial attributes of each element in each individual, including: obtaining the center position coordinates in the chip; and determining the position score of each individual in the initial population based on the positions of each element in the single individual and the center position coordinates in the chip.

[0124] In the embodiment of the present invention, the position score of each individual in the initial population can be determined according to the spatial attributes of each element in each individual, as shown in formula (2):

[0125] Formula (2)

[0126] Among them, x refers to the horizontal coordinate of each element, and y refers to the vertical coordinate of each element. Refers to the horizontal coordinate of the center position in the chip, Refers to the vertical coordinate of the center position in the chip.

[0127] In one example, the position of component A is (x, y) = (0.1, 0.2), and the center position of the chip is (0.15, 0.25). It can be calculated that =14.14.

[0128] In one embodiment of the present invention, the power consumption score of each individual in the initial population is determined based on the operating parameters of each component in each individual, including: determining the power consumption score of each individual in the initial population based on the operating current and operating resistance of each component in a single individual.

[0129] In the embodiment of the present invention, the power consumption score of each individual in the initial population can be determined according to the operating parameters of each component in each individual, as shown in formula (3):

[0130] Formula (3)

[0131] in, Refers to the power consumption rating, I refers to the operating current of each component, and R refers to the operating resistance of each component.

[0132] In one example, the position of component A is (x, y) = (0.1, 0.2), the operating current is I = 1A, and the operating resistance is R = 0.1Ω. =10.

[0133] In one embodiment of the present invention, the vector score of each individual in the initial population is determined based on the working parameters and spatial properties of each component in each individual, including: respectively obtaining the offset of each component in a single individual in multiple vector directions; determining the temperature value of each component in multiple vector directions based on the offset of each component in multiple vector directions, the working parameters and spatial properties of each component; determining the vector score of each component based on the temperature value of each component in multiple vector directions; and determining the vector score of each individual in the initial population based on the vector score of each component.

[0134] In the embodiment of the present invention, the offset of each element in the eight vector directions can be obtained first, and then set ( ) is used for the offset in the 8 vector directions, and then the coordinate value of the current component is calculated based on the offset of each component in the 8 vector directions, that is, ( ).

[0135] Then, the temperature values ​​of each component in multiple vector directions can be determined based on the offset of each component in multiple vector directions, the operating parameters of each component, and the spatial properties, as shown in formula (4):

[0136] Formula (4)

[0137] Where T(x,y) represents the temperature at the chip position (x,y). represents the ambient temperature, I represents the current passing through the component, R(x,y) represents the component resistance at position (x,y), A(x,y) represents the component area at position (x,y), (x,y) represents the dynamic thermal resistance coefficient at position (x,y), d1(x,y) and d2(x,y) represent the minimum and maximum spacing between components at position (x,y), respectively.

[0138] The vector score of a single individual can be further calculated using the following formula:

[0139] Formula (5)

[0140] in, refers to the vector score, ( ) is used for offsets in 8 vector directions.

[0141] In one example, assuming that the temperatures in the eight vector directions are T1, T2, T3…, T1=80℃, T2=85℃, T3=90℃, T4=95, T5=100, T6=105, T7=110, T8=115℃, we can calculate =0.0832.

[0142] Assuming weighting factors: =0.3, =0.5, =0.2, then we can calculate =9.25864.

[0143] In one embodiment of the present invention, determining a target layout of each component in a chip based on a candidate layout includes: determining whether a preset termination condition is satisfied; and determining the target layout of each component in the chip based on the candidate layout if the preset termination condition is satisfied.

[0144] In an embodiment of the present invention, after obtaining a candidate layout, it may be determined whether a preset termination condition is satisfied. If the preset termination condition is satisfied, the current candidate layout is determined as the target layout.

[0145] In one example, the preset termination condition is that the chip temperature is lower than 75 degrees Celsius. The current temperature of the chip corresponding to the current candidate layout is 74.5 degrees Celsius, which means that the current candidate layout meets the preset termination condition. At this time, the candidate layout can be output as the target layout.

[0146] By presetting termination conditions, the present invention can determine in real time whether the optimal solution has been reached during the algorithm operation, avoiding meaningless over-computation. This allows chip layout optimization to quickly converge to a high-quality solution under limited resources, and ensure the comprehensive optimality of the target layout in terms of physical constraints and performance indicators through quantitative standards, effectively balancing the time cost and design accuracy requirements in engineering practice.

[0147] In one embodiment of the present invention, the preset termination condition includes reaching a preset number of iterations, or the temperature of the chip drops to a preset temperature.

[0148] In the embodiment of the present invention, the preset termination condition is an artificially set standard for measuring whether the optimization process can be stopped, and can be set according to user needs.

[0149] When the preset termination condition is reaching a preset number of iterations, for example, the preset termination condition is reaching 1000 iterations, when the iteration reaches the 1000th time, the current candidate layout is output as the target layout.

[0150] When the preset termination condition is that the chip temperature drops to a preset temperature, for example, the preset termination condition is that the chip temperature drops to 75°C, when the chip temperature drops to 74°C at the 63rd iteration, the current chip candidate layout can be used as the target layout.

[0151] The preset termination conditions in the present invention include reaching a preset number of iterations and the temperature of the chip dropping to a preset temperature. These two settings ensure the efficiency and performance of chip component layout optimization from different dimensions. On the one hand, reaching the preset number of iterations sets a clear time and computing resource boundary for the optimization process, preventing endless calculations due to falling into local optimal solutions, avoiding excessive consumption of computing resources and lengthening the design cycle, helping the project to proceed as planned, and improving R&D efficiency while ensuring design quality; on the other hand, the temperature of the chip drops to a preset temperature. By using the heat dissipation effect as a hard standard for optimization termination, it is ensured that the final target layout can effectively solve the chip thermal management problem, reduce the impact of high temperature on component performance and life, and enhance the stability and reliability of chip operation.

[0152] In one embodiment of the present invention, the method further includes: if the preset termination condition is not met, returning to the step of determining candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component, until the preset termination condition is met and the candidate layout is determined as the target layout.

[0153] In an embodiment of the present invention, when it is determined that the preset termination condition is not met, it is necessary to return to the step of determining the candidate layout of each component in the chip based on the working parameters and spatial properties of each component, until the preset termination condition is met, and then use the current candidate layout as the target layout; in one example, the preset termination condition is 500 iterations, and the current number of iterations is 498 times, which is less than 500 times, then it is necessary to continue to return to the step of re-determining the candidate layout of each chip based on the working parameters and spatial properties of each step, and repeat the above steps until the number of iterations reaches 500 times.

[0154] The present invention iterates the loop steps until the preset termination condition is met when the preset termination condition is not met, thereby ensuring that the chip layout design can obtain a layout solution that meets the performance requirements within a reasonable time and resource range, thereby improving the efficiency and success rate of chip design.

[0155] like Figure 2 , shows a flow chart of a chip component layout optimization method provided by an embodiment of the present invention, firstly, the population is initialized to obtain multiple individuals, then the fitness value of each individual is calculated, the individual with high fitness is used as the parent individual, and then new individuals are generated by genetic annealing combined with a multi-objective algorithm, and then the fitness value of the new individual is calculated to determine whether the preset termination condition is met. If the termination condition is met, the layout of the current new individual is output as the target layout. If the termination condition is not met, the process returns to the step of recalculating the fitness value of each individual until the preset termination condition is met.

[0156] The present invention discloses a component layout optimization method for a chip. The present invention can determine candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component in the chip, and then determine a target layout based on the candidate layouts. The method can accurately predict the impact of various component layout schemes on the chip temperature distribution, can adapt to different process nodes and design requirements, and improve the flexibility and applicability of the design; through a multi-dimensional combination strategy, the target layout can achieve a balance in key indicators such as heat dissipation performance, signal integrity, and chip area, effectively improving the reliability and work efficiency of the chip and reducing labor costs.

[0157] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0158] Reference Figure 3 , shows a structural block diagram of a chip component layout optimization device of the present invention, the device may include the following modules:

[0159] An acquisition module 201 is configured to acquire operating parameters and spatial properties of each component in the chip; the operating parameters include at least one of thermal resistivity, operating current, and operating resistance; and the spatial properties include at least one of maximum spacing, minimum spacing, position, and area.

[0160] A first determination module 202 is configured to determine candidate layouts of components in the chip based on operating parameters and spatial properties of the components;

[0161] The second determining module 203 is configured to determine a target layout of each component in the chip based on the candidate layouts.

[0162] The present invention discloses a device for optimizing the component layout of a chip. The device can determine candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component in the chip, and then determine a target layout based on the candidate layouts. The device can accurately predict the impact of various component layout schemes on the chip temperature distribution, adapt to different process nodes and design requirements, and improve the flexibility and applicability of the design. Through a multi-dimensional combination strategy, the target layout can achieve a balance in key indicators such as heat dissipation performance, signal integrity, and chip area, effectively improving the reliability and work efficiency of the chip and reducing labor costs.

[0163] In one embodiment of the present invention, the first determining module includes:

[0164] The first determination submodule is used to determine an initial population; the initial population includes a plurality of individuals, each of the plurality of individuals including position parameters of each component in the chip;

[0165] The second determination submodule is used to determine the fitness value of each individual in the initial population based on the working parameters and spatial properties of each component in each individual;

[0166] The selection submodule is used to select individuals with larger fitness values ​​in the initial population as parent individuals;

[0167] The first generation submodule is used to generate a new population by performing crossover and mutation operations on parent individuals;

[0168] The second generation submodule is used to generate candidate layouts in the neighborhood of the new population.

[0169] In one embodiment of the present invention, the first determining submodule includes:

[0170] A first determining unit, configured to determine a population size N;

[0171] A generation unit is used to generate, for each individual Pi, the position parameters Xi = (xi1, yi1, xi2, yi2, ..., xim, yim) of each component in the chip. The position parameters are coordinate values ​​generated according to the specific position of each component, where m is the number of components;

[0172] The formation unit is used to put all generated individuals Pi into the population P to form the initial population.

[0173] In one embodiment of the present invention, the second determining submodule includes:

[0174] a position score determination unit, for determining a position score for each individual in the initial population based on the spatial attributes of each element in each individual;

[0175] a power consumption score determination unit, configured to determine a power consumption score of each individual in the initial population based on an operating parameter of each component in each individual;

[0176] A vector score determination unit, configured to determine a vector score for each individual in the initial population based on the operating parameters and spatial properties of each component in each individual;

[0177] a weight acquisition unit, configured to acquire a first weight of a location score, a second weight of a power consumption score, and a third weight of a vector score;

[0178] The second determining unit is used to determine the fitness value of each individual in the initial population according to the position score, power consumption score and vector score of each individual in the initial population, and the first weight, the second weight and the third weight.

[0179] In one embodiment of the present invention, the location score determination unit includes:

[0180] A first acquisition subunit is used to acquire the center position coordinates in the chip;

[0181] The first determination subunit is used to determine the position score of a single individual in the initial population according to the position of each component in the single individual and the center position coordinates in the chip.

[0182] In one embodiment of the present invention, a power consumption score determining unit includes:

[0183] The second determining subunit is configured to determine the power consumption score of a single individual in the initial population according to the operating current and the operating resistance of each component in the single individual.

[0184] In one embodiment of the present invention, the vector score determination unit includes:

[0185] The second acquisition subunit is used to respectively acquire the offset of each element in a single individual in multiple vector directions;

[0186] a third determining subunit, configured to determine the temperature value of each element in the multiple vector directions according to the offset of each element in the multiple vector directions, the operating parameters of each element, and the spatial properties;

[0187] a fourth determining subunit, configured to determine a vector score of each component according to the temperature values ​​of each component in a plurality of vector directions;

[0188] The fifth determining subunit is configured to determine the vector score of each individual in the initial population according to the vector scores of the respective elements.

[0189] In one embodiment of the present invention, the second determining module includes:

[0190] The judgment submodule is used to judge whether the preset termination condition is met;

[0191] The third determining submodule is configured to determine a target layout of each component in the chip according to the candidate layouts when a preset termination condition is met.

[0192] In one embodiment of the present invention, the preset termination condition includes reaching a preset number of iterations, or the temperature of the chip drops to a preset temperature.

[0193] In one embodiment of the present invention, the present invention further includes:

[0194] The fourth determination submodule is used to return to the step of determining the candidate layout of each component in the chip according to the operating parameters and spatial properties of each component if the preset termination condition is not met, until the preset termination condition is met and the candidate layout is determined as the target layout.

[0195] The present invention discloses a device for optimizing the component layout of a chip. The device can determine candidate layouts of each component in the chip based on the operating parameters and spatial properties of each component in the chip, and then determine a target layout based on the candidate layouts. The device can accurately predict the impact of various component layout schemes on the chip temperature distribution, adapt to different process nodes and design requirements, and improve the flexibility and applicability of the design. Through a multi-dimensional combination strategy, the target layout can achieve a balance in key indicators such as heat dissipation performance, signal integrity, and chip area, effectively improving the reliability and work efficiency of the chip and reducing labor costs.

[0196] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0197] An embodiment of the present invention further provides an electronic device, including:

[0198] The present invention comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, each process of the above-mentioned chip component layout optimization method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0199] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned chip component layout optimization method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0200] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0201] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatuses, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0202] The embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0203] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0204] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0205] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0206] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0207] The above is a detailed introduction to the component layout optimization method, device, equipment and medium of a chip provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for optimizing chip component layout, characterized in that: The method comprises: Obtaining operating parameters and spatial properties of each component in the chip; the operating parameters include at least one of thermal resistance coefficient, operating current, and operating resistance; the spatial properties include at least one of maximum spacing, minimum spacing, position, and area; determining candidate layouts of the components in the chip based on the operating parameters and spatial properties of the components; determining a target layout of each component in the chip based on the candidate layout; Determining the target layout of each component in the chip based on the candidate layouts includes: determining the candidate layout whose temperature reaches a preset temperature as the target layout of each component in the chip; Determining a candidate layout of each component in the chip according to the operating parameters and spatial properties of each component includes: Determine an initial population; the initial population includes a plurality of individuals, each of the plurality of individuals including position parameters of each component in the chip; determining a position score for each individual in the initial population based on the spatial attributes of each element in each individual; determining a power consumption score of each individual in the initial population according to an operating parameter of each component in each individual; Obtain the offset of each component in a single entity in multiple vector directions respectively; determining temperature values ​​of the respective elements in the plurality of vector directions according to offsets of the respective elements in the plurality of vector directions, operating parameters of the respective elements, and spatial properties; determining a vector score for each component according to temperature values ​​of each component in a plurality of vector directions; determining a vector score of a single individual in the initial population based on the vector scores of the respective elements; Obtaining a first weight of the location score, a second weight of the power consumption score, and a third weight of the vector score; Determining a fitness value of each individual in the initial population according to the position score, power consumption score, and vector score of each individual in the initial population, and the first weight, the second weight, and the third weight; Determining a parent individual from the initial population according to the fitness value of each individual in the initial population; Generate a new population by performing crossover and mutation operations on the parent individuals; The candidate layouts are generated within a neighborhood of the new population.

2. The chip component layout optimization method according to claim 1, characterized in that: The determining of the initial population comprises: Determine the population size N; For each individual Pi, generate the position parameters Xi=(xi1, yi1, xi2, yi2, ..., xim, yim) of each element in the chip, where the position parameters are coordinate values ​​generated according to the specific positions of the elements, where m is the number of elements; All generated individuals Pi are placed into the population P to form the initial population.

3. The chip component layout optimization method according to claim 1, characterized in that: Determining the position score of each individual in the initial population according to the spatial attributes of each element in each individual includes: Obtaining the center position coordinates in the chip; The position score of each individual in the initial population is determined according to the position of each element in the individual and the center position coordinates in the chip.

4. The chip component layout optimization method according to claim 1, characterized in that: Determining the power consumption score of each individual in the initial population according to the operating parameters of each component in each individual includes: The power consumption score of each individual in the initial population is determined according to the operating current and the operating resistance of each component in the individual.

5. The chip component layout optimization method according to claim 1, characterized in that: Determining a target layout of each component in the chip according to the candidate layout includes: Determine whether the preset termination condition is met; When the preset termination condition is met, a target layout of each component in the chip is determined according to the candidate layout.

6. The chip component layout optimization method according to claim 5, characterized in that: The preset termination condition includes reaching a preset number of iterations, or the temperature of the chip drops to a preset temperature.

7. The chip component layout optimization method according to claim 5, characterized in that: Also includes: If the preset termination condition is not met, the process returns to the step of determining candidate layouts of the components in the chip according to the operating parameters and spatial properties of the components, until the preset termination condition is met and the candidate layout is determined as the target layout.

8. A device for optimizing chip component layout, characterized in that: The device comprises: an acquisition module, configured to acquire operating parameters and spatial properties of each component in the chip; the operating parameters including at least one of thermal resistance coefficient, operating current, and operating resistance; and the spatial properties including at least one of maximum spacing, minimum spacing, position, and area; A first determining module, configured to determine a candidate layout of each component in the chip based on the operating parameters and spatial properties of each component; a second determining module, configured to determine a target layout of each component in the chip based on the candidate layout; and a second determining module, configured to determine a candidate layout whose temperature reaches a preset temperature as the target layout of each component in the chip; The first determining module includes: A first determination submodule is configured to determine an initial population; the initial population includes a plurality of individuals, each of the plurality of individuals including position parameters of each component in the chip; a position score determining unit, configured to determine a position score of each individual in the initial population based on a spatial attribute of each element in each individual; a power consumption score determining unit, configured to determine a power consumption score of each individual in the initial population based on an operating parameter of each component in each individual; The second acquisition subunit is used to respectively acquire the offset of each element in a single individual in multiple vector directions; a third determining subunit, configured to determine the temperature values ​​of the respective elements in the plurality of vector directions according to the offsets of the respective elements in the plurality of vector directions, the operating parameters of the respective elements, and the spatial properties; a fourth determining subunit, configured to determine a vector score of each component according to temperature values ​​of each component in a plurality of vector directions; a weight acquiring unit, configured to acquire a first weight of the location score, a second weight of the power consumption score, and a third weight of the vector score; a second determining unit, configured to determine a fitness value of each individual in the initial population according to a position score, a power consumption score, and a vector score of each individual in the initial population, and the first weight, the second weight, and the third weight; A selection submodule, configured to determine a parent individual from the initial population according to the fitness value of each individual in the initial population; A first generation submodule is used to generate a new population by performing crossover and mutation operations on the parent individuals; The second generation submodule is configured to generate the candidate layout within the neighborhood of the new population.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the chip component layout optimization method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip component layout optimization method according to any one of claims 1 to 7 are implemented.

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