A chip layout determination method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a chip layout determination method and device, electronic equipment and storage medium, the method comprising: obtaining initialization information and a preset key value of a chip; the chip comprising a power interface module and a plurality of power management modules; the initialization information comprising the position of the power interface module; the preset key value comprising the grade coefficient and weight constant of the plurality of power management modules; determining the weight value between each two of the plurality of power management modules according to the grade coefficient and weight constant; arranging the plurality of power management modules according to the position of the power interface module and the weight value between each two of the plurality of power management modules, to obtain a plurality of candidate chip layouts; and selecting a target chip layout from the plurality of candidate chip layouts. Thus, the plurality of power management modules in the chip are automatically arranged, without relying on engineers with rich experience to manually plan the layout, thereby saving a large amount of time and labor costs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip layout, in particular to a chip layout determination method, a chip layout determination device, an electronic device and a computer readable storage medium. BACKGROUND

[0002] In the field of chips, analog layout is a key link in the design of analog circuits. With the increasing integration of integrated circuits, the design complexity of analog circuits also increases, and analog circuits generally have strict requirements for precision, noise, power consumption and stability. These characteristics are largely affected by the layout design of analog circuits. The design and implementation of the layout of a PMU (Power Management Unit, power management unit) is an important part of analog circuits, which provides stable power supply and reference voltage for chips. In related technologies, when performing top-level layout of the PMU layout, layout planning needs to be performed according to the rich experience of analog layout engineers, which requires a large amount of time and labor costs. SUMMARY

[0003] In view of the above problems, the present application embodiment is proposed in order to provide a chip layout determination method, a chip layout determination device, an electronic device and a computer readable storage medium which overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, the present application embodiment discloses a chip layout determination method, comprising:

[0005] Obtain initialization information and a preset key value of a chip; the chip comprises a power interface module and a plurality of power management modules; the initialization information comprises the position of the power interface module; the preset key value comprises the grade coefficient and the weight constant of the plurality of power management modules;

[0006] According to the grade coefficient and the weight constant, determine the weight value between each two of the plurality of power management modules;

[0007] According to the position of the power interface module and the weight value between each two of the plurality of power management modules, layout the plurality of power management modules to obtain a plurality of candidate chip layouts;

[0008] Select a target chip layout from the plurality of candidate chip layouts.

[0009] Optionally, the plurality of power management modules comprises a low dropout linear regulator module; and the plurality of power management modules are arranged according to positions of the power interface modules and weight values between the plurality of power management modules, to obtain a plurality of candidate chip layouts, comprising:

[0010] The position of the low dropout linear regulator module is determined according to the positions of the power interface modules;

[0011] After the position of the low dropout linear regulator module is determined, the positions of the power management modules whose positions are not determined are determined according to the weight values between the plurality of power management modules, to obtain the plurality of candidate chip layouts.

[0012] Optionally, the positions of the power management modules whose positions are not determined are determined according to the weight values between the plurality of power management modules, comprising:

[0013] The weight values between the plurality of power management modules are sorted;

[0014] According to the sorting result, the positions of the power management modules whose positions are not determined are sequentially allocated according to a plurality of placement rules; the plurality of placement rules comprise right-side adjacent placement, upper-side adjacent placement, left-side adjacent placement and lower-side adjacent placement.

[0015] Optionally, the positions of the power management modules whose positions are not determined are sequentially allocated according to the sorting result and the plurality of placement rules, comprising:

[0016] According to the order of the sorting result, two target power management modules corresponding to the weight values are sequentially determined;

[0017] When the two target power management modules contain the power management module whose position is determined, the position of the other target power management module is allocated according to the position of the power management module whose position is determined and the plurality of placement rules;

[0018] When the two target power management modules are both the power management modules whose positions are not determined, the positions of the two target power management modules are allocated according to the weight values between the two target power management modules, the weight values between the plurality of power management modules, the positions of the power management modules whose positions are determined and the plurality of placement rules.

[0019] Optionally, the initialization information further comprises boundary constraints of the chip; and after the positions of the power management modules whose positions are not determined are sequentially allocated according to the sorting result and the plurality of placement rules, the method further comprises:

[0020] When the assigned position of the power management module does not meet the boundary constraint condition, or the assigned position is occupied, the positions of other power management modules are automatically switched according to the multiple placement rules until the assigned position determined meets the boundary constraint condition and the assigned position is not occupied.

[0021] Optionally, after the assigning positions to the power management modules without determined positions according to the sorting result and the multiple placement rules, the method further includes:

[0022] When the assigned positions of the power management modules are all occupied, the assigning to the power management modules without determined positions is continued after skipping the occupied positions until the assigned position is not occupied.

[0023] Optionally, the filtering of the target chip layout from the multiple candidate chip layouts includes:

[0024] determining a space utilization rate and a balance coefficient corresponding to the multiple candidate chip layouts;

[0025] from the multiple candidate chip layouts, determining a candidate chip layout with a space utilization rate meeting a preset utilization rate interval;

[0026] determining, as the target chip layout, a candidate chip layout with the smallest balance coefficient from the candidate chip layouts with the space utilization rate meeting the preset utilization rate interval.

[0027] Optionally, after the assigning positions to the power management modules without determined positions according to the sorting result and the multiple placement rules, the method further includes:

[0028] When the assigned position is abnormal, the assigning to the power management modules without determined positions is interrupted, and abnormal information is output.

[0029] Optionally, the balance coefficient is calculated from the weight values between two power management modules.

[0030] Embodiments of the application further provide a chip layout determination device, including:

[0031] An acquisition module is configured to acquire initialization information and a preset key value of a chip; the chip includes a power interface module and multiple power management modules; the initialization information includes a position of the power interface module; and the preset key value includes a level coefficient and a weight constant of the multiple power management modules.

[0032] A determination module is configured to determine weight values between two power management modules according to the level coefficient and the weight constant.

[0033] a layout module, configured to layout a plurality of power management modules according to positions of the power interface modules and weight values between the power management modules two by two, to obtain a plurality of candidate chip layouts;

[0034] a screening module, configured to screen a target chip layout from the plurality of candidate chip layouts.

[0035] Optionally, the plurality of power management modules comprises a low-dropout linear regulator module; and the layout module comprises:

[0036] a first determining sub-module, configured to determine positions of the low-dropout linear regulator modules according to the positions of the power interface modules;

[0037] a second determining sub-module, configured to determine positions of the power management modules without determined positions according to the weight values between the power management modules two by two after determining the positions of the low-dropout linear regulator modules, to obtain the plurality of candidate chip layouts.

[0038] Optionally, the second determining sub-module comprises:

[0039] a sorting unit, configured to sort the weight values between the power management modules two by two;

[0040] a first allocating unit, configured to allocate positions to the power management modules without determined positions according to a plurality of placement rules in sequence according to a sorting result; the plurality of placement rules comprise right-side adjacent placement, upper-side adjacent placement, left-side adjacent placement and lower-side adjacent placement.

[0041] Optionally, the first allocating unit comprises:

[0042] a first determining sub-unit, configured to determine two target power management modules corresponding to the weight values in sequence according to the sorting result;

[0043] a first allocating sub-unit, configured to allocate a position of another target power management module according to the position of the power management module with determined position when the two target power management modules contain the power management module with determined position;

[0044] a second allocating sub-unit, configured to allocate positions of the two target power management modules according to the weight value between the two target power management modules, the weight values between the power management modules two by two and the positions of the power management modules with determined positions according to the plurality of placement rules when the two target power management modules are both the power management modules without determined positions.

[0045] Optionally, the initialization information further comprises boundary constraint conditions of the chip; and the second determining sub-module further comprises:

[0046] The second allocating unit is configured to automatically switch positions of other power management modules according to the multiple placement rules when the allocated position of the power management module does not meet the boundary constraint conditions or the allocated position is occupied, until the allocated position determined meets the boundary constraint conditions and the allocated position is not occupied.

[0047] Optionally, the second determining sub-module further comprises:

[0048] The third allocating unit is configured to continue allocating the power management modules in the undetermined positions by skipping the occupied positions and according to the multiple placement rules, until the allocated position is not occupied, when the allocated positions of the power management modules are all occupied.

[0049] Optionally, the screening module comprises:

[0050] The third determining sub-module is configured to determine space utilization rates and balance coefficients corresponding to the multiple candidate chip layouts;

[0051] The fourth determining sub-module is configured to determine, from the multiple candidate chip layouts, a candidate chip layout whose space utilization rate meets a preset utilization rate interval;

[0052] The fifth determining sub-module is configured to determine, as a target chip layout, a candidate chip layout whose balance coefficient is the smallest in the candidate chip layouts whose space utilization rates meet the preset utilization rate interval.

[0053] Optionally, the second determining sub-module further comprises:

[0054] The output unit is configured to interrupt the allocation of the positions of the power management modules in the undetermined positions and output abnormal information when the allocated position is abnormal.

[0055] Optionally, the balance coefficient is calculated from weight values between two power management modules.

[0056] The application further discloses an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the chip layout determining method when executing the computer program.

[0057] The application further discloses a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the chip layout determining method when executed by a processor.

[0058] Embodiments of the present application include the following advantages:

[0059] In the embodiments of the present application, when the chip is laid out, the initialization information of the chip and the preset key value are acquired first, wherein the initialization information includes the position of the power interface module, and the preset key value includes the level coefficient and the weight constant of the plurality of power management modules; then the weight value between the plurality of power management modules is determined according to the level coefficient and the weight constant; then the plurality of power management modules is laid out according to the position of the power interface module and the weight value between the plurality of power management modules, to obtain a plurality of candidate chip layouts; finally, the target chip layout is selected from the plurality of candidate chip layouts. Thus, the plurality of power management modules in the chip is automatically laid out based on the level coefficient and the weight constant of the plurality of power management modules and the position of the power interface module, without relying on engineers with rich experience to manually plan the layout, thereby saving a large amount of time cost and labor cost. BRIEF DESCRIPTION OF DRAWINGS

[0060] Figure 1 is a step flow chart of a chip layout determination method provided by the embodiments of the present application;

[0061] Figure 2 is a structural block of a chip layout provided by the embodiments of the present application Figure One ;

[0062] Figure 3 is a structural block of a chip layout provided by the embodiments of the present application Figure Two ;

[0063] Figure 4 is a structural block of a chip layout provided by the embodiments of the present application Figure Three ;

[0064] Figure 5 is a structural block of a chip layout provided by the embodiments of the present application Figure Four ;

[0065] Figure 6 is a structural block of a chip layout provided by the embodiments of the present application Figure Five ;

[0066] Figure 7 is a structural block of a chip layout provided by the embodiments of the present application Figure Six ;

[0067] Figure 8 is a structural block of a chip layout provided by the embodiments of the present application Figure Seven ;

[0068] Figure 9is a structural block diagram of a chip layout determination device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the above-mentioned objectives, features and advantages of the present application more apparent and comprehensible, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0070] In the related art, when performing PMU layout top layer layout, layout planning needs to be performed according to rich experience of analog layout engineers, which needs to consume a large amount of time cost and labor cost. In order to solve the above technical problem, the present application provides a chip layout determination method, the core idea of which is that when performing layout on a chip, initialization information and preset key values of the chip can be acquired first, wherein the initialization information includes the position of a power interface module, and the preset key values include the grade coefficients and weight constants of a plurality of power management modules. Then, the weight values between the plurality of power management modules are determined according to the grade coefficients and weight constants. Then, the plurality of power management modules are laid out according to the position of the power interface module and the weight values between the plurality of power management modules, to obtain a plurality of candidate chip layouts. Finally, a target chip layout is selected from the plurality of candidate chip layouts. Thus, based on the grade coefficients and weight constants of the plurality of power management modules and the position of the power interface module, the plurality of power management modules in the chip are automatically laid out, without relying on engineers with rich experience to perform manual layout planning, thereby saving a large amount of time cost and labor cost.

[0071] REFERENCE Figure 1 , a step flowchart of a chip layout determination method provided by an embodiment of the present application is shown, and the method can specifically include the following steps:

[0072] In step 101, initialization information and preset key values of a chip are acquired; the chip includes a power interface module and a plurality of power management modules; the initialization information includes the position of the power interface module; and the preset key values include the grade coefficients and weight constants of the plurality of power management modules.

[0073] In the embodiment of the present application, the chip can be a PMU, and the chip layout can also be a layout for the PMU. When performing layout on the chip, initialization information and preset key values of the chip can be acquired first, wherein the initialization information can include the position of the power interface module, and the power interface module can be an integrated module of a VOD (Voltage Drain Drain) module, an IO (Input / Output) module and a PAD (Bonding Pad) module. The preset key values can include the grade coefficients and weight constants of the plurality of power management modules.

[0074] In the application, each power management module corresponds to a level coefficient, in the analog circuit, signal lines can be classified according to different standards, for example: according to the signal frequency, the signal lines can be divided into low frequency signal lines, medium frequency signal lines and high frequency signal lines, according to the signal sensitivity, the signal lines can be divided into low sensitivity signal lines, medium sensitivity signal lines and high sensitivity signal lines, etc., wherein the high frequency signal line is easy to cause interference to other signal lines in the chip layout, causing the phenomenon of chip function disorder, therefore, special processing is needed for this kind of signal line, reducing the distance of this kind of signal line across the chip, for example: double line width is used for high frequency signal line to avoid EM effect, double spacing is used to avoid crosstalk between signals. Therefore, the level coefficient in the application can be defined as the degree that the signal line priority meets the shortest distance of the line crossing distance, that is, the size of the level coefficient in the application represents the distance of the signal line layout of the power management module in the chip.

[0075] In the application, the level coefficient can be represented by , wherein N represents the value of the level coefficient, the larger the value is, the higher the level coefficient is, and the shorter the distance of the signal line crossing the chip layout should be satisfied in priority. In the application, the specific value of N can be set according to actual needs, which is not limited in the application.

[0076] In the application, in the layout of the analog circuit, the line distance of each signal line can be balanced according to actual needs to achieve a relatively reasonable parasitic environment, therefore, the weight constant is introduced in the application to balance the relationship between a single signal line with a high level coefficient and multiple signal lines with low level coefficients, that is, the weight constant in the application represents the weight of the signal line of the power management module. In the application, the weight constant can be defined as: the priority value of b signal lines with a level coefficient of is equal to that of 1 signal line with a level coefficient of , the weight constant is represented by , , that is , wherein represents 1 signal line with a level coefficient of , and the weight constant of b signal lines with a level coefficient of . The weight constant in the application can be set according to actual needs , represents 1 signal line with a level coefficient of , and the weight constant of b signal lines with a level coefficient of .

[0077] Step 102, according to the level coefficient and the weight constant, determining the weight value between each two of the plurality of power management modules.

[0078] ​In this invention, after obtaining the chip's processing information and preset keywords, the weight values ​​between multiple power management modules can be determined based on the level coefficients and weight constants.

[0079] In this invention, the weight value of any power management module in the chip relative to other power management modules can be calculated using a rank coefficient and a weight constant. That is, the weight values ​​between multiple power management modules can be calculated. Thus, during layout, adjacent placement can be prioritized based on the magnitude of the weight values. In this invention, the magnitude of the weight values ​​represents the priority order of placing two power management modules adjacent to each other.

[0080] For example: This indicates the weight value between the first power management module and the second power management module. Where b is the rank coefficient. The number of signal lines, where N is the number of power management modules. This indicates that the root grade coefficient is 1 The signal line for the b-th root has a level coefficient of 1. The weight constant of the signal line.

[0081] Step 103: Based on the position of the power interface module and the weight values ​​between each pair of the power management modules, the power management modules are laid out to obtain multiple candidate chip layouts.

[0082] In the embodiments of the invention, after determining the weight values ​​between each pair of multiple power management modules, the multiple power management modules can be laid out according to the position of the power interface module and the weight values ​​between each pair of multiple power management modules to obtain a variety of candidate chip layouts.

[0083] In an embodiment of the invention, the multiple power management modules include: a low-dropout linear regulator module; the multiple power management modules are laid out according to the position of the power interface module and the weight values ​​between each pair of the multiple power management modules to obtain multiple candidate chip layouts, including: determining the position of the low-dropout linear regulator module according to the position of the power interface module; after determining the position of the low-dropout linear regulator module, determining the position of the power management module whose position is not determined according to the weight values ​​between each pair of the multiple power management modules to obtain multiple candidate chip layouts.

[0084] In this invention, the low dropout linear regulator module can be an LDO (Low Dropout Regulator) module. The location of the LDO module can be determined based on the location of the power interface module, and the LDO module is arranged adjacent to the power interface module. For example... Figure 2 The diagram illustrates a structural framework of a chip layout provided by an embodiment of the present invention. Figure Onewherein MM represents a power interface module. After determining the position of the LDO module, the positions of the power management modules with undetermined positions can be determined according to the weight values between the power management modules, to obtain a plurality of chip layouts. Thus, the position of the low-dropout linear regulator module can be accurately determined based on the position of the power interface module, so that the low-dropout linear regulator module can be connected to the power management module at the shortest distance.

[0085] In the embodiments of the application, the positions of the power management modules with undetermined positions are determined according to the weight values between the power management modules, including: sorting the weight values between the power management modules; and according to the sorting result, sequentially assigning positions to the power management modules with undetermined positions according to a plurality of placement rules.

[0086] After determining the position of the low-dropout linear regulator module, the weight values between the power management modules can be sorted from high to low to obtain a sorting result, and then the positions of the power management modules with undetermined positions can be sequentially assigned according to a plurality of placement rules according to the sorting result, so that the power management modules can be automatically laid out according to the weight values and the plurality of placement rules when the plurality of power management modules are laid out.

[0087] In the embodiments of the application, the plurality of placement rules can include right-side adjacent placement, upper-side adjacent placement, left-side adjacent placement and lower-side adjacent placement. For example, one placement rule is to sequentially place according to the priority of right-side adjacent placement, upper-side adjacent placement, left-side adjacent placement and lower-side adjacent placement. Another placement rule is to place according to the priority of upper-side adjacent placement, left-side adjacent placement, lower-side adjacent placement and right-side adjacent placement.

[0088] In the embodiments of the application, the positions of the power management modules with undetermined positions are sequentially assigned according to a plurality of placement rules according to the sorting result, including: two target power management modules corresponding to the weight values are sequentially determined according to the order of the sorting result; when the two target power management modules contain a power management module with a determined position, the position of the other target power management module is assigned according to the plurality of placement rules and the position of the power management module with the determined position; when the two target power management modules are both power management modules with undetermined positions, the positions of the two target power management modules are assigned according to the plurality of placement rules, the weight values between the two target power management modules, the weight values between the power management modules, and the positions of the power management modules with the determined positions.

[0089] In the present application, according to the order of the sorting result, two target power management modules with the largest weight value can be determined first. When there is a power management module with a determined position in the two target power management modules, the position of another target power management module can be allocated according to the position of the power management module with a determined position and according to the multiple placement rules. According to the above example in the present embodiment, the power management module with a determined position is only the LDO module. Then, it can be determined whether there is an LDO module in the two target power management modules. If there is an LDO module, the position of another target power management module can be allocated according to the multiple placement rules. At this time, the position of another target power management module is adjacent to the LDO module. When there is no LDO module in the two target power management modules, the positions of the two target power management modules can be allocated according to the multiple placement rules. Meanwhile, the target power management module with a higher weight value can be preferentially placed adjacent to the LDO module according to the weight values of the two target power management modules and the LDO module. Then, the two target power management modules corresponding to the weight values can be determined in turn according to the order of the sorting result, and the positions of the target power management modules can be allocated.

[0090] When the two target power management modules are both power management modules with undetermined positions, i.e., the positions of the two power management modules are determined for the first time, it is first determined whether there is a power management module with the highest weight value for the existing power management module with a determined position in the two target power management modules. If there is a power management module with the highest weight value for the existing power management module with a determined position in the two target power management modules, the position of the target power management module can be allocated according to the multiple placement rules, and the position of another target power management module can be allocated according to the multiple placement rules. If there is no power management module with the highest weight value for the existing power management module with a determined position in the two target power management modules, the two target power management modules can be classified according to the multiple placement rules, and the target power management module with a higher weight value for the remaining power management module with an undetermined position in the two target power management modules can be placed away from the chip boundary.

[0091] In the present application, the initialization information can also include a preset distance between the power management modules. When the positions of the power management modules are allocated, the positions of the power management modules can be allocated according to the preset distance. Thus, the present application can arrange the target power management modules according to different situations in turn according to the sorting result of the weight values between the power management modules two by two, so as to make the wiring distance between the power management modules in the arranged chip the shortest.

[0092] The initialization information in the embodiment of the present application further comprises boundary constraint conditions of the chip; and after the power management modules with undetermined positions are sequentially allocated positions according to the sorting result and the plurality of placement rules, the embodiment further comprises: when the allocated positions of the power management modules do not conform to the boundary constraint conditions, or the allocated positions are occupied, the positions of other power management modules are automatically switched according to the plurality of placement rules until the allocated positions determined conform to the boundary constraint conditions and the allocated positions are not occupied.

[0093] In the present application, when the allocated positions of the power management modules do not conform to the boundary constraint conditions, i.e., the allocated positions exceed the boundary of the chip, the positions of other power management modules can be automatically switched and allocated according to the plurality of placement rules, or when the allocated positions exist the power management modules determined, the positions of other power management modules can be automatically switched and allocated according to the plurality of placement rules. Thus, the phenomenon that the power management modules are laid out beyond the boundary of the chip and the phenomenon that multiple power management modules are allocated to the same position are avoided.

[0094] In the embodiment of the present application, after the power management modules with undetermined positions are sequentially allocated positions according to the sorting result and the plurality of placement rules, the embodiment further comprises: when the allocated positions of the power management modules are all occupied, the occupied positions are skipped and the power management modules with undetermined positions are continuously allocated according to the plurality of placement rules until the allocated positions are not occupied.

[0095] In the present application, when the positions are allocated according to the plurality of placement rules and the allocated positions all exist the power management modules determined, i.e., the positions cannot be allocated according to the plurality of placement rules, the power management modules with determined positions can be skipped and the positions can be continuously allocated according to the plurality of placement rules to form the layout of the automatically switched power management modules. Thus, the phenomenon that the positions cannot be allocated due to the occupation of the positions when the positions of the power management modules are allocated is avoided.

[0096] Step 104: filtering a target chip layout from the plurality of candidate chip layouts.

[0097] In the present application, after the plurality of candidate chip layouts are obtained, the target chip layout can be filtered from the plurality of candidate chip layouts.

[0098] In the embodiment of the present application, filtering the target chip layout from the plurality of candidate chip layouts comprises: determining the space utilization rate and the balance coefficient corresponding to the plurality of candidate chip layouts; determining the candidate chip layout with the space utilization rate conforming to the preset utilization rate interval from the plurality of candidate chip layouts; and determining the candidate chip layout with the minimum balance coefficient in the candidate chip layout with the space utilization rate conforming to the preset utilization rate interval as the target chip layout.

[0099] In the present application, for a plurality of candidate chip layouts, the space utilization and the balance coefficient of each candidate chip layout can be determined, and then the candidate chip layout with the space utilization meeting the preset utilization interval can be determined, the preset utilization interval can be greater than or equal to 70% and less than or equal to 80%, and the specific interval value of the preset utilization interval can be set according to actual needs, which is not specifically limited in the present application. After determining the candidate chip layout with the space utilization meeting the preset utilization interval, the candidate chip layout with the smallest balance coefficient can be determined as the target chip layout. In the present application, the balance coefficient represents the rationality of the candidate chip layout. The smaller the balance coefficient is, the more reasonable the layout is, so that the most reasonable and most cost-saving layout can be determined according to the space utilization and the balance coefficient.

[0100] In the present application, the balance coefficient is calculated by the weight values between the power management modules two by two. For example, the balance coefficient can be calculated by the following formula (1):

[0101]

[0102] Formula (1)

[0103] wherein S represents the balance coefficient, represents the weight value of the first power management module and the nth power management module, represents the distance from the first power management module to the center point of the nth power management module. Each term in formula (1) represents the weight value of the required power management module multiplied by the distance to any power management module, and then the balance coefficient is accumulated. Thus, the balance coefficient calculated by the weight value meets the requirement of more reasonable layout.

[0104] In the embodiment of the present application, according to the sorting result, after the position of the power management module with an undetermined position is allocated according to a plurality of placement rules, it further includes: when the allocation of the position of the power management module with an undetermined position is interrupted, and an abnormal information is outputted.

[0105] In the present application, when an abnormality occurs during the allocation of the position of the power management module, the abnormality can indicate that the position of the power management module cannot be allocated by the layout method of the present application, or the current chip layout is too complex to be automatically completed. The allocation of the position of the power management module can be interrupted to stop the automatic layout, and an abnormal information can be outputted to remind the engineer, so that the engineer can timely adjust the layout of the chip, and the efficiency of the chip layout is improved, so as to avoid affecting the automatic layout of the next chip.

[0106] In order to better illustrate and understand the present application, first, the embodiments of the present application are described in conjunction with specific examples. For example, in the present application, the power interface module is MM, the plurality of power management modules include low dropout linear regulator LDO, and the first power management module IP1, the second power management module IP2, the third power management module IP3, the fourth power management module IP4, the fifth power management module IP5, the sixth power management module IP6, and the seventh power management module IP7. First, the LDO, IP1, IP2, IP3, IP4, IP5, IP6, and IP7 need to be laid out. At this time, the weight values between the plurality of power management modules can be calculated according to the equal coefficients and weight constants of each power management module, for example, the calculated weight values are as shown in Table (1):

[0107] Table (1)

[0108]

[0109] Then, the position of the LDO can be determined according to the position of the MM, as shown in Figure 2 . Then, the above weight values can be sorted to obtain a sorting result, and the positions of the power modules whose positions are not determined are allocated according to a plurality of placement rules in turn. The present application takes the rule of placing in turn according to the priority of right side adjacent placement, upper side adjacent placement, left side adjacent placement, and lower side adjacent placement as an example.

[0110] According to the order of the sorting result, it can be determined that the weight value of the LDO to the IP6 is the highest, which is 44. At this time, the positions of the LDO and the IP6 need to be allocated, but the position of the LDO has been determined. Therefore, according to the placement rule of placing on the side of the LDO, the position of the IP6 is determined, as shown in Figure 3 , which shows a structure frame of a chip layout provided by the embodiment of the present application. Figure Two .

[0111] Next, according to the order of the sorting result, the weight value of the LDO to the IP1 is the highest, which is 40. At this time, the positions of the LDO and the IP1 need to be allocated, but the position of the LDO has been determined. Therefore, according to the placement rule of placing on the side of the LDO, but the position of the IP6 already exists at this time, so the upper side adjacent placement of the IP1 is automatically switched, and the position of the IP1 is determined, as shown in Figure 4 , which shows a structure frame of a chip layout provided by the embodiment of the present application. Figure Three .

[0112] Next, according to the order of the sorting result, the weight value of IP5 to IP3 is the highest as 38 at this time, and IP5 and IP3 are both power management modules with undetermined positions, among the determined IPs, the weight value of IP5 to LDO is the highest as 34, therefore, according to the placement rule, LDO is placed on the right side, but at this time, the position of IP6 exists, then it is automatically switched to the upper side, but at this time, the position of IP1 exists on the upper side, then it is automatically switched to the left side, but the left side exceeds the boundary of the chip, at this time, it is automatically switched to the lower side, but the lower side also exceeds the boundary of the chip, then it is skipped to the occupied position, that is, the position of IP6 on the right side, and IP5 is placed on the right side, that is, the position of IP5 is determined as the right side of IP6. Then IP3 is placed, according to the placement rule, IP5 is placed on the right side, but at this time, the right side exceeds the boundary of the chip, then it is automatically switched to the upper side, and the position of IP3 is determined as the upper side of IP5. As shown in FIG. 6, a structural block diagram of a chip layout provided by the embodiment of the application is shown. Figure 5 . Figure Four

[0113] Next, according to the order of the sorting result, the weight value of IP4 to IP5 is the highest as 31 at this time, and IP5 is a determined power management module, at this time, according to the placement rule, IP4 is placed on the right side of IP5, but the right side exceeds the boundary of the chip, then it is automatically switched to the upper side, and IP4 is placed on the upper side of IP5, but the upper side has IP3, then it is automatically switched to the left side, and IP4 is placed on the left side of IP5, but the left side has IP6, then it is automatically switched to the lower side, and IP4 is placed on the lower side of IP5, but the lower side exceeds the boundary of the chip, at this time, the occupied position is skipped, because the right side of IP5 is the boundary, that is, the position of IP on the upper side is skipped, and the position of IP4 is placed according to the placement rule, but after the right side is placed, the boundary of the chip is exceeded, then it is automatically switched to the upper side, that is, IP4 is placed on the upper side of IP3. As shown in FIG. 7, a structural block diagram of a chip layout provided by the embodiment of the application is shown. Figure 6 . Figure Five

[0114] ​​Next, according to the order of the sorting result, at this time, the weight value of IP4 to IP1 is the highest as 30, but the positions of IP4 and IP1 have been determined, then continue to determine the weight value of IP2 to IP4 according to the order of the sorting result, at this time, the weight value of IP2 to IP4 is the highest as 27, at this time, according to the right side adjacent in the placement rule, IP2 is placed to the right side adjacent of IP4, but the position after the placement exceeds the chip boundary, then automatically switches to the upper side adjacent placement, IP2 is placed to the upper side adjacent of IP4, but the position after the placement exceeds the chip boundary, automatically switches to the left side adjacent placement, IP2 is placed to the left side adjacent of IP4. As shown in FIG. 8, a structure block diagram of a chip layout provided by the embodiment of the present application is shown. Figure 7 Figure Six .

[0115] Next, according to the order of the sorting result, at this time, the weight value of IP2 to LDO is the highest as 25, but the positions of IP2 and LDO have been determined, then continue to determine the weight value of IP7 and IP3 according to the order of the sorting result, at this time, the weight value of IP7 and IP3 is the highest as 23, then according to the above placement rule, it can be determined that IP7 is placed to the left side of IP2. As shown in FIG. 9, a structure block diagram of a chip layout provided by the embodiment of the present application is shown. Figure 8 Figure Seven .

[0116] In this way, the placement rule of the priority of the right side adjacent placement, the upper side adjacent placement, the left side adjacent placement and the lower side adjacent placement is followed to determine a candidate chip layout.

[0117] Then, the placement rule of the priority of the upper side adjacent placement, the left side adjacent placement, the lower side adjacent placement and the right side placement is switched to determine the next candidate chip layout. Until all the candidate chip layouts are determined, then the target chip layout is screened from the candidate chip layouts.

[0118] In the embodiment of the present application, the initialization information and the preset key value of the chip are obtained; the chip includes a power interface module and a plurality of power management modules; the initialization information includes the position of the power interface module; the preset key value includes the level coefficient and the weight constant of the plurality of power management modules; the weight value between the two power management modules is determined according to the level coefficient and the weight constant; the plurality of power management modules are laid out according to the position of the power interface module and the weight value between the two power management modules, to obtain a plurality of candidate chip layouts; the target chip layout is screened from the plurality of candidate chip layouts. Thus, based on the level coefficient and the weight constant of the plurality of power management modules, and the position of the power interface module, the plurality of power management modules in the chip are automatically laid out, without relying on the engineers with rich experience to manually plan the layout, thereby saving a large amount of time cost and labor cost. ​​

[0119] It should be noted that for the method embodiments, the series of acts complement each other to achieve the present application embodiments, and the present application embodiments are not limited to the order of the acts described. Further, those skilled in the art will appreciate that one or more acts can be carried out concurrently, or with partial concurrence, or in different orders, depending on the application. Also, the embodiments described in this specification are preferred embodiments only, and thus do not limit the scope of the application.

[0120] Referring to Figure 9 , a structural block diagram of a chip layout determination apparatus provided by an embodiment of the present application is shown, which can specifically include the following modules:

[0121] The acquisition module 901 is configured to acquire initialization information of a chip and a preset key value; the chip includes a power interface module and a plurality of power management modules; the initialization information includes a position of the power interface module; and the preset key value includes a level coefficient and a weight constant of the plurality of power management modules.

[0122] The determination module 902 is configured to determine a weight value between each two of the plurality of power management modules according to the level coefficient and the weight constant.

[0123] The layout module 903 is configured to perform layout on the plurality of power management modules according to the position of the power interface module and the weight value between each two of the plurality of power management modules, to obtain a plurality of candidate chip layouts.

[0124] The screening module 904 is configured to screen a target chip layout from the plurality of candidate chip layouts.

[0125] In an embodiment, the plurality of power management modules includes a low dropout linear regulator module; and the layout module 903 includes:

[0126] The first determination submodule is configured to determine the position of the low dropout linear regulator module according to the position of the power interface module.

[0127] The second determination submodule is configured to, after determining the position of the low dropout linear regulator module, determine the positions of the power management modules whose positions are not determined according to the weight value between each two of the plurality of power management modules, to obtain the plurality of candidate chip layouts.

[0128] In an embodiment, the second determination submodule includes:

[0129] The sorting unit is configured to sort the weight value between each two of the plurality of power management modules.

[0130] The first distribution unit is configured to distribute positions of the power management modules without determined positions according to the sorting result and a plurality of placement rules in sequence, wherein the plurality of placement rules comprise right-side adjacent placement, upper-side adjacent placement, left-side adjacent placement and lower-side adjacent placement.

[0131] In an embodiment, the first distribution unit comprises:

[0132] The first determining sub-unit is configured to determine two target power management modules corresponding to the weight values in sequence according to the sequence of the sorting result.

[0133] The first distribution sub-unit is configured to distribute a position of another target power management module according to a position of a power management module with determined position when the two target power management modules comprise the power management module with determined position.

[0134] The second distribution sub-unit is configured to distribute positions of the two target power management modules according to the weight values between the two target power management modules, the weight values between the plurality of power management modules, and the position of the power management module with determined position when the two target power management modules are both power management modules without determined position.

[0135] In an embodiment, the initialization information further comprises a boundary constraint condition of the chip, and the second determining sub-module further comprises:

[0136] The second distribution unit is configured to automatically switch positions of other power management modules according to the plurality of placement rules until the distributed position meets the boundary constraint condition and the distributed position is not occupied when the distributed position of the power management module does not meet the boundary constraint condition or the distributed position is occupied.

[0137] In an embodiment, the second determining sub-module further comprises:

[0138] The third distribution unit is configured to continue to distribute positions of the power management modules without determined positions according to the plurality of placement rules after skipping the occupied positions when the distributed positions of the power management modules are all occupied until the distributed position is not occupied.

[0139] In an embodiment, the screening module 904 comprises:

[0140] The third determining sub-module is configured to determine a space utilization rate and a balance coefficient corresponding to the plurality of candidate chip layouts.

[0141] A fourth determining sub-module is configured to determine a candidate chip layout with a space utilization rate that meets a preset utilization rate interval from the plurality of candidate chip layouts.

[0142] A fifth determining sub-module is configured to determine a candidate chip layout with the smallest balance coefficient from the candidate chip layouts with the space utilization rate that meets the preset utilization rate interval as a target chip layout.

[0143] In an embodiment, the second determining sub-module further includes:

[0144] An output unit is configured to interrupt the allocation of the power management module position to the undetermined position when an abnormality occurs in the allocated position, and output abnormality information.

[0145] In an embodiment, the balance coefficient is calculated from the weight values between the power management modules.

[0146] In the embodiment of the present application, the acquisition module is configured to acquire initialization information and a preset key value of a chip; the chip includes a power interface module and a plurality of power management modules; the initialization information includes a position of the power interface module; and the preset key value includes a level coefficient and a weight constant of the plurality of power management modules.

[0147] The determining module is configured to determine the weight values between the power management modules according to the level coefficient and the weight constant; the layout module is configured to perform layout on the plurality of power management modules according to the position of the power interface module and the weight values between the power management modules, to obtain a plurality of candidate chip layouts; and the screening module is configured to screen a target chip layout from the plurality of candidate chip layouts. Thus, the plurality of power management modules in the chip are automatically laid out based on the level coefficient and the weight constant of the plurality of power management modules and the position of the power interface module, without relying on engineers with rich experience to perform manual layout planning, thereby saving a large amount of time cost and labor cost.

[0148] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0149] The embodiment of the present application further provides an electronic device, which includes:

[0150] The electronic device includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, each process of the chip layout determining method embodiment is implemented, and the same technical effect is achieved. To avoid repetition, no further description is given here.

[0151] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, the computer program is executed by a processor to realize each process of the chip layout determination method embodiment, and the same technical effects can be achieved, and thus details are not repeated herein.

[0152] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment are referred to each other.

[0153] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device or computer program product. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer usable program codes.

[0154] The embodiments of the present application are described with reference to flowcharts and / or block diagrams according to the method, terminal device (system) and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to a general-purpose computer, special-purpose computer, embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the computer or other programmable data processing terminal device produce a device for realizing the functions specified in the flowcharts and / or block diagrams. Figure One The functions specified in one flow or multiple flows and / or blocks Figure One The functions specified in one flow or multiple flows and / or blocks

[0155] These computer program instructions can also be stored in a computer readable memory capable of guiding the computer or other programmable data processing terminal device to work in a specific manner, so that the instructions stored in the computer readable memory produce a product including instruction devices, which realize the functions specified in the flowcharts and / or block diagrams. Figure One The functions specified in one flow or multiple flows and / or blocks Figure One The functions specified in one flow or multiple flows and / or blocks

[0156] These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operation steps are performed on the computer or other programmable terminal device to produce a computer implemented process, so that the instructions executed on the computer or other programmable terminal device provide a device for realizing the functions specified in the flowcharts and / or block diagrams. Figure Oneone or more processes and / or blocks Figure One the steps of a function specified in one or more blocks.

[0157] While preferred embodiments of the application have been described, those skilled in the art will appreciate that other modifications than those specifically described can be made within the scope of the present application. Accordingly, all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.

[0158] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to distinguish one element from another, and are not intended to denote a physical or logical relationship between such elements. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0159] The chip layout determination method, the chip layout determination apparatus, the electronic device, and the computer readable storage medium provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed, and the above description of the embodiments should not be understood as a limitation of the present application.

Claims

1. A method of chip layout determination, characterized by, The method comprises the following steps: obtaining initialization information and preset key values of a chip; the chip comprises a power interface module and a plurality of power management modules; the initialization information comprises the position of the power interface module; the preset key values comprise grade coefficients and weight constants of the plurality of power management modules; the size of the grade coefficients represents the distance spanned by the signal line layout of the power management module in the chip; the grade coefficients comprise high-grade coefficients and low-grade coefficients; the weight constant represents the relationship between a single signal line of the high-grade coefficient and multiple signal lines of the low-grade coefficient in the power management module; the weight constant is calculated according to the corresponding number of the signal lines of the low-grade coefficient, the grade coefficient, and the grade coefficient of the signal line of the high-grade coefficient; determining the weight values between the plurality of power management modules according to the grade coefficients and the weight constants; the size of the weight values represents the priority order of the adjacent placement of the two power management modules; according to the position of the power interface module and the weight values between the plurality of power management modules, the positions of the plurality of power management modules are laid out to obtain a plurality of candidate chip layouts; the positions of the plurality of power management modules are sequentially distributed according to the size order of the weight values and a plurality of placement rules; selecting a target chip layout from the plurality of candidate chip layouts.

2. The chip layout determination method according to claim 1, characterized by, The plurality of power management modules comprise low-dropout linear regulator modules; the layout of the plurality of power management modules according to the position of the power interface module and the weight values between the plurality of power management modules to obtain a plurality of candidate chip layouts comprises: determining the positions of the low-dropout linear regulator modules according to the position of the power interface module; after determining the positions of the low-dropout linear regulator modules, the positions of the power management modules whose positions are not determined are determined according to the weight values between the plurality of power management modules to obtain a plurality of candidate chip layouts.

3. The chip layout determination method according to claim 2, characterized by, The determination of the positions of the power management modules whose positions are not determined according to the weight values between the plurality of power management modules comprises: sorting the weight values between the plurality of power management modules; according to the sorting result, the positions of the power management modules whose positions are not determined are sequentially distributed according to a plurality of placement rules; the plurality of placement rules comprise right-side adjacent placement, upper-side adjacent placement, left-side adjacent placement, and lower-side adjacent placement.

4. The chip layout determining method according to claim 3, wherein The distribution of the positions of the power management modules whose positions are not determined according to the sorting result comprises: determining two target power management modules corresponding to the weight values in sequence according to the sorting result; when the two target power management modules contain a power management module whose position is determined, the position of the other target power management module is distributed according to the plurality of placement rules and the position of the power management module whose position is determined. When the two target power management modules are the power management modules with undetermined positions, positions of the two target power management modules are allocated according to a weight value between the two target power management modules, a weight value between each two of the plurality of power management modules, and a position of a power management module with a determined position, according to a plurality of placement rules.

5. The chip layout determining method according to claim 3, wherein The initialization information further includes a boundary constraint condition of the chip; and after the positions of the power management modules with undetermined positions are allocated according to the sorting result and the plurality of placement rules, the method further includes: When the allocated position of the power management module does not conform to the boundary constraint condition, or the allocated position is occupied, positions of other power management modules are automatically switched according to the plurality of placement rules until the allocated position determined conforms to the boundary constraint condition and the allocated position is not occupied.

6. The chip layout determining method according to claim 3, wherein After the positions of the power management modules with undetermined positions are allocated according to the sorting result and the plurality of placement rules, the method further includes: When the allocated positions of the power management modules are all occupied, the positions of the power management modules with undetermined positions are continuously allocated after skipping the occupied positions, according to the plurality of placement rules, until the allocated position is not occupied.

7. The chip layout determining method according to claim 1, wherein The target chip layout is selected from the plurality of candidate chip layouts, including: A space utilization rate and a balance coefficient corresponding to the plurality of candidate chip layouts are determined; From the plurality of candidate chip layouts, a candidate chip layout with a space utilization rate conforming to a preset utilization rate interval is determined; The candidate chip layout with the smallest balance coefficient in the candidate chip layout with the space utilization rate conforming to the preset utilization rate interval is determined as the target chip layout.

8. The chip layout determining method according to claim 3, wherein After the positions of the power management modules with undetermined positions are allocated according to the sorting result and the plurality of placement rules, the method further includes: When the allocated position is abnormal, the allocation of the positions of the power management modules with undetermined positions is interrupted, and abnormal information is output.

9. The chip layout determining method according to claim 7, wherein The balance coefficient is calculated from the weight values between each two of the plurality of power management modules.

10. A chip layout determination apparatus characterized by comprising: Including: An acquisition module is configured to acquire initialization information and a preset key value of a chip; The chip includes a power interface module and a plurality of power management modules; The initialization information includes a position of the power interface module; the preset key value includes a level coefficient of the plurality of power management modules and a weight constant; the size of the level coefficient represents a distance spanned by a signal line layout of the power management module in the chip; the level coefficient includes a high-level coefficient and a low-level coefficient; the weight constant represents a relationship between a single signal line of the high-level coefficient and a plurality of signal lines of the low-level coefficient in the power management module; the weight constant is calculated according to a corresponding number of the low-level coefficient, the level coefficient, and the high-level coefficient of the signal line; and determining a weight value between each two of the plurality of power management modules according to the level coefficient and the weight constant; the weight value representing a priority order of the two power management modules being placed adjacently; a layout module configured to layout positions of the plurality of power management modules according to the position of the power interface module and the weight value between each two of the plurality of power management modules, to obtain a plurality of candidate chip layouts; the positions of the plurality of power management modules being distributed according to the priority order of the weight value and a plurality of placement rules; a screening module configured to screen a target chip layout from the plurality of candidate chip layouts.

11. An electronic device, comprising: comprising: a processor, a memory, and a computer program stored on the memory and capable of running on the processor, the computer program being executed by the processor to implement the steps of the chip layout determination method according to any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, a computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps of the chip layout determination method according to any one of claims 1-9.

Images