Synchronous rectification control circuit, synchronous rectification control method and synchronous rectification circuit

Abstract

The invention provides a synchronous rectification control circuit, a synchronous rectification control method and a synchronous rectification circuit, and the circuit comprises a first detection unit which is used for comparing a drain-source voltage signal of a synchronous rectification switch with a reference current signal, and generating a synchronous rectification reset signal; the second detection unit is coupled with the output end of the first detection unit and is used for comparing the drain-source voltage signal with a reference voltage signal based on the synchronous rectification reset signal and generating a synchronous rectification opening condition signal; and the turn-on control unit is coupled with the output end of the second detection unit and is used for generating a synchronous rectification control signal according to the drain-source voltage signal and the synchronous rectification turn-on condition signal. According to the invention, when the turn-on time of the primary side switch is short, the problems of current backward flow and voltage stress caused by forced turn-on of the secondary side synchronous rectifier tube can be avoided, and meanwhile, mistaken turn-on of the secondary side synchronous rectifier tube can be avoided when ESD noise exists.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and specifically but not limited to, a synchronous rectification control circuit, a synchronous rectification control method, and a synchronous rectification circuit. Background Art

[0002] like Figure 1 As shown in FIG, the basic principle of the existing synchronous rectification technology (SR) is to use the channel of the MOSFET to replace the diode for freewheeling when the secondary side is freewheeling after the PWM signal of the primary side switch is turned off.

[0003] In general, in order to ensure that the voltage oscillation in the initial stage of freewheeling does not cause premature shutdown and thus cause low efficiency, the synchronous rectifier will be forced to be turned on for a period of time after it is turned on, that is, the minimum on time T on_min The minimum on-time T of synchronous rectification is generally required. on_min The freewheeling time must be shorter than the normal freewheeling time, otherwise the freewheeling may end but the synchronous rectifier may still be on, which may cause current backflow and excessive stress. However, under certain extreme conditions, the primary switch is only on for the LEB time (i.e., the minimum on-time of the primary side), which may result in a very short freewheeling time on the secondary side, even less than the minimum on-time T of the synchronous rectifier. on_min , it will cause the problem of excessive stress and seriously endanger the reliability of the system.

[0004] The working sequence of the existing synchronous rectification circuit is as follows: Figure 2 As shown, during the t1~t2 period, the primary switch is turned on for the minimum on-time LEB of the primary side. During the t2~t3 period, the synchronous rectifier is turned on for the minimum on-time T on_min Since the primary switch is only on for the LEB time, the secondary side freewheeling time is less than T on_min This causes the output capacitor to generate a current backflow, which further strengthens the oscillation intensity. During the t4-t5 period, the strengthened oscillation will cause the synchronous rectifier to be turned on incorrectly. Once the synchronous rectifier is turned on incorrectly, it is necessary to turn on T on_min During the t6-t9 period, the synchronous rectifier is mistakenly turned on again due to the oscillation; during the t7-t8 period, the primary switch is turned on again, causing the primary and secondary sides to be connected, resulting in a huge primary current and a huge secondary backflow current, causing very large voltage stress on both the primary and secondary sides.

[0005] Usually the synchronous rectifier chip also sets a minimum off time T off_minTo limit the opening interval of two synchronous rectification signals SR_PWM, that is, after the synchronous rectification signal SR_PWM = 0, no more synchronous rectification signal SR_PWM is allowed to be issued within a period of time. Under certain continuous working conditions, by setting the minimum off time T off_min It can shield the short-term opening of the primary switch. However, the minimum off time T off_min The duration setting is very limited. If the minimum off time T off_min If the minimum off time T is set too long, the synchronous rectifier will not be turned on for a long time during high-frequency continuous flow. off_min If the setting is too short, it will not be able to effectively shield the short-term opening of the primary switch. In addition, the minimum off time T off_min This method cannot shield the randomly occurring electrostatic discharge noise ESD, and under certain circumstances it will still cause the synchronous rectification to be mistakenly turned on, thereby causing excessive stress.

[0006] By setting the minimum off time T off_min To shield the secondary side control circuit from being opened by mistake, the working sequence is as follows Figure 3 As shown, in the stage t1 to t2, the synchronous rectification signal SR_PWM is normally issued, and at time t2 the synchronous rectification signal SR_PWM changes to 0, and the minimum off time T off_min Start timing at the minimum off time T off_min The synchronous rectification signal SR_PWM is not allowed to be turned on during the time. In the period from t2 to t4, at time t3, the primary switch voltage signal V ds Less than the synchronous rectification turn-on threshold V th_on , meeting the synchronous rectification opening conditions, but still within the minimum off time T off_min time, so the synchronous rectification signal SR_PWM is not allowed to send pulses at time t3, and the minimum off time T at time t4 off_min After the timing is over, the synchronous rectification signal SR_PWM is allowed to pulse again. In the t5~t6 stage, at time t5, the primary switch voltage signal V ds Less than the synchronous rectification turn-on threshold V th_on , due to the minimum off time T off_min The timing has ended, so the electrostatic discharge noise ESD will cause the synchronous rectification to turn on, and the synchronous rectification will be forced to turn on the minimum turn-on time T on_min , which will also cause the stress of current backflow to exceed the standard.

[0007] Therefore, it can be seen that when the primary side switch has an extremely short on-time, the existing synchronous rectification control circuit is very likely to cause continuous synchronous rectification on the secondary side and the occurrence of common primary and secondary sides, which in turn causes serious voltage stress problems and cannot effectively shield the randomly occurring electrostatic discharge noise ESD.

[0008] In view of this, it is necessary to provide a new structure or control method to solve at least part of the above problems. Summary of the Invention

[0009] At least in response to one or more problems in the background technology, the present invention proposes a synchronous rectification control circuit, a synchronous rectification control method and a synchronous rectification circuit, which can avoid the secondary side synchronous rectifier tube being forced to turn on when the primary side switch is turned on for a short time, thereby causing current backflow and voltage stress problems, and can also avoid the secondary side synchronous rectifier tube from being mistakenly turned on when ESD noise exists.

[0010] According to one aspect of the present invention, a synchronous rectification control circuit is coupled to a synchronous rectification switch, comprising:

[0011] a first detection unit, configured to compare a drain-source voltage signal of the synchronous rectification switch with a reference current signal to generate a synchronous rectification reset signal;

[0012] a second detection unit, coupled to the output terminal of the first detection unit, configured to compare the drain-source voltage signal with a reference voltage signal based on the synchronous rectification reset signal to generate a synchronous rectification turn-on condition signal;

[0013] The opening control unit is coupled to the output terminal of the second detection unit and is used to generate a synchronous rectification control signal according to the drain-source voltage signal and the synchronous rectification opening condition signal.

[0014] Optionally, the synchronous rectification reset signal includes a first state signal and a second state signal with opposite levels, wherein the first state signal is used to characterize that the change rate of the drain-source voltage signal is positive, and the second state signal is used to characterize that the change rate of the drain-source voltage signal is non-positive.

[0015] Optionally, the first detection unit includes:

[0016] a capacitor, one end of which is coupled to the drain-source voltage signal and is used to generate a current signal representing the drain-source voltage signal;

[0017] The first comparison module is coupled to the other end of the capacitor, and is used to compare the current signal with a reference current signal, and output a first state signal when the current signal is greater than or equal to the reference current signal, and output a second state signal when the current signal is less than the reference current signal.

[0018] Optionally, the first detection unit includes:

[0019] a capacitor, one end of which is coupled to the drain-source voltage signal and is used to generate a current signal representing the drain-source voltage signal;

[0020] A threshold current generating module, configured to generate a threshold current signal according to a reference current signal;

[0021] A second comparison module is coupled to the other end of the capacitor and the output end of the threshold current generating module, and is used to compare the current signal with the threshold current signal, and output a first state signal when the current signal is greater than or equal to the threshold current signal, and output a second state signal when the current signal is less than the threshold current signal.

[0022] Optionally, the synchronous rectification on condition signal includes a third state signal and a fourth state signal with opposite levels, wherein the third state signal is used to indicate that synchronous rectification is allowed to be turned on, and the fourth state signal is used to indicate that synchronous rectification is not allowed to be turned on.

[0023] Optionally, the second detection unit includes:

[0024] a third comparison module, configured to compare the drain-source voltage signal with a reference voltage signal, and output a first comparison signal when the drain-source voltage signal is greater than or equal to the reference voltage signal, and output a second comparison signal when the drain-source voltage signal is less than the reference voltage signal;

[0025] a timing module coupled to the output terminal of the first detection unit and the output terminal of the third comparison module, configured to detect a duration of the first comparison signal based on the synchronous rectification reset signal, and output a first condition detection signal when the duration exceeds a time threshold, otherwise output a second condition detection signal;

[0026] A signal generating module is coupled to the output end of the first detection unit and the output end of the timing module, and is used to output a third state signal based on the synchronous rectification reset signal and the first condition detection signal, and to output a fourth state signal based on the synchronous rectification reset signal and the second condition detection signal.

[0027] Optionally, the signal generating module includes:

[0028] An RS trigger, whose reset end is connected to the output end of the first detection unit, whose set end is connected to the output end of the timing module, and whose output end is used to output the synchronous rectification turning-on condition signal.

[0029] According to another aspect of the present invention, a synchronous rectification circuit includes a primary circuit and a secondary circuit, wherein the secondary circuit includes a synchronous rectification switch and any one of the above-mentioned synchronous rectification control circuits.

[0030] According to another aspect of the present invention, a synchronous rectification control method is provided for controlling a synchronous rectification switch, comprising:

[0031] Acquiring a drain-source voltage signal of the synchronous rectification switch, comparing the drain-source voltage signal with a reference current signal, and generating a synchronous rectification reset signal;

[0032] comparing the drain-source voltage signal and a reference voltage signal according to the synchronous rectification reset signal, and generating a synchronous rectification turn-on condition signal;

[0033] A synchronous rectification control signal is generated according to the drain-source voltage signal and the synchronous rectification turn-on condition signal.

[0034] Optionally, a corresponding current signal is generated according to the drain-source voltage signal, the drain-source voltage signal is converted into a corresponding current signal through a capacitor, a reset signal is output when the current signal ≥ a reference current signal, and a non-reset signal is output when the current signal < the reference current signal.

[0035] Optionally, a corresponding current signal is generated according to the drain-source voltage signal, the drain-source voltage signal is converted into a corresponding current signal through a capacitor, the reference current signal is converted into a threshold current signal through a current mirror, and a reset signal is output when the current signal is ≥ the threshold current signal, and a non-reset signal is output when the current signal is < the threshold current signal.

[0036] Optionally, when the drain-source voltage signal is greater than or equal to the reference voltage signal and the synchronous rectification reset signal is a reset signal, recording a duration for which the drain-source voltage signal is greater than or equal to the reference voltage signal, and outputting a turn-on condition signal when the duration is greater than a time threshold; otherwise, outputting a turn-on condition signal not permitted;

[0037] When the drain-source voltage signal is greater than or equal to the reference voltage signal and the synchronous rectification reset signal is a non-reset signal, outputting a non-allowed turn-on condition signal;

[0038] When the drain-source voltage signal is less than the reference voltage signal, a non-allowed turn-on condition signal is output.

[0039] The synchronous rectification control circuit, synchronous rectification control method and synchronous rectification circuit proposed in the present invention avoid the secondary side synchronous rectifier tube being forced to turn on when the primary side switch is turned on for a short time, thereby causing current backflow and voltage stress, and at the same time avoid the secondary side synchronous rectifier tube from being turned on incorrectly when ESD noise exists. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the present invention and, together with the description, to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0041] Figure 1 A schematic diagram of an existing synchronous rectification circuit is shown;

[0042] Figure 2 Shows the working timing diagram of the existing synchronous rectification circuit;

[0043] Figure 3 The present invention shows a working sequence diagram of the existing synchronous rectification circuit for shielding the false opening;

[0044] Figure 4 A schematic diagram of a synchronous rectification control circuit of the present invention is shown;

[0045] Figure 5 A schematic structural diagram of a first detection unit and a second detection unit according to an embodiment of the present invention is shown;

[0046] Figure 6 shows a key timing diagram of the first detection unit and the second detection unit according to an embodiment of the present invention;

[0047] Figure 7 A schematic structural diagram of a first detection unit and a second detection unit according to another embodiment of the present invention is shown;

[0048] Figure 8 FIG2 shows an operation timing diagram of a synchronous rectification control circuit according to an embodiment of the present invention;

[0049] Figure 9 FIG2 shows an operation timing diagram of a synchronous rectification control circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0050] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0052] It is understood that the terms "first," "second," and the like used herein may be used to describe various elements herein, but these elements are not limited by these terms. These terms are used solely to distinguish a first element from another element. For example, without departing from the scope of this application, a first activation condition may be referred to as a second activation condition, and similarly, a second activation condition may be referred to as a first activation condition. Both the first activation condition and the second activation condition are activation conditions, but they are not the same activation condition.

[0053] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0054] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0055] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0056] According to one aspect of the present invention, a synchronous rectification control circuit, such as Figure 4 As shown, it includes a first detection unit, a second detection unit and an activation control unit, which are specifically as follows:

[0057] The first detection unit is used to compare the drain-source voltage V ds Signal and reference current I ref signal, according to the drain-source voltage V ds Signal and reference current I ref The signal generates a synchronous rectification reset signal RESET. The synchronous rectification reset signal RESET is used to represent the drain-source voltage V ds In one embodiment, the synchronous rectification reset signal RESET includes a first state signal and a second state signal with opposite levels, wherein the first state signal is used to represent the drain-source voltage V ds The rate of change of the signal |dv / dt| is positive, and the second state signal is used to represent the drain-source voltage V ds The rate of change of the signal |dv / dt| is non-positive.

[0058] The second detection unit is coupled to the output terminal of the first detection unit, and is used to compare the drain-source voltage V based on the synchronous rectification reset signal RESET. ds Signal and reference voltage V H_thSignal, generating a synchronous rectification on condition signal SR_ON_Condition1. In one embodiment, the synchronous rectification on condition signal SR_ON_Condition1 includes a third state signal and a fourth state signal with opposite levels, wherein the third state signal is used to indicate that the synchronous rectification switch is allowed to be turned on, and the fourth state signal is used to indicate that the synchronous rectification switch is not allowed to be turned on.

[0059] The opening control unit is coupled to the output terminal of the second detection unit, and is used to open the control unit according to the drain-source voltage V ds signal and the synchronous rectification on condition signal SR_ON_Condition1 to generate a synchronous rectification control signal SR_PWM.

[0060] In one embodiment, Figure 7 As shown, the first detection unit includes a capacitor C1 and a first comparison module, specifically as follows:

[0061] One end of the capacitor C1 is coupled to the drain-source voltage V ds signal, capacitor C1 is used to generate a voltage representing the drain-source voltage V ds Signal current I dv / dt Signal.

[0062] The first comparison module is coupled to the other end of the capacitor C1 and is used to compare the current I dv / dt Signal and reference current I ref signal, and the current I dv / dt signal ≥ the reference current I ref signal outputs a first state signal, and the current I dv / dt signal < the reference current I ref signal, and outputs the second state signal.

[0063] In another embodiment, Figure 5 As shown, the first detection unit includes a capacitor C1, a threshold current generating module and a second comparing module, specifically as follows:

[0064] One end of the capacitor C1 is coupled to the drain-source voltage V d signal, capacitor C1 is used to generate a voltage representing the drain-source voltage V ds Signal current I dv / dt Signal.

[0065] One end of the threshold current generating module is coupled to the reference current I ref signal, the threshold current generation module is used to generate a threshold current according to the reference current I ref Signal generation threshold current I dv / dt_th Signal.

[0066] The second comparison module is coupled to the other end of the capacitor C1 and the output end of the threshold current generating module, and is used to compare the current I dv / dt signal and the threshold current I dv / dt_th signal, and the current I dv / dt signal ≥ the threshold current I dv / dt_th signal outputs a first state signal, and the current I dv / dt signal < the threshold current I dv / dt_th signal, and outputs the second state signal.

[0067] In one embodiment, Figure 5 As shown, the second detection unit includes a third comparison module, a timing module and a signal generation module, which are specifically as follows:

[0068] The third comparison module is used to compare the drain-source voltage V ds Signal and reference voltage V H_th signal, and the drain-source voltage V ds signal ≥ the reference voltage V H_th signal outputs the first comparison signal when the drain-source voltage V ds signal < the reference voltage V H_th signal, and outputs a second comparison signal.

[0069] The timing module is coupled to the output end of the first detection unit and the output end of the third comparison module. The timing module is used to detect the duration of the first comparison signal based on the synchronous rectification reset signal RESET, and output a first condition detection signal Condition1_detect when the duration exceeds a time threshold, otherwise output a second condition detection signal.

[0070] The signal generation module is coupled to the output end of the first detection unit and the output end of the timing module. The signal generation module is configured to output a third state signal SR_ON_Condition1 based on the synchronous rectification reset signal RESET and the first condition detection signal Condition1_detect, and output a fourth state signal based on the synchronous rectification reset signal RESET and the second condition detection signal. In a specific embodiment, the signal generation module includes an RS trigger, wherein the reset end of the RS trigger is connected to the output end of the first detection unit, the set end of the RS trigger is connected to the output end of the timing module, and the output end of the RS trigger is configured to output the synchronous rectification on condition signal SR_ON_Condition1.

[0071] according to Figure 5 and Figure 6 The principle of the first detection unit is described as follows:

[0072] Drain-source voltage V ds When a rising edge occurs, there is a current I on capacitor C1. dv / dt Produced, and I dv / dt =C1*dV ds / dt. When the current I dv / dt Greater than the threshold current I dv / dt_th When the voltage V A Gradually increase, when the voltage V A Exceeds the turn-on threshold voltage V of MOS tube N5 B +V th_N5 After that, the voltage V B Will rise rapidly when the voltage V B Exceeds the turn-on threshold voltage V of MOS tube N3 th_N3 and the turn-on threshold voltage V of MOS tube N4 th_N4 When , MOS tube N4 generates pull-down current. N3 =I dv / dt -I dv / dt_th , I N4 and I N3 Proportional. When I N4 >I1, the voltage V C Pulled down to GND, the synchronous rectification reset signal RESET = 1.

[0073] Therefore, as long as the drain-source voltage V ds If there is a rising edge signal, it can be compared through the first detection unit and the threshold current I can be reasonably designed. dv / dt_th and capacitor C1, we can determine the drain-source voltage V ds When the primary side is turned on, the drain-source voltage V ds There is a large rising edge signal on the drain-source voltage V ds The rising edge |dv / dt| is used to determine the turn-on moment of the primary side.

[0074] according to Figure 5 and Figure 6 The principle of the second detection unit is described as follows:

[0075] When the drain-source voltage V ds Exceeds the reference voltage V H_th (In this embodiment, V H_th =VDD), the voltage V1 rises. When the voltage V1 rises to the turn-on threshold voltage VDD-|V th_P3|, MOS transistor P3 is turned off. After MOS transistor P3 is turned off, voltage V2 is pulled down to GND, and MOS transistor N9 is turned off. (1) After MOS transistor N9 is turned off, if synchronous rectification reset signal RESET=0, MOS transistor P4 starts to charge capacitor C2. When capacitor C2 is charged to the turn-on threshold VDD-|V of MOS transistor P5, th_P5 |, the input of the invertor INV1 becomes 0, and the condition detection signal Condition1_detect = 1. (2) After the MOS transistor N9 is turned off, if the synchronous rectification reset signal RESET = 1, the voltage V3 remains = 0, the input of the invertor INV1 remains high, and the condition detection signal Condition1_detect = 0.

[0076] When the drain-source voltage V ds Less than the reference voltage V H_th = VDD, the voltage V1 is pulled down to GND, and the voltage V2 is pulled up to the reference voltage V H_th =VDD, MOS tube N9 is turned on, voltage V3 is pulled down to GND, the input of invertor INV1 is maintained high, and the condition detection signal Condition1_detect=0.

[0077] It can be seen from this that when the synchronous rectification reset signal RESET=0, if the condition detection signal Condition1_detect=1, the synchronous rectification turn-on condition signal SR_ON_condition1=1, allowing the synchronous rectification switch to be turned on; when the synchronous rectification reset signal RESET=1, if the condition detection signal Condition1_detect=0, the synchronous rectification turn-on condition signal SR_ON_Condition1=0, and the synchronous rectification switch is not allowed to be turned on.

[0078] like Figure 6 The key timing of the first detection unit and the second detection unit is shown and described as follows:

[0079] 1) During the t1~t2 phase, the primary side is turned on at time t1, and the drain-source voltage of the synchronous rectifier switch V ds A rising edge occurs, when C1*dV ds / dt>I dv / dt_th At t2, the synchronous rectification reset signal RESET = 1, and the synchronous rectification turn-on condition signal SR_ON_Condition1 is reset to 0. At t2, the drain-source voltage V ds When the rising edge ends, the synchronous rectification reset signal RESET becomes 0.

[0080] 2) During the t2~t3 phase, after the synchronous rectification reset signal RESET=0, the drain-source voltage V ds Reference voltage V H_last(=VDD), the voltage V3 starts to rise, and after time T H_last (which is a preset time threshold) and then the condition detection signal Condition1_detect=1, the synchronous rectification on condition signal SR_ON_Condition1=1, allowing the synchronous rectification switch to be turned on.

[0081] 3) At t4, the drain-source voltage V ds <Reference voltage V H_th , condition detection signal Condition1_detect=0.

[0082] According to another aspect of the present invention, a synchronous rectification circuit includes a primary circuit and a secondary circuit, wherein the secondary circuit includes a synchronous rectification switch and the above-mentioned synchronous rectification control circuit.

[0083] According to another aspect of the present invention, a synchronous rectification control method is provided for controlling a synchronous rectification switch, comprising:

[0084] S1. Obtain the drain-source voltage V of the synchronous rectification switch ds signal, comparing the drain-source voltage V ds Signal and reference current I ref signal, and generates a synchronous rectification reset signal RESET.

[0085] In one embodiment, the drain-source voltage V ds The signal is converted into the corresponding current I dv / dt signal, when the current I dv / dt Signal ≥ reference current I ref signal outputs a reset signal RESET = 1, and the current I dv / dt signal < the reference current I ref The output does not reset the signal when RESET=0.

[0086] In another embodiment, the drain-source voltage V ds The signal is converted into the corresponding current I dv / dt signal, the reference current I ref The signal is converted into a threshold current I dv / dt_th signal, when the current I dv / dt Signal ≥ threshold current I dv / dt_th signal outputs a reset signal RESET = 1, and the current I dv / dt signal < the threshold current I dv / dt_th The output does not reset the signal when RESET=0.

[0087] S2. Compare the drain-source voltage V according to the synchronous rectification reset signal RESETds Signal and reference voltage V H_th signal, and generates the synchronous rectification turn-on condition signal SR_ON_Condition1.

[0088] S3, according to the drain-source voltage V ds signal and the synchronous rectification on condition signal SR_ON_Condition1 to generate a synchronous rectification control signal SR_PWM.

[0089] In one embodiment, when the drain-source voltage V ds signal ≥ the reference voltage V H_th signal and the synchronous rectification reset signal is the reset signal RESET=1, record the drain-source voltage V ds signal ≥ the reference voltage V H_th The duration of the signal, when the duration> time threshold T H_last When the condition signal SR_ON_condition1 is enabled, 1 is output; otherwise, the condition signal SR_ON_condition1 is not enabled, 0 is output.

[0090] When the drain-source voltage V ds signal ≥ the reference voltage V H_th signal and the synchronous rectification reset signal is the non-reset signal RESET=0, the output is the non-enabling turn-on condition signal SR_ON_condition1=0.

[0091] When the drain-source voltage V ds signal < the reference voltage V H_th When the signal is 0, the output does not allow the on condition signal SR_ON_condition1 = 0.

[0092] In a specific embodiment, the working sequence to avoid the primary side being turned on too short and causing the secondary side synchronous rectification switch to be forced to turn on is as follows: Figure 8 As shown, the details are as follows:

[0093] 1) t1~t3 stage:

[0094] Before time t1, the synchronous rectification control signal SR_PWM pulses normally.

[0095] At time t1, the primary side is turned on and the drain-source voltage V ds The synchronous rectification reset signal RESET changes to 1, and the synchronous rectification turn-on condition signal SR_ON_Condition1 changes to 0.

[0096] When the rising edge ends at time t2, the synchronous rectification reset signal RESET signal changes to 0. However, due to the interval T between t2 and t3last Less than the time threshold T H_last , so the condition detection signal Condition1_detect is still 0, and the synchronous rectification turn-on condition signal SR_ON_Condition1 is also still 0.

[0097] After t3, the drain-source voltage V ds < Turn-on threshold voltage V th_on , the synchronous rectification switch will not turn on.

[0098] 2) T4 to T9 stage:

[0099] At time t4 , the condition detection signal Condition1_detect becomes 1, and the synchronous rectification on condition signal SR_ON_Condition1 becomes 1.

[0100] At time t5 , the synchronous rectification reset signal RESET changes to 1, and the synchronous rectification on condition signal SR_ON_Condition1 is reset to 0.

[0101] At t7, the drain-source voltage of the synchronous rectifier switch V ds >V H_last And it continues to exceed the time threshold T H_last , the condition detection signal Condition1_detect becomes 1, the synchronous rectification turn-on condition signal SR_ON_Condition1 becomes 1, and the synchronous rectification control signal SR_PWM is allowed to pulse.

[0102] At time t9, the synchronous rectification control signal SR_PWM normally sends PWM pulses.

[0103] In another specific embodiment, the working sequence to avoid the secondary side synchronous rectification switch from being turned on by mistake when ESD noise exists is as follows: Figure 9 As shown, the details are as follows:

[0104] 1) t1~t5 stage:

[0105] During the period t1 to t2, the synchronous rectification control signal SR_PWM normally generates PWM pulses.

[0106] At time t3, ESD noise occurs, the synchronous rectification reset signal RESET changes to 1, and the synchronous rectification turn-on condition signal SR_ON_Condition1 changes to 0.

[0107] Drain-source voltage V at time t4 ds When the rising edge ends, the synchronous rectification reset signal RESET becomes 0.

[0108] During the t4~t5 period, the drain-source voltage V ds < Turn-on threshold voltage Vth_on , the synchronous rectification switch will not be turned on by mistake.

[0109] 2) t5-t6 stage:

[0110] At t6, the drain-source voltage V ds >V H_last And it continues to exceed the threshold time T H_last , the condition detection signal Condition1_detect becomes 1, the synchronous rectification turn-on condition signal SR_ON_Condition1 becomes 1, and the synchronous rectification control signal SR_PWM is allowed to pulse.

[0111] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the synchronous rectification control method are implemented.

[0112] In another embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps of the above-mentioned synchronous rectification control method when executing the computer program.

[0113] Those skilled in the art will appreciate that all or part of the processes in the synchronous rectification control method of the above-mentioned embodiment can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0114] In the description of this specification, reference to the terms "some embodiments" or "other embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A synchronous rectification control circuit coupled to a synchronous rectification switch, characterized in that: include: a first detection unit, configured to compare a drain-source voltage signal of the synchronous rectification switch with a reference current signal to generate a synchronous rectification reset signal; a second detection unit, coupled to the output terminal of the first detection unit, configured to compare the drain-source voltage signal with a reference voltage signal based on the synchronous rectification reset signal to generate a synchronous rectification turn-on condition signal; The opening control unit is coupled to the output terminal of the second detection unit and is used to generate a synchronous rectification control signal according to the drain-source voltage signal and the synchronous rectification opening condition signal.

2. The synchronous rectification control circuit according to claim 1, wherein: The synchronous rectification reset signal includes a first state signal and a second state signal with opposite levels, wherein the first state signal is used to represent that the change rate of the drain-source voltage signal is positive, and the second state signal is used to represent that the change rate of the drain-source voltage signal is non-positive.

3. The synchronous rectification control circuit according to claim 1 or 2, characterized in that: The first detection unit includes: a capacitor, one end of which is coupled to the drain-source voltage signal and is used to generate a current signal representing the drain-source voltage signal; The first comparison module is coupled to the other end of the capacitor, and is used to compare the current signal with a reference current signal, and output a first state signal when the current signal is greater than or equal to the reference current signal, and output a second state signal when the current signal is less than the reference current signal.

4. The synchronous rectification control circuit according to claim 1 or 2, characterized in that: The first detection unit includes: a capacitor, one end of which is coupled to the drain-source voltage signal and is used to generate a current signal representing the drain-source voltage signal; A threshold current generating module, configured to generate a threshold current signal according to a reference current signal; A second comparison module is coupled to the other end of the capacitor and the output end of the threshold current generating module, and is used to compare the current signal with the threshold current signal, and output a first state signal when the current signal is greater than or equal to the threshold current signal, and output a second state signal when the current signal is less than the threshold current signal.

5. The synchronous rectification control circuit according to claim 1, wherein: The synchronous rectification on condition signal includes a third state signal and a fourth state signal with opposite levels, wherein the third state signal is used to indicate that synchronous rectification is allowed to be turned on, and the fourth state signal is used to indicate that synchronous rectification is not allowed to be turned on.

6. The synchronous rectification control circuit according to claim 1 or 5, characterized in that: The second detection unit includes: a third comparison module, configured to compare the drain-source voltage signal with a reference voltage signal, and output a first comparison signal when the drain-source voltage signal is greater than or equal to the reference voltage signal, and output a second comparison signal when the drain-source voltage signal is less than the reference voltage signal; a timing module coupled to the output terminal of the first detection unit and the output terminal of the third comparison module, configured to detect a duration of the first comparison signal based on the synchronous rectification reset signal, and output a first condition detection signal when the duration exceeds a time threshold, otherwise output a second condition detection signal; A signal generating module is coupled to the output end of the first detection unit and the output end of the timing module, and is used to output a third state signal based on the synchronous rectification reset signal and the first condition detection signal, and to output a fourth state signal based on the synchronous rectification reset signal and the second condition detection signal.

7. The synchronous rectification control circuit according to claim 6, characterized in that: The signal generating module comprises: An RS trigger, whose reset end is connected to the output end of the first detection unit, whose set end is connected to the output end of the timing module, and whose output end is used to output the synchronous rectification turning-on condition signal.

8. A synchronous rectification circuit, comprising a primary circuit and a secondary circuit, characterized in that: The secondary circuit includes a synchronous rectification switch and the synchronous rectification control circuit according to any one of claims 1 to 7.

9. A synchronous rectification control method for controlling a synchronous rectification switch, characterized in that: include: Acquiring a drain-source voltage signal of the synchronous rectification switch, comparing the drain-source voltage signal with a reference current signal, and generating a synchronous rectification reset signal; comparing the drain-source voltage signal and a reference voltage signal according to the synchronous rectification reset signal, and generating a synchronous rectification turn-on condition signal; A synchronous rectification control signal is generated according to the drain-source voltage signal and the synchronous rectification turn-on condition signal.

10. The synchronous rectification control method according to claim 9, characterized in that: The drain-source voltage signal is converted into a corresponding current signal through a capacitor, and a reset signal is output when the current signal is greater than or equal to a reference current signal, and a non-reset signal is output when the current signal is less than the reference current signal.

11. The synchronous rectification control method according to claim 9, wherein: The drain-source voltage signal is converted into a corresponding current signal through a capacitor, and the reference current signal is converted into a threshold current signal through a current mirror. When the current signal is greater than or equal to the threshold current signal, a reset signal is output, and when the current signal is less than the threshold current signal, a non-reset signal is output.

12. The synchronous rectification control method according to claim 10 or 11, characterized in that: When the drain-source voltage signal is greater than or equal to the reference voltage signal and the synchronous rectification reset signal is a reset signal, recording the duration of the drain-source voltage signal being greater than or equal to the reference voltage signal, and outputting a turn-on condition signal when the duration is greater than a time threshold; otherwise, outputting a turn-on condition signal not being allowed; When the drain-source voltage signal is greater than or equal to the reference voltage signal and the synchronous rectification reset signal is a non-reset signal, outputting a non-allowed turn-on condition signal; When the drain-source voltage signal is less than the reference voltage signal, a non-allowed turn-on condition signal is output.

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