FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generator

Abstract

The present invention provides a FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generator, relating to the field of pulse technology. The device comprises: a power supply module, an MCU control module, an FPGA signal generation module, and a low-frequency current modulation signal generation module, all connected in sequence; a human-machine interface module connected to the power supply module and the MCU control module; an intermediate frequency bipolar pulse generation module and an electrode unit, wherein the power supply module, the intermediate frequency bipolar pulse generation module, and the electrode unit are connected in sequence, the electrode unit serving as the output end of the intermediate frequency current pulse signal generator being connected to acupuncture points on the human body; and the power supply module is further connected to the FPGA signal generation module and the low-frequency current modulation signal generation module, respectively. The technical solution of the present invention overcomes the problem of unstable and controllable intermediate frequency current pulse signals in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of pulse technology, and in particular to a FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device. Background Art

[0002] In the biomedical field, electrical stimulation technology is frequently used for the treatment, rehabilitation, and physical therapy of human diseases. Electrical signals used for electrical stimulation are generally categorized by frequency range: low-frequency, medium-frequency, and high-frequency. In addition to being used for physiological treatments such as analgesia, blood circulation, muscle training, adhesion release, and inflammation, medium-frequency signals can also be combined with Traditional Chinese Medicine (TCM) acupuncture techniques for transcutaneous electrical acupoint stimulation (TEAS). By modulating the amplitude of a medium-frequency (1kHz-10kHz) signal with a low-frequency (10-1kHz) signal, the modulated medium-frequency signal combines the physiological effects of both low- and medium-frequency signals while minimizing the body's adaptation to stimulation intensity that occurs with continuous medium-frequency constant-amplitude stimulation. Furthermore, by modulating the amplitude of the medium-frequency signal with low-frequency signals of varying patterns or waveforms and applying them to acupoints, it can simulate the techniques of acupoint massage, such as lifting, pulling, pressing, and kneading.

[0003] A Chinese patent (CN119030503A) for a dual-channel low-frequency modulated intermediate-frequency bipolar pulse signal generation system has the following problems:

[0004] 1) Medium and low frequency current signals are generated by the MCU controller software via the D / A interface. When the MCU software runs multiple tasks, the D / A interface data update will be delayed, which will cause the low frequency current signal waveform to be distorted.

[0005] 2) When the current signal amplitude is adjusted, if it happens to correspond to the effective period of the intermediate frequency carrier signal pulse level, the pulse width of the modulated pulse current signal will be cut off, resulting in the instability of the pulse width of the pulse current signal;

[0006] 3) This patent uses a Holland current source structure. When the Holland current source improves its accuracy, it requires an increased resistance value and a higher matching accuracy. Therefore, in the application scenario of high-precision biomedical current stimulation, the high-precision matching of resistors becomes more difficult.

[0007] All of the above problems will have an adverse effect on the treatment effect.

[0008] Therefore, there is a need for a controllable and stable FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device that combines intermediate frequency current pulse stimulation and low frequency current stimulation. Summary of the Invention

[0009] The main purpose of the present invention is to provide a FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device to solve the problem of unstable and controllable intermediate frequency current pulse signals in the prior art.

[0010] To achieve the above-mentioned objectives, the present invention provides a FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device, comprising: a power supply module, an MCU control module, an FPGA signal generating module and a low-frequency current modulation signal generating module connected in sequence; further comprising: a human-machine interface module connected to the power supply module and the MCU control module; further comprising: an intermediate frequency bipolar pulse generating module and an electrode unit, wherein the power supply module, the intermediate frequency bipolar pulse generating module and the electrode unit are connected in sequence, and the electrode unit serves as the output end of the intermediate frequency current pulse signal generating device and is connected to acupuncture points on the human body; the power supply module is also connected to the FPGA signal generating module and the low-frequency current modulation signal generating module respectively; wherein the FPGA signal generating module comprises: a waveform data storage unit and a signal generating unit connected to each other, and the signal generating unit is connected to the MCU control module; the low-frequency current modulation signal generating module comprises: a D / A conversion unit and a voltage-controlled current source unit connected to each other, and the signal generating unit is connected to the D / A conversion unit; and the intermediate frequency bipolar pulse generating module comprises: an H-bridge driving unit and an H-bridge circuit unit connected to each other.

[0011] Furthermore, the power supply module includes a boost circuit and a buck circuit. The boost circuit is connected to the voltage-controlled current source unit; the buck circuit provides working power for the MCU control module, the FPGA signal generation module, and the intermediate frequency bipolar pulse generation module.

[0012] Furthermore, the signal generating unit includes: a first accumulator register, a second accumulator register and a third accumulator register, the waveform data storage unit includes a waveform data table ROM, and the waveform data table ROM is connected to the D / A conversion unit; the frequency word F_WORD is input into the first accumulator register, and under the control of the system clock CLK, the first accumulator register and the F_WORD of the second accumulator register are accumulated, and the output binary code is added to the phase control word P_WORD input into the third accumulator register as the address of the waveform data table ROM, and then the waveform data table ROM is addressed, and the output signal amplitude is converted into a low-frequency modulated waveform through the D / A conversion unit as the input of the voltage-controlled current source unit, thereby outputting a current signal in the voltage-controlled current source unit, and the current signal is stored in the waveform data storage unit, and the current signal includes a sine wave, a square wave, a triangle wave, a sawtooth wave, a trapezoidal wave and an exponential wave.

[0013] Furthermore, the first accumulator register, the second accumulator register, and the third accumulator register are identical. The first accumulator register includes a digital full adder and a digital phase register. When the rising edge signal of the system clock F_CLK arrives, the phase accumulation data output from the digital phase register and the frequency control word K are superimposed in the digital full adder 1111. The added result is then sent to the data input terminal of the first accumulator register, so that the adder continues to add the frequency control word under the action of the next clock.

[0014] Furthermore, the analog signal DAC generated by the FPGA signal generation module and converted by the D / A conversion unit is connected to the non-inverting input terminal of the first operational amplifier U2 in the voltage-controlled current source unit. The voltage-controlled current source unit includes: a first operational amplifier U2, a second operational amplifier U3, a PNP transistor Q3, an NPN transistor Q4, multiple capacitors and multiple resistors. The voltage signal DOUT output by the D / A conversion unit enters the non-inverting input terminal of the first operational amplifier U2 through the sixth capacitor C6. The reverse input terminal of the first operational amplifier U2 is connected to the fourteenth resistor R14 and connected to GND through the sixteenth resistor R16. The output terminal of the first operational amplifier U2 is connected to the thirteenth resistor R13 and then to the base of the NPN transistor Q4. The collector of the NPN transistor Q4 is connected to the eleventh resistor R11 and then to the power supply VCC30. At the same time, the collector voltage of the NPN transistor Q4 serves as the input terminal of the non-inverting input terminal of the second operational amplifier U3. The inverting input terminal of the second operational amplifier U3 is connected to the ninth resistor R9 and the power supply VCC30. The inverting input terminal of the second operational amplifier U3 is connected to the seventh capacitor C7 and then to the output terminal of the second operational amplifier U3. The inverting input terminal of the second operational amplifier U3 is also connected to the ninth resistor R9 and the tenth resistor R10 in sequence. The output terminal of the second operational amplifier U3 is connected to the twelfth resistor R12 and to the base of the PNP transistor Q3. The emitter of the PNP transistor Q3 is connected to the tenth resistor R10 and then to the power supply VCC30. The collector of the PNP transistor Q3 is connected to the fifteenth resistor R15 and then to GND. The collector of the PNP transistor Q3 serves as a variable current source CUR_DET1 and is directly connected to the H-bridge circuit unit in the intermediate frequency bipolar pulse generation module.

[0015] Furthermore, the H-bridge circuit unit includes: a sixth chip U6 and a seventh chip U7, wherein the gate G1 of the first NMOS tube in the sixth chip U6 is connected to the output switching signal PWM1_A_MOS1 of the H-bridge driving unit, the gate G2 of the second NMOS tube in the seventh chip U7 is connected to the output switching signal PWM1_A_MOS2 of the H-bridge driving unit, the gate G2 of the second NMOS tube in the sixth chip U6 is connected to the output switching signal PWM1_B_MOS2 of the H-bridge driving unit, the gate G1 of the first NMOS tube in the seventh chip U7 is connected to the output switching signal PWM1_B_MOS1 of the H-bridge driving unit, a filter circuit consisting of a twenty-first resistor R21 and a ninth capacitor C9 in series is connected in parallel between the drain D1 and the source S1 of the first NMOS tube in the sixth chip U6, and a twenty-second resistor R22 and a tenth capacitor C1 are connected in parallel between the drain D2 and the source S2 of the second NMOS tube in the sixth chip U6. 10 in series, and the source S1 of the first NMOS transistor in the sixth chip U6 is connected to the drain D2 of the second NMOS transistor, and then connected to the first electrode signal VS1; similarly, a filtering circuit formed by a twenty-third resistor R23 and an eleventh capacitor C11 in series is connected in parallel between the drain D1 and source S1 of the first NMOS transistor in the seventh chip U7, and a filtering circuit formed by a twenty-fourth resistor R24 ​​and a twelfth capacitor C12 in series is connected in parallel between the drain D2 and source S2 of the second NMOS transistor in the sixth chip U6, and the source S1 of the first NMOS transistor in the seventh chip U7 is connected to the drain D2 of the second NMOS transistor, and then connected to the second electrode signal VS2; the drain D1 of the first NMOS transistor in the sixth chip U6 and the drain D1 of the first NMOS transistor in the seventh chip U7 are connected, and then connected to the collector output terminal CUR_DET1 of the PNP transistor Q3 in the voltage-controlled current source unit, thereby receiving the low-frequency current modulation signal.

[0016] Furthermore, the MCU control module generates two PWM signals, PWM_A and PWM_B. The high levels of PWM_A and PWM_B cannot overlap in the same cycle. That is, when PWM_A is high, PWM_B must be low. Conversely, when PWM_B is high, PWM_A must be low.

[0017] Furthermore, assume that the PWM_A and PWM_B signal frequencies are the same , set the PWM_A pulse width to ,PWM_B pulse width is , then = = , that is, the pulse width of the two PWM_A and PWM_B signals is the same, and the period of the PWM_A and PWM_B signals is Same duty cycle The same, and satisfy:

[0018] , , ;

[0019] Set the pulse width of PWM_A , the pulse width of PWM_B , and there are , among which, is the dead time.

[0020] Furthermore, , pulse width , , ; The period when PWM_A and PWM_B signals are both low level. .

[0021] Furthermore, the low-level write signal generated by the signal generating unit is triggered by the falling edge of PWM_B, and the low-level signal generated is connected to the D / A conversion unit after passing through the OR gate logic circuit. pin.

[0022] The present invention has the following beneficial effects:

[0023] The FPGA-based multi-mode electrical stimulation circuit provided by the present invention sends two PWM signals through the MCU controller. On the one hand, it provides a switching control signal for the bi-phase pulse generating circuit. On the other hand, the state change of the PWM pulse signal is synchronized with the current change in the FPGA signal generating module, thereby ensuring the stability of the effective pulse width of the bi-phase polarity pulse signal; further, because the FPGA signal generating module independently generates current waveforms of different modes, it avoids the distortion of the current waveform caused by the MCU software running multiple tasks when the MCU software realizes different mode current waveforms through software; therefore, the present invention can better ensure the integrity of the bipolar pulse current signal waveform and the effectiveness of treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0025] Figure 1The structure diagram of the FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device of the present invention is shown.

[0026] Figure 2 The schematic diagram of the signal generating unit of the present invention is shown.

[0027] Figure 3 Shown Figure 2 Schematic diagram of the accumulator register.

[0028] Figure 4 The circuit principle diagram of the D / A conversion unit of the present invention is shown.

[0029] Figure 5 The circuit principle diagram of the voltage-controlled current source unit of the present invention is shown.

[0030] Figure 6 The circuit diagram of the chip U4 in the H-bridge driving unit of the present invention is shown.

[0031] Figure 7 The circuit diagram of chip U5 in the H-bridge driving unit of the present invention is shown.

[0032] Figure 8 The diagram of the H-bridge circuit unit of the present invention is shown.

[0033] Figure 9 A schematic diagram of the PWM_A and PWM_B signal waveforms is shown.

[0034] Figure 10 The figure shows the signal connection diagram between the MCU control module and the FPGA signal generation module of the present invention.

[0035] Figure 11 The bipolar pulse waveform output by the H-bridge circuit unit of the present invention is shown.

[0036] Figure 12 The waveform diagram of the half-sine wave modulation signal output by the D / A conversion unit of the present invention is shown.

[0037] Figure 13 It shows the waveform of the square wave modulation signal output by the D / A conversion unit of the present invention.

[0038] Figure 14 It shows the waveform of the triangle wave modulation signal output by the D / A conversion unit of the present invention.

[0039] Figure 15 The waveform of the sawtooth wave modulation signal output by the D / A conversion unit of the present invention is shown.

[0040] Figure 16 The waveform diagram of the trapezoidal wave modulation signal output by the D / A conversion unit of the present invention is shown.

[0041] Figure 17 The waveform diagram of the exponential wave modulation signal output by the D / A conversion unit of the present invention is shown.

[0042] Figure 18 The waveform of a bipolar intermediate frequency modulated sinusoidal intermediate frequency modulated signal after amplitude modulation by the device provided by the present invention is shown.

[0043] Figure 19 The waveform diagram of the bipolar intermediate frequency modulated square wave intermediate frequency modulated signal after amplitude modulation by the device provided by the present invention is shown.

[0044] Figure 20 The waveform of the bipolar intermediate frequency modulated triangle wave intermediate frequency modulated signal after amplitude modulation by the device provided by the present invention is shown.

[0045] Figure 21 The waveform of a bipolar intermediate frequency modulated sawtooth intermediate frequency modulated signal after amplitude modulation by the device provided by the present invention is shown.

[0046] Figure 22 The waveform diagram of the bipolar intermediate frequency modulated trapezoidal wave intermediate frequency modulated signal after amplitude modulation by the device provided by the present invention is shown.

[0047] Figure 23 The waveform diagram of the bipolar intermediate frequency modulated exponential wave intermediate frequency modulated signal after amplitude modulation by the device provided by the present invention is shown.

[0048] The reference numerals in the above drawings are:

[0049] 1. FPGA signal generation module; 11. Signal generation unit; 111. First accumulator register; 1111. Digital full adder; 1112. Digital phase register; 112. Second accumulator register; 113. Third accumulator register; 12. Waveform data storage unit; 121. Waveform data table ROM; 2. Low-frequency current modulation signal generation module; 21. D / A conversion unit; 22. Voltage-controlled current source unit; 3. Intermediate-frequency bipolar pulse generation module; 31. H-bridge drive unit; 32. H-bridge circuit unit; 4. MCU control module; 5. Power supply module; 6. Electrode unit; 7. Human-machine interface module. DETAILED DESCRIPTION

[0050] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0051] like Figure 1The device is a FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generator, comprising: a power supply module 5, an MCU control module 4, an FPGA signal generation module 1, and a low-frequency current modulation signal generation module 2 connected in sequence; further comprising: a human-machine interface module 7 connected to the power supply module and the MCU control module; further comprising: an intermediate frequency bipolar pulse generation module and an electrode unit 6, wherein the power supply module, the intermediate frequency bipolar pulse generation module 3, and the electrode unit are connected in sequence, and the electrode unit serves as the output end of the intermediate frequency current pulse signal generator and is connected to the acupuncture points of the human body; the power supply module is also connected to the FPGA signal generation module and the low-frequency current modulation signal generation module respectively; wherein the FPGA signal generation module comprises The waveform data storage unit 12 and the signal generation unit 11 are interconnected, and the signal generation unit is connected to the MCU control module. The low-frequency current modulation signal generation module includes: a D / A conversion unit 21 and a voltage-controlled current source unit 22 are interconnected, and the signal generation unit is connected to the D / A conversion unit. The D / A conversion unit is composed of a DAC circuit, which is used to convert the digital low-frequency waveform signals of different modes output by the signal generation unit into analog low-frequency waveform signals of corresponding modes. The DAC circuit includes: a digital-to-analog conversion chip, multiple resistors, and multiple power supplies. The analog signal output pin (outputting analog voltage signal) of the digital-to-analog conversion chip is connected to the non-inverting input terminal of the first operational amplifier U2 in the voltage-controlled current source unit circuit. The low-frequency current modulation signal generation module is used to convert the digital low-frequency signal output by the FPGA signal generation module from digital to analog. The converted low-frequency analog waveform signal is converted into a low-frequency analog voltage signal. The low-frequency analog voltage signal is then converted to a current signal of different waveform modes by the voltage-current source unit and amplified. Current signals with different waveform patterns serve as power signals for the intermediate-frequency bipolar pulse generation module, thereby modulating the amplitude of the intermediate-frequency bipolar pulse signal. Since the low-frequency waveform signal is a current signal, the resulting low-frequency modulated intermediate-frequency bipolar pulse signal is a current pulse signal. When the waveform generated by the FPGA changes, the amplitude envelope waveform of the intermediate-frequency bipolar pulse signal also changes accordingly. Similarly, when the amplitude of the waveform generated by the FPGA changes, the current amplitude of the intermediate-frequency bipolar pulse signal also changes accordingly. The MCU control module is connected to the FPGA signal generation module via control signal lines. Under the control of the human-machine interface module, it issues control instructions to the FPGA signal generation module, controlling it to generate the corresponding waveform and change the waveform amplitude according to the actual control flow. This ultimately controls the modulated waveform and current amplitude of the output intermediate-frequency bipolar pulse signal. The power supply module includes a boost circuit and a buck circuit. The boost circuit is connected to the voltage-controlled current source unit; the buck circuit provides operating power to the MCU control module, FPGA signal generation module, and intermediate-frequency bipolar pulse generation module.The FPGA signal generation module includes: an FPGA and a peripheral circuit, and the peripheral circuit is connected to the low-frequency current modulation signal generation module through 8 data pins, 1 clock pin and 1 chip selection pin.

[0052] The FPGA signal generation module 1 stores data for six low-frequency digital waveforms (including sine, square, triangle, sawtooth, trapezoidal, and exponential waveforms) for generating these six low-frequency digital waveforms. Under the guidance of the human-machine interface module 7, these six low-frequency digital waveforms can each be a continuous low-frequency digital waveform or a combination of two or more waveforms. The low-frequency current modulation signal generation module 2 converts the discrete digital waveform signal generated by the FPGA signal generation module 1 into a time-continuous analog voltage signal. This signal then passes through a voltage-to-current conversion circuit to generate low-frequency current signals of varying waveforms. This low-frequency current signal serves as the power source for the H-bridge switching circuit of the intermediate-frequency bipolar pulse generation module, generating a positively and negatively symmetrical bipolar current pulse signal from the H-bridge to the electrode unit 6.

[0053] The intermediate frequency bipolar pulse generation module includes: Figure 6 and Figure 7 The H-bridge driving unit 31 and the H-bridge circuit unit 32 are connected to each other. The MCU control module is connected to the Bluetooth module via serial communication, so that human-computer interaction can be achieved using a mobile phone via Bluetooth communication.

[0054] Specifically, if Figure 2As shown, the signal generating unit includes: a first accumulator register, a second accumulator register and a third accumulator register, and the waveform data storage unit includes a waveform data table ROM121, which is connected to the D / A conversion unit; the frequency word F_WORD is input into the first accumulator register, and under the control of the system clock CLK, the first accumulator register and the F_WORD of the second accumulator register are accumulated, and the output binary code is added to the phase control word P_WORD input into the third accumulator register as the address of the waveform data table ROM, and then the waveform data table ROM is addressed, and the output signal amplitude is converted into a low-frequency modulated waveform through the D / A conversion unit as the input of the voltage-controlled current source unit, so that the voltage-controlled current source unit outputs a current signal, and the current signal is stored in the waveform data storage unit. The current signal includes a sine wave, a square wave, a triangle wave, a sawtooth wave, a trapezoidal wave and an exponential wave. F_WORD is the frequency control word, represented by K, where N is its bit width. K is generally an integer, and its numerical value controls the frequency of the output signal. A larger numerical value indicates a higher frequency, while a smaller numerical value indicates a lower frequency. P_WORD is the phase control word, generally an integer, and its numerical value controls the phase offset of the output signal. It is primarily used for phase signal modulation. Under the control of the clock frequency CLK, the first accumulator register 111 accumulates F_WORD. The output binary code is added to the phase control word P_WORD and used as the address of the waveform data table ROM 121. The waveform data table ROM 121 is then addressed. The output signal amplitude is converted into a low-frequency modulated waveform by the D / A converter unit 21. This serves as the DAC input of the voltage-controlled current source unit 22 in the low-frequency modulation module, thereby outputting a stepped current signal.

[0055] The FPGA signal generation module is used to generate low-frequency digital waveform signals in different modes. Each current signal waveform generated by the FPGA signal generation module can be output individually or in combination, and the waveform amplitude is adjustable. The internal logic of the signal generation unit includes multiple accumulator registers, which are connected via a digital full adder. The waveform data storage unit generates a waveform data table, imports the waveform data, and then uses ROM addressing to output the data. The signal generation unit is used to generate six low-frequency pulses to achieve different modes. The waveform data storage unit converts the low-frequency pulse waveforms into MIF files and stores them for easy access. The waveform data storage unit 12 stores data corresponding to six waveforms: sine, square, triangle, sawtooth, trapezoidal, and exponential, at different peak currents. Each waveform has 60 amplitude data points, corresponding to the waveform data for each current value when the output current starts at 0.5 mA and increases in steps of 0.5 mA to 30 mA. Each of the six waveforms can be output continuously or in combination.

[0056] The waveform data storage unit 12 uses the FPGA's internal ROM unit to store waveform data. In this embodiment, the ROM port settings are accessed in the Quartus II software, a ROM port is established, and the ROM IP core is configured. In this embodiment, the ROM data bit width is selected to be 8 bits. Since six types of waveform data and 60 different amplitude values ​​are required, the data depth of each waveform and each amplitude value is 64, requiring a total of 23,040 data addresses. Therefore, the total data depth is selected to be 32,768, providing ample margin for waveform data modification and program debugging. The use of a single clock control achieves simple control timing and low read latency. The external clock operating frequency of the FPGA signal generation module is 32.768 MHz, meaning that the FPGA signal generation module reads waveform data from the ROM read-only memory at 32.768 MHz. The operating frequency of the arithmetic units such as the adder designed in the software programming is also 32.768 MHz, ensuring timing consistency during the ROM table lookup process.

[0057] When designing the RTL circuit of the waveform data storage unit 12, you can first define the address reg type variable rom_add1 to represent the waveform data address, and then define the reg type variable rom_addr_reg to read the waveform data address in the ROM. This variable takes the upper six bits of the variable F_WORD, that is, the ROM read address is not updated at each system clock, but the address is updated once at multiple clocks. This ensures that when the phase accumulator overflows, the waveform data address read from the ROM table is exactly one cycle sampling point. After calling the ROM IP core, a .v file is generated in the project folder to establish the FPGA read ROM table port connection, which needs to be instantiated into the top-level module of the project. The module consumes a total of 262144 storage units and 1145 logic units. The final CLK clock frequency is set to 50MHz. When the reset signal rst is pulled low to 0, the entire system starts working. F_WORD starts to accumulate at the clock frequency, and the read address variable rom_addr_reg starts counting when the lower 26 bits of fword are all 1, that is, the upper 6 bits of F_WORD data are read, and then the value is assigned to the address variable rom_add1, and finally the waveform data is output at d_out.

[0058] Specifically, if Figure 3As shown, the first accumulator register 111, the second accumulator register 112, and the third accumulator register 113 are identical. The first accumulator register includes a digital full adder 1111 and a digital phase register 1112. When the rising edge of the system clock F_CLK arrives, the phase accumulation data output from the digital phase register and the frequency control word K are added together in the digital full adder 1111. The added result is then sent to the data input of the first accumulator register, allowing the adder to continue adding the frequency control word at the next clock. In this way, the accumulator register performs phase accumulation under the influence of the system clock. When the register is full, the accumulator register overflows. The entire process takes one cycle, which is called the DDS synthesis signal cycle.

[0059] Specifically, if Figure 4 As shown, the analog signal DAC generated by the FPGA signal generation module and converted by the D / A conversion unit is connected to the non-inverting input terminal of the first operational amplifier U2 in the voltage-controlled current source unit, as shown in FIG. Figure 5As shown, the voltage-controlled current source unit comprises a first operational amplifier U2, a second operational amplifier U3, a PNP transistor Q3, an NPN transistor Q4, multiple capacitors, and multiple resistors. The op amps are rail-to-rail output to ensure maximum output. Therefore, the voltage-controlled current source, consisting of a two-stage amplifier circuit and a common load ground, uses the OPA2192 dual op amp chip. The voltage signal DOUT output by the D / A converter unit passes through the sixth capacitor C6 and enters the non-inverting input of the first operational amplifier U2. The inverting input of the first operational amplifier U2 is connected to the fourteenth resistor R14 and then to GND via the sixteenth resistor R16. The eighth capacitor C8 and the fourteenth resistor R14 ensure circuit stability during transient changes in input voltage and load, and can be considered a filter circuit. R14 should be larger than R16, but not too large, as this will cause the bias current of the op amp to generate a large bias voltage. The RC parameters also affect the dynamic response speed of the circuit, so they should not be too large. The output of the first operational amplifier U2 is connected to a thirteenth resistor R13 and then to the base of an NPN transistor Q4. The collector of the NPN transistor Q4 is connected to an eleventh resistor R11 and then to the power supply VCC30. The collector voltage of the NPN transistor Q4 serves as the input to the non-inverting input of the second operational amplifier U3. The inverting input of the second operational amplifier U3 is connected to a ninth resistor R9 and then to the power supply VCC30. The inverting input of the second operational amplifier U3 is connected to a seventh capacitor C7 and then to the output of the second operational amplifier U3. The inverting input of the second operational amplifier U3 is also connected in sequence to the ninth resistor R9 and the tenth resistor R10. The output of the second operational amplifier U3 is connected to a twelfth resistor R12 and then to the base of a PNP transistor Q3. The emitter of the PNP transistor Q3 is connected to the tenth resistor R10 and then to the power supply VCC30. The collector of the PNP transistor Q3 is connected to a fifteenth resistor R15 and then to GND. Resistor R15 is a test load resistor, representing the output current load. In actual implementation, the collector of PNP transistor Q3 functions as a variable current source, CUR_DET1, directly connected to the H-bridge circuit unit in the intermediate-frequency bipolar pulse generator module. The voltage-controlled current source unit comprises two operational amplifier stages: a voltage-to-current conversion circuit comprised of a first operational amplifier, U2, and a current amplification circuit, comprised of a second operational amplifier, U3.In the voltage-current conversion circuit composed of the first operational amplifier U2 of the voltage-controlled current source unit, the non-inverting input terminal of the first operational amplifier U2 is connected to the data output pin of the D / A conversion unit, and the output of the first operational amplifier U2 is connected to the NPN transistor Q4; the emitter of the NPN transistor Q4 is connected to the fourteenth resistor R14 to the inverting input terminal of the first operational amplifier U2 to form negative feedback; the collector of the NPN transistor Q4 outputs the required current and is connected to the non-inverting input terminal of the second operational amplifier U3, the second operational amplifier U3 and the PNP transistor Q3 form a current amplification circuit, and the output terminal of the second operational amplifier U3 is connected to the base of the PNP transistor Q3; after the current of the NPN transistor Q4 in the first-stage operational amplifier is amplified, it is output by the collector of the PNP transistor Q3 in the second-stage operational amplifier as the output current and connected to the intermediate frequency bipolar pulse generation module.

[0060] The eight digital pins (DB0 to DB7) of the high-speed D / A converter device U9 used by the D / A converter unit 21, as well as the chip select pin and write pins Connect to the FPGA pin defined by FPGA signal generation module 1.

[0061] The H-bridge driver unit 31 is composed of two H-bridge driver chips, as shown in the attached figure. Figure 7 As shown in the figure, two H-bridge driver chips, U4 and U5 (optional chips such as the IR2110), connect to the HIN and LIN pins of the upper and lower IR2110 chips, respectively, and receive two PWM signals, PWM1_A and PWM1_B. After passing through the two H-bridge driver chips, the two PWM signals generate six signals: PWM1_A_HO, PWM1_A_LO, PWM1_B_HO, PWM1_B_LO, VS1, and VS2.

[0062] Of the six signals generated by the two H-bridge drive units, PWM1_A_HO passes through resistor R3, diode D2, voltage regulator D3, and resistor R4 to generate a switching signal PWM1_A_MOS1 for the gate G1 of the first NMOS transistor in the sixth chip U6 in the H-bridge circuit unit. PWM1_A_LO passes through resistor R5, diode D4, voltage regulator D5, and resistor R6 to generate a switching signal PWM1_A_MOS2 for the gate G2 of the second NMOS transistor in the seventh chip U7 in the H-bridge circuit unit. The level states of PWM1_A_MOS1 and PWM1_A_MOS2 are synchronized with the level state of PWM1_A in the PWM signal.

[0063] Of the six signals generated by the two H-bridge drive units, PWM1_B_HO passes through resistor R17, diode D7, voltage regulator D8, and resistor R18 to generate a switching signal PWM1_B_MOS1 for the gate G1 of the first NMOS transistor in the seventh chip U7 of the H-bridge circuit unit. PWM1_B_LO passes through resistor R19, diode D9, voltage regulator D10, and resistor R20 to generate a switching signal PWM1_B_MOS2 for the gate G2 of the second NMOS transistor in the sixth chip U6 of the H-bridge circuit unit. The voltage levels of PWM1_B_MOS1 and PWM1_B_MOS2 are synchronized with the voltage level of PWM1_B in the PWM signal.

[0064] Among the six signals generated by the two H-bridge driver chips, VS1 and VS2 serve as two electrode signals added to the load. After passing through the electrode unit, they can be connected to the skin electrode patch to generate bipolar pulse current signals acting on the human body.

[0065] Specifically, if Figure 8As shown, the H-bridge circuit unit includes: a sixth chip U6 and a seventh chip U7, which use the same NMOS tube devices. Each device has two identical NMOS switch tubes inside, thus forming an H-bridge circuit containing 4 NMOS switches. Among them, the gate G1 of the first NOMS tube in the sixth chip U6 is connected to the output switching signal PWM1_A_MOS1 of the H-bridge driving unit, the gate G2 of the second NMOS tube in the seventh chip U7 is connected to the output switching signal PWM1_A_MOS2 of the H-bridge driving unit, the gate G2 of the second NMOS tube in the sixth chip U6 is connected to the output switching signal PWM1_B_MOS2 of the H-bridge driving unit, the gate G1 of the first NMOS tube in the seventh chip U7 is connected to the output switching signal PWM1_B_MOS1 of the H-bridge driving unit, a filtering circuit consisting of a twenty-first resistor R21 and a ninth capacitor C9 in series is connected in parallel between the drain D1 and the source S1 of the first NMOS tube in the sixth chip U6, a filtering circuit consisting of a twenty-second resistor R22 and a tenth capacitor C10 in series is connected in parallel between the drain D2 and the source S2 of the second NMOS tube in the sixth chip U6, and the The source S1 of the first NMOS transistor in the sixth chip U6 and the drain D2 of the second NMOS transistor are connected and then connected to the first electrode signal VS1. Similarly, a filter circuit consisting of a twenty-third resistor R23 and an eleventh capacitor C11 is connected in parallel between the drain D1 and source S1 of the first NMOS transistor in the seventh chip U7. A filter circuit consisting of a twenty-fourth resistor R24 ​​and a twelfth capacitor C12 is connected in parallel between the drain D2 and source S2 of the second NMOS transistor in the sixth chip U6. Moreover, the source S1 of the first NMOS transistor in the seventh chip U7 and the drain D2 of the second NMOS transistor are connected and then connected to the second electrode signal VS2. The drain D1 of the first NMOS transistor in the sixth chip U6 and the drain D1 of the first NMOS transistor in the seventh chip U7 are connected and then connected to the collector output terminal CUR_DET1 of the PNP transistor Q3 in the voltage-controlled current source unit, thereby receiving the low-frequency current modulation signal. The sixth chip U6 and the fourth chip U7 use the same NMOS transistor device, and each device has two identical NMOS switch transistors inside, thus forming an H-bridge circuit containing four NMOS switches.

[0066] The two intermediate-frequency PWM signals with unequal phases generated by the MCU control module are first connected to the FPGA signal generation module. After passing through the internal timing circuit of the FPGA signal generation module, the two intermediate-frequency PWM signals have two functions: the first function is to output to the driver chip in the H-bridge circuit unit as the switching signal to control the four MOS tubes in the H-bridge circuit unit; the second function is to participate in controlling the digital input of the waveform of the D / A conversion unit of the FPGA signal generation module, so that when the current value changes, the low-frequency current modulation signal generation module remains synchronized with the effective pulse generation of the H-bridge switching signal, thereby avoiding instability in the pulse width of the modulated bipolar pulse.

[0067] The H-bridge circuit unit consists of an H-bridge driver chip and four NMOS switches. Two intermediate-frequency PWM signals, after passing through the H-bridge driver chip, serve as on / off control signals for the four NMOS switches. Each of the two intermediate-frequency PWM signals simultaneously controls the switching of two NMOS transistors. When either PWM signal is at an active high level, the corresponding two NMOS transistors are simultaneously closed. To ensure that two NMOS transistors in the H-bridge circuit unit are closed, the other two must be open. Both PWM signals cannot be at an active high level at the same time. By simultaneously opening and closing groups of two of the four NMOS transistors in the H-bridge circuit unit, a bipolar intermediate-frequency signal with different current directions is generated at the load.

[0068] The H-bridge circuit unit is connected to an electrode unit having two output terminals, and an external electrode sheet can be connected through the electrode unit to act on a human body load.

[0069] The peripheral circuit of the MCU control module also includes a human-machine interface module consisting of a waveform mode selection button circuit and a current size (gear) adjustment encoder interface circuit. The waveform selection button circuit can be used to select current waveforms of different modes; the current size can be controlled and adjusted through the current size adjustment encoder circuit.

[0070] The present invention uses an MCU control module to send two PWM signals, which, on the one hand, provide a switching control signal for the bipolar pulse generating circuit. On the other hand, the state change of the PWM pulse signal is synchronized with the current change in the FPGA signal generating module, thereby ensuring the stability of the effective pulse width of the bipolar polarity pulse signal. Because the FPGA signal generating module independently generates current waveforms of different modes, it avoids the distortion of the current waveform caused by the MCU software running multiple tasks when the MCU software implements different mode current waveforms through software. Therefore, the present invention can better ensure the integrity of the bipolar pulse current signal waveform and the effectiveness of treatment. When the two PWM signals are used as switching signals to generate bipolar pulses through the above-mentioned H-bridge circuit unit, the amplitude of the bipolar pulse is modulated by the low-frequency current modulation signal, and finally a medium-frequency current pulse signal with multi-mode current amplitude modulation is generated between the two electrode sheets connected between the first electrode VS1 and the second electrode VS2.

[0071] Specifically, if Figure 9 As shown, the MCU control module generates two PWM signals, PWM_A and PWM_B. The high levels of PWM_A and PWM_B cannot overlap in the same cycle. That is, when PWM_A is high, PWM_B must be low. Conversely, when PWM_B is high, PWM_A must be low.

[0072] Specifically, if Figure 9 As shown, assume that the PWM_A and PWM_B signal frequencies are the same , set the PWM_A pulse width to ,PWM_B pulse width is , then = = , that is, the pulse width of the two PWM_A and PWM_B signals is the same, and the period of the PWM_A and PWM_B signals is Same duty cycle The same, and satisfy:

[0073] , , ;

[0074] Set the pulse width of PWM_A , the pulse width of PWM_B , and there are , among which, This is the dead time to prevent all NMOS transistors of the H-bridge from being turned on at the same time.

[0075] Specifically, , pulse width , , ; The period when PWM_A and PWM_B signals are both low level. .

[0076] Specifically, the low-level write signal generated by the signal generating unit is triggered by the falling edge of PWM_B, and the low-level signal generated is connected to the D / A conversion unit after passing through the OR gate logic circuit. pin.

[0077] In this embodiment, the two PWM signals generated by the MCU control module 4 are input to the FPGA signal generation module. Under the above-mentioned characterization parameters, when the signal generation unit receives the MCU control instruction to change the current value, in order to prevent the current value change from occurring during the high level period of the PWM signal, thereby destroying the pulse width of the final output bipolar current pulse and affecting the treatment effect, the signal generation unit's write operation to the D / A conversion unit must occur before the effective high level of the two PWM signals, that is, during the Figure 9 in Therefore, in this embodiment, the low-level effective write signal generated by the signal generating unit must be triggered by the falling edge of PWM_B, and then connected to the D / A conversion unit after the PWM_A and PWM_B signals are connected to the D / A conversion unit. To ensure that the signal written to D / A is In this embodiment, a high-speed D / A converter, such as AD7801, is used, and the maximum effective time for writing and generating output signals is .

[0078] In this embodiment, after the two PWM signals PWM_A and PWM_B generated by the MCU controller module 4 are input into the FPGA signal generation module, in addition to participating in the synchronization of the signal writing to the D / A conversion unit, they are also connected to the H-bridge drive unit 31 circuit via the FPGA pins as the two signals PWM1_A and PWM1_B.

[0079] In this embodiment, the MCU control module 4 can be based on an STM32F103RCT6 microprocessor. In addition to generating two PWM signals, the MCU control module 4 also includes a human-machine interface circuit. This circuit includes a Bluetooth interface circuit and an EC11 rotary encoder control switch. By connecting the Bluetooth module via the MCU's serial communication interface and interfacing with the control software of a Bluetooth-enabled host computer (such as a mobile phone or tablet), functions such as low-frequency current signal waveform mode selection and low-current waveform frequency selection can be implemented, as well as output current range (current level) control. Output current level control can also be achieved via the EC11 rotary encoder control switch.

[0080] In this embodiment, in addition to PWM_A and PWM_B, the signal connection between the MCU control module and the FPGA is also connected to the FPGA signal generation module through an 11-bit control line, and control commands are sent to the signal generation unit through the 11-bit control line, including gear (current size) control, current waveform mode selection, current waveform frequency selection, etc. The connection between the MCU control module and the FPGA signal generation module is as follows Figure 10 shown.

[0081] The power supply module mainly includes a boost circuit and a buck circuit. First, the system's external power supply adopts a 12V lithium battery or a 12V DC power supply; the 12V power supply and 5V power supply are mainly used to power the driver chip IR2110, that is, the H-bridge driver unit 32; 3.3V is mainly used to power the main control chip STM32F103RCT6, that is, the MCU control module 4; the 36V power supply is mainly used to power the op amp chip and transistor of the voltage-controlled current source module 22.

[0082] Figure 11 This is a bipolar pulse waveform diagram of the H-bridge circuit of the present invention during normal output. Under the control of PWM signals with two pulse widths of 200μs, the width of the generated bipolar positive pulse and negative pulse are both 200μs.

[0083] Figure 12-17 This is the low-frequency current signal waveform diagram of the normal output of the present invention. The low-frequency digital pulse signal emitted by the FPGA signal generating module 1 is converted into voltage / current by the D / A conversion unit 21 and amplified for processing. The six waveforms have a pulse width of 6ms to 300ms and a period of 15ms to 1000ms, that is, a frequency of 60Hz to 1Hz.

[0084] Figures 18-23 This is a waveform diagram of a bipolar intermediate frequency modulated current pulse signal after amplitude modulation during normal output of the present invention. The current signal output by the voltage-controlled current source unit 22 is used as a power supply signal for the H-bridge circuit unit 32, ultimately achieving amplitude adjustment of the bipolar carrier signal.

[0085] In summary, the device provided by the present invention has the following beneficial effects:

[0086] (1) The present invention realizes precise control of stimulation current with a minimum resolution of 0.1 mA. By rotating the EC11 rotary encoder, the stimulation current is adjusted. The preset current value is adjustable from 0 to 30 mA and is divided into 60 gears. Every time the rotary encoder rotates once, the current value increases or decreases by 0.5 mA, so that the current can be changed in steps of up to 0.5 mA. Through testing and research, it was found that when the rotary encoder changes, the average change in the measured current value is 0.508 mA, which is within the allowable error range and meets the design requirements, thereby achieving the effect of precise current control.

[0087] (2) The present invention achieves precise control of the electrical stimulation frequency. In the carrier design of the present invention, the frequency is 2 kHz, and there is a 240 μs delay between the two PWM channels, thus forming an H-bridge circuit. In actual system testing, the intermediate frequency carrier can reach 2.0012 kHz, and under software design, the minimum dead time between the two PWM channels is controlled to 400 ns, meeting the design requirements. In actual testing, the intermediate frequency modulation wave frequency can be varied between 0 and 100 Hz, thus achieving precise frequency control.

[0088] (3) The present invention achieves precise control of waveform output. The present invention is designed to have seven modes, with a total of six signals. Each signal is output continuously, for a total of six modes; the seventh mode is a mode in which the six signals are output alternately and cyclically at a certain time interval. In the first six modes, the waveform can be controlled by the host computer or the mode selection button so that it can be output under the preset waveform. In the seventh mode, the six waveforms can be output alternately and cyclically.

[0089] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A device for generating a multi-mode amplitude-modulated intermediate frequency current pulse signal based on FPGA, characterized in that: include: The power supply module, MCU control module, FPGA signal generation module and low-frequency current modulation signal generation module are connected in sequence; It also includes: a human-machine interface module connected to the power supply module and the MCU control module; it also includes: an intermediate frequency bipolar pulse generation module and an electrode unit, the power supply module, the intermediate frequency bipolar pulse generation module and the electrode unit are connected in sequence, and the electrode unit serves as the output end of the intermediate frequency current pulse signal generation device and is connected to the acupuncture points of the human body; the power supply module is also connected to the FPGA signal generation module and the low-frequency current modulation signal generation module respectively; wherein the FPGA signal generation module includes: a waveform data storage unit and a signal generation unit connected to each other, and the signal generation unit is connected to the MCU control module; the low-frequency current modulation signal generation module includes: a D / A conversion unit and a voltage-controlled current source unit connected to each other, and the signal generation unit is connected to the D / A conversion unit; the intermediate frequency bipolar pulse generation module includes: an H-bridge drive unit and an H-bridge circuit unit connected to each other; The signal generating unit includes: a first accumulator register, a second accumulator register and a third accumulator register; the waveform data storage unit includes a waveform data table ROM, and the waveform data table ROM is connected to the D / A conversion unit; the frequency word F_WORD is input into the first accumulator register, and under the control of the system clock CLK, the first accumulator register and the F_WORD of the second accumulator register are accumulated, and the output binary code is added to the phase control word P_WORD input into the third accumulator register as the address of the waveform data table ROM, and then the waveform data table ROM is addressed, and the output signal amplitude is converted into a low-frequency modulated waveform through the D / A conversion unit as the input of the voltage-controlled current source unit, so that the voltage-controlled current source unit outputs a current signal, and the current signal is stored in the waveform data storage unit, and the current signal includes a sine wave, a square wave, a triangle wave, a sawtooth wave, a trapezoidal wave and an exponential wave; The MCU control module generates two PWM signals, PWM_A and PWM_B. The high level of PWM_A and the high level of PWM_B cannot overlap in the same cycle. That is, when PWM_A is high, PWM_B must be low. Conversely, when PWM_B is high, PWM_A must be low. Assume that the PWM_A and PWM_B signal frequencies are the same , set the PWM_A pulse width to ,PWM_B pulse width is , then = = , that is, the pulse width of the two PWM_A and PWM_B signals is the same, and the period of the PWM_A and PWM_B signals is Same duty cycle The same, and satisfy: ， , ； Set the pulse width of PWM_A , the pulse width of PWM_B , and there are , among which, is the dead time; , pulse width , , ; The period when PWM_A and PWM_B signals are both low level. .

2. The FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device according to claim 1, characterized in that: The power supply module includes: a boost circuit and a buck circuit; the boost circuit is connected to the voltage-controlled current source unit; the buck circuit provides working power for the MCU control module, FPGA signal generation module, and intermediate frequency bipolar pulse generation module.

3. The FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device according to claim 1, characterized in that: The first, second, and third accumulator registers are identical. The first accumulator register includes a digital full adder and a digital phase register. When the rising edge signal of the system clock F_CLK arrives, the phase accumulation data output from the digital phase register and the frequency control word K are superimposed in the digital full adder 1111. The result of the addition is then sent to the data input terminal of the first accumulator register, so that the adder continues to add the frequency control word under the action of the next clock.

4. The FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device according to claim 1, characterized in that: The analog signal DAC generated by the FPGA signal generation module and converted by the D / A conversion unit is connected to the non-inverting input terminal of the first operational amplifier U2 in the voltage-controlled current source unit. The voltage-controlled current source unit includes: a first operational amplifier U2, a second operational amplifier U3, a PNP transistor Q3, an NPN transistor Q4, multiple capacitors and multiple resistors. The voltage signal DOUT output by the D / A conversion unit enters the non-inverting input terminal of the first operational amplifier U2 through the sixth capacitor C6. The reverse input terminal of the first operational amplifier U2 is connected to the fourteenth resistor R14 and connected to GND through the sixteenth resistor R16. The output terminal of the first operational amplifier U2 is connected to the thirteenth resistor R13 and then to the base of the NPN transistor Q4. The collector of the NPN transistor Q4 is connected to the eleventh resistor R11 and then to the power supply VCC30. The collector voltage of the N transistor Q4 serves as the input of the non-inverting input terminal of the second operational amplifier U3. The inverting input terminal of the second operational amplifier U3 is connected to the ninth resistor R9 and the power supply VCC30. The inverting input terminal of the second operational amplifier U3 is connected to the seventh capacitor C7 and then to the output terminal of the second operational amplifier U3. The inverting input terminal of the second operational amplifier U3 is also connected to the ninth resistor R9 and the tenth resistor R10 in sequence. The output terminal of the second operational amplifier U3 is connected to the twelfth resistor R12 and to the base of the PNP transistor Q3. The emitter of the PNP transistor Q3 is connected to the tenth resistor R10 and then to the power supply VCC30. The collector of the PNP transistor Q3 is connected to the fifteenth resistor R15 and then to GND. The collector of the PNP transistor Q3 serves as a variable current source CUR_DET1 and is directly connected to the H-bridge circuit unit in the intermediate frequency bipolar pulse generation module.

5. The FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device according to claim 1, characterized in that: The H-bridge circuit unit includes: a sixth chip U6 and a seventh chip U7, wherein the gate G1 of the first NMOS tube in the sixth chip U6 is connected to the output switching signal PWM1_A_MOS1 of the H-bridge driving unit, the gate G2 of the second NMOS tube in the seventh chip U7 is connected to the output switching signal PWM1_A_MOS2 of the H-bridge driving unit, the gate G2 of the second NMOS tube in the sixth chip U6 is connected to the output switching signal PWM1_B_MOS2 of the H-bridge driving unit, the gate G1 of the first NMOS tube in the seventh chip U7 is connected to the output switching signal PWM1_B_MOS1 of the H-bridge driving unit, a filter circuit consisting of a twenty-first resistor R21 and a ninth capacitor C9 in series is connected in parallel between the drain D1 and the source S1 of the first NMOS tube in the sixth chip U6, and a filter circuit consisting of a twenty-second resistor R22 and a tenth capacitor C10 in series is connected in parallel between the drain D2 and the source S2 of the second NMOS tube in the sixth chip U6. A filtering circuit is formed by connecting the source S1 of the first NMOS transistor and the drain D2 of the second NMOS transistor in the sixth chip U6, and the filtering circuit is connected to the first electrode signal VS1. Similarly, a filtering circuit formed by connecting the twenty-third resistor R23 and the eleventh capacitor C11 in series is connected in parallel between the drain D1 and the source S1 of the first NMOS transistor in the seventh chip U7. A filtering circuit formed by connecting the twenty-fourth resistor R24 ​​and the twelfth capacitor C12 in series is connected in parallel between the drain D2 and the source S2 of the second NMOS transistor in the sixth chip U6. The source S1 of the first NMOS transistor in the seventh chip U7 and the drain D2 of the second NMOS transistor are connected, and then connected to the second electrode signal VS2. The drain D1 of the first NMOS transistor in the sixth chip U6 and the drain D1 of the first NMOS transistor in the seventh chip U7 are connected, and then connected to the collector output terminal CUR_DET1 of the PNP transistor Q3 in the voltage-controlled current source unit, thereby receiving the low-frequency current modulation signal.

6. The FPGA-based multi-mode amplitude modulation intermediate frequency current pulse signal generating device according to claim 1, characterized in that: The low-level write signal generated by the signal generation unit is triggered by the falling edge of PWM_B, and the low-level signal is connected to the D / A conversion unit after passing through the OR gate logic circuit. pin.

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