PCIe Tag reordering implementation method and system based on shared cache

Abstract

The invention provides a PCIe Tag reordering implementation method and system based on a shared cache, and relates to the technical field of communication data transmission. Comprising the following steps: initializing an idle BD queue; receiving a Cpld message, extracting a Tag field, and querying a queue information RAM (Random Access Memory); determining a physical address of a query queue information RAM according to the applied idle BD, performing physical enqueue, and linking the used idle BD to a BD linked list so as to complete physical enqueue according to a preset condition; updating the queue information RAM when the physical enqueue is completed; when all the preset Cpld messages corresponding to the preset Tag number are returned, sending a dequeuing instruction; when a dequeue instruction is received, a plurality of BD pointers are obtained according to the updated queue information RAM, and physical dequeue is carried out along the BD linked list to complete physical dequeue; and when the physical dequeue is completed, updating the updated queue information RAM. Therefore, cross-Tag multiplexing can be realized, and the transmission delay can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of communication data transmission, and in particular to a method and system for implementing Peripheral Component Interconnect Express Tag (PCIe Tag) reordering based on a shared cache. Background Art

[0002] In the data transmission architecture of the Peripheral Component Interconnect Express (PCIe) Direct Memory Access (DMA) engine, traditional out-of-order packet handling mechanisms generally employ a static pre-allocated storage model. This model pre-allocates a fixed-capacity storage area for each tag number based on the maximum read request size (MRRS) and maximum number of tags specified in the PCIe protocol, forming physically isolated independent storage blocks. While this model offers the advantage of a simple hardware implementation, it exhibits significant drawbacks in practical applications. Due to the dynamic fluctuations in the actual transmission volume of packets corresponding to different tags, the fixed allocation strategy causes storage space utilization to remain below a certain threshold for a long period of time. This leads to a large number of "storage holes" in unused areas, especially in high-concurrency, small-packet scenarios. Furthermore, the strong coupling between the number of tags and storage space limits system scalability. When link bandwidth is upgraded or protocol versions are updated, the storage architecture must be redesigned to accommodate the new MRRS parameters, resulting in wasted hardware resources. Therefore, it is necessary to improve and expand the static pre-allocated storage mode, which can be achieved through PCIe Tag reordering of the shared cache.

[0003] Currently, traditional shared-cache PCIe tag reordering methods typically require a strictly sequential storage access mechanism. However, in traditional shared-cache PCIe tag reordering methods, each tag is bound to a fixed physical address segment, and the DMA controller must process completion packets (Cpld) in tag number order. Even if data from lower-sequence tags has not yet arrived, the storage area of higher-sequence tags cannot be reused, making cross-tag multiplexing impossible with existing technologies. When long-delay tags are present, subsequent arriving data is forced to queue, increasing overall transmission latency. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a method and system for implementing PCIe tag reordering based on a shared cache, so as to solve the problem that the prior art cannot realize cross-tag multiplexing and increases the overall transmission delay.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a method for implementing PCIe tag reordering based on a shared cache, comprising:

[0007] Initialize the idle BD queue and obtain the initialized idle BD;

[0008] Receive Cpld message, extract Tag field according to Cpld message, and use Tag field as address to query queue information RAM;

[0009] Apply for the initialized free BD, determine the physical address corresponding to the query queue information RAM based on the applied free BD, and perform physical enqueue based on the physical address. Link the free BD used for physical enqueue to the BD linked list to complete the physical enqueue according to the preset conditions;

[0010] When physical enqueue is completed, update the queue information RAM;

[0011] Determine whether all the preset Cpld messages corresponding to the preset Tag number are returned. If so, send a dequeue instruction;

[0012] When receiving the dequeue instruction, multiple BD pointers are obtained according to the updated queue information RAM, and physical dequeue is performed along the BD linked list according to the multiple BD pointers to complete the physical dequeue;

[0013] When the physical dequeue is completed, the updated queue information RAM is updated to obtain Cpld messages with sequence, so as to complete the reordering of the Cpld messages.

[0014] A second aspect of the present invention provides a PCIe tag reordering implementation system based on a shared cache, comprising:

[0015] The idle BD management module is used to initialize the idle BD queue and obtain the initialized idle BD;

[0016] The reordering input control module is used to receive the Cpld message, extract the Tag field according to the Cpld message, and use the Tag field as the address to query the queue information RAM;

[0017] The reorder input control module is also used to apply for the initialized idle BD, determine the physical address corresponding to the query queue information RAM based on the applied idle BD, and perform physical enqueue according to the physical address;

[0018] The BD linked list management module is used to link the idle BDs used for physical enqueuing to the BD linked list to complete the physical enqueuing according to preset conditions;

[0019] The queue information management module is used to update the queue information RAM when the physical enqueue is completed;

[0020] The tag number management module is used to determine whether all the preset Cpld messages corresponding to the preset tag number are returned. If so, it sends a dequeue instruction;

[0021] The reordering output control module is used to obtain multiple BD pointers according to the updated queue information RAM when receiving the dequeue instruction, and perform physical dequeue along the BD linked list according to the multiple BD pointers to complete the physical dequeue;

[0022] The queue information management module is further configured to update the updated queue information RAM when the physical dequeueing is completed, to obtain Cpld messages with a sequence, so as to complete the reordering of the Cpld messages.

[0023] Compared with the prior art, the PCIe Tag reordering implementation method and system based on shared cache provided by the present invention initialize the idle BD queue to obtain an initialized idle BD; receive a Cpld message, extract the Tag field according to the Cpld message, and use the Tag field as the address to query the queue information RAM; apply for the initialized idle BD, determine the physical address corresponding to the query queue information RAM according to the idle BD after the application, and perform physical enqueue according to the physical address, link the idle BD used for physical enqueue to the BD linked list to complete the physical enqueue according to the preset conditions; when the physical enqueue is completed, update the queue information RAM; determine whether all the preset Cpld messages corresponding to the preset Tag number are returned, and if so, send a dequeue instruction; when the dequeue instruction is received, obtain multiple BD pointers according to the updated queue information RAM, and perform physical dequeue along the BD linked list according to the multiple BD pointers to complete the physical dequeue; when the physical dequeue is completed, update the updated queue information RAM to obtain Cpld messages with order to complete the reordering of the Cpld messages. In this way, the idle BDs in use can be linked to the BD linked list, and cross-tag multiplexing can be achieved based on the BD linked list. Initializing the idle BD queue can realize the division of the buffer according to the idle BD pointers, and perform physical enqueue and dequeue control based on the BD block linked list, so as to support the adaptive reorganization of non-continuous tag data and reduce the transmission delay in burst traffic scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0025] Figure 1 The flowchart of the method for implementing PCIe Tag reordering based on shared cache is schematically shown;

[0026] Figure 2 A schematic diagram schematically shows the queue information RAM format;

[0027] Figure 3 The following schematically shows the format of the BD link list information RAM;

[0028] Figure 4 The structure of the PCIe Tag reordering implementation system based on shared cache is schematically shown. DETAILED DESCRIPTION

[0029] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0030] It should be noted that, unless otherwise specified, the technical or scientific terms used in the present invention should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0031] The method in the embodiment of the present invention is described in detail below.

[0032] Figure 1 The flowchart of the PCIe Tag reordering method based on shared cache in the embodiment of the present invention is schematically shown. Figure 1 As shown, the PCIe Tag reordering implementation method based on shared cache may include:

[0033] S101: Initialize an idle BD queue to obtain initialized idle BDs.

[0034] Specifically, initializing the idle BD queue to obtain initialized idle BDs includes:

[0035] Step A1: Get the free BD pointer.

[0036] Step A2: The idle BD pointers are sequentially written into the first-in-first-out (FIFO) corresponding to the idle BD queue to partition the buffer and obtain initialized idle BDs.

[0037] The buffer is used to store out-of-order Cpld messages.

[0038] S102: Receive a Cpld message, extract a Tag field from the Cpld message, and use the Tag field as an address to query the queue information RAM.

[0039] Specifically, before step S102, when the DMA engine sends a memory request descriptor (Mrd) request, it will apply to the tag number management module for a free tag number on the current bus. At this time, the tag number management module will check whether there is an available tag number. If there is, the tag number will be returned as a response and filled into the tag number field of the Mrd transaction layer packet (TLP) message. After receiving the DMA read request, the CPU will use the tag number to fill in the Cpld message and return it. However, since the MRRS and the maximum completion packet length (Max Payload Size, MPS) are not necessarily equal, the CPU may return several Cpld packets for a DMA read request. However, in order to ensure that the Mrd request is not blocked, the CPU will return the Cpld messages in the order of responses rather than the order of requests. This may cause the Cpld messages to be returned to the DMA engine out of order.

[0040] When receiving a Cpld message, the reordering input control module first extracts the Tag field, uses the Tag field as an address to query the queue information RAM, and determines whether a corresponding Cpld message has been returned for the Tag field.

[0041] Figure 2 A schematic diagram schematically shows the queue information RAM format, see Figure 2 As shown, the queue information RAM format includes a head pointer, a tail pointer, and the number of BDs. The head pointer represents the starting BD of the queue corresponding to the current tag number, the tail pointer represents the ending BD of the queue corresponding to the current tag number, and the number of BDs represents the number of BDs currently in use in the queue corresponding to the tag number.

[0042] S103: Apply for an initialized idle BD, determine the physical address corresponding to the query queue information RAM based on the applied idle BD, perform physical enqueueing based on the physical address, link the idle BD used for physical enqueueing to the BD linked list, and complete physical enqueueing according to preset conditions.

[0043] Specifically, applying for an initialized idle BD and determining the physical address corresponding to the query queue information RAM according to the applied idle BD include:

[0044] Step B1: Apply for an initialized free BD and obtain the applied free BD.

[0045] When receiving the Cpld message, the reordering input control module applies for an initialized idle BD from the idle BD management module, that is, reads a BD from the initialized idle BD FIFO.

[0046] Step B2: Determine the physical address corresponding to the query queue information RAM according to the idle BDs after application, the byte size of the idle indication of each BD after application, and the offset value of the idle BD after application.

[0047] Specifically, the expression for querying the physical address corresponding to the queue information RAM is:

[0048] In_Queue_Addr=BD_ptr*BD_size+BD_offset;

[0049] In_Queue_Addr is the physical address corresponding to the query queue information RAM, BD_ptr is the idle BD after the request, BD_size is the byte size indicated by each idle BD after the request, and BD_offset is the offset value of the idle BD after the request. The offset value range of the idle BD after the request is related to the byte size indicated by each idle BD after the request and the data bit width of the data bus.

[0050] Specifically, physical enqueuing is completed according to preset conditions, including:

[0051] During the physical enqueuing process, when the current offset number meets the offset number of the idle BD after the application, the physical enqueuing is completed;

[0052] The expression for the offset number of idle BDs after application is:

[0053] BD_offset_num=BD_size / (Data_width / 8);

[0054] BD_offset_num is the offset number of the idle BD after application, BD_size is the byte size indicated by each idle BD after application, Data_width is the data bit width of the data bus, and Data_width / 8 is the number of bytes per beat of input and output data.

[0055] For example, when the byte size indicated by each idle BD after application is 64 bytes and the data bit width of the data bus is 128 bits, namely 16 bytes, writing 4 beats of data will use up one BD, so the number of offsets of the idle BD after each application is 4.

[0056] When physically enqueuing, the BD offset value increments from 0 with each write, and the physical enqueuing is completed when the offset number is reached. Alternatively, the physical enqueuing is completed when the last Cpld message is written to the corresponding physical address.

[0057] When writing the Cpld message into the Cpld storage RAM, the idle BD pointers used need to be linked to the BD linked list of the current physical enqueuing queue in sequence, thereby completing the logical physical enqueuing. The BD linked list management module maintains the link relationship of the BD linked list. Figure 3 The format diagram of the BD link list information RAM is schematically shown. Figure 3 As shown, the BD linked list includes a BD linked list entry. The format of the BD linked list includes the first frame length and the next BD pointer. The BD pointer is used as the address. The upper 32 bits of the entry indicate the first frame length of the BD queue occupied by the BD, and the lower 32 bits of the entry indicate the next BD pointer of the current BD pointer. This BD linked list can be used to maintain the link relationship between multiple queues. By writing the current enqueued BD pointer into the next hop field of the current queue's tail pointer, the idle BD used for physical enqueue can be linked to the BD linked list.

[0058] S104. When physical enqueuing is completed, update the queue information RAM.

[0059] The queue information RAM includes a queue head pointer, a queue tail pointer, and the number of BDs.

[0060] When physical enqueue is completed, the queue information RAM is updated, including:

[0061] Step C1: Determine whether the number of BDs in the queue in the queue information RAM is zero.

[0062] Determine whether the number of BDs in the queue in the queue information RAM is zero. If so, execute step C2; if not, execute step C3.

[0063] Step C2: Update the queue head pointer, queue tail pointer and BD quantity in the queue information RAM.

[0064] Step C3: Update the queue tail pointer and BD quantity in the queue information RAM.

[0065] For queues whose BD count in the queue information RAM is zero, this indicates that the currently enqueued Cpld message is the first Cpld message returned by the DMA read request for that tag number. Therefore, the queue head pointer, queue tail pointer, and BD count need to be updated simultaneously. For queues whose BD count in the queue information RAM is non-zero, this indicates that a Cpld message has already been returned for that tag number, and the queue head pointer is already determined. Therefore, only the queue tail pointer and BD count after this enqueue are updated.

[0066] S105: Determine whether all preset Cpld messages corresponding to the preset Tag numbers are returned. If so, send a dequeue instruction.

[0067] Determine whether all the preset Cpld messages corresponding to the preset Tag numbers are returned. If so, send a dequeue instruction, including:

[0068] Step D1: When the tag number corresponding to the Tag field is the same as the preset tag number, determine whether the length of the remaining unreturned bytes in the returned preset Cpld message is the same as the currently returned byte length.

[0069] When the Tag number corresponding to the Tag field is the same as the preset Tag number, it indicates that the preset Tag number complies with the order of the DMA request. Next, it is necessary to extract the current returned byte length and the length of the remaining unreturned bytes of the returned preset Cpld message, and determine whether the length of the remaining unreturned bytes in the returned preset Cpld message is the same as the current returned byte length. If they are the same, it indicates that the currently returned preset Cpld message is already the last preset Cpld message returned by the DMA read request of the preset Tag number, and step D2 needs to be executed. If they are not the same, it indicates that the currently returned preset Cpld message is no longer the last preset Cpld message returned by the DMA read request of the preset Tag number, and the preset Cpld messages have not all been returned, and the return operation of the preset Cpld message needs to be continued.

[0070] Step D2: When the length of the remaining bytes not returned is the same as the length of the bytes currently returned, all preset Cpld messages are returned and a dequeue instruction is sent.

[0071] When the length of the remaining unreturned bytes is the same as the length of the currently returned bytes, all preset Cpld messages are returned, and the dequeue flag corresponding to the preset tag number is raised. If the dequeue flag corresponding to the expected returned preset tag number is detected to be raised, a dequeue instruction is sent to indicate preparation for physical dequeue.

[0072] S106 , when a dequeue instruction is received, a plurality of BD pointers are respectively obtained according to the updated queue information RAM, and physical dequeue is respectively performed along the BD linked list according to the plurality of BD pointers to complete the physical dequeue.

[0073] The multiple BD pointers include a head pointer, a next BD pointer, and another BD pointer, and the another BD pointer is a next pointer of the next BD pointer.

[0074] Specifically, when a dequeue instruction is received, multiple BD pointers are obtained according to the updated queue information RAM, and physical dequeue is performed along the BD linked list according to the multiple BD pointers to complete the physical dequeue, including:

[0075] Step E1: When a dequeue instruction is received, a head pointer is obtained according to the updated queue information RAM.

[0076] Step E2: Calculate the address of the first read storage RAM according to the head pointer.

[0077] The expression for the address of the first read storage RAM is:

[0078] De_Queue_Addr=BD_ptr0*BD_size0+BD_offset0;

[0079] Wherein, De_Queue_Addr is the address of the first read storage RAM, BD_ptr0 is the head pointer, BD_size0 is the byte size indicated by the head pointer, and BD_offset0 is the offset value of the head pointer.

[0080] Step E3: Read the corresponding Cpld message according to the address of the first read storage RAM to complete the physical dequeue along the BD linked list.

[0081] Step E4: Obtain the next BD pointer according to the updated queue information RAM.

[0082] Step E5: Calculate the address of the second read storage RAM according to the next BD pointer.

[0083] Step E6: Read the corresponding Cpld message according to the address of the second read storage RAM to complete the physical dequeue along the BD linked list, and use another BD pointer as the next BD pointer, return to the step of obtaining the next BD pointer according to the updated queue information RAM, until the length of the remaining unreturned bytes in the returned Cpld message is the same as the length of the currently returned bytes, the physical dequeue is completed to complete the physical dequeue.

[0084] For the BD pointer currently being dequeued, the first dequeue is the head pointer retrieved from the queue information RAM. After all the bytes indicated by the head pointer are dequeued, the BD linked list is queried with the head pointer as the address, and the next BD pointer is used as the new dequeue BD pointer BD_ptr0 to continue physical dequeueing. Then, another BD pointer is used as the next BD pointer, and the process returns to step E4 to continue physical dequeueing. When the length of the remaining unreturned bytes in the returned Cpld message is the same as the length of the currently returned bytes, the physical dequeueing is completed.

[0085] After the physical dequeue is performed, a counter will be maintained to count the byte length of the dequeue.

[0086] S107 . When the physical dequeue is completed, the updated queue information RAM is updated to obtain Cpld messages with sequence, so as to complete the reordering of the Cpld messages.

[0087] Specifically, when the physical dequeue is completed, the updated queue information RAM is updated to obtain Cpld messages with order to complete the reordering of the Cpld messages, including:

[0088] When the physical dequeue is completed, the BD quantity field in the updated queue information RAM is cleared to update the updated queue information RAM, and the Cpld messages with sequence are obtained to complete the reordering of the Cpld messages.

[0089] When the physical dequeue is completed, the tag number needs to be recycled.

[0090] The present invention constructs dynamically scalable storage through the collaborative design of a shared cache pool and a BD linked list, breaking through the resource limitations of the traditional fixed pre-allocation mode. Specifically, after the receiving end parses the Tag information of the Cpld message packet, it dynamically applies for BD from the shared pool according to the real-time load status, supporting the completion of block address mapping and linked list node updates within a single cycle. For multi-Tag concurrent scenarios, a fast matching mechanism based on content-addressable memory (CAM) is adopted to maintain independent linked list head and tail pointers and expected data volume counters for each active tag, and the arrival progress of data packets is tracked in real time through the hardware state machine. When it is detected that all data packets of the same tag have been received, the DMA engine is triggered to reorganize the data stream in the order of the BD linked list. In addition, the circuit supports dynamic configuration of BD block size (adjustable 64B / 128B / 256B) and cache pool capacity during runtime, and realizes automatic adaptation to the PCIe protocol version through the register interface. During the upgrade process from Gen4 to Gen5, the MRRS parameter change requirements can be met without hardware reconstruction, and the system scalability is greatly improved.

[0091] Based on the above Figure 1 It can be seen from the implementation method that the embodiment of the present invention initializes the idle BD queue to obtain an initialized idle BD; receives a Cpld message, extracts the Tag field according to the Cpld message, and uses the Tag field as the address to query the queue information RAM; applies for the initialized idle BD, determines the physical address corresponding to the query queue information RAM according to the idle BD after the application, and performs physical enqueueing according to the physical address, and links the idle BD used for physical enqueueing to the BD linked list to complete the physical enqueueing according to the preset conditions; when the physical enqueueing is completed, updates the queue information RAM; determines whether all the preset Cpld messages corresponding to the preset Tag number are returned, and if so, sends a dequeue instruction; when receiving the dequeue instruction, obtains multiple BD pointers according to the updated queue information RAM, and performs physical dequeueing along the BD linked list according to the multiple BD pointers to complete the physical dequeueing; when the physical dequeueing is completed, updates the updated queue information RAM to obtain Cpld messages with sequence to complete the reordering of the Cpld messages. In this way, the idle BDs in use can be linked to the BD linked list, and cross-tag multiplexing can be achieved based on the BD linked list. Initializing the idle BD queue can realize the division of the buffer according to the idle BD pointers, and perform physical enqueue and dequeue control based on the BD block linked list, so as to support the adaptive reorganization of non-continuous tag data and reduce the transmission delay in burst traffic scenarios.

[0092] Based on the same inventive concept, as an implementation of the above-mentioned PCIe Tag reordering implementation method based on shared cache, an embodiment of the present invention further provides a PCIe Tag reordering implementation system based on shared cache. Figure 4 This is a structural diagram of a PCIe Tag reordering implementation system based on shared cache in an embodiment of the present invention, see Figure 4 As shown, the PCIe Tag reordering implementation system based on shared cache may include:

[0093] The idle BD management module 401 is used to initialize the idle BD queue and obtain initialized idle BDs;

[0094] The reorder input control module 402 is used to receive the Cpld message, extract the Tag field according to the Cpld message, and use the Tag field as an address to query the queue information RAM;

[0095] The reorder input control module 402 is further used to apply for an initialized idle BD, determine the physical address corresponding to the query queue information RAM according to the applied idle BD, and perform physical enqueue according to the physical address;

[0096] The BD link list management module 403 is used to link the idle BDs used for physical enqueuing to the BD link list to complete the physical enqueuing according to preset conditions;

[0097] The queue information management module 404 is used to update the queue information RAM when the physical enqueue is completed;

[0098] Tag number management module 405, used to determine whether all preset Cpld messages corresponding to the preset Tag number are returned, and if so, send a dequeue instruction;

[0099] The reorder output control module 406 is configured to obtain multiple BD pointers according to the updated queue information RAM when receiving a dequeue instruction, and perform physical dequeue along the BD linked list according to the multiple BD pointers to complete the physical dequeue;

[0100] The queue information management module 404 is further configured to update the updated queue information RAM when the physical dequeueing is completed, to obtain Cpld messages with sequence, so as to complete the reordering of the Cpld messages.

[0101] The idle BD management module 401 is specifically used to obtain idle BD pointers; write the idle BD pointers into the FIFOs corresponding to the idle BD queues in sequence to realize the division of the buffer zone and obtain initialized idle BDs. The buffer zone is used to store out-of-order Cpld messages.

[0102] The reorder input control module 402 is specifically used to apply for the initialized free BD and obtain the free BD after the application; determine the physical address corresponding to the query queue information RAM according to the free BD after the application, the byte size of the free indication of each BD after the application, and the offset value of the free BD after the application.

[0103] In the reorder input control module 402, the expression for the physical address corresponding to the query queue information RAM is:

[0104] In_Queue_Addr=BD_ptr*BD_size+BD_offset;

[0105] Among them, In_Queue_Addr is the physical address corresponding to the query queue information RAM, BD_ptr is the idle BD after application, BD_size is the byte size indicated by each idle BD after application, and BD_offset is the offset value of the idle BD after application.

[0106] The reordering input control module 402 completes the physical enqueuing according to the preset conditions, including: during the physical enqueuing process, when the current offset number meets the offset number of the idle BD after the application, completing the physical enqueuing;

[0107] The expression for the offset number of idle BDs after application is:

[0108] BD_offset_num=BD_size / (Data_width / 8);

[0109] BD_offset_num is the offset number of the idle BD after application, BD_size is the byte size indicated by each idle BD after application, Data_width is the data bit width of the data bus, and Data_width / 8 is the number of bytes per beat of input and output data.

[0110] The queue information management module 404 is specifically used to determine whether the BD quantity of the queue in the queue information RAM is zero; if so, update the queue head pointer, queue tail pointer and BD quantity in the queue information RAM; if not, update the queue tail pointer and BD quantity in the queue information RAM.

[0111] The tag number management module 405 is specifically used to determine whether the length of the remaining unreturned bytes in the returned preset Cpld message is the same as the length of the currently returned bytes when the tag number corresponding to the Tag field is the same as the preset tag number; when the length of the remaining unreturned bytes is the same as the length of the currently returned bytes, all preset Cpld messages are returned and a dequeue instruction is sent.

[0112] The reordering output control module 406 is specifically used to obtain a head pointer according to the updated queue information RAM when receiving a dequeue instruction, wherein the multiple BD pointers include a head pointer, a next BD pointer and another BD pointer, and the another BD pointer is the next pointer of the next BD pointer; calculate the address of the first read storage RAM according to the head pointer; read the corresponding Cpld message according to the address of the first read storage RAM to complete physical dequeue along the BD linked list; obtain the next BD pointer according to the updated queue information RAM; calculate the address of the second read storage RAM according to the next BD pointer; read the corresponding Cpld message according to the address of the second read storage RAM to complete physical dequeue along the BD linked list, and use the another BD pointer as the next BD pointer, and return to the step of obtaining the next BD pointer according to the updated queue information RAM, until the length of the remaining unreturned bytes in the returned Cpld message is the same as the length of the currently returned bytes, and the physical dequeue is completed to complete the physical dequeue.

[0113] The queue information management module 404 is specifically configured to clear the BD quantity field in the updated queue information RAM to zero when the physical dequeue is completed, so as to update the updated queue information RAM and obtain Cpld messages with order, thereby completing the reordering of the Cpld messages.

[0114] The tag number management module 405 is further used to maintain a certain number of tag numbers, which is the maximum number of tag numbers supported in parallel by the current DMA engine.

[0115] When the DMA engine is used to send Mrd TLP, it needs to fill the fields according to PCIe rules, including the Tag field, and initiate an application to the Tag number management module 405 through the valid_ready handshake model.

[0116] The tag number management module 405 also checks the number of free BDs in the entire shared buffer to determine whether to respond to the request. If the number of free BDs is insufficient to store the length of the DMA request, the request is rejected. If the number of free BDs is sufficient, the module checks whether there are any free tags. If not, this indicates that the number of tags on the bus has reached the maximum number of tags supported concurrently by the DMA engine, and the request is rejected. If both the sufficient number of free BDs and the availability of free tags are met, the module returns an available tag number to respond to the request and sets the tag number status of the response to "busy."

[0117] The reordering output control module 406 is further configured to return the corresponding tag number after the physical dequeue is completed, and at this time, the state of the tag number is reset to "idle", thereby realizing a tag number recycling mechanism.

[0118] The reordering output control module 406 is further configured to write the dequeued BDs back to the idle BD management module 401 and maintain queue information after all physical dequeuing is completed.

[0119] The queue information management module 404 is also used to maintain the queue information RAM.

[0120] The PCIe Tag reordering implementation system based on shared cache also includes a Cpld storage RAM 407, which is used to store Cpld messages, write addresses, write Cpld messages and read addresses, wherein the write addresses and write Cpld messages are calculated by the reordering input control module 402, and the read address is calculated by the reordering output control module 406.

[0121] It should be noted that the above description of the embodiment of the PCIe Tag reordering system based on a shared cache is similar to the description of the embodiment of the PCIe Tag reordering method based on a shared cache, and has similar beneficial effects as the embodiment of the PCIe Tag reordering method based on a shared cache. For any technical details not disclosed in the embodiment of the PCIe Tag reordering system based on a shared cache according to the present invention, please refer to the description of the embodiment of the PCIe Tag reordering method based on a shared cache according to the present invention.

[0122] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for implementing PCIe tag reordering based on shared cache, characterized in that: include: Initialize the idle BD queue and obtain the initialized idle BD; Receive a Cpld message, extract a Tag field from the Cpld message, and use the Tag field as an address to query the queue information RAM; Applying for the initialized idle BD, determining the physical address corresponding to the query queue information RAM according to the applied idle BD, performing physical enqueuing according to the physical address, linking the idle BD used for physical enqueuing to the BD linked list, and completing physical enqueuing according to preset conditions; When physical enqueuing is completed, updating the queue information RAM; Determine whether all the preset Cpld messages corresponding to the preset Tag number are returned. If so, send a dequeue instruction; When receiving the dequeue instruction, obtaining multiple BD pointers according to the updated queue information RAM respectively, and performing physical dequeue along the BD linked list respectively according to the multiple BD pointers to complete the physical dequeue; When the physical dequeue is completed, the updated queue information RAM is updated to obtain Cpld messages with sequence, so as to complete the reordering of the Cpld messages.

2. The PCIe tag reordering method based on shared cache according to claim 1, characterized in that: Initializing the idle BD queue to obtain initialized idle BDs includes: Get the free BD pointer; The idle BD pointers are sequentially written into the FIFOs corresponding to the idle BD queues to partition the buffer zone and obtain the initialized idle BDs. The buffer zone is used to store out-of-order Cpld messages.

3. The PCIe tag reordering method based on shared cache according to claim 1, characterized in that: The applying for the initialized idle BD and determining the physical address corresponding to the query queue information RAM according to the applied idle BD include: Applying for the initialized idle BD to obtain the applied idle BD; The physical address corresponding to the query queue information RAM is determined according to the idle BDs after the application, the byte size of the idle indication of each BD after the application, and the offset value of the idle BDs after the application.

4. The method for implementing PCIe tag reordering based on shared cache according to claim 3, wherein: The expression of the physical address corresponding to the query queue information RAM is: In_Queue_Addr=BD_ptr*BD_size+BD_offset; Among them, In_Queue_Addr is the physical address corresponding to the query queue information RAM, BD_ptr is the idle BD after the application, BD_size is the byte size indicated by each idle BD after the application, and BD_offset is the offset value of the idle BD after the application.

5. The method for implementing PCIe tag reordering based on shared cache according to claim 4, wherein: The physical enqueuing is completed according to the preset conditions, including: During the physical enqueuing process, when the current offset number meets the offset number of the idle BD after the application, the physical enqueuing is completed; The expression for the offset number of the idle BD after the application is: BD_offset_num=BD_size / (Data_width / 8); BD_offset_num is the offset number of the idle BD after the application, BD_size is the byte size indicated by each idle BD after the application, Data_width is the data bit width of the data bus, and Data_width / 8 is the number of bytes per beat of input and output data.

6. The method for implementing PCIe tag reordering based on shared cache according to claim 1, wherein: When the physical enqueue is completed, updating the queue information RAM includes: Determine whether the number of BDs in the queue in the queue information RAM is zero; If yes, then update the queue head pointer, queue tail pointer and the number of BDs in the queue information RAM; If not, the queue tail pointer and the BD quantity in the queue information RAM are updated.

7. The method for implementing PCIe tag reordering based on shared cache according to claim 1, wherein: The step of determining whether all preset Cpld messages corresponding to the preset Tag numbers are returned, and if so, sending a dequeue instruction, includes: When the tag number corresponding to the Tag field is the same as the preset tag number, determining whether the length of the remaining unreturned bytes in the returned preset Cpld message is the same as the currently returned byte length; When the length of the remaining unreturned bytes is the same as the length of the currently returned bytes, all of the preset Cpld messages are returned, and the dequeue instruction is sent.

8. The method for implementing PCIe tag reordering based on shared cache according to claim 1, wherein: The multiple BD pointers include a head pointer, a next BD pointer, and another BD pointer, where the another BD pointer is a next pointer of the next BD pointer. When receiving the dequeue instruction, the multiple BD pointers are obtained according to the updated queue information RAM, and physical dequeue is performed along the BD linked list according to the multiple BD pointers to complete the physical dequeue, including: Upon receiving the dequeue instruction, obtaining the head pointer according to the updated queue information RAM; Calculating the address of the first read storage RAM according to the head pointer; Reading the corresponding Cpld message according to the address of the first read storage RAM to complete physical dequeue along the BD linked list; Obtaining the next BD pointer according to the updated queue information RAM; Calculating the address of the second read storage RAM according to the next BD pointer; The corresponding Cpld message is read according to the address of the second read storage RAM to complete the physical dequeue along the BD linked list, and the other BD pointer is used as the next BD pointer, and the step of obtaining the next BD pointer according to the updated queue information RAM is returned until the length of the remaining unreturned bytes in the returned Cpld message is the same as the length of the currently returned bytes, and the physical dequeue is completed to complete the physical dequeue.

9. The method for implementing PCIe tag reordering based on shared cache according to claim 8, characterized in that: When the physical dequeue is completed, the updated queue information RAM is updated to obtain Cpld messages with order to complete the reordering of the Cpld messages, including: When the physical dequeue is completed, the BD quantity field in the updated queue information RAM is cleared to update the updated queue information RAM, and the Cpld messages with sequence are obtained to complete the reordering of the Cpld messages.

10. A PCIe Tag reordering implementation system based on shared cache, characterized in that: include: The idle BD management module is used to initialize the idle BD queue and obtain the initialized idle BD; a reordering input control module, configured to receive a Cpld message, extract a Tag field from the Cpld message, and query a queue information RAM using the Tag field as an address; The reorder input control module is further configured to apply for the initialized idle BD, determine the physical address corresponding to the query queue information RAM according to the applied idle BD, and perform physical enqueueing according to the physical address; The BD linked list management module is used to link the idle BDs used for physical enqueuing to the BD linked list to complete the physical enqueuing according to preset conditions; A queue information management module, configured to update the queue information RAM when physical enqueuing is completed; The tag number management module is used to determine whether all the preset Cpld messages corresponding to the preset tag number are returned. If so, it sends a dequeue instruction; a reordering output control module, configured to, upon receiving the dequeue instruction, obtain a plurality of BD pointers according to the updated queue information RAM, and perform physical dequeue along the BD linked list according to the plurality of BD pointers, so as to complete the physical dequeue; The queue information management module is further configured to update the updated queue information RAM when physical dequeueing is completed, to obtain Cpld messages with a sequence, so as to complete the reordering of the Cpld messages.

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