Semiconductor device

Abstract

Disclosed is a semiconductor device including: a lower dielectric layer including a cell array region and a connection region; vertical channel patterns spaced apart from each other in the first direction and the second direction on the cell array region; gate lines spaced apart from each other in a first direction on the cell array region and extending in a second direction, in which at least one of the vertical channel patterns is between the gate lines in the first direction; a capacitor structure on the cell array region, where the capacitor structure is connected to the vertical channel pattern; and a dummy structure on the connection region, in which the dummy structure includes: dummy substrate patterns spaced apart from each other in a first direction and a second direction; and a peripheral dielectric layer between the dummy substrate patterns.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0017523 filed on February 5, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical channel transistor. Background Art

[0004] The reduction of design rules for semiconductor devices has led to the development of manufacturing technology to increase the integration density, operation speed and manufacturing yield of semiconductor devices. Therefore, transistors with vertical channels have been proposed to increase their integration density, resistance, current driving capability, etc. Summary of the Invention

[0005] Some embodiments of the inventive concept may provide a semiconductor device having enhanced reliability and improved electrical characteristics.

[0006] Some embodiments of the inventive concept may provide a semiconductor device and a method of manufacturing the same in which a bare silicon wafer is used to reduce costs.

[0007] The objects of the present inventive concept are not limited to the above, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0008] According to some embodiments of the present invention, a semiconductor device may include: a lower dielectric layer including a cell array region and a connection region adjacent to the cell array region; a plurality of vertical channel patterns spaced apart from each other in a first direction and a second direction on the cell array region of the lower dielectric layer, wherein the first direction and the second direction are parallel to an upper surface of the lower dielectric layer and intersect with each other; a plurality of gate lines spaced apart from each other in the first direction and extending in the second direction on the cell array region of the lower dielectric layer, wherein at least one of the vertical channel patterns is located between the gate lines in the first direction; a capacitor structure located on the cell array region of the lower dielectric layer, wherein the capacitor structure is electrically connected to the vertical channel patterns; and a dummy structure located on the connection region of the lower dielectric layer, wherein the dummy structure includes: a plurality of dummy substrate patterns spaced apart from each other in the first direction and the second direction; and a peripheral dielectric layer between the dummy substrate patterns.

[0009] According to some embodiments conceived in the present invention, a semiconductor device may include: a lower dielectric layer, which includes a cell array region and a connection region adjacent to the cell array region; a plurality of vertical channel patterns, which are spaced apart from each other in a first direction and a second direction on the cell array region of the lower dielectric layer, wherein the first direction and the second direction are parallel to the upper surface of the lower dielectric layer and intersect each other; a plurality of gate lines, which are spaced apart from each other in the first direction and extend in the second direction on the cell array region of the lower dielectric layer, wherein at least one of the vertical channel patterns is located between the gate lines in the first direction; a capacitor structure on the cell array region of the lower dielectric layer, wherein the capacitor structure is electrically connected to the vertical channel pattern; and a dummy structure on the connection region of the lower dielectric layer, wherein the upper surface of each of the vertical channel patterns is coplanar with the upper surface of the dummy structure.

[0010] According to some embodiments of the present invention, a semiconductor device may include: a lower dielectric layer including a cell array region and a connection region extending from the cell array region; a bit line on the cell array region of the lower dielectric layer, wherein the bit line extends in a first direction; a plurality of vertical channel patterns spaced apart from each other in the first direction on the bit line; a plurality of gate lines on the bit line, wherein a gate line among the gate lines is adjacent to a corresponding vertical channel pattern among the vertical channel patterns, the gate lines intersect the bit lines, and extend in a second direction intersecting the first direction; a capacitor structure on the vertical channel pattern, wherein the capacitor structure includes a plurality of lower electrodes spaced apart from each other in the first direction, a dielectric layer on the lower electrodes, and an upper electrode on the dielectric layer and the lower electrodes; and a dummy structure on the connection region of the lower dielectric layer, wherein the dummy structure includes: a plurality of dummy substrate patterns spaced apart from each other in the first direction; and a dummy dielectric pattern between the dummy substrate patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A block diagram showing a semiconductor device according to some embodiments of the inventive concept is shown.

[0012] Figure 2 and Figure 3 Simplified perspective views showing semiconductor devices according to some embodiments of the inventive concept are illustrated.

[0013] Figure 4 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown.

[0014] Figure 5A and Figure 5B Shown along Figure 4 A cross-sectional view taken along line AA' and line BB'.

[0015] Figures 6 to 9 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A and Figure 14A Shown along Figure 4 A cross-sectional view taken along line AA′ shows a method of fabricating a semiconductor device according to some embodiments of the present inventive concept.

[0016] Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B and Figure 14B Shown along Figure 4 A cross-sectional view taken along line BB′ shows a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept.

[0017] Figures 15 to 22 Cross-sectional views showing semiconductor devices according to some embodiments of the inventive concept are illustrated.

[0018] Figure 23 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown.

[0019] Figure 24 Shown along Figure 23 A cross-sectional view taken along line AA'.

[0020] Figures 25 to 35 Shown along Figure 23 A cross-sectional view taken along line AA′ shows a method of fabricating a semiconductor device according to some embodiments of the present inventive concept.

[0021] Figures 36 to 39 Cross-sectional views showing semiconductor devices according to some embodiments of the inventive concept are illustrated.

[0022] Figure 40 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown.

[0023] Figure 41 Shown along Figure 40 A cross-sectional view taken along line AA'.

[0024] Figures 42 to 47 Shown along Figure 40 A cross-sectional view taken along line AA′ shows a method of fabricating a semiconductor device according to some embodiments of the present inventive concept.

[0025] Figures 48 to 51 Cross-sectional views showing semiconductor devices according to some embodiments of the inventive concept are illustrated. DETAILED DESCRIPTION

[0026] Figure 1 A block diagram showing a semiconductor device according to some embodiments is shown.

[0027] Reference Figure 1 , a semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and a control logic 5.

[0028] The memory cell array 1 may include a plurality of memory cells MC arranged in two or three dimensions. Each of the memory cells MC may be connected to a word line WL and a bit line BL that intersect each other (between a word line WL and a bit line BL). It should be understood that when an element or layer is referred to as being "located on another element or layer," "connected to another element or layer," "responsive to another element or layer," or "coupled to another element or layer," the element or layer may be directly located on, connected to, responsive to, or coupled to another element or layer, or one or more intermediate elements or layers may be present. Conversely, when an element is referred to as being "directly located on," "directly connected to," "directly responsive to," or "directly coupled to," no intermediate elements are present. In addition, "electrically connected" conceptually includes both physical connection and physical separation. Here, unless clearly stated otherwise, connection may refer to physical connection and / or electrical connection.

[0029] Each of the memory cells MC may include a selection element TR and a data storage element DS. The selection element TR and the data storage element DS may be (electrically) connected to each other. The selection element TR may be connected to both the word line WL and the bit line BL. For example, the selection element TR may be provided at an intersection between the word line WL and the bit line BL.

[0030] The selection element TR may include a field effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of the transistor serving as the selection element TR may be connected to a word line WL, and the source / drain terminals of the transistor may be connected to a bit line BL and the data storage element DS.

[0031] The row decoder 2 can decode an address input from the outside and select one of the word lines WL of the memory cell array 1. The address decoded in the row decoder 2 can be provided to a row driver (not shown), and in response to the control operation of the control circuit, the row driver can provide a specific voltage to each of the unselected word lines WL and the selected word line WL. As used hereinafter, the terms "external configuration / external configuration", "external device / external device", "external power / external power", "external signal / external signal" or "external" are intended to broadly refer to devices, circuits, blocks, modules, power and / or signals that exist externally (e.g., exist externally in terms of function or in terms of physical boundaries) relative to a given circuit, block, module, system or device.

[0032] In response to an address decoded from the column decoder 4 , the sense amplifier 3 may detect and amplify a voltage difference between a selected bit line BL (of the plurality of bit lines BL) and a reference bit line BL, and may then output the amplified voltage difference.

[0033] The column decoder 4 may provide a data transfer path between the sense amplifier 3 and an external device (eg, a memory controller), and may decode an externally input address and select one of the bit lines BL.

[0034] The control logic 5 may generate control signals for controlling operations for writing data to the memory cell array 1 and / or reading data from the memory cell array 1 .

[0035] Figure 2 and Figure 3 A simplified perspective view showing a semiconductor device according to some embodiments is shown.

[0036] Reference Figure 2 and Figure 3 , the semiconductor device may include a peripheral circuit structure PS and a cell structure CS (stacked) on the peripheral circuit structure PS.

[0037] The peripheral circuit structure PS may include core / peripheral circuits formed on the substrate SUB. The core / peripheral circuits may include reference Figure 1 The row decoder 2 and column decoder 4, sense amplifier 3 and control logic 5 are discussed.

[0038] The cell structure CS may include memory cells having a two-dimensional or three-dimensional arrangement (eg, Figure 1 Memory cell MC) of a memory cell array (eg, Figure 1 Memory cell array 1). As described above, the memory cells (e.g., Figure 1 Each of the memory cells MC) may include a selection element TR and a data storage element DS.

[0039] In some embodiments, a vertical channel transistor (VCT) may be included as a transistor for each memory cell (eg, Figure 1 The vertical channel transistor may include a channel having a longitudinal direction perpendicular to the upper surface (eg, top surface) of the substrate SUB. A capacitor may be used as a memory cell (eg, Figure 1 A data storage element DS of each of the memory cells MC).

[0040] exist Figure 2 In an embodiment, the peripheral circuit structure PS may be disposed on the substrate SUB, and the cell structure CS may be disposed on the peripheral circuit structure PS.

[0041] exist Figure 3 In an embodiment, the peripheral circuit structure PS may be provided on a first substrate SUB1, and the cell structure CS may be provided on a second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 may face each other. For example, the first substrate SUB1, the peripheral circuit structure PS, the cell structure CS, and the second substrate SUB2 may be stacked in sequence (in a direction perpendicular to the upper surface of the first substrate SUB1).

[0042] The peripheral circuit structure PS may be provided with a first metal pad LMP on an upper portion (eg, uppermost portion) thereof. The first metal pad LMP may be electrically connected to the core / peripheral circuit (see FIG. Figure 1 2, 3, 4 and 5).

[0043] The cell structure CS may be provided with a second metal pad UMP on a lower portion (eg, a lowermost portion) thereof. The second metal pad UMP may be electrically connected to the memory cell array (eg, Figure 1 The second metal pad UMP may (directly) contact the first metal pad LMP of the peripheral circuit structure PS and / or be bonded to the first metal pad LMP of the peripheral circuit structure PS.

[0044] Figure 4 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown. Figure 5A and Figure 5B Shown along Figure 4 A cross-sectional view taken along line AA' and line BB'.

[0045] Reference Figure 4 、 Figure 5A and Figure 5B , a cell structure CS may be provided. The cell structure CS may include a lower dielectric layer 400 having a cell array region CAR and a connection region CNR. The lower dielectric layer 400 may extend in a first direction D1 and a second direction D2 oriented from the cell array region CAR toward the connection region CNR. In some embodiments, the cell array region CAR may be adjacent to the connection region CNR. In this description, the first direction D1 and the second direction D2 may be parallel to the upper surface (e.g., top surface) 400a of the lower dielectric layer 400 and intersect each other. The first direction D1 and the second direction D2 may each be referred to as a horizontal direction. The third direction D3 may be perpendicular to the upper surface (e.g., top surface) 400a of the lower dielectric layer 400. The third direction D3 may be referred to as a vertical direction. For example, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0046] When viewed in a plan view, the connection region CNR may extend from the cell array region CAR in a first direction D1 (or a direction opposite to the first direction D1) and a second direction D2 (or a direction opposite to the second direction D2). For example, in a plan view, the connection region CNR may extend around (e.g., surround) the cell array region CAR.

[0047] Unlike shown, the lower dielectric layer 400 may include a plurality of stacked dielectric layers. The lower dielectric layer 400 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric.

[0048] The bit lines BL may be disposed in (on) the cell array region CAR of the lower dielectric layer 400. The bit lines BL may extend along a first direction D1. A plurality of bit lines BL may be provided, and the plurality of bit lines BL may be spaced apart from each other in a second direction D2. The upper surfaces (e.g., top surfaces) of the bit lines BL may be coplanar with the upper surface (e.g., top surface) 400a of the lower dielectric layer 400.

[0049] For example, the bit line BL may include doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, and / or Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, and / or RuTiN), a conductive metal silicide, and / or a conductive metal oxide (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba, Sr)RuO3), CRO (CaRuO3), and / or LSCo), but the inventive concept is not limited thereto. The bit line BL may include one or more layers of one or more of the materials discussed above. In some embodiments, the bit line BL may include a two-dimensional semiconductor material such as graphene, carbon nanotubes, and / or any combination thereof.

[0050] The vertical channel pattern SP may be disposed on the bit line BL in the cell array region CAR of the lower dielectric layer 400. The vertical channel pattern SP may have a lower surface (e.g., a bottom surface) that contacts the upper surface (e.g., a top surface) of the bit line BL. The vertical channel pattern SP may be connected to the bit line BL. A plurality of vertical channel patterns SP may be provided. A plurality of vertical channel patterns SP may be spaced apart from each other in the first direction D1 on one bit line BL. The vertical channel patterns SP may be spaced apart from each other in the first direction D1 and the second direction D2 on the plurality of bit lines BL. Each of the vertical channel patterns SP may have a lower surface (e.g., a bottom surface) that contacts the upper surface (e.g., a top surface) of a corresponding one of the bit lines BL. Each of the vertical channel patterns SP may have a vertical channel structure whose channel length extends along the third direction D3. A lower portion of the vertical channel pattern SP may serve as a first source / drain section (not shown), an upper portion of the vertical channel pattern SP may serve as a second source / drain section (not shown), and a portion of the vertical channel pattern SP between the first and second source / drain sections may serve as a channel section (not shown).

[0051] The vertical channel pattern SP may have a first width W1 in the first direction D1 and a second width W2 in the second direction D2. The vertical channel pattern SP may have a first thickness H1 in the vertical direction D3. In this specification, the term "thickness" may be measured from an upper surface (e.g., top surface) 400a of the lower dielectric layer 400 in the vertical direction D3.

[0052] The gate structure GST may be disposed on the cell array region CAR of the lower dielectric layer 400. A plurality of gate structures GST may be provided. The plurality of gate structures GST may be spaced apart from one another in the first direction D1. The gate structure GST may be disposed adjacent to the vertical channel pattern SP. In some embodiments, the gate structure GST may be located between adjacent vertical channel patterns SP in the first direction D1. Each of the gate structures GST may include a gate line GL, a first buried layer 125, and a second buried layer 130. The gate lines GL may include a first gate line GL1, a second gate line GL2, and a back gate line BGL.

[0053] The vertical channel patterns SP may be respectively arranged between the gate lines GL (in the first direction D1). In some embodiments, at least one of the vertical channel patterns SP may be arranged between the gate lines GL in the first direction D1. For example, the first vertical channel pattern SP1 may be defined as a vertical channel pattern SP arranged adjacent to the first gate line GL1. The second vertical channel pattern SP2 may be defined as a vertical channel pattern SP arranged adjacent to the second gate line GL2. The vertical channel patterns SP may be spaced apart from each other by a first distance A1 in the first direction D1. For example, one of the first vertical channel patterns SP1 may be spaced apart from one of the second vertical channel patterns SP2 by a first distance A1 in the first direction D1. The first vertical channel patterns SP1 may be spaced apart from each other by a second distance A2 in the second direction D2. The second vertical channel patterns SP2 may be spaced apart from each other by a second distance A2 in the second direction D2. For example, the vertical channel patterns SP may be spaced apart from each other by a second distance A2 in the second direction D2.

[0054] The back gate line BGL may be arranged between the first vertical channel pattern SP1 and the second vertical channel pattern SP2. For example, the first vertical channel pattern SP1 may be arranged between the first gate line GL1 and the back gate line BGL. The second vertical channel pattern SP2 may be arranged between the back gate line BGL and the second gate line GL2. The first gate line GL1, the second gate line GL2 and the back gate line BGL may extend in the second direction D2 while extending across (for example, intersecting or overlapping in the third direction D3) the bit line BL. However, the present invention is not limited to this. According to some embodiments, the back gate line BGL may be omitted. Therefore, the semiconductor device may have a single-gate transistor structure. As used herein, "element A overlaps with element B in direction X" (or similar language) means that there is at least one line that extends in direction X and intersects both elements A and B.

[0055] For example, the first gate line GL1, the second gate line GL2, and the back gate line BGL may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, and / or any combination thereof. For example, the gate line GL may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and / or any combination thereof, but the present inventive concept is not limited thereto.

[0056] The first buried layer 125 may be disposed between the upper surface (e.g., top surface) of the bit line BL and the lower surface (e.g., bottom surface) of each of the gate lines GL. The second buried layer 130 may be disposed on the upper surface (e.g., top surface) of each of the gate lines GL. For example, the first buried layer 125 and the second buried layer 130 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric.

[0057] A gate dielectric layer Gox may be interposed between the gate structure GST and the vertical channel pattern SP (in the first direction D1). For example, the gate dielectric layer Gox may be interposed between the vertical channel pattern SP and the gate line GL of the gate structure GST. The gate dielectric layer Gox may extend between the first buried layer 125 and the vertical channel pattern SP (in the first direction D1) and between the second buried layer 130 and the vertical channel pattern SP (in the first direction D1). The gate dielectric layer Gox may be located on the sidewalls of each of the vertical channel patterns SP (e.g., extending around or encircling the sidewalls of each of the vertical channel patterns SP). Unlike shown, in some embodiments, the gate dielectric layer Gox may only contact two of the sidewalls of the vertical channel pattern SP that face the gate line GL. The gate dielectric layer Gox may be omitted from the two sidewalls of the vertical channel pattern SP that do not face the gate line GL. For example, the gate dielectric layer Gox may be disposed on sidewalls of the vertical channel pattern SP opposite (spaced apart) from each other in the first direction D1 and may be omitted on sidewalls of the vertical channel pattern SP opposite (spaced apart) from each other in the second direction D2.

[0058] For example, the gate dielectric layer Gox may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a dielectric constant greater than that of the silicon oxide layer, and / or any combination thereof. For example, the high-k dielectric layer may include a metal oxide and / or a metal oxynitride (e.g., formed of a metal oxide and / or a metal oxynitride). For example, the high-k dielectric layer may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, and / or any combination thereof.

[0059] The dielectric pattern 120 may be disposed between the vertical channel patterns SP spaced apart from each other in the second direction D2 and between the gate structures GST spaced apart from each other in the first direction D1. The dielectric pattern 120 may have a lower surface (e.g., a bottom surface) that contacts the upper surface (e.g., a top surface) 400a of the lower dielectric layer 400. The dummy substrate pattern 101 may be disposed on one side of the first gate line GL1 (with respect to the first direction D1). For example, the dielectric pattern 120 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric.

[0060] The interlayer dielectric layer 200 may be disposed on the gate structure GST on (in) the cell array region CAR of the lower dielectric layer 400. The interlayer dielectric layer 200 may extend onto the dummy substrate pattern 101 disposed on one side of the first gate line GL1 (with respect to the first direction D1).

[0061] The dummy structure DST may be disposed on (in) the connection region CNR of the lower dielectric layer 400. The dummy structure DST may include dummy substrate patterns 101 spaced apart from each other in the first direction D1 and the second direction D2. The dummy structure DST may include a peripheral dielectric layer 112 between the dummy substrate patterns 101.

[0062] Each of the dummy substrate patterns 101 may have a first width X1 in the first direction D1 and a second width X2 in the second direction D2. The first width X1 of the dummy substrate pattern 101 may be similar to the first width W1 of the vertical channel pattern SP in the first direction D1. For example, the first width X1 of the dummy substrate pattern 101 in the first direction D1 may be the same as (or may be equal to) the first width W1 of the vertical channel pattern SP in the first direction D1. The second width X2 of the dummy substrate pattern 101 in the second direction D2 may be similar to the second width W2 of the vertical channel pattern SP in the second direction D2. For example, the second width X2 of the dummy substrate pattern 101 in the second direction D2 may be the same as (or may be equal to) the second width W2 of the vertical channel pattern SP in the second direction D2.

[0063] The peripheral dielectric layer 112 may have a second thickness H2 in the vertical direction D3. Each of the dummy substrate patterns 101 may have a third thickness H3 in the vertical direction D3. The first thickness H1 of the vertical channel pattern SP in the vertical direction D3 may be the same as (or may be equal to) the second thickness H2 of the peripheral dielectric layer 112 and the third thickness H3 of the dummy substrate pattern 101. For example, the upper surface (e.g., top surface) SPa of the vertical channel pattern SP may be coplanar with the upper surface (e.g., top surface) DSTa of the dummy structure DST. The upper surface (e.g., top surface) SPa of the vertical channel pattern SP may be coplanar with the upper surface (e.g., top surface) 112a of the peripheral dielectric layer 112 and the upper surface (e.g., top surface) 101a of the dummy substrate pattern 101.

[0064] The dummy substrate patterns 101 may be spaced apart from each other by a first distance B1 in the first direction D1. The dummy substrate patterns 101 may be spaced apart from each other by a second distance B2 in the second direction D2. The first distance B1 between the dummy substrate patterns 101 in the first direction D1 may be similar to the first distance A1 between the vertical channel patterns SP in the first direction D1. For example, the first distance B1 between the dummy substrate patterns 101 in the first direction D1 may be the same as (or may be equal to) the first distance A1 between the vertical channel patterns SP in the first direction D1. Thus, the first distance B1 between the dummy substrate patterns 101 in the first direction D1 may be the same as (or may be equal to) the first distance A1 between one of the first vertical channel patterns SP1 and one of the second vertical channel patterns SP2 in the first direction D1. The second distance B2 between the dummy substrate patterns 101 in the second direction D2 may be similar to the second distance A2 between the vertical channel patterns SP in the second direction D2. As such, the second distance B2 by which the dummy substrate patterns 101 are spaced apart from each other in the second direction D2 may be the same as (may be equal to) the second distance A2 by which the vertical channel patterns SP are spaced apart from each other in the second direction D2.

[0065] According to the present invention, the vertical channel pattern SP and the dummy substrate pattern 101 may have similar or identical (equal) spacing distances in the horizontal directions D1 and D2. In addition, the vertical channel pattern SP and the dummy substrate pattern 101 may have similar or identical (equal) widths in the horizontal directions D1 and D2. For example, the cell array region CAR and the connection region CNR may have similar (or identical) pattern densities. Therefore, in the method of manufacturing a semiconductor device according to the present invention described later, dishing can be reduced (e.g., prevented) when a planarization process is performed, and the reliability and electrical characteristics of the semiconductor device can be improved.

[0066] The capacitor contact 205 may be correspondingly disposed on the vertical channel pattern SP. The capacitor contact 205 may be disposed in the interlayer dielectric layer 200. The capacitor contact 205 may (directly) contact the upper surface (e.g., top surface) SPa of the corresponding vertical channel pattern SP. When viewed in a plane, the capacitor contact 205 may vertically overlap the corresponding vertical channel pattern SP (may overlap with it in the third direction D3). The upper surface (e.g., top surface) of the capacitor contact 205 may be coplanar with the upper surface (e.g., top surface) of the interlayer dielectric layer 200. For example, the capacitor contact 205 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x、RuO x and / or any combination thereof (eg, formed of them), but the inventive concept is not limited thereto.

[0067] The capacitor structure CAP may be disposed on the interlayer dielectric layer 200. The capacitor structure CAP may include a lower electrode (e.g., bottom electrode) BE spaced apart from each other in the horizontal direction, a dielectric layer 230 located on (e.g., covering) the lower electrode (e.g., bottom electrode) BE, and an upper electrode (e.g., top electrode) TE located on (e.g., covering) the dielectric layer 230 and the lower electrode (e.g., bottom electrode) BE. The dielectric layer 230 may be interposed between the lower electrode (e.g., bottom electrode) BE and the upper electrode (e.g., top electrode) TE.

[0068] The lower electrodes (e.g., bottom electrodes) BE may contact the capacitor contacts 205 and be electrically connected to the capacitor contacts 205. When viewed in a plane, each of the lower electrodes (e.g., bottom electrodes) BE may have a circular, oval, rectangular, square, diamond, hexagonal, or any other suitable shape. For example, the lower electrodes (e.g., bottom electrodes) BE and the upper electrode (e.g., top electrode) TE may include doped polysilicon, a metal nitride such as titanium nitride, and / or a metal such as tungsten, aluminum, and copper.

[0069] The first upper dielectric layer 300 may be disposed on (cover) the capacitor structure CAP and the dummy structure DST on (in) the connection region CNR. An upper surface (e.g., top surface) CSa of the first upper dielectric layer 300 and a lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400 may be opposite to (spaced apart from) each other in the third direction D3.

[0070] Figures 6 to 9 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A and Figure 14A Shown along Figure 4 A cross-sectional view taken along line AA′ shows a method of fabricating a semiconductor device according to some embodiments of the present inventive concept. Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B and Figure 14B Shown along Figure 4 The cross-sectional view taken along line BB' shows a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept. To simplify the description, repeated explanations may be omitted.

[0071] Reference Figure 6A substrate 100 may be provided. The substrate 100 may be a bare silicon wafer. A first sacrificial layer 102 and a second sacrificial layer 104 may be sequentially formed on the substrate 100. For example, the first sacrificial layer 102 may be disposed between the substrate 100 and the second sacrificial layer 104 in the third direction D3. The first sacrificial layer 102 and the second sacrificial layer 104 may be formed using a film formation technique such as physical vapor deposition (PVD) and / or chemical vapor deposition (CVD). For example, the first sacrificial layer 102 and the second sacrificial layer 104 may include a dielectric material.

[0072] Reference Figure 7 , a dummy substrate pattern 101 may be formed on (in) the cell array region CAR and the connection region CNR of the substrate 100. For example, the dummy substrate pattern 101 may be formed in the upper portion of the substrate 100 in the cell array region CAR and the connection region CNR. A first sacrificial pattern 103 and a second sacrificial pattern 105 may be formed on the dummy substrate pattern 101. The pattern structure may include the dummy substrate pattern 101, the first sacrificial pattern 103, and the second sacrificial pattern 105. The pattern structure may be provided in plurality. The plurality of pattern structures may be spaced apart from each other in the horizontal directions D1 and D2. For example, the formation of the dummy substrate pattern 101, the first sacrificial pattern 103, and the second sacrificial pattern 105 may include: forming a mask pattern (not shown) on the second sacrificial layer 104; using the mask pattern as an etching mask to pattern the second sacrificial layer 104, the first sacrificial layer 102, and the upper portion of the substrate 100; and removing the mask pattern. The patterning may be performed by an anisotropic etching process.

[0073] Reference Figure 8 , a third sacrificial layer 106 may be formed on the cell array region CAR of the substrate 100 to fill the space between (each of) the pattern structures (e.g., the dummy substrate pattern 101, the first sacrificial pattern 103, and / or the second sacrificial pattern 105). A separation dielectric layer 110 may be formed on the connection region CNR of the substrate 100 to fill the space between (each of) the pattern structures (e.g., the dummy substrate pattern 101, the first sacrificial pattern 103, and / or the second sacrificial pattern 105). The separation dielectric layer 110 may extend onto the cell array region CAR to be located on an upper surface (e.g., a top surface) of the third sacrificial layer 106 (e.g., covering the third sacrificial layer 106 or overlapping with the third sacrificial layer 106 in the third direction D3).

[0074] The third sacrificial layer 106 may include a carbon-containing material. For example, the third sacrificial layer 106 may include a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL). The separation dielectric layer 110 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material.

[0075] Reference Figure 9, an initial peripheral dielectric layer 111 may be formed on (in) the connection region CNR of the substrate 100. The initial peripheral dielectric layer 111 may be formed between the dummy substrate patterns 101 on (in) the connection region CNR. For example, forming the initial peripheral dielectric layer 111 may include planarizing the separation dielectric layer 110 and the third sacrificial layer 106 until the upper surface (e.g., top surface) of the second sacrificial pattern 105 is exposed. For example, the planarization process may include a chemical mechanical polishing (CMP) process or an etch-back process.

[0076] The third sacrificial layer 106 may be removed on (in) the cell array region CAR of the substrate 100. For example, the third sacrificial layer 106 may be removed through an ashing process and / or a wet etching process.

[0077] Reference Figure 10A and Figure 10B , a first buried layer 125 , a second buried layer 130 , a gate line GL, a gate dielectric layer Gox, a vertical channel pattern SP, a peripheral dielectric layer 112 , and a dielectric pattern 120 may be formed.

[0078] For example, the formation of the vertical channel pattern SP may include: implanting impurities into the dummy substrate pattern 101 on (in) the cell array region CAR; and performing an annealing process. In the case of NMOS, the implantation process may include implanting, for example, one or both of arsenic (As) and phosphorus (P), and in the case of PMOS, the implantation process may include implanting, for example, boron (B).

[0079] The gate dielectric layer Gox may be formed to be located on the sidewall of each of the vertical channel patterns SP (e.g., extending around or encircling the sidewall). For example, in a plan view, the gate dielectric layer Gox may surround each of the vertical channel patterns SP. The gate dielectric layer Gox may be formed by using a film formation technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD), which has excellent step coverage.

[0080] The formation of the first buried layer 125 , the gate line GL, the second buried layer 130 , and the dielectric pattern 120 may include using a film formation technique such as chemical vapor deposition (CVD) and / or physical vapor deposition (PVD).

[0081] The first sacrificial pattern 103 and the second sacrificial pattern 105 may be removed. The removal of the first sacrificial pattern 103 and the second sacrificial pattern 105 may be achieved through a planarization process. In the planarization process, an upper portion of the initial peripheral dielectric layer 111 may be etched to form a peripheral dielectric layer 112.

[0082] Reference Figure 11A and Figure 11BAn interlayer dielectric layer 200 may be formed on (in) the cell array region CAR, covering the dielectric pattern 120 and the second buried layer 130 (e.g., overlapping the dielectric pattern 120 and the second buried layer 130 in the third direction D3). A capacitor contact 205 may be formed in the interlayer dielectric layer 200. A lower electrode (e.g., a bottom electrode) BE may be formed on the capacitor contact 205. Forming the lower electrode (e.g., a bottom electrode) BE may include: forming a lower electrode layer (e.g., a bottom electrode layer) (not shown); and subsequently patterning the lower electrode layer (e.g., a bottom electrode layer). A plurality of lower electrodes (e.g., a bottom electrode) BE may be formed. A dielectric layer 230 may be formed on the lower electrode (e.g., a bottom electrode) BE (e.g., to cover or overlap the lower electrode BE). The dielectric layer 230 may conformally cover the lower electrode (e.g., a bottom electrode) BE.

[0083] Reference Figure 12A and Figure 12B , a capacitor structure CAP may be formed. Forming the capacitor structure CAP may include forming an upper electrode (e.g., a top electrode) TE located on the dielectric layer 230 (e.g., covering the dielectric layer 230). A first upper dielectric layer 300 may be formed on the capacitor structure CAP and the dummy structure DST on (in) the connection region CNR (e.g., to cover the capacitor structure CAP and the dummy structure DST).

[0084] Reference Figure 13A and Figure 13B , refer to Figure 12A and Figure 12B The resulting structure discussed above can be flipped upside down. For example, the resulting structure can be flipped so that the first upper dielectric layer 300 faces downward and the substrate 100 faces upward. After flipping the resulting structure, the substrate 100 can be removed. For example, removing the substrate 100 can include performing a planarization process until the peripheral dielectric layer 112 is exposed. For example, the planarization process can include a chemical mechanical polishing (CMP) process or an etch-back process.

[0085] According to the present invention, as shown in FIG. Figure 4 、 Figure 5A and Figure 5B As discussed, the pattern densities of the cell array region CAR and the connection region CNR may be similar (or identical) to each other. Therefore, dishing may be reduced (eg, prevented) during a planarization process, and reliability and electrical characteristics of the semiconductor device may be improved.

[0086] Reference Figure 14A and Figure 14BA bit line BL may be formed on (in) the cell array region CAR. For example, forming the bit line BL may include: forming a bit line layer (not shown); forming a mask pattern (not shown) on the bit line layer; patterning the bit line layer using the mask pattern as an etching mask; and removing the mask pattern. A plurality of bit lines BL may be formed. The plurality of bit lines BL may be formed so as to contact corresponding vertical channel patterns SP.

[0087] Return to reference Figure 5A and Figure 5B , a lower dielectric layer 400 may be formed to be located on (eg, completely cover) (all elements therein) the cell array region CAR and the connection region CNR.

[0088] Figures 15 to 22 1 and 2. A cross-sectional view showing a semiconductor device according to some embodiments of the present inventive concept is shown. To simplify the description, repeated explanation may be omitted.

[0089] Reference Figure 15 According to some embodiments, a bit line contact plug BLCP may be disposed in the lower dielectric layer 400. The bit line contact plug BLCP may be connected to the bit line BL. The bit line contact plug BLCP may be electrically connected to the first bonding pad 450 through a connection circuit line 430 and a connection contact plug 410. The connection circuit line 430 and the connection contact plug 410 may include a conductive material such as a metal.

[0090] The capacitor contact plug CCP may be provided to extend through (e.g., through) the dummy structure DST, (a portion of) the lower dielectric layer 400, and (a portion of) the first upper dielectric layer 300. The capacitor contact plug CCP may be connected to the capacitor structure CAP. The capacitor contact plug CCP may be electrically connected to the first bonding pad 450 via the connection circuit line 430 and the connection contact plug 410.

[0091] The connection pad CPD may be provided on the first upper dielectric layer 300. A through contact plug TCP may be provided to extend in (a portion of) the first upper dielectric layer 300, the dummy structure DST, and the lower dielectric layer 400 (e.g., through the first upper dielectric layer 300, the dummy structure DST, and the lower dielectric layer 400). The through contact plug TCP may be connected to the connection pad CPD. The through contact plug TCP may be electrically connected to the first bonding pad 450 via the connection circuit line 430 and the connection contact plug 410.

[0092] The first bonding pad 450 may be provided in a plurality. The plurality of first bonding pads 450 may be provided adjacent to the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400. The lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400 may not cover the lower surface (e.g., bottom surface) of the first bonding pad 450. For example, the lower surface of the first bonding pad 450 may be exposed from the lower dielectric layer 400. The lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400 may be coplanar with the lower surface (e.g., bottom surface) of the first bonding pad 450.

[0093] The peripheral circuit structure PS may be disposed on a lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400. The peripheral circuit structure PS may include: a peripheral circuit transistor PTR on (in) the peripheral substrate 10; a peripheral contact plug 31; a peripheral circuit line 33 electrically connected to the peripheral circuit transistor PTR through the peripheral contact plug 31; and a first dielectric layer 30 extending around (e.g., surrounding) the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33. For example, at least a portion of the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33 may be located in the first dielectric layer 30.

[0094] In some embodiments, the peripheral circuit may include (e.g., may be composed of) a peripheral circuit transistor PTR, a peripheral contact plug 31, and a peripheral circuit line 33. In some embodiments, each of the peripheral circuit transistors PTR may include a peripheral gate dielectric layer 21, a peripheral gate electrode 23, a peripheral capping pattern 25, a peripheral gate spacer 27, and a peripheral source / drain section 29.

[0095] The peripheral gate dielectric layer 21 may be disposed (in the third direction D3) between the peripheral gate electrode 23 and the peripheral substrate 10. The peripheral capping pattern 25 may be disposed on the peripheral gate electrode 23. The peripheral gate spacers 27 may be located on the sidewalls of the peripheral gate dielectric layer 21, the sidewalls of the peripheral gate electrode 23, and / or the sidewalls of the peripheral capping pattern 25 (e.g., may cover the sidewalls of the peripheral gate dielectric layer 21, the sidewalls of the peripheral gate electrode 23, and / or the sidewalls of the peripheral capping pattern 25). The peripheral source / drain regions 29 may be disposed in the peripheral substrate 10 adjacent to opposite sides of the peripheral gate electrode 23 (in the first direction D1).

[0096] The peripheral circuit line 33 may be electrically connected to the peripheral circuit transistors PTR through the peripheral contact plugs 31. For example, each of the peripheral circuit transistors PTR may be an NMOS transistor, a PMOS transistor, or a gate-around transistor. The peripheral contact plugs 31 and the peripheral circuit line 33 may include conductive materials such as metal.

[0097] The first dielectric layer 30 may be disposed on an upper surface (e.g., top surface) of the peripheral substrate 10. On the peripheral substrate 10, the first dielectric layer 30 may be disposed on (e.g., covering, extending around, or surrounding) the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33. The first dielectric layer 30 may include a plurality of dielectric layers forming a multilayer structure. For example, the first dielectric layer 30 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric.

[0098] The second bonding pad 35 may be provided to be electrically connected to the peripheral circuit transistor PTR through the peripheral contact plug 31 and the peripheral circuit line 33. The first dielectric layer 30 may not cover the upper surface (e.g., top surface) of the second bonding pad 35. The upper surface (e.g., top surface) of the first dielectric layer 30 may be coplanar with the upper surface (e.g., top surface) of the second bonding pad 35. For example, the upper surface of the second bonding pad 35 may be exposed from the first dielectric layer 30.

[0099] The lower surface (e.g., bottom surface) of the first bonding pad 450 may correspondingly (directly) contact the upper surface (e.g., top surface) of the second bonding pad 35. For example, the first bonding pad 450 and the second bonding pad 35 may include a metal such as copper (Cu), tungsten (W), aluminum (Al), nickel (Ni) and / or tin (Sn). For example, the first bonding pad 450 and the second bonding pad 35 may include copper (Cu). The first bonding pad 450 and the second bonding pad 35 may constitute a single integral shape without any interface between them. Although the first bonding pad 450 and the second bonding pad 35 are shown as having their sidewalls (in the third direction D3) aligned with each other in a straight line, the inventive concept is not limited thereto, and when viewed in a plane, the sidewalls of the first bonding pad 450 and the second bonding pad 35 may be spaced apart from each other.

[0100] Reference Figure 16 , according to some embodiments, Figure 15 The semiconductor device may further include a through-plug liner layer TCPL (conformally) extending around (e.g., surrounding) a lateral side surface (side surface) of the through-contact plug TCP. The through-plug liner layer TCPL may be interposed between the lateral side surface of the through-contact plug TCP and each of the first upper dielectric layer 300, the dummy structure DST, and the lower dielectric layer 400.

[0101] Figure 15The semiconductor device may further include a capacitor plug liner layer CCPL that conformally covers (extends around or encloses) the lateral side surface (side surface) of the capacitor contact plug CCP. The capacitor plug liner layer CCPL may be interposed between the lateral side surface of the capacitor contact plug CCP and each of the first upper dielectric layer 300, the dummy structure DST, and the lower dielectric layer 400.

[0102] For example, the through-plug liner layer TCPL and the capacitor plug liner layer CCPL may include a dielectric material. In some embodiments, unlike the illustration, the through-contact plug TCP and the capacitor contact plug CCP may extend into (e.g., pass through) the dummy substrate pattern 101. In this case, the through-plug liner layer TCPL and the capacitor plug liner layer CCPL may be included to insulate the through-contact plug TCP and the capacitor contact plug CCP from the dummy substrate pattern 101, respectively.

[0103] Reference Figure 17 According to some embodiments, the interface layer AL may be disposed on the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400. The peripheral circuit structure PS may be disposed on the lower surface (e.g., bottom surface) of the interface layer AL. The peripheral circuit structure PS may include a peripheral through-contact 37 electrically connected to the peripheral circuit transistor PTR through the peripheral contact plug 31 and the peripheral circuit line 33. The peripheral through-contact 37 may extend in the peripheral circuit structure PS and the interface layer AL (e.g., pass through the peripheral circuit structure PS and the interface layer AL) to electrically connect to the connection circuit line 430.

[0104] The interface layer AL may have a single layer or multilayer structure of, for example, silicon carbonitride (SiCN) and / or silicon oxide. For example, the formation of the interface layer AL may include: forming a first interface layer (not shown) on the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400; and forming a second interface layer (not shown) on the upper surface (e.g., top surface) of the peripheral substrate 10. Plasma treatment may be performed on the surfaces of the first interface layer and the second interface layer to remove the -CN groups at the distal ends of the SiCN layer and form dangling bonds. Deionized water treatment may be performed on the surfaces of the first interface layer and the second interface layer to form -OH groups on the dangling bonds. The first interface layer and the second interface layer may contact each other, and a hot pressing process may be performed. During the hot pressing process, the -OH groups may be bonded to each other in the shape of H2O at the interface between the first interface layer and the second interface layer, while the remaining -O- groups and the Si surrounding them may be bonded to each other to form a SiO2 layer between the first interface layer and the second interface layer. Therefore, the peripheral circuit structure PS may be bonded to the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400, and an interface layer AL may be formed between the peripheral circuit structure PS and the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400. The interface layer AL may include a three-layer structure in which a SiCN layer, a SiO2 layer, and a SiCN layer are stacked in this order.

[0105] Although not shown, a dielectric layer (not shown) may be interposed between the peripheral substrate 10 and the sidewalls of the peripheral through-contact 37. This configuration can insulate the peripheral through-contact 37 from the peripheral substrate 10. For example, when a dielectric layer (not shown) through which the peripheral through-contact 37 passes is pre-formed on the peripheral substrate 10, process failures and process burdens can be reduced, compared to a case where the dielectric layer is formed to cover the entire sidewalls of the peripheral through-contact 37.

[0106] Reference Figure 18 , according to some embodiments, Figure 17 The semiconductor device may further include: a through plug liner layer TCPL that extends around (e.g., surrounds) a lateral side surface (side surface) of the through contact plug TCP (conformally); and a capacitor plug liner layer CCPL that extends around (e.g., surrounds) a lateral side surface (side surface) of the capacitor contact plug CCP (conformally). In this case, as described with reference to Figure 16 The discussion may include a through plug liner layer TCPL and a capacitor plug liner layer CCPL to insulate the through contact plug TCP and the capacitor contact plug CCP from the dummy substrate pattern 101, respectively.

[0107] Reference Figure 19According to some embodiments, a capacitor contact plug CCP may be disposed in the first upper dielectric layer 300 . The capacitor contact plug CCP may be connected to the capacitor structure CAP. The capacitor contact plug CCP may be connected to the upper circuit line 330 .

[0108] The bit line contact plug BLCP may be provided to extend in a portion of the first upper dielectric layer 300 and the dummy structure DST (e.g., pass through a portion of the first upper dielectric layer 300 and the dummy structure DST). The bit line contact plug BLCP may be connected to the bit line BL. The bit line contact plug BLCP may be connected to the upper circuit line 330.

[0109] The connection pad CPD may be provided on the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400. The through contact plug TCP may be provided to extend through (e.g., pass through) a portion of the first upper dielectric layer 300, the lower dielectric layer 400, and the dummy structure DST to connect to the connection pad CPD. The through contact plug TCP may be connected to the upper circuit line 330.

[0110] The second upper dielectric layer 500 may be disposed on the first upper dielectric layer 300. Upper contact plugs 510 and upper bonding pads 550 may be disposed in the second upper dielectric layer 500. The upper surface (e.g., top surface) of the second upper dielectric layer 500 may not be located on (or may not cover) the upper surface (e.g., top surface) of the upper bonding pads 550. The upper surface (e.g., top surface) of the second upper dielectric layer 500 may be coplanar with the upper surface (e.g., top surface) of the upper bonding pads 550. The capacitor contact plugs CCP, the bit line contact plugs BLCP, and the through contact plugs TCP may be electrically connected to the upper bonding pads 550 through the upper contact plugs 510.

[0111] The peripheral circuit structure PS may be disposed on an upper surface (eg, top surface) of the second upper dielectric layer 500. The peripheral circuit structure PS may include a peripheral through-contact 37 electrically connected to the peripheral circuit transistor PTR through a peripheral contact plug 31 and a peripheral circuit line 33.

[0112] The second dielectric layer 50 may be disposed on the lower surface (e.g., bottom surface) 10b of the peripheral substrate 10. The second dielectric layer 50 may include a lower contact plug 51, a lower circuit line 53, and a lower bonding pad 55. The lower surface (e.g., bottom surface) of the second dielectric layer 50 may not be located on the lower surface (e.g., bottom surface) of the lower bonding pad 55 (may not cover the lower surface of the lower bonding pad 55). The lower surface (e.g., bottom surface) of the second dielectric layer 50 may be coplanar with the lower surface (e.g., bottom surface) of the lower bonding pad 55. The peripheral through-contact 37 may extend in the peripheral substrate 10 (e.g., pass through the peripheral substrate 10) to be electrically connected to the lower bonding pad 55 through the lower contact plug 51 and the lower circuit line 53.

[0113] The lower surface (e.g., bottom surface) of the lower bonding pad 55 may correspondingly (directly) contact the upper surface (e.g., top surface) of the upper bonding pad 550. For example, the lower bonding pad 55 and the upper bonding pad 550 may include a metal such as copper (Cu), tungsten (W), aluminum (Al), nickel (Ni) and / or tin (Sn). For example, the lower bonding pad 55 and the upper bonding pad 550 may include copper (Cu). The lower bonding pad 55 and the upper bonding pad 550 may constitute a single integral shape without any interface between them. Although the lower bonding pad 55 and the upper bonding pad 550 are shown as having their side walls (in the third direction D3) aligned with each other in a straight line, the inventive concept is not limited thereto, and when viewed in a plane, the side walls of the lower bonding pad 55 and the upper bonding pad 550 may be spaced apart from each other.

[0114] Reference Figure 20 , Figure 19 The semiconductor device may further include a through-plug liner layer TCPL (conformally) extending around (eg, surrounding) a lateral side surface (side surface) of the through-contact plug TCP. Figure 16 As discussed, the through-plug liner layer TCPL may serve to insulate between the dummy substrate pattern 101 and the through-contact plug TCP.

[0115] Reference Figure 21 According to some embodiments, the interface layer AL may be disposed on the first upper dielectric layer 300. The peripheral circuit structure PS may be disposed on the interface layer AL. Figure 17 As discussed, this may reduce process failures and process burdens compared to a case where the dielectric layer is formed to extend around (eg, cover) the (entire) sidewall of the peripheral through-contact 37 .

[0116] Reference Figure 22 , according to some embodiments, Figure 21The semiconductor device may further include a through-plug liner layer TCPL (conformally) extending around (eg, surrounding) a lateral side surface (side surface) of the through-contact plug TCP. Figure 16 As discussed, the through-plug liner layer TCPL may serve to insulate between the dummy substrate pattern 101 and the through-contact plug TCP.

[0117] Figure 23 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown. Figure 24 Shown along Figure 23 For simplicity of description, repeated explanation may be omitted.

[0118] Reference Figure 23 and Figure 24 , a cell structure CS may be provided. The cell structure CS may include a lower dielectric layer 400. The dummy structure DST may be disposed on (in) the connection region CNR of the lower dielectric layer 400. An upper surface (e.g., top surface) DSTa of the dummy structure DST may be coplanar with an upper surface (e.g., top surface) SPa of the vertical channel pattern SP.

[0119] The dummy structure DST may include a peripheral dielectric layer 112 and a stop pattern 115 interposed between the peripheral dielectric layer 112 and the gate structure GST. For example, the stop pattern 115 may be interposed between the peripheral dielectric layer 112 and the dummy substrate pattern 101 disposed on one side of the first gate line GL1 (in the first direction D1). The stop pattern 115 may have a fourth thickness H4 in the vertical direction D3. The fourth thickness H4 of the stop pattern 115 may be the same as the first thickness H1 of the vertical channel pattern SP and the second thickness H2 of the peripheral dielectric layer 112. For example, the upper surface (e.g., top surface) SPa of the vertical channel pattern SP may be coplanar with the upper surface (e.g., top surface) 112a of the peripheral dielectric layer 112 and the upper surface (e.g., top surface) 115a of the stop pattern 115.

[0120] Peripheral dielectric layer 112 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric. Stop pattern 115 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric. In some embodiments, stop pattern 115 and peripheral dielectric layer 112 include different materials. For example, stop pattern 115 may not include the same material as peripheral dielectric layer 112.

[0121] Figures 25 to 35 Shown along Figure 23 The cross-sectional view taken along line AA' shows a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept. To simplify the description, repeated explanations may be omitted.

[0122] Reference Figure 25 and Figure 26 A substrate 100 may be provided. The substrate 100 may be a bare silicon wafer. A first sacrificial layer 102 and a second sacrificial layer 104 may be sequentially formed on the substrate 100. For example, the first sacrificial layer 102 may be disposed between the substrate 100 and the second sacrificial layer 104 in the third direction D3.

[0123] An initial first sacrificial pattern p103 and an initial second sacrificial pattern p105 may be formed on (in) the cell array region CAR of the substrate 100. For example, the formation of the initial first sacrificial pattern p103 and the initial second sacrificial pattern p105 may include: forming a mask pattern (not shown) on the second sacrificial layer 104; using the mask pattern as an etching mask to etch the second sacrificial layer 104, the first sacrificial layer 102, and the upper portion of the substrate 100 on (in) the connection region CNR; and removing the mask pattern.

[0124] Reference Figure 27 , an initial stop layer p107 may be formed. The initial stop layer p107 may be located on the upper surface (e.g., top surface) of the initial second sacrificial pattern p105 (e.g., covering the upper surface of the second sacrificial pattern p105), and may extend along the initial second sacrificial pattern p105, the initial first sacrificial pattern p103, and the lateral side surfaces (e.g., side surfaces) of the substrate 100, thereby extending to the upper surface (e.g., top surface) of the substrate 100 (e.g., the remaining portion of the substrate 100 in the connection region CNR after etching the upper portion of the substrate 100 in the connection region CNR). The initial stop layer p107 may be formed by utilizing a film formation technique (which has excellent step coverage) such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD).

[0125] A semiconductor layer 108 may be formed on the initial stop layer p107. The semiconductor layer 108 may (completely) cover the cell array region CAR and the connection region CNR (of the substrate 100) (overlapping the cell array region CAR and the connection region CNR in the third direction D3). For example, the semiconductor layer 108 may include polycrystalline silicon. The semiconductor layer 108 may be formed using a film formation technique such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0126] Reference Figure 28 , a stop layer 107 may be formed. For example, forming the stop layer 107 may include planarizing the semiconductor layer 108 and the initial stop layer p107 (e.g., removing or etching back the semiconductor layer 108 and the initial stop layer p107) until an upper surface (e.g., a top surface) of the initial second sacrificial pattern p105 is exposed.

[0127] A semiconductor layer p109 may be formed on (in) the connection region CNR of the substrate 100 and on the stop layer 107. After forming the stop layer 107, the formation of the semiconductor layer p109 may include, for example, etching an upper portion of the semiconductor layer 108 on (in) the connection region CNR.

[0128] A separation dielectric layer 110 may be formed on (in) the connection region CNR of the substrate 100 and on the stop layer 107 and the semiconductor layer p109. An upper surface (eg, top surface) of the separation dielectric layer 110 may be coplanar with an upper surface (eg, top surface) of the initial second sacrificial pattern p105.

[0129] Reference Figure 29 , a dummy substrate pattern 101 may be formed on (in) the cell array region CAR of the substrate 100. A first sacrificial pattern 103 and a second sacrificial pattern 105 may be formed on the dummy substrate pattern 101. The formation of the dummy substrate pattern 101, the first sacrificial pattern 103 and the second sacrificial pattern 105 may be similar to the reference Figure 7 The discussion is (essentially) the same.

[0130] A semiconductor pattern 109 and an initial peripheral dielectric layer 111 may be formed on (in) the connection region CNR of the substrate 100. For example, the formation of the semiconductor pattern 109 and the initial peripheral dielectric layer 111 may include forming a mask pattern (not shown) on the separation dielectric layer 110, patterning the separation dielectric layer 110 and the semiconductor layer p109 using the mask pattern as an etching mask, and removing the mask pattern. The patterning may be performed by an anisotropic etching process.

[0131] Reference Figure 30 , a peripheral dielectric layer 112 may be formed on (in) the connection region CNR of the substrate 100. The formation of the peripheral dielectric layer 112 may include depositing an additional dielectric layer to fill the space between the semiconductor pattern 109 and the initial peripheral dielectric layer 111. In some embodiments, the additional dielectric layer may be disposed between the semiconductor patterns 109 (may fill the space between the semiconductor patterns 109). In some embodiments, the additional dielectric layer may be disposed between the initial peripheral dielectric layers 111 (may fill the space between the initial peripheral dielectric layers 111). The additional dielectric layer and the initial peripheral dielectric layer 111 may be collectively referred to as the peripheral dielectric layer 112. In some embodiments, the additional dielectric layer and the initial peripheral dielectric layer 111 may include (e.g., may be) the same material.

[0132] Reference Figure 31 , a first buried layer 125, a second buried layer 130, a gate line GL, a gate dielectric layer Gox, a vertical channel pattern SP and a dielectric pattern 120 may be formed. This step may be performed by referring to Figure 10A and Figure 10B The methods discussed are implemented in (essentially) the same way.

[0133] Reference Figure 32 , an interlayer dielectric layer 200, a capacitor contact 205, a capacitor structure CAP and a first upper dielectric layer 300 can be formed. This step can be performed by referring to Figures 11A to 12B The methods discussed are implemented in (essentially) the same way.

[0134] Reference Figure 33 , you can Figure 32 The resulting structure is flipped upside down. For example, the resulting structure can be flipped so that the first upper dielectric layer 300 faces downward and the substrate 100 faces upward. After flipping the resulting structure, a portion of the substrate 100 can be removed. For example, the partial removal of the substrate 100 can include performing a planarization process until the upper surface (e.g., top surface) of the stop layer 107 on (in) the connection region CNR is exposed. For example, the planarization process can include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0135] Reference Figure 34 , a stop pattern 115 may be formed. The formation of the stop pattern 115 may be achieved by a patterning process. For example, a planarization process may be performed until the semiconductor pattern 109 is completely removed on (in) the connection region CNR.

[0136] According to the present inventive concept, the pattern density of the vertical channel patterns SP on (in) the cell array region CAR can be similar to (or the same as) the pattern density of the semiconductor patterns 109 on (in) the connection region CNR. Therefore, the dishing phenomenon can be prevented during the planarization process, and the reliability and electrical characteristics of the semiconductor device can be improved.

[0137] Reference Figure 35 , a bit line BL can be formed. The bit line BL can be connected to the reference Figure 14A and Figure 14B The method discussed is (essentially) the same method as the one used to form it.

[0138] Return to reference Figure 24 , the lower dielectric layer 400 may be formed to (completely) cover the cell array region CAR and the connection region CNR (eg, overlap the cell array region CAR and the connection region CNR in the third direction D3 ).

[0139] Figures 36 to 39 1 and 2. A cross-sectional view showing a semiconductor device according to some embodiments of the present inventive concept is shown. To simplify the description, repeated explanation may be omitted.

[0140] Reference Figure 36According to some embodiments, a peripheral dielectric layer 112 may be disposed on the lower dielectric layer 400, and a stop pattern 115 may be interposed between the peripheral dielectric layer 112 and the gate structure GST (in the first direction D1). For example, the stop pattern 115 may be interposed between the peripheral dielectric layer 112 and the dummy substrate pattern 101 disposed on one side of the first gate line GL1 (in the first direction D1).

[0141] A bit line contact plug BLCP, a connection circuit line 430, and a connection contact plug 410 may be provided in the lower dielectric layer 400. The bit line contact plug BLCP, the connection circuit line 430, and the connection contact plug 410 may be provided with reference to FIG. Figure 15 The ones discussed are (essentially) the same.

[0142] The capacitor contact plug CCP may be provided to extend in (e.g., pass through) the dummy structure DST, (a portion of) the lower dielectric layer 400, and a portion of the first upper dielectric layer 300. The capacitor contact plug CCP may be provided with reference to Figure 15 The discussion is (essentially) the same.

[0143] The connection pad CPD may be provided on the first upper dielectric layer 300. The through contact plug TCP may be provided to extend in (e.g., pass through) the first upper dielectric layer 300, the dummy structure DST, and a portion of the lower dielectric layer 400. The through contact plug TCP may be provided with reference to Figure 15 The discussion is (essentially) the same.

[0144] The first bonding pad 450 may be provided to be electrically connected to the bit line contact plug BLCP, the capacitor contact plug CCP, and the through contact plug TCP. Figure 15 The discussion is (essentially) the same.

[0145] The peripheral circuit structure PS may be disposed on a lower surface (eg, bottom surface) CSb of the lower dielectric layer 400. The peripheral circuit structure PS may be disposed on a lower surface (eg, bottom surface) CSb of the lower dielectric layer 400. Figure 15 The discussion is (essentially) the same.

[0146] The lower surface (eg, bottom surface) of the first bonding pad 450 may correspondingly (directly) contact the upper surface (eg, top surface) of the second bonding pad 35. The first bonding pad 450 and the second bonding pad 35 may constitute a single integral shape without any interface therebetween.

[0147] Reference Figure 37According to some embodiments, the peripheral dielectric layer 112 may be disposed on (the upper surface 400a of) the lower dielectric layer 400, and the stop pattern 115 may be interposed (in the first direction D1) between the peripheral dielectric layer 112 and the gate structure GST. The interface layer AL may be disposed on the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400. The peripheral circuit structure PS may be disposed on the lower surface (e.g., bottom surface) of the interface layer AL. The interface layer AL may be disposed on the reference Figure 17 The discussion is (essentially) the same. Figure 17 As discussed, this case can reduce process failures and process burdens compared to the case where the dielectric layer is formed to cover the entire sidewall of the peripheral through-contact 37 .

[0148] Reference Figure 38 According to some embodiments, the peripheral dielectric layer 112 may be disposed on (the upper surface 400a of) the lower dielectric layer 400, and the stop pattern 115 may be interposed (in the first direction D1) between the peripheral dielectric layer 112 and the gate structure GST. The second upper dielectric layer 500 may be disposed on (the upper surface of) the first upper dielectric layer 300. The peripheral circuit structure PS may be disposed on the top surface (upper surface) CSa of the second upper dielectric layer 500. The components included in the first upper dielectric layer 300, the second upper dielectric layer 500, and the peripheral circuit structure PS may be the same as those in reference 1. Figure 19 The ones discussed are (essentially) the same.

[0149] The lower surface (eg, bottom surface) of the lower bonding pad 55 may correspondingly (directly) contact the upper surface (eg, top surface) of the upper bonding pad 550. The lower bonding pad 55 and the upper bonding pad 550 may constitute a single integral shape without any interface therebetween.

[0150] Reference Figure 39 According to some embodiments, the peripheral dielectric layer 112 may be disposed on (the upper surface 400a of) the lower dielectric layer 400, and the stop pattern 115 may be interposed (in the first direction D1) between the peripheral dielectric layer 112 and the gate structure GST. The interface layer AL may be disposed on (the upper surface CSa of) the first upper dielectric layer 300. The peripheral circuit structure PS may be disposed on (the upper surface of) the interface layer AL. The interface layer AL may be disposed on (the upper surface of) the reference Figure 17 The discussion is (basically) the same. Figure 17 As discussed above, this case can reduce process failures and process burdens compared to the case where the dielectric layer is formed to cover the entire sidewall of the peripheral through-contact 37.

[0151] Figure 40 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown. Figure 41 Shown along Figure 40For simplicity of description, repeated explanation may be omitted.

[0152] Reference Figure 40 and Figure 41 , a cell structure CS may be provided. The cell structure CS may include a lower dielectric layer 400. The dummy structure DST may be disposed on (in) the connection region CNR of the lower dielectric layer 400. An upper surface (e.g., top surface) DSTa of the dummy structure DST may be coplanar with an upper surface (e.g., top surface) SPa of the vertical channel pattern SP.

[0153] The dummy structure DST may include a peripheral dielectric layer 112 and a stop pattern 115 interposed between the peripheral dielectric layer 112 and the gate structure GST (in the first direction D1). For example, the stop pattern 115 may be interposed between the peripheral dielectric layer 112 and the dummy substrate pattern 101 disposed on one side of the first gate line GL1 (in the first direction D1). The stop pattern 115 may have a fourth thickness H4 in the vertical direction D3.

[0154] The dummy structure DST may further include a vertical portion 109V of the semiconductor pattern (109), the vertical portion 109V of the semiconductor pattern (109) being interposed between the stop pattern 115 and the peripheral dielectric layer 112. The vertical portion 109V of the semiconductor pattern (109) may have a fifth thickness H5 in the vertical direction D3. The fifth thickness H5 of the semiconductor pattern may be equal to the first thickness H1 of the vertical channel pattern SP, the second thickness H2 of the peripheral dielectric layer 112, and the fourth thickness H4 of the stop pattern 115. For example, an upper surface (e.g., top surface) SPa of the vertical channel pattern SP may be coplanar with an upper surface (e.g., top surface) 112a of the peripheral dielectric layer 112, an upper surface (e.g., top surface) 115a of the stop pattern 115, and an upper surface (e.g., top surface) 109Va of the vertical portion 109V of the semiconductor pattern (109).

[0155] For example, the vertical portion 109V of the semiconductor pattern (109) may include polysilicon.

[0156] Figures 42 to 47 Shown along Figure 40 The cross-sectional view taken along line AA' shows a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept. To simplify the description, repeated explanations may be omitted.

[0157] Reference Figure 42 , a substrate 100 may be provided. The substrate 100 may be a bare silicon wafer.

[0158] An initial first sacrificial pattern p103 and an initial second sacrificial pattern p105 may be formed on (in) the cell array region CAR of the substrate 100. The initial first sacrificial pattern p103 may be disposed between the initial second sacrificial pattern p105 and the substrate 100 in the third direction D3. Figure 25 and Figure 26 The initial first sacrificial pattern p103 and the initial second sacrificial pattern p105 are formed by (substantially) the same method as discussed above.

[0159] An initial stop layer p107 may be formed. The initial stop layer p107 may be located on an upper surface (e.g., top surface) of the initial second sacrificial pattern p105 (e.g., covering the upper surface of the initial second sacrificial pattern p105), and may extend along the initial second sacrificial pattern p105, the initial first sacrificial pattern p103, and side surfaces (e.g., lateral side surfaces) of the substrate 100, thereby extending onto the upper surface (e.g., top surface) of the substrate 100.

[0160] A semiconductor layer 108 may be formed on the initial stop layer p107. The semiconductor layer 108 may conformally cover the upper surface (e.g., top surface) and side surfaces (e.g., lateral side surfaces) of the initial stop layer p107. The semiconductor layer 108 may be formed using a film formation technique (which has excellent step coverage) such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD). For example, the semiconductor layer 108 may include polycrystalline silicon.

[0161] Reference Figure 43 , a stop layer 107 and a semiconductor layer p109 may be formed. For example, forming the stop layer 107 and the semiconductor layer p109 may include planarizing a portion of the semiconductor layer 108 and a portion of the initial stop layer p107 until an upper surface (eg, a top surface) of the initial second sacrificial pattern p105 is exposed.

[0162] A separation dielectric layer 110 may be formed on (in) the connection region CNR of the substrate 100 and on the semiconductor layer p109. An upper surface (eg, top surface) of the separation dielectric layer 110 may be coplanar with an upper surface (eg, top surface) of the preliminary second sacrificial pattern p105.

[0163] Reference Figure 44 , a dummy substrate pattern 101 may be formed on (in) the cell array region CAR of the substrate 100. A first sacrificial pattern 103 and a second sacrificial pattern 105 may be formed on the dummy substrate pattern 101. The formation of the dummy substrate pattern 101, the first sacrificial pattern 103 and the second sacrificial pattern 105 may be similar to the reference Figure 7 The discussion is (essentially) the same.

[0164] A semiconductor pattern 109 and an initial peripheral dielectric layer 111 may be formed on (in) the connection region CNR of the substrate 100. Figure 29 The semiconductor pattern 109 and the initial peripheral dielectric layer 111 are formed in (substantially) the same manner as discussed above.

[0165] The semiconductor pattern 109 may include a horizontal portion 109H and a vertical portion 109V. The horizontal portion 109H of the semiconductor pattern 109 may be a portion in contact with the upper surface (e.g., top surface) of the stop layer 107. The vertical portion 109V of the semiconductor pattern 109 may have a shape extending in the vertical direction D3 while contacting the side surface (e.g., lateral side surface) of the stop layer 107. For example, the horizontal portion 109H of the semiconductor pattern 109 may be disposed between the initial peripheral dielectric layer 111 and the stop layer 107 in the third direction D3, and / or between the vertical portion 109V of the semiconductor pattern 109 and the stop layer 107 in the third direction D3. In some embodiments, the vertical portion 109V of the semiconductor pattern 109 may be disposed between the initial peripheral dielectric layer 111 and the stop layer 107 in the first direction D1.

[0166] Reference Figure 45 , a peripheral dielectric layer 112, a first buried layer 125, a second buried layer 130, a gate line GL, a gate dielectric layer Gox, a vertical channel pattern SP and a dielectric pattern 120 may be formed. This step may be performed by referring to Figure 10A and Figure 10B The methods discussed are implemented in (essentially) the same way.

[0167] An interlayer dielectric layer 200, a capacitor contact 205, and a first upper dielectric layer 300 may be formed. This step may be performed by referring to Figures 11A to 12B The methods discussed are implemented in (essentially) the same way.

[0168] Reference Figure 46 , you can Figure 45 The resulting structure is flipped upside down. For example, the resulting structure can be flipped so that the first upper dielectric layer 300 faces downward and the substrate 100 faces upward. After flipping the resulting structure, a portion of the substrate 100 can be removed. For example, the partial removal of the substrate 100 can include performing a planarization process until the upper surface (e.g., top surface) of the stop layer 107 on (in) the connection region CNR is exposed. For example, the planarization process can include a chemical mechanical polishing (CMP) process or an etch-back process.

[0169] Reference Figure 47, a stop pattern 115 may be formed. Forming the stop pattern 115 may include performing a planarization process until all horizontal portions 109H of the semiconductor pattern 109 on (in) the connection region CNR are removed. After the planarization process, (at least a portion of) the vertical portions 109V of the semiconductor pattern 109 may remain.

[0170] According to the present inventive concept, the pattern density of the vertical channel patterns SP on (in) the cell array region CAR may be similar to (or equal to) the pattern density of the semiconductor patterns 109 on (in) the connection region CNR. Therefore, the dishing phenomenon may be reduced (e.g., prevented) during the planarization process, and the reliability and electrical characteristics of the semiconductor device may be improved.

[0171] Return to reference Figure 41 , a bit line BL can be formed. Figure 14A and Figure 14B The bit lines BL are formed in the same manner as discussed above. The lower dielectric layer 400 may be formed to completely cover the cell array region CAR and the connection region CNR (eg, overlap the cell array region CAR and the connection region CNR in the third direction D3).

[0172] Figures 48 to 51 1 and 2. A cross-sectional view showing a semiconductor device according to some embodiments of the present inventive concept is shown. To simplify the description, repeated explanation may be omitted.

[0173] Reference Figure 48 According to some embodiments, the dummy structure DST may further include a vertical portion 109V of the semiconductor pattern ( 109 ), the vertical portion 109V of the semiconductor pattern ( 109 ) being interposed between the stop pattern 115 and the peripheral dielectric layer 112 .

[0174] A bit line contact plug BLCP, a connection circuit line 430, and a connection contact plug 410 may be provided in the lower dielectric layer 400. The bit line contact plug BLCP, the connection circuit line 430, and the connection contact plug 410 may be provided with reference to FIG. Figure 15 The discussion is (essentially) the same.

[0175] The capacitor contact plug CCP may be provided to extend in (e.g., pass through) the dummy structure DST, (a portion of) the lower dielectric layer 400, and a portion of the first upper dielectric layer 300. The capacitor contact plug CCP may be provided with reference to Figure 15 The discussion is (essentially) the same.

[0176] The connection pad CPD may be provided on the first upper dielectric layer 300. The through contact plug TCP may be provided to extend in (e.g., pass through) the first upper dielectric layer 300, the dummy structure DST, and a portion of the lower dielectric layer 400. The through contact plug TCP may be provided with reference to Figure 15 The discussion is (essentially) the same.

[0177] The first bonding pad 450 may be provided to be electrically connected to the bit line contact plug BLCP, the capacitor contact plug CCP, and the through contact plug TCP. Figure 15 The discussion is (essentially) the same.

[0178] The peripheral circuit structure PS may be disposed on a lower surface (eg, bottom surface) CSb of the lower dielectric layer 400. The peripheral circuit structure PS may be disposed on a lower surface (eg, bottom surface) CSb of the lower dielectric layer 400. Figure 15 The discussion is (essentially) the same.

[0179] The lower surface (eg, bottom surface) of the first bonding pad 450 may correspondingly (directly) contact the upper surface (eg, top surface) of the second bonding pad 35. The first bonding pad 450 and the second bonding pad 35 may constitute a single integral shape without any interface therebetween.

[0180] Reference Figure 49 According to some embodiments, the dummy structure DST may further include a vertical portion 109V of the semiconductor pattern (109), the vertical portion 109V of the semiconductor pattern (109) being interposed between the stop pattern 115 and the peripheral dielectric layer 112. The interface layer AL may be disposed on the lower surface (e.g., bottom surface) CSb of the lower dielectric layer 400. The peripheral circuit structure PS may be disposed on the lower surface (e.g., bottom surface) of the interface layer AL. The interface layer AL may be disposed on the reference Figure 17 The discussion is (essentially) the same. Figure 17 As discussed, this case can reduce process failures and process burdens compared to the case where the dielectric layer is formed to cover the entire sidewall of the peripheral through-contact 37 .

[0181] Reference Figure 50 According to some embodiments, the dummy structure DST may further include a vertical portion 109V of the semiconductor pattern (109), the vertical portion 109V of the semiconductor pattern (109) being interposed between the stop pattern 115 and the peripheral dielectric layer 112. The second upper dielectric layer 500 may be disposed on (the upper surface of) the first upper dielectric layer 300. The peripheral circuit structure PS may be disposed on an upper surface (e.g., top surface) CSa of the second upper dielectric layer 500. The components included in the first upper dielectric layer 300, the second upper dielectric layer 500, and the peripheral circuit structure PS may be the same as those in the reference numerals. Figure 19 The ones discussed are (essentially) the same.

[0182] The lower surface (eg, bottom surface) of the lower bonding pad 55 may correspondingly (directly) contact the upper surface (eg, top surface) of the upper bonding pad 550. The lower bonding pad 55 and the upper bonding pad 550 may constitute a single integral shape without any interface therebetween.

[0183] Reference Figure 51 According to some embodiments, the dummy structure DST may further include a vertical portion 109V of the semiconductor pattern (109), the vertical portion 109V of the semiconductor pattern being interposed between the stop pattern 115 and the peripheral dielectric layer 112. The interface layer AL may be disposed on (the upper surface of) the first upper dielectric layer 300. The peripheral circuit structure PS may be disposed on (the upper surface of) the interface layer AL. The interface layer AL may be disposed on (the upper surface of) the reference Figure 17 The discussion is (essentially) the same. Figure 17 As discussed above, this case can reduce process failures and process burdens compared to the case where the dielectric layer is formed to cover the entire sidewall of the peripheral through-contact 37.

[0184] In the semiconductor device according to the inventive concept, a unit structure may be formed using a bare silicon wafer, and thus, there may be an advantageous effect of reducing costs.

[0185] In addition, since the cell array region and the connection region are formed to have similar (or equal) pattern density when forming the cell structure, dishing can be reduced (eg, prevented) in a planarization process, and reliability and electrical characteristics of the semiconductor device can be improved.

[0186] Although the present invention has been described in conjunction with some embodiments of the inventive concept shown in the drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the inventive concept.

Claims

1. A semiconductor device comprising: a lower dielectric layer including a cell array region and a connection region adjacent to the cell array region; a plurality of vertical channel patterns spaced apart from each other in a first direction and a second direction on the cell array region of the lower dielectric layer, wherein the first direction and the second direction are parallel to an upper surface of the lower dielectric layer and intersect each other; a plurality of gate lines spaced apart from each other in the first direction and extending in the second direction on the cell array region of the lower dielectric layer, wherein at least one vertical channel pattern of the plurality of vertical channel patterns is located between the plurality of gate lines in the first direction; a capacitor structure located on the cell array region of the lower dielectric layer, wherein the capacitor structure is electrically connected to the plurality of vertical channel patterns; and a dummy structure located on the connection region of the lower dielectric layer, Wherein, the dummy structure includes: a plurality of dummy substrate patterns spaced apart from each other in the first direction and the second direction, and A peripheral dielectric layer is located between the plurality of dummy substrate patterns.

2. The semiconductor device according to claim 1, wherein A first distance at which the plurality of vertical channel patterns are spaced apart from each other in the first direction is equal to a second distance at which the plurality of dummy substrate patterns are spaced apart from each other in the first direction, and The third distance between the plurality of vertical channel patterns and each other in the second direction is equal to the fourth distance between the plurality of dummy substrate patterns and each other in the second direction.

3. The semiconductor device according to claim 1, wherein A first width of each of the plurality of vertical channel patterns in the first direction is equal to a second width of each of the plurality of dummy substrate patterns in the first direction, and The third width of each of the plurality of vertical channel patterns in the second direction is equal to the fourth width of each of the plurality of dummy substrate patterns in the second direction.

4. The semiconductor device according to claim 1 , further comprising: a plurality of bit lines located on the cell array region of the lower dielectric layer; as well as a gate dielectric layer located between one gate line of the plurality of gate lines and a corresponding one vertical channel pattern of the plurality of vertical channel patterns, A lower surface of each of the plurality of vertical channel patterns contacts an upper surface of a corresponding one of the plurality of bit lines.

5. The semiconductor device according to claim 1 , further comprising: an interlayer dielectric layer located between the plurality of gate lines and the capacitor structure; a first upper dielectric layer located on the capacitor structure and the dummy structure on the connection region; a capacitor contact plug extending in the dummy structure, wherein the capacitor contact plug is electrically connected to the capacitor structure; a plurality of bit lines in the lower dielectric layer, wherein the plurality of bit lines are electrically connected to the plurality of vertical channel patterns; and A plurality of bit line contact plugs in the lower dielectric layer, wherein each of the plurality of bit line contact plugs is electrically connected to a corresponding one of the plurality of bit lines.

6. The semiconductor device according to claim 5, further comprising: a connection pad located on the upper surface of the first upper dielectric layer on the connection region; a through-contact plug extending in the first upper dielectric layer and the dummy structure on the connection region, wherein the through-contact plug extends in a portion of the lower dielectric layer and is electrically connected to the connection pad; a plurality of first bonding pads adjacent to a lower surface of the lower dielectric layer, wherein the plurality of first bonding pads are electrically connected to the plurality of bit line contact plugs, the capacitor contact plugs, and the through contact plugs; and a peripheral circuit structure located on the lower surface of the lower dielectric layer, Wherein, the peripheral circuit structure includes: a plurality of peripheral circuit transistors; and A plurality of second bonding pads are electrically connected to the plurality of peripheral circuit transistors, wherein the plurality of first bonding pads respectively contact the plurality of second bonding pads.

7. The semiconductor device according to claim 6, further comprising: a through-plug liner layer extending around a side surface of the through-contact plug; as well as A capacitor plug liner layer extends around side surfaces of the capacitor contact plug.

8. The semiconductor device according to claim 5, further comprising: a connection pad located on the upper surface of the first upper dielectric layer on the connection region; a through-contact plug extending in the first upper dielectric layer and the dummy structure on the connection region, wherein the through-contact plug extends in a portion of the lower dielectric layer and is electrically connected to the connection pad; a plurality of connecting contact plugs in the lower dielectric layer; a plurality of connection circuit lines in the lower dielectric layer, wherein the plurality of connection contact plugs and the plurality of connection circuit lines are electrically connected to the plurality of bit line contact plugs, the capacitor contact plugs, and the through contact plugs; an interface layer located on a lower surface of the lower dielectric layer; and a peripheral circuit structure located on the lower surface of the interface layer, Wherein, the peripheral circuit structure includes: a plurality of peripheral circuit transistors; and a plurality of peripheral through-contacts, wherein the plurality of peripheral through-contacts are electrically connected to corresponding peripheral circuit transistors, The plurality of peripheral through-contacts extend in the interface layer and are electrically connected to the plurality of connection circuit lines respectively.

9. The semiconductor device according to claim 8, further comprising: a through-plug liner layer extending around a side surface of the through-contact plug; as well as A capacitor plug liner layer extends around side surfaces of the capacitor contact plug.

10. The semiconductor device according to claim 1, wherein Each of the plurality of vertical channel patterns extends in a third direction perpendicular to the upper surface of the lower dielectric layer, and A first thickness of each of the plurality of vertical channel patterns in the third direction is equal to a second thickness of the peripheral dielectric layer in the third direction and is equal to a third thickness of each of the plurality of dummy substrate patterns in the third direction.

11. A semiconductor device comprising: a lower dielectric layer including a cell array region and a connection region adjacent to the cell array region; a plurality of vertical channel patterns spaced apart from each other in a first direction and a second direction on the cell array region of the lower dielectric layer, wherein the first direction and the second direction are parallel to an upper surface of the lower dielectric layer and intersect each other; a plurality of gate lines spaced apart from each other in the first direction and extending in the second direction on the cell array region of the lower dielectric layer, wherein at least one of the plurality of vertical channel patterns is located between the plurality of gate lines in the first direction; a capacitor structure located on the cell array region of the lower dielectric layer, wherein the capacitor structure is electrically connected to the plurality of vertical channel patterns; and a dummy structure located on the connection region of the lower dielectric layer, Wherein, an upper surface of each of the plurality of vertical channel patterns is coplanar with an upper surface of the dummy structure.

12. The semiconductor device according to claim 11, wherein The dummy structure includes: a peripheral dielectric layer; and A stop pattern is located between the peripheral dielectric layer and the plurality of gate lines.

13. The semiconductor device according to claim 12, wherein Each of the plurality of vertical channel patterns extends in a third direction perpendicular to the upper surface of the lower dielectric layer, and A first thickness of each of the plurality of vertical channel patterns in the third direction is equal to a second thickness of the peripheral dielectric layer in the third direction, and is equal to a third thickness of the stop pattern in the third direction.

14. The semiconductor device according to claim 12, further comprising: an interlayer dielectric layer located between the plurality of gate lines and the capacitor structure; a first upper dielectric layer on the capacitor structure and the dummy structure on the connection region; a capacitor contact plug extending in the dummy structure, wherein the capacitor contact plug is electrically connected to the capacitor structure; a plurality of bit lines in the lower dielectric layer, wherein the plurality of bit lines are electrically connected to the plurality of vertical channel patterns; and A plurality of bit line contact plugs are formed in the lower dielectric layer, wherein the plurality of bit line contact plugs are electrically connected to the plurality of bit lines, respectively.

15. The semiconductor device according to claim 14, further comprising: a connection pad located on the upper surface of the first upper dielectric layer on the connection region; a through-contact plug extending in the first upper dielectric layer and the dummy structure on the connection region, wherein the through-contact plug extends in a portion of the lower dielectric layer and is electrically connected to the connection pad; a plurality of first bonding pads adjacent to a lower surface of the lower dielectric layer, wherein the plurality of first bonding pads are electrically connected to the plurality of bit line contact plugs, the capacitor contact plugs, and the through contact plugs, respectively; and a peripheral circuit structure located on the lower surface of the lower dielectric layer, Wherein, the peripheral circuit structure includes: a plurality of peripheral circuit transistors; and a plurality of second bonding pads electrically connected to the plurality of peripheral circuit transistors, The plurality of first bonding pads respectively contact the plurality of second bonding pads.

16. The semiconductor device according to claim 14, further comprising: a connection pad located on the upper surface of the first upper dielectric layer on the connection region; a through-contact plug extending in the first upper dielectric layer and the dummy structure on the connection region, wherein the through-contact plug extends in a portion of the lower dielectric layer and is electrically connected to the connection pad; a plurality of connecting contact plugs in the lower dielectric layer; a plurality of connection circuit lines in the lower dielectric layer, wherein the plurality of connection contact plugs and the plurality of connection circuit lines are electrically connected to the plurality of bit line contact plugs, the capacitor contact plugs, and the through contact plugs; an interface layer on the lower surface of the lower dielectric layer; and The peripheral circuit structure on the lower surface of the interface layer, Wherein, the peripheral circuit structure includes: a plurality of peripheral circuit transistors; and a plurality of peripheral through-contacts, wherein the plurality of peripheral through-contacts are electrically connected to the plurality of peripheral circuit transistors, The plurality of peripheral through-contacts extend in the interface layer and are electrically connected to the plurality of connection circuit lines respectively.

17. The semiconductor device according to claim 12, further comprising: A vertical portion of a semiconductor pattern, wherein the vertical portion of the semiconductor pattern is located between the stop pattern and the peripheral dielectric layer.

18. The semiconductor device according to claim 17, wherein Each of the plurality of vertical channel patterns extends in a third direction perpendicular to the upper surface of the lower dielectric layer, and A first thickness of each of the plurality of vertical channel patterns in the third direction is equal to a second thickness of the peripheral dielectric layer in the third direction, equal to a third thickness of the stop pattern in the third direction, and equal to a fourth thickness of the vertical portion of the semiconductor pattern in the third direction.

19. A semiconductor device comprising: a lower dielectric layer including a cell array region and a connection region extending from the cell array region; a bit line located on the cell array region of the lower dielectric layer, wherein the bit line extends in a first direction; a plurality of vertical channel patterns spaced apart from each other in the first direction on the bit lines; a plurality of gate lines on the bit line, wherein a gate line of the plurality of gate lines is adjacent to a corresponding vertical channel pattern of the plurality of vertical channel patterns, the plurality of gate lines intersect the bit line and extend in a second direction intersecting the first direction; a capacitor structure located on the plurality of vertical channel patterns, wherein the capacitor structure includes a plurality of lower electrodes spaced apart from each other in the first direction, a dielectric layer on the plurality of lower electrodes, and an upper electrode on the dielectric layer and the plurality of lower electrodes; and a dummy structure located on the connection region of the lower dielectric layer, Wherein, the dummy structure includes: a plurality of dummy substrate patterns spaced apart from each other in the first direction; and A dummy dielectric pattern is located between the plurality of dummy substrate patterns.

20. The semiconductor device according to claim 19, wherein A first distance by which the plurality of vertical channel patterns are spaced apart from each other in the first direction is equal to a second distance by which the plurality of dummy substrate patterns are spaced apart from each other in the first direction.

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