Stepped structure and method for forming stepped structure

Abstract

Stepped structures and methods for forming stepped structures are disclosed herein. Systems, devices, and methods for fabricating stepped structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a method includes providing a first stack of first stacks including first sacrificial layers and first isolation layers extending in a first direction. At least a portion of the first stack is etched to form a first stepped structure. A second stack adjacent to the first stack in a second direction is provided, the second stack including a second stack of second sacrificial layers and second isolation layers extending in the first direction, the second sacrificial layers and the second isolation layers alternating with each other in the second direction. At least a portion of the second stack is etched to form a second stepped structure. A contact structure extending in the second direction through at least one of the first stepped structure or the second stepped structure is formed.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and fabrication processes for semiconductor devices. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers in a similar footprint. A 3D memory device generally includes a memory array of memory cells and peripheral circuitry for facilitating the operation of the memory array. The memory cells can include vertical structures. Summary of the Invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of the present disclosure is characterized by a semiconductor device comprising: a first stack including a first stepped structure extending along a first direction; and a second stack adjacent to the first stack along a second direction perpendicular to the first direction, wherein the second stack includes a second stepped structure, and wherein the first stepped structure is adjacent to or has a gap with the second stepped structure in the first direction.

[0005] In some embodiments, the second stack includes a stack of conductive layers and isolation layers alternating with each other along the second direction, and the stack of conductive layers and isolation layers is adjacent to the first stepped structure along the second direction.

[0006] In some embodiments, the first direction and the second direction define a first plane, wherein the first region is a projection of the first stepped structure on the first plane, wherein the second region is a projection of the second stepped structure on the first plane, and wherein the first region has the same shape as the second region.

[0007] In some embodiments, each of the first region and the second region is a V-shaped region.

[0008] In some embodiments, the first stepped structure includes a first stepped substructure and a second stepped substructure, the first stepped substructure including first stepped steps descending in a first direction, and the second stepped substructure including second stepped steps ascending in the first direction.

[0009] In some embodiments, the first stack includes an array region, a wall region, and a connection region including a first stepped structure, wherein the wall region is adjacent to the connection region along a third direction perpendicular to the first direction and the second direction, and wherein the second step steps ascending along the first direction are coupled to the array region via the wall region.

[0010] In some embodiments, the first stack includes a third stepped structure adjacent to the first stepped structure in the first direction, and the second stack includes a fourth stepped structure with a gap therebetween in the first direction.

[0011] In some embodiments, the third region is a projection of the third stepped structure on the first plane, wherein the fourth region is a projection of the fourth stepped structure on the first plane, and wherein the third region has the same shape as the fourth region.

[0012] In some embodiments, each of the first stepped structure and the third stepped structure is located between the second stepped structure and the fourth stepped structure along the first direction.

[0013] In some embodiments, a semiconductor device includes a contact structure having a first segment located in a first stack and a second segment located in a second stack, and wherein each of the first segment and the second segment has a first diameter at a top and a second diameter at a bottom along a second direction, and the first diameter is greater than the second diameter.

[0014] Another aspect of the present disclosure is characterized by a method comprising: providing a first stack comprising a first stack of first sacrificial layers and first isolation layers extending along a first direction, the first sacrificial layers and the first isolation layers alternating with each other along a second direction perpendicular to the first direction; etching at least a portion of the first stack to form a first stepped structure; providing a second stack adjacent to the first stack along a second direction, the second stack comprising a second stack of second sacrificial layers and second isolation layers extending along the first direction, the second sacrificial layers and the second isolation layers alternating with each other along the second direction; etching at least a portion of the second stack to form a second stepped structure; and forming a contact structure extending along the second direction through at least one of the first stepped structure or the second stepped structure.

[0015] In some embodiments, the first stepped structure is adjacent to the second stepped structure in the first direction or has a gap therebetween.

[0016] In some embodiments, the first stepped structure includes stair-steps, and wherein the method includes depositing a protective layer on top surfaces of the stair-steps.

[0017] In some embodiments, the first stack includes a first array region and a first connection region, wherein the first connection region includes a first stepped structure and is adjacent to the first array region along a first direction, and wherein the method includes: (i) forming a first gate line hole in the first array region and the first connection region, (ii) forming a first channel hole in the first array region and the first connection region, and (iii) forming a first contact hole in the first connection region, wherein the first gate line hole, the first channel hole, and the first contact hole extend through the first stack along a second direction, and wherein the first gate line hole, the first channel hole, and the first contact hole are formed during the same first etching process.

[0018] In some embodiments, the second stack includes a second array region and a second connection region, wherein the second connection region includes a second stepped structure and is adjacent to the second array region along a first direction, and wherein the method includes: after providing the second stack, (i) forming a second gate line hole in the second array region and the second connection region, (ii) forming a second channel hole in the second array region and the second connection region, and (iii) forming a second contact hole in the second connection region, wherein the second gate line hole, the second channel hole, and the second contact hole extend through the second stack along a second direction, and wherein the second gate line hole, the second channel hole, and the second contact hole are formed during the same second etching process.

[0019] In some embodiments, after forming the second gate line hole, the second channel hole, and the second contact hole, the method includes: removing sacrificial material from the first sacrificial layer and the second sacrificial layer; and depositing conductive material in the first sacrificial layer and the second sacrificial layer to form a first conductive layer and a second conductive layer, respectively.

[0020] In some embodiments, forming a contact structure that extends through at least one of the first stepped structure or the second stepped structure includes: forming a first contact structure and a second contact structure, wherein the first contact structure extends through the first stepped structure and does not extend through the second stepped structure, and wherein the second contact structure extends through the second stepped structure and does not extend through the first stepped structure.

[0021] In some embodiments, the first contact structure extends through the second conductive layer and the second isolation layer, and the second contact structure extends through the first conductive layer and the first isolation layer; or the first contact structure extends through an insulating structure included in the second stack, and the second contact structure extends through the first conductive layer and the first isolation layer.

[0022] In some embodiments, etching at least a portion of the first stack to form a first stepped structure includes: etching a first portion of the first stack to form the first stepped structure, while a second portion of the first stack remains unetched, wherein the second portion of the first stack is adjacent to the first portion of the first stack along a third direction perpendicular to the first direction and the second direction, and wherein the second portion of the first stack includes a portion of a first stack of a first sacrificial layer and a first isolation layer; removing sacrificial material from the sacrificial layer of the second portion of the first stack; and depositing at least one conductive material in the second portion of the first stack to form a wall region.

[0023] Yet another aspect of the present disclosure is characterized by a system comprising: a semiconductor device comprising: a first stack including a first stepped structure, wherein the first stepped structure has a first starting point and a first end point in a first direction, and wherein the first starting point and the first end point define a first interval; and a second stack adjacent to the first stack along a second direction perpendicular to the first direction, wherein the second stack includes a second stepped structure, wherein the second stepped structure has a second starting point and a second end point in the first direction, and wherein the second starting point and the second end point define a second interval; and wherein the first interval is adjacent to the second interval or has a gap with the second interval; and a memory controller electrically connected to the semiconductor device, wherein the memory controller is configured to control the semiconductor device.

[0024] The present technology can be applied to various types of semiconductor devices, including volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase change memory (PCM) (e.g., PCRAM), spin transfer torque (STT)-magnetoresistive random access memory (MRAM), and others. The present technology can also be applied to charge trapping-based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating gate-based memory devices. The present technology can be applied to three-dimensional (3D) memory devices. The present technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (quad-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, the present technology may be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, and others.

[0025] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable one of ordinary skill in the art to make and use the disclosure.

[0027] Figure 1A An exemplary 3D semiconductor structure is shown.

[0028] Figure 1B A top view of an exemplary 3D semiconductor structure according to some aspects of the present disclosure is shown.

[0029] Figure 1C Depicts some aspects of the present disclosure along Figure 1B Cross-sectional view of an exemplary 3D semiconductor structure along cut lines AA′ and BB′ shown in FIG.

[0030] Figure 2A-2C A first exemplary stepped structure for a 3D semiconductor structure according to aspects of the present disclosure is shown.

[0031] Figure 3A-3C A second exemplary staircase structure for a 3D semiconductor structure according to aspects of the present disclosure is shown.

[0032] Figure 4A-4B A third exemplary stepped structure for a 3D semiconductor structure according to aspects of the present disclosure is shown.

[0033] Figures 5A-5O Cross-sectional views of the structure of an exemplary semiconductor structure after various stages of the fabrication process according to aspects of the present disclosure are shown.

[0034] Figure 6 is a flow chart of an exemplary process for forming a semiconductor structure according to some aspects of the present disclosure.

[0035] Figure 7 A block diagram of a system having one or more semiconductor devices according to one or more embodiments of the present disclosure is shown.

[0036] Like reference numbers and designations in the various drawings indicate like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0037] Figure 1AAn exemplary 3D semiconductor structure 100A is shown. As shown, the exemplary 3D semiconductor structure 100A includes three stacks 106A, 108A, and 110A stacked vertically (i.e., along the Z direction). Along the Y direction, the exemplary 3D semiconductor structure 100A includes a stepped structure 102A and a wall region 104A. In some examples, the stepped structure 102A is formed after forming all three stacks 106A, 108A, and 110A. Figure 1B-1C Other exemplary multi-stacked 3D semiconductor structures formed using different processes than the exemplary 3D semiconductor structure 100A are depicted. Figure 1B-1C In the described exemplary 3D semiconductor structure, each stacked stepped structure is formed during a corresponding formation process of a corresponding stack.

[0038] Figure 1B An exemplary 3D semiconductor structure 100B is shown, and Figure 1C An exemplary 3D semiconductor structure 100C is shown that corresponds to exemplary 3D semiconductor structure 100B. Although exemplary 3D semiconductor structure 100B and exemplary 3D semiconductor structure 100C are similar 3D semiconductor structures, exemplary 3D semiconductor structure 100C may include more, fewer, or different structures than exemplary 3D semiconductor structure 100B. Figure 1B is a top view of an exemplary 3D semiconductor structure 100B, and Figure 1C Depicts the Figure 1B 1 , and a cross-sectional view of an exemplary 3D semiconductor structure 100C along cut lines AA′ and BB′ is shown in FIG. The 3D semiconductor structure 100B and / or the 3D semiconductor structure 100C may be used to form a memory device, such as a 3D NAND memory device.

[0039] It should be noted that the X, Y, and Z axes (also referred to as X, Y, and Z directions) are included in Figure 1A-1B to further illustrate the spatial relationship of various components in the semiconductor structure. The semiconductor layer of the semiconductor structure includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the wafer on which the components of the semiconductor structure can be formed, and a bottom surface on the back side of the wafer opposite to the front side. The Z direction is perpendicular to both the X direction and the Y direction. As used herein, when the semiconductor layer is located in the lowest plane of the semiconductor structure in the Z direction, whether a component (e.g., a layer or a device) is "on", "above" or "below" another component (e.g., a layer or a device) of the semiconductor structure is determined relative to the semiconductor layer of the semiconductor structure in the Z direction (a vertical direction perpendicular to the XY plane, e.g., the thickness direction of the semiconductor layer). The same concept for describing spatial relationships is applied throughout this disclosure.

[0040] Figure 1B A top view of a semiconductor structure 100B according to some aspects of the present disclosure is shown. The semiconductor structure 100B includes an array region 102B and a connection region 104B. The connection region 104B (which may also be referred to as a step region) is adjacent to the array region 102B in a first horizontal direction (e.g., the X direction). The array region 102B includes an array of channel structures 106B. Each channel structure 106B can be used to form a string of memory cells coupled in series along a vertical direction (e.g., the Z direction) perpendicular to the XY plane. The connection region 104B includes a channel structure 110B and a contact structure 112B. The channel structure 110B located in the connection region 104B may also be referred to as a dummy channel structure. The semiconductor structure 100B includes a gate line gap structure 108B extending through both the array region 102B and the connection region 104B along the X direction. In some embodiments, the gate line slit structure in the connection region 104B has a greater width in the second horizontal direction (e.g., the Y direction) than the gate line slit structure in the array region 102B. In some embodiments, the gate line slit structure in the connection region 104B has the same width as the gate line slit structure in the array region 102B. In some embodiments, the gate line slit structure in the connection region 104B has a smaller width than the gate line slit structure in the array region 102B. Figure 1B Also shown is the Figure 1C Cutting lines AA' and BB' in the cross-sectional view.

[0041] Figure 1C 1 shows a cross-sectional view of a semiconductor structure 100C along lines AA' and BB' according to some aspects of the present disclosure. Figure 1C As shown, semiconductor structure 100C includes a semiconductor layer 114C and a stack 115C of a conductive layer 116C and an isolation layer 118C provided on semiconductor layer 114C. Semiconductor layer 114C can be any suitable semiconductor layer having any suitable semiconductor material, such as a single crystal, polycrystalline, or monocrystalline semiconductor. For example, semiconductor layer 114C can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, a III-V compound, or any combination thereof.

[0042] The stack 115C may extend parallel to the top surface of the semiconductor layer 114C in the XY plane. The conductive layers 116C and the isolation layers 118C may alternate in a vertical direction (e.g., the Z direction) perpendicular to the XY plane. The conductive layers 116C and the isolation layers 118C may extend from the array region 102C into the connection region 104C and may be arranged in a stepped structure located in the connection region 104C. The conductive layers 116C may have the same or different thicknesses, for example, in the range of 10-500 nanometers (nm), for example, approximately 35 nm. The isolation layers 118C may also have the same or different thicknesses, for example, in the range of 10-500 nm, for example, approximately 25 nm. The conductive layers 116C may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The isolation layer 118C may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the isolation layer 118C may also include a high-k dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. It should be noted that Figure 1C The number of conductive layers 116C and isolation layers 118C shown in FIG. 1 is for illustration only, and any suitable number of conductive layers and isolation layers may be included in the semiconductor structure 100C.

[0043] like Figure 1C As shown, each contact structure 112C has a head 122C and a body 124C. The contact structure 112C may extend through the connection region 104C in a vertical direction (eg, Z direction). The head 122C of the contact structure 112C may extend through a spacer layer provided on the stack 115C (eg, in FIG. Figure 1C (not shown), and the bottom end of the body 124C may extend through the semiconductor layer 114C. Due to the stair-like structure formed by the stack 115C in the connection region 104C, the body 124C may extend through a portion of the stack 115C included in the step of the stair-like structure (e.g., as shown in FIG. Figure 1C Step 126C) shown.

[0044] The stepped structure formed by the conductive layer 116C and the isolation layer 118C allows the contact structure 112C to connect the conductive layer 116C to external components. Each conductive layer 116C can be coupled to a corresponding contact structure and can be isolated from one or more other contact structures. In some embodiments, each contact structure 112C can be coupled to a corresponding conductive layer. The contact structure 112C can extend through a group of conductive layers of the stack 115C. The contact structure 112C can contact a conductive layer in the group of conductive layers that is closest to the head 122C of the contact structure 112C. For example, Figure 1C As shown, each contact structure 112C can extend through a conductive layer in a stair step (e.g., step 126C) and can be coupled to the topmost conductive layer in the stair step. One or more contact spacers can be located between the contact structure 112C and one or more other conductive layers in a set of conductive layers and can isolate the contact structure 112C from these conductive layers. Each contact spacer can include a dielectric material. In some other embodiments (in Figure 1C (not shown), each contact structure 112C can be coupled to a plurality of conductive layers 116C. In some embodiments, the contact structures 112C can be coupled to conductive contacts on the top surface of the semiconductor structure 100C via the head 122C, or to conductive contacts on the bottom surface of the semiconductor structure 100C via the bottom end of the body 124C, or both.

[0045] The connection region 104C further includes an insulating structure 130C. The insulating structure 130C may include a dielectric material, such as silicon oxide.

[0046] like Figure 1C As shown, the semiconductor structure 100C includes two stacks 134C and 136C stacked together vertically (i.e., along the Z direction). Each stack includes a corresponding subset of the conductive layer and the isolation layer of the stack 115C. The main body 124C of each contact structure 112C includes two segments, each segment being formed in a corresponding stack. The two segments of the main body 124C are connected together in sequence along the vertical direction. Each segment of the main body 124C can be shaped as a column or a truncated cone, and can have a diameter that gradually decreases from top to bottom in the vertical direction. For example, each segment can have a first diameter at the top and a second diameter at the bottom along the Z direction, and the first diameter is larger than the second diameter.

[0047] At the intersection of two adjacent stacks, the top of the lower section of body 124C may have a larger diameter than the bottom of the upper section of body 124C. For example, for each contact structure 112C, the top of the section of contact structure 112C located in stack 136C is thicker than the bottom of another section of contact structure 112C located in stack 134C. It should be noted that Figure 1C The two stacks shown in FIG are for illustration purposes only, and any suitable number (including one) of stacks may be included in the semiconductor structure 100C.

[0048] Contact structure 112C extends through the stack in the Z direction. In some examples, contact structure 112C may include a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some examples, contact structure 112C and conductive layer 116C may be formed from the same material.

[0049] Conductive layer 116C may include a topmost conductive layer (e.g., first conductive layer 138C) and other conductive layers (e.g., second conductive layer 148C) located below the topmost conductive layer. First conductive layer 138C contacts contact structure 112C. In some embodiments, spacer layer 140C is formed between contact structure 112C and second conductive layer 148C. It should be understood that the "topmost conductive layer" used herein refers to Figure 1C The topmost conductive layer of each stepped structure (rather than the entire memory structure) shown in FIG. In other words, the topmost conductive layer in different stepped structures can be a different conductive layer in the entire memory structure. Figure 1C As shown, the spacer layer 140C extends along the Z-direction and insulates the contact structure 112C from the second conductive layer 148C.

[0050] First conductive layer 138C includes a first portion 142C having a first thickness W1 and a second portion 144C having a second thickness W2 less than the first thickness that contacts contact structure 112C. First portion 142C of first conductive layer 138C is disposed over isolation layer 118C, and second portion 144C of first conductive layer 138C is disposed over spacer layer 140C.

[0051] In other words, first portion 142C of first conductive layer 138C contacts second portion 144C of first conductive layer 138C, and second portion 144C protrudes beyond first portion 142C in the X direction, which is perpendicular to the Z direction. In some embodiments, a top surface of first portion 142C of first conductive layer 138C is coplanar with a top surface of second portion 144C of first conductive layer 138C. In some embodiments, second conductive layer 148C has a third thickness that is less than the first thickness of first portion 142C.

[0052] The channel structure 106C and the dummy channel structure 110C extend through the stack 115C in a vertical direction (e.g., the Z direction). Each channel structure 106C may have one or more segments. Each of the one or more segments is located in a corresponding stack of the semiconductor structure 100C and is shaped like a column or a truncated cone. The channel structure 106C may include a storage film and a semiconductor channel. In some examples, the storage film includes a blocking layer, a charge trapping layer, and a tunneling layer. In some examples, the material for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material (e.g., aluminum oxide or hafnium oxide); the material for the charge trapping layer may include polysilicon, silicon nitride, or silicon oxynitride; and the material for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material (e.g., aluminum oxide or hafnium oxide). In an example, the materials of the blocking layer, the charge trapping layer, the tunneling layer, and the semiconductor channel may include silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively. Each dummy channel structure 110C may include a structure and material similar to the channel structure 106C. In some embodiments, the dummy channel structure 110 may be used to support a stack 115C within the connection region 104C.

[0053] Figure 1C A cross-sectional view of the gate line slit structure 108C along line AA' is shown. The gate line slit structure 108C extends through the stack 115C in the Z direction. The gate line slit structure 108C can divide the semiconductor structure 100C into a plurality of blocks. Each gate line slit structure 108C may include a gate line trench filled with a trench filler material (e.g., polysilicon). The gate line trenches may be formed in the following process. A series of gate line holes may be formed in the semiconductor structure 100C along the X direction. Each of the gate line holes extends through the semiconductor structure 100C along the Z direction. Each gate line hole in the series of gate line holes may then be expanded (e.g., by etching). Two adjacent gate line holes may be connected to each other after expansion, which converts the series of gate line holes into gate line trenches.

[0054] Figures 2A-4B Shown for Figure 1A-1BAn exemplary staircase structure of a 3D semiconductor structure similar to or identical to the 3D semiconductor structure 100A / 3D semiconductor structure 100B in FIG. Figures 2A-4B The exemplary ladder structure described is not limited to Figure 1A-1B For example, regarding the 3D semiconductor structure 100A / 3D semiconductor structure 100B Figures 2A-4B Any of the exemplary stepped structures described may be formed in a 3D semiconductor structure in which gate line trenches are not formed based on gate line holes.

[0055] Figure 2A-2C A first exemplary staircase structure for a 3D semiconductor structure 200 (which may be similar in operation and / or structure to the 3D semiconductor structure 100A / 3D semiconductor structure 100B) according to some aspects of the present disclosure is shown. Figure 2A-2B As depicted, the 3D semiconductor structure 200 includes three stacks stacked together vertically (i.e., along the Z direction). Each of the three stacks includes a corresponding connection region. For example, the stack located at the bottom along the Z direction includes a connection region 202, the stack located in the middle along the Z direction includes a connection region 204, and the stack located at the top along the Z direction includes a connection region 206. Each of the three connection regions includes a corresponding stepped structure extending along a first horizontal direction (e.g., the X direction). For example, the connection region 202 includes stepped structures 208 and 210, and the connection region 204 includes stepped structures 212 and 214.

[0056] In some embodiments, for two stacks adjacent to each other in a vertical direction, where the first stack includes a first stepped structure and the second stack includes a second stepped structure, the first stepped structure is adjacent to the second stepped structure in the first horizontal direction or has a gap with the second stepped structure. The projection of the first stepped structure in the first horizontal direction can be a line segment having a first starting point X1 and a first end point X2 in the first horizontal direction. The first starting point X1 and the first end point X2 define a first interval [X1, X2]. Similarly, the projection of the second stepped structure in the first horizontal direction can be another line segment having a second starting point Y1 and a second end point Y2 in the first horizontal direction. The second starting point Y1 and the second end point Y2 define a second interval [Y1, Y2]. In some cases, the first stepped structure is adjacent to the second stepped structure in the first horizontal direction, so that the first interval [X1, X2] is adjacent to the second interval [Y1, Y2] (i.e., X2=Y1 or X1=Y2). In other cases, the first stepped structure has a gap with the second stepped structure in the first horizontal direction, so the first interval [X1, X2] does not overlap with the second interval [Y1, Y2]. The same concept for describing spatial relationships is applied throughout this disclosure.

[0057] For example, Figure 2A-2BAs depicted, stepped structure 208 is adjacent to stepped structure 212 in the X-direction. In some embodiments, stepped structure 208 can have a gap from stepped structure 212 in the X-direction.

[0058] In some cases, the first stack includes a third stepped structure, and the third stepped structure is adjacent to the first stepped structure in the first horizontal direction. The second stack includes a fourth stepped structure, and the second stepped structure has a gap with the fourth stepped structure in the first horizontal direction. For example, Figure 2A-2B As depicted, the first stack includes a stepped structure 210, and the stepped structure 210 is adjacent to the stepped structure 208 in the X direction. The second stack includes a stepped structure 214, and the stepped structure 212 is spaced apart from the stepped structure 214 in the X direction.

[0059] In some examples, the first horizontal direction and the vertical direction define a first plane (e.g., an XZ plane). The first region is a projection of the first stepped structure on the first plane. The second region is a projection of the second stepped structure on the first plane. In some examples, the first region has the same shape as the second region. In one example, Figure 2B As depicted, assuming that the first region is a projection of the step structure 208 on the XZ plane, and the second region is a projection of the step structure 212 on the XZ plane, the first region has the same shape as the second region. Figure 2B As depicted, assuming that the third region is a projection of the stepped structure 210 on the XZ plane, and the fourth region is a projection of the stepped structure 214 on the XZ plane, the third region has the same shape as the fourth region.

[0060] In some examples, the stair structure includes a first stair substructure and a second stair substructure, the first stair substructure including first stair steps descending in a first horizontal direction, and the second stair substructure including second stair steps ascending in the first horizontal direction. Figure 2A-2B As depicted, the stepped structure 208 includes a first stepped substructure 216 including first stair steps descending in the X-direction and a second stepped substructure 218 including second stair steps ascending in the X-direction.

[0061] In some examples, the stackup includes an array region (in addition to the connection region) Figure 2A-2B The wall region is adjacent to the connection region along a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction and the vertical direction. The second step steps rising along the first horizontal direction are coupled to the array region via the wall region. For example, in addition to the connection region 202, the stack also includes an array region 222 (e.g., Figure 2C) and wall region 220. Wall region 220 is adjacent to connection region 202 along the Y direction. The second step of second stepped substructure 218, which rises in the X direction, is coupled to the array region via wall region 220. In some cases, the wall region includes a plurality of alternating conductive layers and isolation layers. The conductive layer of the wall region can be coupled to (i) the topmost conductive layer of the second stepped steps and (ii) a word line coupled to a conductive layer of the array region (e.g., conductive layer 116). By doing this for each of the second stepped steps, the second stepped steps rising in the first horizontal direction can be coupled to the array region via the wall region.

[0062] like Figure 2C As depicted, the connection region 202 includes a stack 230 of conductive layers and isolation layers that alternate with each other along the Z direction, and the stack 230 of conductive layers and isolation layers is adjacent to the stepped structure 212 along the Z direction. Figure 2C Some components (e.g., 208, 212, and 230) in FIG. Figure 2A-2B These components are shown with the same reference numerals, but Figure 2C The illustrations of these components can be omitted Figure 2A-2B Contact structure 224 extends through stepped structure 208 and insulating structure 228, but does not extend through stepped structure 212. On the other hand, contact structure 226 extends through stepped structure 212 and stack 230 of conductive and insulating layers, but does not extend through stepped structure 208.

[0063] Figure 3A-3C A second exemplary staircase structure for a 3D semiconductor structure 300 (which may be similar in operation and / or structure to the 3D semiconductor structure 100A / 3D semiconductor structure 100B) according to some aspects of the present disclosure is shown. Figure 3A-Figure 3B As depicted, the 3D semiconductor structure 300 includes three stacks stacked together vertically (i.e., along the Z direction). Each of the three stacks includes a corresponding connection region. For example, the stack located at the bottom along the Z direction includes a connection region 302, the stack located in the middle along the Z direction includes a connection region 304, and the stack located at the top along the Z direction includes a connection region 306. Each of the three connection regions includes a corresponding stepped structure extending along a first horizontal direction (e.g., the X direction). For example, the connection region 302 includes a stepped structure 308, the connection region 304 includes a stepped structure 312, and the connection region 306 includes a stepped structure 314.

[0064] In some embodiments, for two stacks adjacent to each other in a vertical direction, wherein the first stack comprises a first stepped structure and the second stack comprises a second stepped structure, the first stepped structure is adjacent to the second stepped structure in a first horizontal direction or has a gap therebetween. Figure 3A-Figure 3B As depicted, stepped structure 308 is adjacent to stepped structure 312 in the X-direction. In some embodiments, stepped structure 308 can have a gap from stepped structure 312 in the X-direction.

[0065] In some examples, the first horizontal direction and the vertical direction define a first plane (e.g., an XZ plane). The first region is a projection of the first stepped structure on the first plane. The second region is a projection of the second stepped structure on the first plane. In some examples, the first region has the same shape as the second region. For example, Figure 3B As depicted, assuming that the first region is a projection of the step structure 308 on the XZ plane, and the second region is a projection of the step structure 312 on the XZ plane, the first region has the same shape as the second region.

[0066] In some examples, the stair structure includes a first stair substructure and a second stair substructure, the first stair substructure including first stair steps descending in a first horizontal direction, and the second stair substructure including second stair steps ascending in the first horizontal direction. Figure 3A-Figure 3B As depicted, the stepped structure 308 includes a first stepped substructure 316 including first stair steps descending in the X-direction and a second stepped substructure 318 including second stair steps ascending in the X-direction.

[0067] In some examples, the stackup includes an array region (in addition to the connection region) Figure 3A-Figure 3B The wall region is adjacent to the connection region along a second horizontal direction (e.g., Y direction) perpendicular to the first horizontal direction and the vertical direction. The second step steps rising along the first horizontal direction are coupled to the array region via the wall region. For example, in addition to the connection region 302, the stack also includes an array region 322 (e.g., Figure 3C ) and a wall region 320, wherein the wall region 320 is adjacent to the connection region 302 in the Y direction, and wherein the second step steps of the second stepped substructure 318 ascending in the X direction are coupled to the array region via the wall region 320. The wall region 320 can be similar in operation and / or structure to the wall region 220, and details are omitted here for the sake of brevity.

[0068] like Figure 3C As depicted, the connection region 304 includes a stack 330 of conductive and insulating layers alternating with each other along the Z direction. Figure 3CSome components (e.g., 308, 314, and 330) in FIG. Figure 3A-Figure 3B These components are shown with the same reference numerals, but Figure 3C The illustrations of these components can be omitted Figure 3A-Figure 3B . The stack of conductive and isolating layers 330 is adjacent to the stepped structure 314 and the stepped structure 308 along the Z direction. The contact structure 324 extends through the stepped structure 308 and the stack of conductive and isolating layers 330, but does not extend through the stepped structure 314. On the other hand, the contact structure 326 extends through the stepped structure 314 and the stack of conductive and isolating layers 330, but does not extend through the stepped structure 308.

[0069] Figure 4A-4B A third exemplary staircase structure for a 3D semiconductor structure 400 (which may be similar in operation and / or structure to the 3D semiconductor structure 100A / 3D semiconductor structure 100B) according to some aspects of the present disclosure is shown. Figure 4A As depicted, the 3D semiconductor structure 400 includes three stacks stacked together vertically (i.e., along the Z direction). Each of the three stacks includes a corresponding connection region. For example, the stack located at the bottom along the Z direction includes a connection region 402, the stack located in the middle along the Z direction includes a connection region 404, and the stack located at the top along the Z direction includes a connection region 406. Each of the three connection regions includes a corresponding stepped structure extending along a first horizontal direction (e.g., the X direction). For example, the connection region 402 includes a stepped structure 408, the connection region 404 includes a stepped structure 412, and the connection region 406 includes a stepped structure 414.

[0070] In some embodiments, for two stacks adjacent to each other in a vertical direction, wherein the first stack comprises a first stepped structure and the second stack comprises a second stepped structure, the first stepped structure is adjacent to the second stepped structure in a first horizontal direction or has a gap therebetween. Figure 4A As depicted, stepped structure 408 is adjacent to stepped structure 412 in the X-direction. In some embodiments, stepped structure 408 can have a gap from stepped structure 412 in the X-direction.

[0071] In some examples, the first horizontal direction and the vertical direction define a first plane (e.g., an XZ plane). The first region is a projection of the first stepped structure on the first plane. The second region is a projection of the second stepped structure on the first plane. In some examples, the first region has the same shape as the second region. For example, Figure 4AAs depicted, assuming that the first region is a projection of the stepped structure 408 on the XZ plane and the second region is a projection of the stepped structure 412 on the XZ plane, the first region has the same shape as the second region. In some cases, each of the first region and the second region is a V-shaped region.

[0072] In some examples, the stackup includes an array region (in addition to the connection region) Figure 4A For example, in addition to the connection region 402, the stack also includes an array region 422 (e.g., Figure 4B As shown). Figure 4B As depicted, the connection region 404 includes a stack 430 of conductive and insulating layers alternating with each other along the Z direction. Figure 4B Some components (e.g., 408, 414, and 430) in Figure 4A These components are shown with the same reference numerals, but Figure 4B The illustrations of these components can be omitted Figure 4A . The stack of conductive and isolating layers 430 is adjacent to the stepped structure 414 and the stepped structure 408 along the Z direction. The contact structure 424 extends through the stepped structure 408 and the stack of conductive and isolating layers 430, but does not extend through the stepped structure 414. On the other hand, the contact structure 426 extends through the stepped structure 414 and the stack of conductive and isolating layers 430, but does not extend through the stepped structure 408.

[0073] The embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, in some examples (e.g., regarding Figure 3A-3C The second exemplary ladder structure described and the Figure 4A-4B The total space occupied by the stepped structure can be smaller than that of other stepped structures (e.g., Figure 2A-2C (The first exemplary staircase structure described above is shown in FIG. 1 ). Therefore, fewer portions of the stack of sacrificial layers and insulating layers need to be removed to form the staircase structure, and the saved portions of the stack can provide additional support for the entire semiconductor structure. As a result, the stability of the entire semiconductor structure can be enhanced. In some examples, the shape of a staircase structure in a stack can be the same as the shape of another staircase structure in another stack. Therefore, similar or identical staircase formation processes can be used to form staircase structures on different stacks. This can simplify the fabrication process of the semiconductor structure and, therefore, reduce fabrication costs.

[0074] Figures 5A-5O A cross-sectional view of an exemplary semiconductor structure after various stages of a fabrication process according to some aspects of the present disclosure is shown. The semiconductor structure may be Figure 1A-1BThe semiconductor structure 100A / 3D semiconductor structure 100B (or a portion of the semiconductor structure 100A / 3D semiconductor structure 100B) in Figure 2A-2C The semiconductor structure 200 (or a portion of the semiconductor structure 200) in Figure 3A-3C The semiconductor structure 300 (or a portion of the semiconductor structure 300) in Figure 4A-4B The semiconductor structure 400 (or a portion of the semiconductor structure 400 ) in FIG.

[0075] Figure 5A The structure 500a is shown after the first stage of forming the semiconductor structure. For example, the first stage includes providing a first sacrificial layer 502 and a first isolation layer 504 extending along a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction) (e.g., corresponding to Figure 1C The first stack 510 of the first sacrificial layer 502 and the first isolation layer 504 is formed by alternating along a vertical direction (e.g., a Z direction) perpendicular to the first horizontal direction and the second horizontal direction. The first sacrificial layer 502 may include a sacrificial material. The sacrificial material may include an insulating material (e.g., silicon dioxide, silicon nitride, or carbon), a semiconductor material (e.g., silicon or gallium arsenide), or other materials.

[0076] In some cases, providing the first stack includes providing a semiconductor layer 506 and depositing a first stack 510 of a first sacrificial layer 502 and a first isolation layer 504 over the semiconductor layer 506. In some embodiments, at least a portion of the first stack can be etched to form a first stepped structure 512.

[0077] In some embodiments, forming the stepped structure may include multiple etching operations. Figure 5B An exemplary process for forming a first stepped structure 512 is shown. As depicted, at step (a), a first etching operation can be performed on the topmost layer of the stack of sacrificial layers and isolation layers (e.g., first stack 510), wherein a first plurality of stepped substructures 514 are formed. At step (b), a second etching operation is performed on at least a portion of the first plurality of stepped substructures 514 to form a second plurality of stepped substructures 516. At step (c), a third etching operation is performed on at least a portion of the second plurality of stepped substructures 516 to form a third plurality of stepped substructures 518. At step (d), a fourth etching operation is performed on at least a portion of the third plurality of stepped substructures 518 to form the first stepped structure 512. It should be noted that although Figure 5B, four etching operations are shown, but any suitable number of etching operations can be performed to form the stepped structure. While at least a portion of the first stack is etched to form the first stepped structure 512, a portion 520 of the first stack can remain unetched. In subsequent operations (multiple), a wall region can be formed based on the portion 520 of the first stack.

[0078] Back to Figure 5A After forming the first stepped structure 512, a protective layer 508 is deposited on the first sacrificial layer 502. After forming the first stepped structure 512, the outer area of the first stack 510 can be exposed, and each pair of the first sacrificial layer 502 and the first isolation layer 504 can form a stair step. The protective layer 508 can then be deposited on the top surface of the stair step. In some embodiments, the protective layer 508 can include polysilicon. The first stepped structure 512 is then surrounded by an insulating structure 513 (e.g., corresponding to Figure 1C The insulating structure 130) is covered.

[0079] Figure 5C The structure 500c is shown after the second stage of forming the semiconductor structure. For example, the second stage includes: (i) forming a semiconductor structure in the first array region (eg, corresponding to the semiconductor structure of FIG. 5 ). Figure 1A-1B ) and the first connection region (e.g., corresponding to the array region 102 in FIG. Figure 1A-1B A first gate line hole 524 (e.g., Figure 5D (ii) forming a first channel hole (not shown) in the first array region and the first connection region, and (iii) forming a first contact hole 522 in the first connection region. The first gate line hole 524 can be used to form a gate line gap structure (e.g., corresponding to Figure 1A-1B The first channel hole may be used to form a channel structure (eg, corresponding to a gate line gap structure 108). Figure 1A-1B The first contact hole 522 may be used to form a contact structure (eg, corresponding to the channel structure 106). Figure 1A-1B The first gate line hole 524, the first channel hole and the first contact hole 522 extend through the first stack in a vertical direction.

[0080] In some embodiments, forming the first gate line hole 524, the first channel hole, and the first contact hole 522 can include performing one or more etching operations to remove portions of the first stack 510 to form the first gate line hole 524, the first channel hole, and the first contact hole 522. In some embodiments, removing portions of the first stack 510 includes removing portions of the insulating structure 513, the first sacrificial layer 502, the first isolation layer 504, the protection layer 508, and / or the semiconductor layer 506.

[0081] In some cases, the first gate line hole 524, the first channel hole, and the first contact hole 522 can have the same depth extending into the semiconductor layer 506. In some embodiments, after forming the first gate line hole 524, the first channel hole, and the first contact hole 522, an oxidation operation can be performed to form an insulating layer on the exposed portion of the semiconductor layer 506. In some embodiments, when the protective layer 508 includes polysilicon, the exposed surface of the protective layer 508 can also be oxidized.

[0082] In some cases, the first gate line hole 524, the first channel hole, and the first contact hole 522 are formed during the same first etching process. For example, the first gate line hole 524, the first channel hole, and the first contact hole 522 can be formed using a single mask. By forming the first gate line hole, the first channel hole, and the first contact hole 522 together, the number of process steps can be significantly reduced, and manufacturing costs can be reduced.

[0083] Figure 5D A cross-sectional view of structure 500c is shown. Figure 5D The first gate line hole 524 and the first contact hole 522 are shown. Figure 5D As shown, the first gate line hole 524 and the first contact hole 522 may have the same depth extending to the semiconductor layer 506 .

[0084] Figure 5E 5 shows a structure 500e after the third stage of forming the semiconductor structure. Figure 5E As shown, after forming the first gate line hole 524 and the first contact hole 522, a first sacrificial filling 526 is formed in the first contact hole 522, and a second sacrificial filling 528 is formed in the first gate line hole 524. Figure 5E In some embodiments, the first sacrificial filler 526, the second sacrificial filler 528, and the third sacrificial filler are formed together in the first contact hole 522, the first gate line hole 524, and the first channel hole in the same deposition process.

[0085] In some embodiments, Figure 5E After the described operations, including something like Figure 5E The second stack of structures in structure 500e can be used with respect to Figures 5A-5E Similar operations as described above are performed on the first stack. Specifically, the operations may include providing a second stack adjacent to the first stack in a vertical direction (at Figures 5A-5O). The second stack includes a second stack of a second sacrificial layer and a second isolation layer extending along a first horizontal direction, the second sacrificial layer and the second isolation layer alternating with each other along the second horizontal direction. Providing the second stack may include depositing a second stack of a second sacrificial layer and a second isolation layer on top of a first stack 510 of a first sacrificial layer 502 and a first isolation layer 504. Then, at least a portion of the second stack may be etched to form a second stepped structure. The second stack may include a second array region and a second connection region, wherein the second connection region includes a second stepped structure and is adjacent to the second array region along the first horizontal direction. After forming the second stepped structure, operations may include: (i) forming a second gate line hole in the second array region and the second connection region, (ii) forming a second channel hole in the second array region and the second connection region, and (iii) forming a second contact hole in the second connection region. The second gate line hole, the second channel hole, and the second contact hole extend through the second stack in a vertical direction. In some embodiments, the second gate line hole, the second channel hole, and the second contact hole are formed during the same second etching process. The second gate line hole can be aligned with the first gate line hole, the second channel hole can be aligned with the first channel hole, and the second contact hole can be aligned with the first contact hole. A sacrificial filler can be formed in the second gate line hole, the second channel hole, and the second contact hole. Similar operations can be used to form any suitable number of stacks. The difference between forming the second or subsequent stack and forming the first stack is that in some embodiments, the second or subsequent stack does not include a semiconductor layer similar to semiconductor layer 506.

[0086] Thus, the techniques described herein enable the formation of a staircase structure for each stack during the corresponding formation process of the corresponding stack. Compared to forming the staircase structure after forming all the stacks, the techniques described herein enable the formation of a staircase structure in some scenarios. These scenarios include situations where a staircase structure is adjacent to another staircase structure in a first direction or has a gap with another staircase structure. For example, the techniques described herein enable the formation of a staircase structure with respect to a first layer. Figure 3A-3C The second exemplary ladder structure described and the Figure 4A-4B A third exemplary ladder structure is described.

[0087] In some embodiments, after forming a plurality of stacks based on the above description, sacrificial materials from the sacrificial layers (eg, the first sacrificial layer and the second sacrificial layer) may be replaced with conductive materials, and the sacrificial materials may be replaced with conductive materials based on the above description. Figure 5F-5O The operations described are used to form contact structures (eg, corresponding to Figure 1A-1B contact structure 112).

[0088] like Figure 5FAs shown, the first sacrificial filler 526 may be removed to expose the first contact hole 522. In some embodiments, during the operation of removing the first sacrificial filler 526, a portion of the first sacrificial layer 502 may also be removed. Figure 5F As shown, the protection layer 508 may protrude along the sidewall of the first contact hole 522. The protruding structure of the protection layer 508 may form a specific shape of the topmost conductive layer in a subsequent operation.

[0089] like Figure 5G As shown, the spacer layer 530 is formed on the sidewalls of the first contact hole 522. In some embodiments, the spacer layer 530 may include silicon oxide. Figure 5F As shown, after forming the spacer layer 530 on the sidewall of the first contact hole 522, a portion of the protection layer 508 is located above the spacer layer 530. In other words, the protruding structure of the protection layer 508 may cover the top surface of the spacer layer 530.

[0090] like Figure 5H As shown, a sacrificial structure 532 (e.g., a dielectric layer) is formed in the first contact hole 522. In some embodiments, the sacrificial structure 532 may include one or more layers of polysilicon. In some embodiments, the sacrificial structure 532 may be formed in one or more deposition operations including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0091] Then, the first sacrificial layer 502 and the protective layer 508 may be replaced by the conductive layer 534 to form a stack having alternating conductive layers 534 and first isolation layers 504. Figure 5I As shown, the second sacrificial filler 528 is removed to expose the first gate line hole 524. Then, as shown in FIG. Figure 5J As shown, a portion of the first sacrificial layer 502 and a portion of the first isolation layer 504 are removed along the sidewalls of the first gate line hole 524. In other words, the first gate line hole 524 can be widened in this operation. In some embodiments, the widened first gate line hole 524 can be connected to other widened first gate line holes 524 along the X direction. A gate line slit structure (e.g., corresponding to the gate line slit structure 108) can be formed in the widened first gate line hole 524 in a subsequent operation. The gate line slit structure can be connected to other gate line slit structures along the X direction in a subsequent operation.

[0092] like Figure 5K As shown, the first sacrificial layer 502 is removed. Figure 5LAs shown, protective layer 508 is removed. In some cases, first sacrificial layer 502 and protective layer 508 are removed in the same removal operation (e.g., the same etching operation). In other cases, first sacrificial layer 502 and protective layer 508 are removed in multiple removal operations (e.g., multiple etching operations). After removing first sacrificial layer 502 and protective layer 508, multiple cavities 538 are formed between first isolation layer 504.

[0093] As described above, a portion of the first stack (e.g., Figure 5B The portion 520 in the first stack remains unetched during the formation of the first stepped structure 512, wherein the portion of the first stack includes a portion of the first stack 510 of the first sacrificial layer 502 and the first isolation layer 504. Figure 5K During the operation of removing the sacrificial material from the sacrificial layer of the portion of the first stack may be removed.

[0094] like Figure 5L As shown, the topmost cavity 536 is formed between the first isolation layer 504 and the insulating structure 513. In some embodiments, the topmost cavity 536 has a first width W1 above the first isolation layer 504 and a second width W2 above the spacer layer 530. In some embodiments, the first width W1 is greater than the second width W2.

[0095] like Figure 5M As shown, conductive layer 534 is formed in the topmost cavity 536 and cavity 538. As described above, the cavity is formed in a portion of the first stack (e.g., Figure 5B 520 in the cavity), and a conductive layer 534 may also be formed in these cavities to form wall regions.

[0096] like Figure 5N As shown, a gate line gap structure 540 is formed in the first gate line hole 524, and the sacrificial structure 532 is removed to expose the first contact hole 522. In some embodiments, an etching operation is performed to clean the sidewalls of the first gate line hole 524, and then the gate line gap structure 540 is formed in the first gate line hole 524. Since the first gate line hole 524 has been widened (e.g., Figure 5J In some embodiments, the gate line slit structure 540 formed in the widened first gate line hole 524 can be connected to other gate line slit structures 540 along the X direction. In some embodiments, the sacrificial structure 532 is removed by performing an etching operation to expose the first contact hole 522.

[0097] like Figure 5OAs shown, a portion of the spacer layer 530 along the sidewall of the first contact hole 522 is removed. In some embodiments, a portion of the spacer layer 530 and a portion of the insulating structure 513 are removed. Then, a contact structure 542 (eg, corresponding to a contact hole 522) is formed in the first contact hole 522. Figure 1A-1B Contact structure 542 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, contact structure 542 and conductive layer 534 may be formed from the same material. The top conductive layer 534 may contact contact structure 542. In some embodiments, a spacer layer 530 is formed between contact structure 542 and conductive layer 534. Spacer layer 530 extends in the Z direction and may insulate contact structure 542 from conductive layer 534.

[0098] By using the above-described process to form the contact structure 542, the gate line gap structure 540, and / or the channel structure, the processes for forming the channel structure, the gate line gap structure, and the contact structure are combined, and all deep hole etching processes can be completed in a simplified operation. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0099] In addition, as shown above, in the Figure 3A-3C The second exemplary ladder structure described and the Figure 4A-4B In the third exemplary stepped structure described, a stack of sacrificial layers and isolation layers may be deposited over the stepped structure (e.g., as shown in FIG. Figure 3C and Figure 4B In such a structure, after the sacrificial material of the sacrificial layer is replaced by a conductive material, holes (e.g., including gate line holes, channel holes, and contact holes) may not be formed, especially because the contact holes may not be able to extend through the conductive layer located above the stepped structure. Figures 5A-5O The described technology enables the use of conductive materials in place of sacrificial materials in sacrificial layers (e.g., Figure 5K-5M The operation described) before forming the hole (for example, Figure 5C-5D Therefore, regarding Figures 5A-5O The described technology enables the production of Figure 3A-3C The second exemplary ladder structure described and the Figure 4A-4B A third exemplary ladder structure is described.

[0100] although Figures 5A-5O The formation of the contact structure 542 is described (eg, with respect to Figure 5N-Figure 5O The operation described) occurs when a sacrificial material of a sacrificial layer is replaced with a conductive material (e.g., Figure 5K-5M), but in some embodiments, the formation of the contact structure 542 may occur before replacing the sacrificial material of the sacrificial layer with a conductive material.

[0101] Figure 6 is a flow chart of an exemplary process 600 for forming a semiconductor structure according to some aspects of the present disclosure. The semiconductor structure may be Figure 1A-1B The semiconductor structure 100A / 3D semiconductor structure 100B (or a portion of the semiconductor structure 100A / 3D semiconductor structure 100B) in Figure 2A-2C The semiconductor structure 200 (or a portion of the semiconductor structure 200) in Figure 3A-3C The semiconductor structure 300 (or a portion of the semiconductor structure 300) in Figure 4A-4B The semiconductor structure 400 (or a portion of the semiconductor structure 400) in FIG. Figure 1A-Figure 5O The exemplary process 600 may include forming Figure 1A-1B 、 Figure 2A-2C 、 Figure 3A-3C or Figure 4A-4B The exemplary process 600 includes steps that may be performed in any suitable order and / or in any combination.

[0102] At step 610, a first stack is provided, the first stack including a first sacrificial layer (eg, Figure 5A The first sacrificial layer 502 in the embodiment of the present invention) and the first isolation layer (eg, Figure 5A The first stack (eg, the first isolation layer 504 in Figure 1C The stack 115 or Figure 5A In some embodiments, providing a first stack includes providing a semiconductor layer (e.g., Figure 1C The semiconductor layer 114 or Figure 5A A semiconductor layer 506 in the embodiment of the present invention is provided, and a first stack of a first sacrificial layer and a first isolation layer is deposited over the semiconductor layer.

[0103] At step 620, at least a portion of the first layer stack may be etched to form a first stepped structure (eg, Figure 5A In some examples, the first stepped structure includes stair steps, and the exemplary process 600 includes depositing a protective layer (e.g., Figure 5A protective layer 508 in the ).

[0104] In some embodiments, the first stack includes a first array region (e.g., Figure 1A-1B Array area 102, Figure 2C Array area 222, Figure 3C Array area 322 or Figure 4B 422 in the array region) and the first connection region (e.g., Figure 2A-2C The connection area 202, Figure 3A-3C The connection area 302 or Figure 4A-4B The first connection region includes a first stepped structure (eg, Figure 2A-2C The ladder structure 208, Figure 3A-3C The ladder structure 308 or Figure 4A-4B The exemplary process 600 includes: (i) forming a first gate line hole (e.g., a first gate line hole in the first array region and a first connection region) in the first direction. Figure 5D (ii) forming a first channel hole in the first array region and the first connection region, and (iii) forming a first contact hole (e.g., Figure 5D The first contact hole 522 in the first layer is formed, wherein the first gate line hole, the first channel hole, and the first contact hole extend through the first stack along the second direction, and wherein the first gate line hole, the first channel hole, and the first contact hole are formed during the same first etching process.

[0105] In some cases, etching at least a portion of the first stack to form the first stepped structure includes etching a first portion of the first stack to form the first stepped structure, while a second portion of the first stack (eg, Figure 5B The portion 520 in the first stack remains unetched, wherein the second portion of the first stack is adjacent to the first portion of the first stack along a third direction perpendicular to the first direction and the second direction, and wherein the second portion of the first stack includes a portion of a first stack of a first sacrificial layer and a first isolation layer. Sacrificial material can be removed from the sacrificial layer of the second portion of the first stack. At least one conductive material can be deposited in the second portion of the first stack to form a wall region (e.g., Figure 2A-2B The wall area 220 or Figure 3A-Figure 3B wall region 320 in the middle).

[0106] At step 630, a second stack may be provided adjacent to the first stack along a second direction, the second stack including a second stack of second sacrificial layers and second isolation layers extending along the first direction, the second sacrificial layers and the second isolation layers alternating with each other along the second direction. In some cases, providing the second stack includes, after the first etching process, depositing the second stack of the second sacrificial layers and the second isolation layers on top of the first stack of the first sacrificial layers and the first isolation layers.

[0107] At step 640, at least a portion of the second stack may be etched to form a second stepped structure (eg, Figure 2A-2C The ladder structure 212, Figure 3A-Figure 3B The ladder structure 312 or Figure 4A In some embodiments, the second stack includes a second array region and a second connection region, wherein the second connection region includes a second stepped structure and is adjacent to the second array region along a first direction, and wherein the method includes: after providing the second stack, (i) forming a second gate line hole in the second array region and the second connection region, (ii) forming a second channel hole in the second array region and the second connection region, and (iii) forming a second contact hole in the second connection region, wherein the second gate line hole, the second channel hole, and the second contact hole extend through the second stack along a second direction, and wherein the second gate line hole, the second channel hole, and the second contact hole are formed during the same second etching process. In some cases, the first stepped structure is adjacent to or has a gap with the second stepped structure in the first direction.

[0108] In some embodiments, the exemplary process 600 includes, after forming the second gate line hole, the second channel hole, and the second contact hole, removing the sacrificial material from the first sacrificial layer and the second sacrificial layer, and depositing a conductive material in the first sacrificial layer and the second sacrificial layer to form a first conductive layer (e.g., Figure 5N-Figure 5O conductive layer 534 in) and a second conductive layer.

[0109] At step 650, a contact structure (eg, Figure 5O In some embodiments, forming a contact structure extending through at least one of the first stepped structure or the second stepped structure includes forming a first contact structure (eg, Figure 2C contact structure 224 in) and a second contact structure (eg, Figure 2C Contact structure 224, Figure 3C The contact structure 324 or Figure 4BIn some cases, the first contact structure extends through the second conductive layer and the second isolation layer, and the second contact structure extends through the first conductive layer and the first isolation layer; or the first contact structure extends through an insulating structure included in the second stack (e.g., Figure 2C The insulating structure 228 in the first conductive layer is provided, and the second contact structure extends through the first conductive layer and the first isolation layer.

[0110] Figure 7 A block diagram of a system 700 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. System 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 7 As shown, system 700 may include a host device 708 and a memory system 702 having one or more 3D memory devices 704 and a memory controller 706. Host device 708 may include a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host device 708 may be configured to send data to or receive data from one or more 3D memory devices 704.

[0111] The 3D memory device 704 may be any 3D memory device disclosed herein, such as Figure 1A-1B The 3D memory device depicted in Figure 2A-2C The 3D memory device of the semiconductor structure 200 or the 3D memory device based on Figure 3A-3C3D memory device of the semiconductor structure 300 in FIG. In some embodiments, the 3D memory device 704 includes a NAND flash memory. A memory controller 706 (also referred to as a controller circuit) is coupled to the 3D memory device 704 and a host device 708. Consistent with embodiments of the present disclosure, the 3D memory device 704 may include a plurality of conductive interconnects passing through a cover layer, the plurality of conductive interconnects contacting conductive pads in a conductive pad layer, and the memory controller 706 may be coupled to the 3D memory device 704 via at least one of the plurality of conductive interconnects. The memory controller 706 is configured to control the 3D memory device 704. For example, the memory controller 706 may be configured to operate a plurality of channel structures via word lines. The memory controller 706 may manage data stored in the 3D memory device 704 and communicate with the host device 708.

[0112] In some embodiments, the memory controller 706 is designed / configured to operate in a low duty cycle environment (e.g., a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 706 is designed / configured to operate in a high duty cycle environment (e.g., an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays). The memory controller 706 can be configured to control the operations of the 3D memory device 704 (e.g., read operations, erase operations, and program (or write) operations). The memory controller 706 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 704, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) on data read from or written to the 3D memory device 704. The memory controller 706 may also perform any other suitable functions, such as formatting the 3D memory device 704.

[0113] The memory controller 706 may communicate with an external device (e.g., the host device 708) according to a specific communication protocol. For example, the memory controller 706 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0114] The memory controller 706 and the one or more 3D memory devices 704 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage device (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of terminal electronic products. Figure 7 In one example shown, a memory controller 706 and a single 3D memory device 704 may be integrated into a memory system 702. The memory system 702 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like.

[0115] The embodiments of the subject matter described in this disclosure and the actions and operations may be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or a combination of one or more of them. The embodiments of the subject matter described in this disclosure may be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by a data processing device or for controlling the operation of the data processing device. The carrier may be a tangible, non-transitory computer storage medium. Alternatively or in addition, the carrier may be an artificially generated propagated signal, for example, a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiver device for execution by the data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage semiconductor layer, a random or serial access memory device or a portion thereof, or a combination of one or more of them. A computer storage medium is not a propagated signal.

[0116] It should be noted that references in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0117] Typically, a term can be understood, at least in part, from its usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "the" can also be understood to convey a singular usage or to convey a plural usage. In addition, also depending at least in part on the context, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described.

[0118] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween. Furthermore, “over” or “over” not only means “over something” or “on something,” but also includes the meaning of “over something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0119] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0120] As used herein, the term "semiconductor layer" refers to the material on which subsequent material layers are added. The semiconductor layer includes a "top" surface and a "bottom" surface. The top surface of the semiconductor layer is typically where the semiconductor devices are formed, and therefore, unless otherwise specified, the semiconductor devices are formed on the top side of the semiconductor layer. The bottom surface is opposite the top surface, and therefore, the bottom side of the semiconductor layer is opposite the top side of the semiconductor layer. The semiconductor layer itself can be patterned. The material added on top of the semiconductor layer can be patterned or can remain unpatterned. In addition, the semiconductor layer can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the semiconductor layer can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0121] As used herein, the term "layer" refers to a material portion comprising an area with a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the semiconductor layer, and the top side is relatively far away from the semiconductor layer. The layer can extend over the entire lower layer or overlying structure, or can have a range that is less than the range of the lower layer or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure, which has a thickness that is less than the thickness of the continuous structure. For example, the layer can be between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The semiconductor layer can be a layer, which can include one or more layers therein, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0122] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values above and / or below the expected value. As used herein, a range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0123] In this disclosure, the term “horizontal / horizontally / laterally” means nominally parallel to a lateral surface of a semiconductor layer, and the term “vertical / vertically” means nominally perpendicular to a lateral surface of a semiconductor layer.

[0124] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a string of vertically oriented memory cell transistors (referred to herein as a "memory string," such as a NAND string) on a laterally oriented semiconductor layer, such that the memory string extends in a vertical direction relative to the semiconductor layer.

[0125] The present disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature may be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0126] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teaching and guidance provided herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0127] Although this disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the claims defined by the claims themselves, but rather as descriptions of features that may be directed to particular embodiments of particular inventions. Certain features described in this disclosure, in the context of separate embodiments, may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, and even initially claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and claims may be directed to sub-combinations or variations of sub-combinations.

[0128] Similarly, although operations are depicted in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, in order to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments. Instead, it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0129] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0130] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: a first stack comprising a first stepped structure extending along a first direction; as well as A second stack is adjacent to the first stack along a second direction perpendicular to the first direction, wherein the second stack includes a second stepped structure, and wherein the first stepped structure is adjacent to the second stepped structure in the first direction or has a gap with the second stepped structure.

2. The semiconductor device according to claim 1, wherein The second stack includes a stack of conductive layers and isolation layers alternating with each other along the second direction, and the stack of conductive layers and isolation layers is adjacent to the first stepped structure along the second direction.

3. The semiconductor device according to claim 1 or 2, wherein The first direction and the second direction define a first plane, wherein the first region is a projection of the first stepped structure on the first plane, wherein the second region is a projection of the second stepped structure on the first plane, and wherein the first region has the same shape as the second region.

4. The semiconductor device according to any one of claims 1 to 3, wherein Each of the first region and the second region is a V-shaped region.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first stepped structure includes a first stepped substructure including first stair steps descending in the first direction and a second stepped substructure including second stair steps ascending in the first direction.

6. The semiconductor device according to any one of claims 1 to 3 and 5, wherein The first stack includes an array region, a wall region, and a connection region including the first stepped structure, wherein the wall region is adjacent to the connection region along a third direction perpendicular to the first direction and the second direction, and wherein the second stepped steps rising along the first direction are coupled to the array region via the wall region.

7. The semiconductor device according to any one of claims 3 and 5-6, wherein The first stack includes a third stepped structure adjacent to the first stepped structure in the first direction, and the second stack includes a fourth stepped structure with a gap therebetween in the first direction.

8. The semiconductor device according to claim 7, wherein The third region is a projection of the third stepped structure on the first plane, wherein the fourth region is a projection of the fourth stepped structure on the first plane, and wherein the third region has the same shape as the fourth region.

9. The semiconductor device according to claim 7 or 8, wherein Each of the first stepped structure and the third stepped structure is located between the second stepped structure and the fourth stepped structure along the first direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein The semiconductor device includes a contact structure having a first segment located in the first stack and a second segment located in the second stack, and wherein each of the first segment and the second segment has a first diameter at the top and a second diameter at the bottom along the second direction, and the first diameter is larger than the second diameter.

11. A method comprising: providing a first stack including a first stack of first sacrificial layers and first isolation layers extending along a first direction, the first sacrificial layers and the first isolation layers alternating with each other along a second direction perpendicular to the first direction; etching at least a portion of the first stack to form a first stepped structure; providing a second stack adjacent to the first stack along the second direction, the second stack comprising a second stack of second sacrificial layers and second isolation layers extending along the first direction, the second sacrificial layers and the second isolation layers alternating with each other along the second direction; etching at least a portion of the second stack to form a second stepped structure; as well as A contact structure is formed extending along the second direction through at least one of the first stepped structure or the second stepped structure.

12. The method according to claim 11, wherein The first stepped structure is adjacent to the second stepped structure in the first direction or has a gap therebetween.

13. The method according to claim 11 or 12, wherein: The first stepped structure comprises stepped steps, and wherein the method comprises: A protective layer is deposited on top surfaces of the stair steps.

14. The method according to any one of claims 11 to 13, wherein: The first stack includes a first array region and a first connection region, wherein the first connection region includes the first stepped structure and is adjacent to the first array region along the first direction, and wherein the method includes: (i) forming a first gate line hole in the first array region and the first connection region, (ii) forming a first channel hole in the first array region and the first connection region, and (iii) forming a first contact hole in the first connection region, wherein the first gate line hole, the first channel hole, and the first contact hole extend through the first stack along the second direction, and wherein the first gate line hole, the first channel hole, and the first contact hole are formed during the same first etching process.

15. The method according to any one of claims 11 to 14, wherein: The second stack includes a second array region and a second connection region, wherein the second connection region includes the second stepped structure and is adjacent to the second array region along the first direction, and wherein the method includes: after providing the second stack, (i) forming a second gate line hole in the second array region and the second connection region, (ii) forming a second channel hole in the second array region and the second connection region, and (iii) forming a second contact hole in the second connection region, wherein the second gate line hole, the second channel hole, and the second contact hole extend through the second stack along the second direction, and wherein the second gate line hole, the second channel hole, and the second contact hole are formed during the same second etching process.

16. The method according to claim 15, comprising: After forming the second gate line hole, the second channel hole and the second contact hole, removing sacrificial material from the first sacrificial layer and the second sacrificial layer; as well as Conductive material is deposited in the first sacrificial layer and the second sacrificial layer to form a first conductive layer and a second conductive layer, respectively.

17. The method according to claim 16, wherein Forming the contact structure extending through at least one of the first stepped structure or the second stepped structure includes: A first contact structure and a second contact structure are formed, wherein the first contact structure extends through the first stepped structure and does not extend through the second stepped structure, and wherein the second contact structure extends through the second stepped structure and does not extend through the first stepped structure.

18. The method according to claim 17, wherein: The first contact structure extends through the second conductive layer and the second isolation layer, and the second contact structure extends through the first conductive layer and the first isolation layer; or The first contact structure extends through an insulating structure included in the second layer stack, and the second contact structure extends through the first conductive layer and the first isolation layer.

19. The method according to any one of claims 11 to 18, wherein: Etching at least a portion of the first stack to form the first stepped structure includes: etching a first portion of the first stack to form the first stepped structure while a second portion of the first stack remains unetched, wherein the second portion of the first stack is adjacent to the first portion of the first stack along a third direction perpendicular to the first direction and the second direction, and wherein the second portion of the first stack includes a portion of a first stack of the first sacrificial layer and the first isolation layer; removing sacrificial material from the sacrificial layer of the second portion of the first stack; and At least one electrically conductive material is deposited in the second portion of the first stack to form a wall region.

20. A system comprising: A semiconductor device comprising: a first stack comprising a first stepped structure, wherein the first stepped structure has a first start point and a first end point in a first direction, and wherein the first start point and the first end point define a first interval; and a second stack adjacent to the first stack along a second direction perpendicular to the first direction, wherein the second stack includes a second stepped structure having a second start point and a second end point in the first direction, the second start point and the second end point defining a second interval, and wherein the first interval is adjacent to the second interval or has a gap therebetween; and A memory controller is electrically connected to the semiconductor device, wherein the memory controller is configured to control the semiconductor device.

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