Semiconductor device and preparation method thereof
By introducing sub-dielectric layers with different density and adjusting the position of the extension portions into the three-dimensional stacking structure, the problem of shorting of adjacent conductive columns is solved, and the performance and stability of semiconductor devices are improved.
Patent Information
- Application Number
- CN202510570069.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-08-05
AI Technical Summary
In a three-dimensional stacking structure, the short-circuit problem between adjacent conductive columns due to different etching rates of the dielectric layer, affecting the performance and stability of the memory.
By introducing subdimedia layers of different density into the stacking structure and providing extensions between adjacent conductive posts, the position of the extensions in the horizontal and vertical directions is adjusted to avoid shorting.
It effectively avoids shorting between adjacent conductive columns and improves the efficiency and reliability of semiconductor devices.
Smart Images
Figure CN120435003A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure device and a preparation method thereof. Background Art
[0002] Memory plays an indispensable and important role in modern electronic products. In addition to storing user data, memory is also responsible for storing program code executed by the central processing unit and information that needs to be temporarily saved during calculations. Memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory). Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). The data in these volatile memories disappears after power is removed and must be re-entered when power is next supplied. Non-volatile memory includes read-only memory (ROM) and flash memory. The data stored in these memories persists even after power is removed, so the previously stored valid data can be directly read after power is restored.
[0003] Advances in semiconductor manufacturing have shifted from planar structures to three-dimensional (3D) stacking to achieve higher cell density per unit wafer area and meet the demand for higher storage capacity. The conductive pillars of memory devices are formed in a stack of alternating dielectric and conductive layers. However, the etching characteristics of the dielectric layer can cause short circuits between adjacent conductive pillars, affecting the performance and stability of the memory. Summary of the Invention
[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem of short circuit between adjacent conductive pillars caused by different etching rates of different dielectric layers in a stacked structure.
[0005] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device, comprising: a substrate;
[0006] A stacked structure, located on the substrate, comprising a plurality of first dielectric layers and a plurality of conductive layers stacked alternately;
[0007] A plurality of conductive pillars are arranged in the stack structure and spaced apart from each other along a horizontal direction;
[0008] A plurality of extensions are located in the stacked structure, the extensions comprising:
[0009] a first extension portion, located in the first dielectric layer;
[0010] a second extension portion, located between the conductive layer and the first extension portion;
[0011] Wherein, a side surface of the first extension portion and a side surface of the second extension portion are not aligned.
[0012] Optionally, the first extension portion and the second extension portion may be spaced apart from or in contact with each other in a vertical direction.
[0013] Optionally, the conductive layer may include:
[0014] a first conductive layer, located between adjacent first dielectric layers;
[0015] The second conductive layer is located between the first dielectric layer and the substrate.
[0016] Optionally, the first dielectric layer may include:
[0017] a first sub-dielectric layer, located on the second conductive layer;
[0018] The second sub-dielectric layer is located on the first sub-dielectric layer, and the density of the first sub-dielectric layer is smaller than the density of the second sub-dielectric layer.
[0019] Optionally, the first sub-dielectric layer and the second sub-dielectric layer may be made of the same material.
[0020] Optionally, the top of the first extension portion may be higher than the top surface of the first sub-dielectric layer.
[0021] Optionally, the top of the second extension portion may be higher than the bottom surface of the first conductive layer adjacent thereto.
[0022] Optionally, the extension distances of the multiple extension portions in the horizontal direction into the first dielectric layer may be different.
[0023] Optionally, an extension distance of the first extension portion extending into the first dielectric layer in the horizontal direction may be greater than an extension distance of the second extension portion extending into the first dielectric layer in the horizontal direction.
[0024] Optionally, the extension portion and the conductive layer may be made of the same material.
[0025] In order to solve the above technical problems, an embodiment of the present invention also provides a semiconductor device, comprising: a substrate;
[0026] A stacked structure, located on a substrate, comprising a plurality of first dielectric layers and a plurality of conductive layers stacked alternately;
[0027] A plurality of conductive pillars are arranged in the stack structure and spaced apart from each other along a horizontal direction;
[0028] A plurality of extensions are located in the stacked structure, wherein the extensions include:
[0029] a first extension portion, located in the first dielectric layer and having a first maximum extension distance in the horizontal direction;
[0030] a second extension portion, located between the conductive layer and the first extension portion and having a second maximum extension distance in a horizontal direction;
[0031] The first maximum extension distance is different from the second maximum extension distance.
[0032] Optionally, the first maximum extension distance may be greater than the second maximum extension distance.
[0033] Optionally, the first extension portion and the second extension portion may be spaced apart from or in contact with each other in a vertical direction.
[0034] In order to solve the above technical problems, an embodiment of the present invention provides a method for preparing a semiconductor device, comprising:
[0035] providing a substrate;
[0036] forming a stacked structure located on the substrate, the stacked structure comprising a plurality of first dielectric layers and a plurality of conductive layers stacked alternately;
[0037] forming a plurality of conductive pillars, which are arranged in the stack structure in a horizontally spaced manner;
[0038] A plurality of extensions are formed and located in the stacked structure, wherein the extensions include:
[0039] a first extension portion, located in the first dielectric layer;
[0040] a second extension portion, located between the conductive layer and the first extension portion;
[0041] Wherein, a side surface of the first extension portion and a side surface of the second extension portion are not aligned.
[0042] Optionally, the step of forming the plurality of conductive pillars may include:
[0043] Etching the stack structure to form a plurality of grooves with bottoms exposed from the substrate and spaced apart from each other along the horizontal direction, and a plurality of depressions extending within the stack structure along the horizontal direction;
[0044] forming a dielectric layer on sidewalls and portions of bottoms of the plurality of recesses;
[0045] forming a barrier layer on the dielectric layer;
[0046] A conductive column is formed on the barrier layer, the conductive column fills the groove and the depression, passes through the groove and directly contacts the substrate, and the conductive column filled in the depression serves as the extension.
[0047] Optionally, the conductive layer may include:
[0048] a first conductive layer, located between adjacent first dielectric layers;
[0049] The second conductive layer is located between the first dielectric layer and the substrate.
[0050] Optionally, the first dielectric layer may include:
[0051] a first sub-dielectric layer, located on the second conductive layer;
[0052] The second sub-dielectric layer is located on the first sub-dielectric layer, and the density of the first sub-dielectric layer is smaller than the density of the second sub-dielectric layer.
[0053] Optionally, the top of the first extension portion may be higher than the top surface of the first sub-dielectric layer.
[0054] Optionally, the top of the second extension portion may be higher than the bottom surface of the first conductive layer adjacent thereto.
[0055] Optionally, the first extension portion and the second extension portion may be spaced apart from or in contact with each other in a vertical direction.
[0056] As described above, the present invention provides a semiconductor device and a method for manufacturing the same, which may specifically include a stacked structure located on a substrate, a plurality of conductive pillars formed in the stacked structure, and a plurality of extensions; wherein the stacked structure includes a plurality of first dielectric layers and a plurality of conductive layers stacked alternately, and the first dielectric layer closest to the substrate may include at least two sub-dielectric layers with different densities, such as a first sub-dielectric layer and a second sub-dielectric layer stacked from bottom to top; the plurality of extensions are arranged in the first dielectric layer between adjacent conductive pillars, such as in the first dielectric layer closest to the substrate, so that the position of the extensions can be shifted between and / or within the plurality of sub-dielectric layers in the first dielectric layer closest to the substrate, thereby avoiding short circuits between adjacent conductive pillars and improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0057] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the present application but do not constitute a limitation of the present application. In the accompanying drawings:
[0058] Figures 1 to 8 Schematic diagram of the structure of the semiconductor device provided in the embodiment of the present invention during the preparation process; wherein,
[0059] Figure 3 A schematic diagram of a partial structure of a semiconductor device provided in a first embodiment of the present invention;
[0060] Figure 4 for Figure 3 An enlarged schematic diagram of a local structure A of the semiconductor device shown;
[0061] Figure 5 A schematic diagram of a partial structure of a semiconductor device provided in a second embodiment of the present invention;
[0062] Figure 6 for Figure 5 An enlarged schematic diagram of a local structure A of the semiconductor device shown;
[0063] Figure 7 A schematic diagram of a partial structure of a semiconductor device provided in a third embodiment of the present invention;
[0064] Figure 8 for Figure 7 An enlarged schematic diagram of a local structure A of the semiconductor device is shown.
[0065] Wherein, the accompanying drawings are marked as follows:
[0066] 100-substrate, 110-second dielectric layer, 120-drain structure, 121-drain barrier layer, 122-drain metal layer, 251-stacked structure, 130 / 130'-first dielectric layer, 131 / 131'-first sub-dielectric layer, 132 / 132'-second sub-dielectric layer, 140-conductive layer, 141-first conductive layer, 142-second conductive layer, 151-dielectric layer, 152-barrier layer, 160-conductive pillar, 170-extension portion, 171-first extension portion, 172-second extension portion, 101-groove, 102-recess, D1-extension distance of the second extension portion in the horizontal direction (second maximum extension distance), D2-extension distance of the first extension portion in the horizontal direction (first maximum extension distance). DETAILED DESCRIPTION
[0067] In order to make the technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present invention, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0068] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. It is understood that the meanings of "on...", "above..." and "above..." in the present invention should be interpreted in the broadest way, so that "on..." not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers. In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be arbitrarily combined without conflict.
[0069] Please refer to Figure 3 and Figure 4 , Figure 3 FIG1 is a cross-sectional view of a local structure of a semiconductor device in a first embodiment of the present invention. Figure 4 for Figure 3 FIG. 1 is an enlarged schematic diagram of a local structure A of a semiconductor device. Figure 3 and Figure 4As shown, the semiconductor device in the first embodiment of the present invention includes a substrate 100 , a stacked structure 251 , a plurality of conductive pillars 160 , and a plurality of extensions 170 . In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate composed of other suitable materials, but not limited thereto; a second dielectric layer 110 is provided on the substrate 100, and the second dielectric layer 110 has at least one drain structure 120, and the drain structure 120 has a drain barrier layer 121 and a drain metal layer 122 stacked in sequence from bottom to top; the second dielectric layer 110 includes a dielectric material, and suitable dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on silica glass (spin-on glass), porous low-k dielectric materials (porous low-k dielectrics) The drain barrier layer 121 comprises a metal barrier material, such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable metal barrier materials, and the drain metal layer 122 comprises a metal material, such as copper, aluminum, tungsten, or other suitable low-resistance metal materials, but is not limited thereto. Exemplarily, the material of the second dielectric layer 110 is silicon oxide (SiO2), the material of the drain barrier layer 121 is titanium nitride, and the material of the drain metal layer 122 is tungsten. Furthermore, those skilled in the art will readily appreciate that various required active and / or passive components (not shown) may be further formed on or within the substrate 100 according to the actual requirements of the three-dimensional transistor device, such as conductive structures or conductive plugs for electrically connecting different components, source structures, gate structures, etc., but are not limited thereto.
[0070] The stacked structure 251 is located on the second dielectric layer 110 and includes a plurality of first dielectric layers 130 and a plurality of conductive layers 140 alternately stacked in a vertical direction (a direction perpendicular to the surface of the substrate 100). Each conductive layer 140 and the first dielectric layer 130 thereon together form a set of conductive-dielectric layer pairs. The specific number of conductive-dielectric layer pairs can be adjusted according to actual needs and is not limited to 1. Figure 3 or Figure 4The figures are limited to the figures shown. Specifically, the conductive layer 140 can be further divided into a first conductive layer 141 and a second conductive layer 142. Thus, the stacked structure 251 can be composed of multiple first dielectric layers 130, multiple first conductive layers 141, and at least one second conductive layer 142. In one embodiment, the second conductive layer 142 overlies the second dielectric layer 110, or can be understood as being located between the first dielectric layer 130 and the second dielectric layer 110, and the first conductive layer 141 is located between adjacent first dielectric layers 130, but this is not limiting. Furthermore, the first dielectric layer 130 at the bottom of the stacked structure 251 and adjacent to the second conductive layer 142 can include multiple sub-dielectric layers of varying densities, such as a first sub-dielectric layer 131 and a second sub-dielectric layer 132 stacked sequentially from bottom to top, and the vertical thickness of the first sub-dielectric layer 131 can be the same as the vertical thickness of the second sub-dielectric layer 132. Exemplarily, the material of the conductive layer 140 (including the first conductive layer 141 and the second conductive layer 142) can be, for example, aluminum, titanium, tantalum, tungsten, copper, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten, titanium nitride, polycrystalline silicon, doped silicon, metal oxide, metal silicide and other metal or non-metallic conductive materials or any combination thereof. The first conductive layer 141 preferably includes tungsten, and the second conductive layer 142 preferably includes metal oxide; and the material of the first dielectric layer 130 can be, for example, silicon oxide, silicon nitride, silicon oxynitride and other dielectric materials or any combination thereof, preferably including silicon oxide, but not limited to this.
[0071] It should be noted that the first sub-dielectric layer 131 and the second sub-dielectric layer 132 in the first dielectric layer 130 located on the second conductive layer 142 can be made of the same dielectric material but with different densities, such as silicon oxide with different densities. Furthermore, the density of the first sub-dielectric layer 131 can be lower than that of the second sub-dielectric layer 132. Under this configuration, during the subsequent etching process to remove a portion of the stacked structure 251 to form a plurality of recesses 101 arranged horizontally (parallel to the surface of the substrate 100), the etching rate of the first sub-dielectric layer 131 with a lower density is higher than the etching rate of the second sub-dielectric layer 132 with a higher density. Consequently, the extension portion 170 located between adjacent conductive pillars 160 is shifted to between and / or within the plurality of sub-dielectric layers of different densities within the first dielectric layer 130 (i.e., including the first sub-dielectric layer 131 and the second sub-dielectric layer 132) closest to the substrate 100. Furthermore, the different etching rates of the different sub-dielectric layers can reduce the horizontal extension distance of the extension portion, thereby preventing short circuits between adjacent conductive pillars 160.
[0072] Furthermore, the plurality of conductive pillars 160 are arranged in the stack structure 251 in a horizontally spaced manner, and each of the conductive pillars 160 penetrates the plurality of first dielectric layers 130 and the plurality of conductive layers 140. Figure 2 As shown, the stacked structure 251 has a plurality of grooves 101 therein. Each groove 101 penetrates through the plurality of first dielectric layers 130 and the plurality of conductive layers 140 in the stacked structure 251, exposing the top of the drain structure 120 in the second dielectric layer 110. The conductive pillars 160 are located within the grooves 101. In one embodiment, a dielectric layer 151 and a barrier layer 152 stacked in sequence are further disposed on the sidewalls of each groove 101 where the conductive pillars 160 are formed. The dielectric layer 151 covers the sidewalls of the groove 101, and the barrier layer 152 covers the dielectric layer 151 and the top of the drain structure 120 exposed at the bottom of the groove 101. Exemplarily, the dielectric layer 151 has an L-shaped cross-sectional structure. The barrier layer 152 conformally covers the recess 101 formed with the dielectric layer 151 but does not fill the recess 101. The conductive pillar 160 covers the barrier layer 152 and fills the remaining space of the recess 101. The material of the dielectric layer 151 can be a high-dielectric constant dielectric material, such as at least one of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), and titanium oxide (TiO2). The material of the barrier layer 152 can include, but is not limited to, titanium, tantalum, titanium nitride, or tantalum nitride.
[0073] Furthermore, at least one extension portion 170 may be further provided in the stacking structure 251 between adjacent conductive pillars 160, and each extension portion 170 is connected to an adjacent conductive pillar 160 at one and only one end in the horizontal direction, for example Figure 3The illustrated extension portion 170 is connected to the left and / or right conductive pillars 160. The extension portion 170 can be divided into a first extension portion 171 and a second extension portion 172 located thereon, based on its vertical position and / or horizontal extension distance into the first dielectric layer 130. Thus, in the first embodiment of the present invention, the first extension portion 171 is located below the second extension portion 172, and the horizontal extension distance (also referred to as a first maximum extension distance D2) of the first extension portion 171 into the first dielectric layer 130 can be different from the horizontal extension distance (also referred to as a second maximum extension distance D1) of the second extension portion 172 into the first dielectric layer 130. For example, the first maximum extension distance D2 is greater than the second maximum extension distance D1 (D2>D1), so that the side surfaces of the first extension portion 171 and the side surfaces of the second extension portion 172 are misaligned. In one embodiment of the present invention, the first extension portion 171 is specifically located in the first dielectric layer 130 including the first sub-dielectric layer 131 and the second sub-dielectric layer 132, and its top is higher than the top surface of the first sub-dielectric layer 131; the second extension portion 172 does not contact the first extension portion 171 in the vertical direction, that is, they are separated from each other. Thus, the second extension portion 172 is specifically located between the conductive layer 140 and the first extension portion 171, and its top is higher than the conductive layer 140 adjacent to it (the first conductive layer 141 located on the second sub-dielectric layer 132, as shown in FIG. Figure 3 In one embodiment, the material of the extension portion 170 may be the same as that of the conductive pillar 160, such as metal tungsten.
[0074] It should be noted that the stacked structure 251 in the embodiment of the present invention has a plurality of conductive pillars 160, so the number of extensions 170 provided in the first dielectric layer 130 between different adjacent conductive pillars 160 may be the same or different. Figure 3 The first dielectric layer 130 located to the right of the rightmost conductive pillar 160 shown may include two extension portions 170, namely the first extension portion 171 and the second extension portion 172. From left to right, only one extension portion 170, such as the first extension portion 171, is provided between the leftmost conductive pillar 160 and the adjacent conductive pillar 160. In other embodiments, only one second extension portion 172 may be provided between adjacent conductive pillars 160, but the present invention is not limited thereto.
[0075] It should be understood that the “common shape” in the embodiment of the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and correlations between two or more shapes.
[0076] Those skilled in the art will readily appreciate that, to meet actual product requirements, the semiconductor device of the present invention may have other configurations and is not limited to the aforementioned configuration. Other embodiments and variations of the semiconductor device of the present invention will be further described below. For simplicity, identical components in each embodiment of the present invention are designated with the same reference numerals to facilitate cross-reference between the various embodiments.
[0077] Please refer to Figure 5 and Figure 6 , Figure 5 The figure shows a partial cross-sectional view of the semiconductor device in the second embodiment of the present invention. Figure 6 for Figure 5 FIG. 1 is an enlarged schematic diagram of a local structure A of a semiconductor device. Figure 5 and Figure 6 As shown, the structure of the semiconductor device in the second embodiment of the present invention is substantially the same as that of the semiconductor device in the first embodiment. For example, the semiconductor device also includes a substrate 100, a stacked structure 251, a plurality of conductive pillars 160, and a plurality of extensions 170. The stacked structure 251 is composed of a plurality of first dielectric layers 130, a plurality of first conductive layers 141, and at least one second conductive layer 142. The first dielectric layer 130 located at the bottom of the stacked structure 251 and adjacent to the second conductive layer 142 may include a plurality of sub-dielectric layers of varying densities, such as a first sub-dielectric layer 131 and a second sub-dielectric layer 132 stacked sequentially from bottom to top. Details of the similarities are omitted here. For ease of distinction, in the second embodiment of the present invention, the first sub-dielectric layer and the second sub-dielectric layer in the first dielectric layer 130 located at the bottom of the stacked structure 251 and adjacent to the second conductive layer 142 are labeled "131'" and "132'," respectively. The main difference between the semiconductor device of the second embodiment of the present invention and the aforementioned first embodiment is that the first dielectric layer 130 located at the bottom of the stacked structure 251 and close to the second conductive layer 142 includes multiple sub-dielectric layers with different densities, and the thicknesses in the vertical direction may be different. For example, the first dielectric layer 130 located at the second conductive layer 142 may include a first sub-dielectric layer 131' and a second sub-dielectric layer 132'. The thickness of the first sub-dielectric layer 131' in the vertical direction may be greater than the thickness of the second sub-dielectric layer 132'. Figure 4 As shown, in other embodiments, the thickness of the first sub-dielectric layer 131 ′ in the vertical direction may be smaller than the thickness of the second sub-dielectric layer 132 ′.
[0078] Please refer to Figure 7 and Figure 8 , Figure 7 The figure shows a partial cross-sectional view of the semiconductor device in the third embodiment of the present invention. Figure 8 for Figure 7 FIG. 1 is an enlarged schematic diagram of a local structure A of a semiconductor device. Figure 7 and Figure 8 As shown, the structure of the semiconductor device in the third embodiment of the present invention is substantially the same as that of the semiconductor device in the first or second embodiment, for example, the semiconductor device also includes a substrate 100, a stacked structure 251, a plurality of conductive pillars 160, and a plurality of extensions 170. The stacked structure 251 may be composed of a plurality of first dielectric layers 130, a plurality of first conductive layers 141, and at least one second conductive layer 142. The first dielectric layer 130 located at the bottom of the stacked structure 251 and adjacent to the second conductive layer 142 may include a plurality of sub-dielectric layers with different densities, for example, a first sub-dielectric layer 131 (131') and a second sub-dielectric layer 132 (132') stacked sequentially from bottom to top. The thicknesses of the first sub-dielectric layer 131 (131') and the second sub-dielectric layer 132 (132') in the vertical direction may be the same or different, and the same parts are not repeated here. The main difference between the semiconductor device of the third embodiment of the present invention and the aforementioned first or second embodiment is that the first extension portion 171 located in the stack structure 251 between adjacent conductive pillars 160 and the second extension portion 172 located thereon are in contact in the vertical direction. Moreover, since the extension distance or the maximum extension distance of the mutually contacting first extension portion 171 and second extension portion 172 in the third embodiment of the present invention extending into the first dielectric layer 130 in the horizontal direction remains unchanged, the purpose of preventing short circuits between adjacent conductive pillars 160 can still be achieved.
[0079] In order to enable general technicians in the technical field to which the present invention belongs to easily understand the semiconductor devices in the first to third embodiments of the present invention, the present invention also provides a method for preparing the semiconductor device. The following will further illustrate the method for preparing the semiconductor device proposed in the present invention in combination with various structural schematic diagrams of the method for preparing the semiconductor device during the preparation process.
[0080] in, Figures 1 to 8 Schematic diagram of the structure of the semiconductor device manufacturing method provided in the first to third embodiments of the present invention during the manufacturing process.
[0081] See also Figure 1A substrate 100 (e.g., a silicon substrate) may be provided. A second dielectric layer 110 (e.g., a silicon oxide layer) may be formed on the surface of the substrate 100 using at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. A drain structure 120 spaced apart horizontally from one another may be formed within the second dielectric layer 110 using at least one of photolithography, etching processes (e.g., dry etching or wet etching processes), and at least one of the above-described deposition processes. The drain structure 120 may include a drain barrier layer 121 (e.g., a titanium nitride layer) and a drain metal layer 122 (e.g., a tungsten metal layer) stacked from bottom to top. A stacked structure 251 comprising a plurality of conductive-dielectric layer pairs may be formed on the second dielectric layer using the above-described deposition process, such as a chemical vapor deposition process. The conductive-dielectric layer pairs may include a conductive layer 140 (e.g., a tungsten metal layer) and a first dielectric layer 130 (e.g., a silicon oxide layer) located thereover. In this embodiment of the present invention, the multiple conductive layers 140 in the stacked structure 251 are further divided into a first conductive layer 141 and a second conductive layer 142, and the at least one first dielectric layer 130 is divided into a first sub-dielectric layer 131 and a second sub-dielectric layer 132. Specifically, the second conductive layer 142 is located on the second dielectric layer 110, the first sub-dielectric layer 131 is located on the second conductive layer 142, and the second sub-dielectric layer 132 is located on the first sub-dielectric layer 131. Multiple conductive-dielectric layer pairs consisting of the first conductive layer 141 and the first dielectric layer 130 located thereon are disposed on the second sub-dielectric layer 132, but the present invention is not limited thereto.
[0082] Exemplarily, after forming the second conductive layer 142, the process parameters for forming the first sub-dielectric layer 131 include: a deposition process with a temperature of approximately 400°C, a reaction pressure of the reaction chamber of approximately 6.5 tor, a microwave power of approximately 0.3 kW to 0.65 kW, and gas flow rates of reaction gases TEOS and O2 of approximately 6.3 g / min and 5000 sccm, respectively, and then a first dielectric layer 131 with a lower density is formed on the second conductive layer 142; the process parameters for forming the second sub-dielectric layer 132 include: a temperature of approximately 400°C, a reaction pressure of the reaction chamber of approximately 6.2 tor, a microwave power of approximately 0.2 kW to 0.42 kW, and gas flow rates of reaction gases TEOS and O2 of approximately 1.2 g / min and 7000 sccm, respectively, but are not limited to these.
[0083] See also Figure 2The stacked structure 251 and the second dielectric layer 110 thereunder may be etched vertically using an etching process, such as a wet etching process, to form a plurality of grooves 101 spaced apart in the horizontal direction, with their bottoms exposed from the substrate 100, and a plurality of recesses 102 extending horizontally within the stacked structure 251. Because the first dielectric layer 130 at the bottom of the stacked structure 251 includes a first sub-dielectric layer 131 and a second sub-dielectric layer 132, and the density of the first sub-dielectric layer 131 is lower than that of the second sub-dielectric layer 132, during the formation of the plurality of grooves 101, due to the different etching rates of materials with different densities, a plurality of recesses 102 may be formed in the stacked structure 251 between adjacent grooves 101. Furthermore, the number, position, and horizontal extension distance (or maximum extension distance) of the recesses 102 formed between different adjacent grooves 101 may be different.
[0084] See also Figures 3 to 8 Then, a deposition process such as a chemical vapor deposition process may be used to further form a dielectric layer 151 (made of, for example, hafnium oxide), a barrier layer 152 (made of, for example, titanium nitride), and a conductive pillar 160 (made of, for example, metal tungsten) in each of the grooves 101. In this process, the metal tungsten of the conductive pillar 160 is also simultaneously filled into the plurality of recesses 102 to serve as the extension portion 170, wherein the extension portion 170 may include a first extension portion 171 and a second extension portion 172. In one embodiment, the first extension portion 171 and the second extension portion 172 located between adjacent conductive pillars 160 may be spaced apart in the vertical direction, for example Figure 3 、 Figure 4 、 Figure 5 or Figure 6 As shown, in other embodiments, the first extension portion 171 and the second extension portion 172 located between adjacent conductive pillars 160 may contact each other in the vertical direction, for example Figure 7 or Figure 8 shown.
[0085] In summary, the semiconductor device and its manufacturing method provided by the present invention may specifically include a stacked structure located on a substrate, a plurality of conductive pillars formed in the stacked structure, and a plurality of extensions; wherein the stacked structure includes a plurality of first dielectric layers and a plurality of conductive layers stacked alternately, and the first dielectric layer closest to the substrate may include at least two sub-dielectric layers with different densities, such as a first sub-dielectric layer and a second sub-dielectric layer stacked from bottom to top; the plurality of extensions are arranged in the first dielectric layer between adjacent conductive pillars, such as in the first dielectric layer closest to the substrate. In this way, the position of the extensions located between adjacent conductive pillars can be transferred to between and / or within the plurality of sub-dielectric layers in the first dielectric layer closest to the substrate, thereby avoiding short circuits between adjacent conductive pillars and improving the performance and reliability of the semiconductor device.
[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.
Claims
1. A semiconductor device, characterized in that: include: substrate; A stacked structure, located on the substrate, comprising a plurality of first dielectric layers and a plurality of conductive layers stacked alternately; A plurality of conductive pillars are arranged in the stack structure and spaced apart from each other along a horizontal direction; A plurality of extensions are located in the stacked structure, the extensions comprising: a first extension portion, located in the first dielectric layer; a second extension portion, located between the conductive layer and the first extension portion; Wherein, a side surface of the first extension portion and a side surface of the second extension portion are not aligned.
2. The semiconductor device according to claim 1, wherein The first extension portion and the second extension portion are spaced apart from or in contact with each other in a vertical direction.
3. The semiconductor device according to claim 1, wherein The conductive layer comprises: a first conductive layer, located between adjacent first dielectric layers; The second conductive layer is located between the first dielectric layer and the substrate.
4. The semiconductor device according to claim 3, wherein The first dielectric layer includes: a first sub-dielectric layer, located on the second conductive layer; The second sub-dielectric layer is located on the first sub-dielectric layer, and the density of the first sub-dielectric layer is smaller than the density of the second sub-dielectric layer.
5. The semiconductor device according to claim 4, wherein The first sub-dielectric layer and the second sub-dielectric layer are made of the same material.
6. The semiconductor device according to claim 4, wherein The top of the first extension portion is higher than the top surface of the first sub-dielectric layer.
7. The semiconductor device according to claim 4, wherein The top of the second extension portion is higher than the bottom surface of the first conductive layer adjacent thereto.
8. The semiconductor device according to claim 1, wherein The multiple extension portions extend into the first dielectric layer by different distances in the horizontal direction.
9. The semiconductor device according to claim 8, wherein An extension distance of the first extension portion extending into the first dielectric layer in the horizontal direction is greater than an extension distance of the second extension portion extending into the first dielectric layer in the horizontal direction.
10. The semiconductor device according to claim 1, wherein The extending portion is made of the same material as the conductive layer.
11. A semiconductor device, characterized in that: include: substrate; A stacked structure, located on a substrate, comprising a plurality of first dielectric layers and a plurality of conductive layers stacked alternately; A plurality of conductive pillars are arranged in the stack structure and spaced apart from each other along a horizontal direction; A plurality of extensions are located in the stacked structure, wherein the extensions include: a first extension portion, located in the first dielectric layer and having a first maximum extension distance in the horizontal direction; a second extension portion, located between the conductive layer and the first extension portion and having a second maximum extension distance in a horizontal direction; The first maximum extension distance is different from the second maximum extension distance.
12. The semiconductor device according to claim 11, wherein The first maximum extension distance is greater than the second maximum extension distance.
13. The semiconductor device according to claim 12, wherein The first extension portion and the second extension portion are spaced apart from or in contact with each other in a vertical direction.
14. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a stacked structure located on the substrate, the stacked structure comprising a plurality of first dielectric layers and a plurality of conductive layers stacked alternately; forming a plurality of conductive pillars, which are arranged in the stack structure in a horizontally spaced manner; A plurality of extensions are formed and located in the stacked structure, wherein the extensions include: a first extension portion, located in the first dielectric layer; a second extension portion, located between the conductive layer and the first extension portion; Wherein, a side surface of the first extension portion and a side surface of the second extension portion are not aligned.
15. The method for manufacturing a semiconductor device according to claim 14, wherein the step of forming the plurality of conductive pillars comprises: Etching the stack structure to form a plurality of grooves with bottoms exposed from the substrate and spaced apart from each other along the horizontal direction, and a plurality of depressions extending within the stack structure along the horizontal direction; forming a dielectric layer on sidewalls and portions of bottoms of the plurality of recesses; forming a barrier layer on the dielectric layer; A conductive column is formed on the barrier layer, the conductive column fills the groove and the depression, passes through the groove and directly contacts the substrate, and the conductive column filled in the depression serves as the extension.
16. The method for manufacturing a semiconductor device according to claim 14, wherein the conductive layer comprises: a first conductive layer, located between adjacent first dielectric layers; The second conductive layer is located between the first dielectric layer and the substrate.
17. The method for manufacturing a semiconductor device according to claim 16, wherein the first dielectric layer comprises: a first sub-dielectric layer, located on the second conductive layer; The second sub-dielectric layer is located on the first sub-dielectric layer, and the density of the first sub-dielectric layer is smaller than the density of the second sub-dielectric layer. 18 . The method for manufacturing a semiconductor device according to claim 17 , wherein a top of the first extension portion is higher than a top surface of the first sub-dielectric layer. 19 . The method for manufacturing a semiconductor device according to claim 17 , wherein a top of the second extension portion is higher than a bottom surface of the first conductive layer adjacent thereto. 20 . The method for manufacturing a semiconductor device according to claim 14 , wherein the first extension portion and the second extension portion are spaced apart from or in contact with each other in a vertical direction.