Magnetic memory device

Abstract

Disclosed is a magnetic memory device including: a substrate; a conductive line on the substrate; a wiring dielectric layer covering the conductive line; a lower shield line in the wiring dielectric layer and extending in the first direction; a data storage pattern including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the lower shield line; and an upper shield line on the data storage pattern and extending in a second direction parallel to the top surface of the substrate. The second direction intersects the first direction. The lower shielded wire and the upper shielded wire include a magnetic material.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0016591, filed with the Korean Intellectual Property Office on February 2, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a magnetic memory device including a magnetic tunnel junction and a method of manufacturing the magnetic memory device. Background art

[0004] As electronic products tend to be high - speed and / or low - power consumption, there is an increasing need for high - speed and low operating voltage for semiconductor memory devices incorporated in electronic products. To meet the above requirements, magnetic memory devices have been developed as semiconductor memory devices. Since magnetic memory devices have a fast operation speed and non - volatile characteristics, magnetic memory devices have attracted wide attention as next - generation semiconductor memory devices.

[0005] Generally, a magnetic memory device may include a magnetic tunnel junction pattern. The magnetic tunnel junction pattern includes two magnetic structures and an insulating layer therebetween. The resistance of the magnetic tunnel junction pattern varies according to the magnetization directions of the two magnetic structures. For example, when the magnetization directions of the two magnetic structures are antiparallel, the magnetic tunnel junction pattern has a high resistance, and when the magnetization directions of the two magnetic structures are parallel, the magnetic tunnel junction pattern has a low resistance. The magnetic memory device can write and read data by using the resistance difference between the high resistance and the low resistance of the magnetic tunnel junction.

[0006] With the rapid development of the electronics industry, there are increasing requirements for high integration and / or low power consumption of magnetic memory devices. In addition, many studies have been conducted to improve the reliability of magnetic memory devices. Summary of the invention

[0007] Some embodiments of the present inventive concept provide a magnetic memory device having improved reliability and a method of manufacturing the magnetic memory device.

[0008] According to some embodiments of the present inventive concept, a magnetic memory device may include: a substrate; a conductive wire on the substrate; a wiring dielectric layer covering the conductive wire; a lower shield wire in the wiring dielectric layer, the lower shield wire extending in a first direction; a data storage pattern including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the lower shield wire; and an upper shield wire on the data storage pattern, the upper shield wire extending in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction. The lower shield wire and the upper shield wire may include a magnetic material.

[0009] According to some embodiments of the inventive concept, a magnetic storage device may include: a substrate; conductive lines on the substrate; a wiring dielectric layer covering the conductive lines; lower shield lines extending in a first direction in the wiring dielectric layer, and each of the lower shield lines being spaced apart from each other in a second direction, the first direction and the second direction intersecting each other and being parallel to the top surface of the substrate; data storage patterns on the lower shield lines, and each of the data storage patterns being spaced apart from each other in the first direction and the second direction; and upper shield lines extending in the second direction on the data storage patterns, and each of the upper shield lines being spaced apart from each other in the first direction. The lower shield lines and the upper shield lines include magnetic materials.

[0010] According to some embodiments of the inventive concept, a magnetic storage device may include: a substrate; conductive lines on the substrate; a wiring dielectric layer covering the conductive lines; lower shield lines extending in a first direction in the wiring dielectric layer, and each of the lower shield lines being spaced apart from each other in a second direction, the first direction and the second direction intersecting each other and being parallel to the top surface of the substrate; data storage patterns on the lower shield lines, and each of the data storage patterns being spaced apart from each other in the first direction and the second direction, and each of the data storage patterns including a bottom electrode, a first magnetic pattern, a tunnel barrier pattern, a second magnetic pattern, and a top electrode stacked in sequence; and upper shield lines extending in the second direction on the data storage patterns, and each of the upper shield lines being spaced apart from each other in the first direction. The bottom surface of each of the bottom electrodes may contact the top surface of the corresponding lower shield line in the lower shield lines. The top surface of each of the top electrodes contacts the bottom surface of the corresponding upper shield line in the upper shield lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A circuit diagram of a unit storage cell of a magnetic storage device according to some embodiments of the inventive concept is shown.

[0012] Figure 2 A plan view of a magnetic storage device according to some embodiments of the inventive concept is shown.

[0013] Figure 3A , Figure 4A , Figure 5A and Figure 6A A cross-sectional view taken along line A-A' of Figure 2 is shown.

[0014] Figure 3B , Figure 4B , Figure 5B and Figure 6B A cross-sectional view taken along line B-B' of Figure 2 is shown.

[0015] Figure 7A cross-sectional view showing an example of a magnetic tunnel junction pattern in a magnetic storage device according to some embodiments of the inventive concept.

[0016] Figure 8A and Figure 8B respectively show cross-sectional views taken along line A-A' and line B-B' of Figure 2 showing a method of manufacturing a magnetic storage device according to some embodiments of the inventive concept.

[0017] Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 show cross-sectional views taken along line A-A' of Figure 2 showing a method of manufacturing a magnetic storage device according to some embodiments of the inventive concept.

[0018] Figure 15A and Figure 15B show cross-sectional views taken along line A-A' and B-B' of Figure 2 showing a method of manufacturing a Figure 3A and Figure 3B magnetic storage device. Detailed Description

[0019] Some embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings. However, the inventive concept can be embodied in many different forms and should not be construed as being limited by the exemplary embodiments set forth herein. It should also be emphasized that the present disclosure provides details of alternative examples, but such a listing of alternatives is not exhaustive. In addition, any detail consistency between the various examples should not be construed as requiring such details.

[0020] It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, the element can be directly connected or coupled to the other element or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or "contacting" another element or "in contact with" another element (or any form of the word "contact" is used), there are no intervening elements at the point of contact.

[0021] Terms such as "identical", "equal", "flat", "coplanar", "parallel", and "perpendicular" used herein encompass identical or approximately identical, including variations that may occur due to conventional manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" can be used herein to emphasize this meaning.

[0022] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. Additionally, a term referred to by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim).

[0023] Articles described herein in the singular may be provided in the plural, as can be seen, for example, in the drawings. Thus, a description of a single article provided in the plural should be understood to apply to the remaining plural articles unless the context indicates otherwise.

[0024] Throughout the specification, when a component is described as "including" a particular element or set of elements, it should be understood that the component is formed only by that element or set of elements, or that the element or set of elements may be combined with additional elements to form the component, unless the context clearly and / or expressly describes the contrary. On the other hand, the term "consisting of" indicates that the component is formed only by the listed elements.

[0025] Figure 1 A circuit diagram of a unit storage cell of a magnetic storage device according to some embodiments of the inventive concept is shown.

[0026] Referring to Figure 1 , the unit storage cell MC may include a storage element ME and a selection element SE. The storage element ME and the selection element SE may be electrically connected in series with each other.

[0027] The storage element ME may be connected between the selection element SE and the bit line BL. The selection element SE may be connected between the storage element ME and the source line SL and may be controlled by the word line WL. The selection element SE may include, for example, a bipolar transistor or a metal oxide semiconductor (MOS) field effect transistor.

[0028] The storage element ME may include a magnetic tunnel junction pattern MTJ, and the magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. One of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be a reference magnetic pattern whose magnetization direction is fixed in one direction regardless of an external magnetic field in a normal use environment. The other of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be a free magnetic pattern whose magnetization direction changes between two stable magnetization directions due to an external magnetic field. The magnetic tunnel junction pattern MTJ may have a resistance whose value is much larger when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are antiparallel to each other than when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are parallel to each other. For example, the resistance of the magnetic tunnel junction pattern MTJ may be controlled by changing the magnetization direction of the free magnetic pattern. The storage element ME may utilize the difference in resistance depending on the magnetization directions of the reference magnetic pattern and the free magnetic pattern, and this mechanism may enable data to be stored in the unit storage cell MC.

[0029] Figure 2 A plan view of a magnetic storage device according to some embodiments of the present inventive concept is shown. Figure 3A Shown is along Figure 2 a cross-sectional view taken along line A-A'. Figure 3B Shown is along Figure 2 a cross-sectional view taken along line B-B'. Figure 7 A cross-sectional view showing an example of a magnetic tunnel junction pattern in a magnetic storage device according to some embodiments of the present inventive concept is shown.

[0030] Referring to Figure 2 , Figure 3A and Figure 3B , a conductive line 101 may be disposed on a substrate 100, and a wiring dielectric layer 110 may be disposed to cover the conductive line 101. The substrate 100 may be a semiconductor substrate including silicon, silicon-on-insulator (SOI), silicon-germanium (SiGe), germanium (Ge), or gallium arsenide (GaAs). The wiring dielectric layer 110 may include one or more of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0031] Although not shown, a select element (see SE of Figure 1 ) may be disposed in the substrate 100. The select element may include, for example, a field effect transistor. The conductive line 101 may be electrically connected to one end (e.g., a source / drain terminal) of the select element. The conductive line 101 may include a metal (e.g., copper).

[0032] The lower shielding line 105 may be disposed on the wiring dielectric layer 110. The lower shielding line 105 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2. In the present specification, the first direction D1 and the second direction D2 may be directions parallel to the top surface 100a of the substrate 100 and intersecting each other. A third direction D3 may be perpendicular to the top surface 100a of the substrate 100. In some examples, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0033] According to an embodiment of the inventive concept, the lower shielding line 105 may be electrically connected to the conductive line 101 through a contact portion (not shown) in the wiring dielectric layer 110. For example, the lower shielding line 105 may be used as a lower wiring.

[0034] The top surface of the lower shielding line 105 may be exposed from the wiring dielectric layer 110. The top surface of the wiring dielectric layer 110 may be substantially coplanar with the top surface of the lower shielding line 105.

[0035] The data storage pattern DS may be disposed on the lower shielding line 105. The data storage patterns DS may be spaced apart from each other in the first direction D1 and the second direction D2. Each data storage pattern DS may have a bottom surface contacting the top surface of a corresponding one of the lower shielding lines in the lower shielding line 105. Each data storage pattern DS may be electrically connected to a terminal (e.g., a drain terminal) of a corresponding selection element through the corresponding lower shielding line 105 and the corresponding conductive line 101. The lower shielding lines 105 may each include a magnetic material. The magnetic material may be, for example, at least one magnetic material selected from cobalt (Co), iron (Fe), and nickel (Ni). According to some embodiments, the lower shielding line 105 may include a soft magnetic material.

[0036] Each data storage pattern DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the corresponding lower shielding line 105. The magnetic tunnel junction pattern MTJ may be interposed between the bottom electrode BE and the top electrode TE. The bottom surface of each bottom electrode BE may contact the top surface of the corresponding lower shielding line in the lower shielding line 105. The bottom electrode BE may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The top electrode TE may include at least one material selected from a metal (e.g., Ta, W, Ru, or Ir) or a conductive metal nitride (e.g., TiN).

[0037] The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP. The bottom electrode BE may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The top electrode TE may include at least one material selected from a metal (e.g., Ta, W, Ru, or Ir) or a conductive metal nitride (e.g., TiN).

[0038] Referring Figure 7 , the first magnetic pattern MP1 may be a reference layer whose magnetization direction MD1 is fixed in one direction, and the second magnetic pattern MP2 may be a free layer whose magnetization direction MD2 varies parallel or antiparallel to the magnetization direction MD1 of the first magnetic pattern MP1. Figure 7 The second magnetic pattern MP2 is disclosed as being a free layer, but the inventive concept is not limited thereto. Different from Figure 7 that shown, the first magnetic pattern MP1 may be a free layer, and the second magnetic pattern MP2 may be a reference layer.

[0039] For example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 can be perpendicular to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 can include at least one of an intrinsic perpendicular magnetic material or a non-intrinsic perpendicular magnetic material. The intrinsic perpendicular magnetic material can include a material that has perpendicular magnetization characteristics even without external factors. The intrinsic perpendicular magnetic material can include at least one material selected from perpendicular magnetic materials (e.g., CoFeTb, CoFeGd, or CoFeDy), perpendicular magnetic materials having an L10 magnetic structure, CoPt having a hexagonal close-packed lattice structure, or a perpendicular magnetic structure. The perpendicular magnetic material having an L10 magnetic structure can include at least one of FePt with an L10 magnetic structure, FePd with an L10 magnetic structure, CoPd with an L10 magnetic structure, or CoPt with an L10 magnetic structure. The perpendicular magnetic structure can include magnetic layers and non-magnetic layers stacked alternately and repeatedly. For example, the perpendicular magnetic structure can include at least one of (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, or (CoCr / Pd)n (where n is the number of stacked layers). The non-intrinsic perpendicular magnetic material can include a material having inherent horizontal magnetization characteristics or perpendicular magnetization characteristics caused by external factors. For example, the non-intrinsic perpendicular magnetic material can have perpendicular magnetization characteristics due to magnetic anisotropy caused by the junction between the tunnel barrier pattern TBP and the first magnetic pattern MP1 (or the second magnetic pattern MP2). The non-intrinsic perpendicular magnetic material can include, for example, CoFeB.

[0040] The tunnel barrier pattern TBP can include at least one layer selected from a magnesium oxide (Mg) layer, a titanium oxide (Ti) layer, an aluminum oxide (Al) layer, a magnesium zinc oxide (MgZn) layer, and a magnesium boride (MgB) layer.

[0041] Referring again to Figure 2 、 Figure 3A and Figure 3B ,the capping dielectric layer can conformally cover the side surfaces of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE. When observed in a plan view, the capping dielectric layer can surround the side surfaces of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE. The capping dielectric layer can include a nitride (e.g., silicon nitride).

[0042] The cell dielectric layer 170 may be disposed on the wiring dielectric layer 110 to cover the data storage pattern DS. The cell dielectric layer 170 may fill the space between the data storage patterns DS. The capping dielectric layer 165 may be interposed between the cell dielectric layer 170 and the side surfaces of each data storage pattern DS and may extend between the wiring dielectric layer 110 and the cell dielectric layer 170. The cell dielectric layer 170 may include, for example, one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0043] The upper shield line 215 may be disposed on the data storage pattern DS. The upper shield line 215 may extend along the second direction D2 and may be spaced apart from each other in the first direction D1. The top surface of each data storage pattern DS may contact the bottom surface of the corresponding upper shield line in the upper shield lines 215. For example, the top surface of each top electrode TE may contact the bottom surface of a corresponding one of the upper shield lines 215. The upper shield line 215 may include a magnetic material. The magnetic material may include, for example, at least one material selected from cobalt (Co), iron (Fe), or nickel (Ni). According to some embodiments, the upper shield line 215 may include a soft magnetic material.

[0044] When observed in a plan view, the lower shield line 105 may intersect the upper shield line 215. The data storage pattern DS may be disposed at the intersection where the lower shield line 105 and the upper shield line 215 vertically overlap.

[0045] Since magnetic storage devices are characterized by storing data based on the magnetization direction, magnetic storage devices may be affected by an external magnetic field. A magnetic storage device employing perpendicular magnetization may have a problem of reduced reliability when there is a horizontal magnetic component in an external magnetic field.

[0046] According to the present inventive concept, the lower shield line 105 and the upper shield line 215 may reduce the magnetic flux of the horizontal component of the external magnetic field. Accordingly, the magnetic flux of the horizontal component passing through the data storage pattern DS may be minimized, thereby providing a magnetic storage device having improved electrical characteristics and increased reliability. In addition, when the lower shield line 105 and the upper shield line 215 are close to the magnetic tunnel junction pattern MTJ, the influence of the external magnetic field on the magnetic tunnel junction pattern MTJ may be successfully reduced. According to Figure 3A and Figure 3B embodiments, the lower shield line 105 and the upper shield line 215 may contact the bottom electrode BE and the top electrode TE, respectively. Accordingly, the lower shield line 105 and the upper shield line 215 may be disposed near the magnetic tunnel junction pattern MTJ, which may minimize the influence of the external magnetic field on the magnetic tunnel junction pattern MTJ. In addition, in this case, the lower shield line 105 and the upper shield line 215 may share the function of electrical wiring and may simplify the method of manufacturing a magnetic storage device.

[0047] Figure 4A shows a cross-sectional view taken along line A-A' of Figure 2 . Figure 4B shows a cross-sectional view taken along line B-B' of Figure 2 . For simplicity of description, repeated explanations of elements described previously may be omitted.

[0048] Referring to Figure 2 , Figure 4A and Figure 4B , the first lower dielectric layer 120 and the second lower dielectric layer 130 may be sequentially disposed on the wiring dielectric layer 110. The first lower dielectric layer 120 may cover the exposed top surface of the lower shield line 105. The first lower dielectric layer 120 and the second lower dielectric layer 130 may include, for example, one or more of silicon oxide, silicon nitride, or silicon oxynitride. According to some embodiments, the second lower dielectric layer 130 may include a material different from the first lower dielectric layer 120. For example, the first lower dielectric layer 120 may include silicon nitride (e.g., SiCN), and the second lower dielectric layer 130 may include silicon oxide (e.g., tetraethyl orthosilicate (TEOS)).

[0049] The data storage pattern DS may be disposed on the second lower dielectric layer 130. The data storage patterns DS may be spaced apart from each other in a first direction D1 and a second direction D2.

[0050] The second lower dielectric layer 130 may have a top surface 130RU that is recessed toward the substrate 100 between the data storage patterns DS. The recessed top surface 130RU of the second lower dielectric layer 130 may be located at a height lower than the uppermost surface 130U1 of the second lower dielectric layer 130. In this specification, the term "height" may indicate a distance measured in a third direction D3.

[0051] The lower electrode contact portion 140 may be disposed in the first lower dielectric layer 120 and the second lower dielectric layer 130. The lower electrode contact portion 140 may be correspondingly disposed below the data storage pattern DS and electrically connected to the data storage pattern DS. The lower electrode contact portion 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130. Each lower electrode contact portion 140 may be connected to a corresponding lower shield line 105. Each data storage pattern DS may be electrically connected to one end (e.g., the drain terminal) of a corresponding selection element through a corresponding lower electrode contact portion 140 and a corresponding lower shield line 105.

[0052] The lower electrode contact portion 140 may include at least one material selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, titanium, or tantalum), metal semiconductor compounds (e.g., metal silicides), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, or tungsten nitride).

[0053] Each data storage pattern DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked in a third direction D3 on the second lower dielectric layer 130. The magnetic tunnel junction pattern MTJ may be interposed between the bottom electrode BE and the top electrode TE. Each lower electrode contact portion 140 may be electrically connected to the bottom electrode BE of a corresponding one of the data storage patterns DS. The bottom electrode BE of each data storage pattern DS may contact the top surface of the corresponding lower electrode contact portion 140 and the uppermost surface 130U1 of the second lower dielectric layer 130.

[0054] The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP.

[0055] The magnetic tunnel junction pattern MTJ may further include a seed pattern 150 between the bottom electrode BE and the first magnetic pattern MP1. At least a part of the seed pattern 150 may be amorphous. Since at least a part of the seed pattern 150 has an amorphous phase, the crystallinity of the bottom electrode BE below the seed pattern 150 can be prevented from transferring into the first magnetic pattern MP1, thereby facilitating the growth of the first magnetic pattern MP1. The seed pattern 150 may include a non-magnetic metal element. The seed pattern 150 may include, for example, one or more of tantalum nitride (TaN) or tantalum (Ta).

[0056] The magnetic tunnel junction pattern MTJ may further include a cap pattern 160 between the top electrode TE and the second magnetic pattern MP2. The cap pattern 160 may prevent deterioration of the second magnetic pattern MP2. The cap pattern 160 may include at least one material selected from, for example, tantalum (Ta), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN).

[0057] The cap dielectric layer 165 may conformally cover the side surfaces of each data storage pattern DS. The cap dielectric layer 165 may be interposed between the cell dielectric layer 170 and the side surfaces of each data storage pattern DS, and may extend between the cell dielectric layer 170 and the recessed top surface 130RU of the second lower dielectric layer 130.

[0058] According to an embodiment of the inventive concept, as Figure 4A and Figure 4BAs shown, the lower shield line 105 and the upper shield line 215 may share a function of electrical wiring, and a method of manufacturing a magnetic memory device may be simplified.

[0059] Figure 5A and Figure 6A Shown along Figure 2 A cross-sectional view taken along line AA'. Figure 5B and Figure 6B Shown along Figure 2 In order to simplify the description, repeated explanations of previously described items may be omitted.

[0060] Reference Figure 2 、 Figure 5A and Figure 5B , the lower wiring 102 can be arranged between the first lower dielectric layer 120 and the lower shield line 105. The lower wiring 102 can be correspondingly inserted between the lower electrode contact portion 140 and the lower shield line 105. The lower wiring 102 can be arranged in the wiring dielectric layer 110. The lower wiring 102 can extend along the first direction D1 and be spaced apart from each other in the second direction D2. The wiring dielectric layer 110 can expose the top surface of the lower wiring 102. The wiring dielectric layer 110 can have a top surface that is substantially coplanar with the top surface of the lower wiring 102. The first lower dielectric layer 120 can be arranged on the wiring dielectric layer 110 and can cover the exposed top surface of the lower wiring 102. The lower wiring 102 can be electrically connected to the conductive line 101 through a contact portion (not shown) present in the wiring dielectric layer 110.

[0061] Each lower electrode contact portion 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 to be electrically connected to a corresponding one of the lower wirings 102. Each data storage pattern DS may be electrically connected to one end (e.g., a drain terminal) of a corresponding selection element through a corresponding lower electrode contact portion 140, a corresponding lower wiring 102, and a corresponding conductive line 101.

[0062] Each of the lower shield lines 105 may have a top surface in contact with a bottom surface of a corresponding one of the lower wirings 102. Each of the lower shield lines 105 may vertically overlap with a corresponding one of the lower wirings 102 when viewed in a plan view.

[0063] The upper wiring 200 can be interposed between the upper shield line 215 and the data storage pattern DS. The upper wiring 200 can extend along the second direction D2 and can be spaced apart from each other in the first direction D1. The upper wiring 200 can be disposed in the cell dielectric layer 170. Each data storage pattern DS can be electrically connected to a corresponding one of the upper wirings 200. Each upper shield line 215 can have a bottom surface that contacts the top surface of a corresponding one of the upper wirings 200. When observed in a plan view, each upper shield line 215 can be vertically overlapped with a corresponding one of the upper wirings 200.

[0064] The lower wiring 102 and the upper wiring 200 can include, for example, copper.

[0065] Referring to Figure 2 、 Figure 6A and Figure 6B ,the lower wiring 102 and the lower shield line 105 can be spaced apart from each other in a direction perpendicular to the top surface 100a of the substrate 100 (e.g., the third direction D3). The wiring dielectric layer 110 can be provided with the lower wiring 102 and the lower shield line 105 therein, and the lower wiring 102 and the lower shield line 105 are spaced apart from each other across a part of the wiring dielectric layer 110. When observed in a plan view, each lower shield line 105 can be vertically overlapped with a corresponding one of the lower wirings 102.

[0066] The cell dielectric layer 170 can expose the top surface of the upper wiring 200. The cell dielectric layer 170 can have a top surface that is substantially coplanar with the top surface of the upper wiring 200. The upper dielectric layer 210 can be disposed on the cell dielectric layer 170. The upper dielectric layer 210 can cover the exposed top surface of the upper wiring 200. The upper dielectric layer 210 can include, for example, one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0067] The upper shield line 215 can be disposed in the upper dielectric layer 210. The upper shield line 215 can extend along the second direction D2 and can be spaced apart from each other in the first direction D1. The upper shield line 215 can be spaced apart from the upper wiring 200 in the vertical direction (e.g., the third direction D3). The upper dielectric layer 210 can be interposed between the upper wiring 200 and the upper shield line 215. The upper wiring 200 and the upper shield line 215 can be spaced apart from each other across a part of the upper dielectric layer 210. When observed in a plan view, each upper shield line 215 can be vertically overlapped with a corresponding one of the upper wirings 200. According to some embodiments, the upper wiring 200 can be elongated along the second direction D2 compared to the upper shield line 215.

[0068] Figure 5A and Figure 5BThe magnetic storage device may further include a lower wiring 102 and an upper wiring 200 that serve as electrical wirings. The lower shielding line 105 and the upper shielding line 215 may be in contact with the corresponding lower wiring 102 and upper wiring 200, but not insulated from the corresponding lower wiring 102 and upper wiring 200. In this case, compared with the embodiments of Figure 6A and Figure 6B , the distances between the magnetic tunnel junction pattern MTJ and the lower shielding line 105 and the upper shielding line 215 may be reduced. Accordingly, the influence of an external magnetic field on the magnetic tunnel junction pattern MTJ may be successfully reduced, and the reliability of the magnetic storage device may be improved.

[0069] In the magnetic storage devices of Figure 6A and Figure 6B , the lower wiring 102 may be spaced apart from and insulated from the lower shielding line 105. The upper wiring 200 may be spaced apart from and insulated from the upper shielding line 215. In this case, the lower shielding line 105 and the upper shielding line 215 may only reduce the magnetic flux of the horizontal component of the external magnetic field. Since the lower wiring 102 and the upper wiring 200 include materials more suitable for electrical wiring and serve as electrical wirings, the electrical characteristics of the magnetic storage device may be improved.

[0070] Figure 8A and Figure 8B respectively show cross-sectional views taken along lines A-A' and B-B' of Figure 2 , showing a method of manufacturing a magnetic storage device according to some embodiments of the present inventive concept. Figures 9 to 14 shows a cross-sectional view taken along line A-A' of Figure 2 , showing a method of manufacturing a magnetic storage device according to some embodiments of the present inventive concept. For the sake of brevity of description, a repeated description of elements described previously may be omitted.

[0071] Referring to Figure 8A and Figure 8B , a substrate 100 may be provided. A select element (see SE of Figure 1 ) may be formed on the substrate 100. A conductive line 101 may be formed on the substrate 100. The conductive line 101 may be electrically connected to one end of the select element (e.g., a source / drain terminal).

[0072] A wiring dielectric layer 110 may be formed on the substrate 100. The wiring dielectric layer 110 may cover the conductive line 101. Different from the illustration, the wiring dielectric layer 110 may include multiple layers.

[0073] The lower shielding line 105 may be formed in the wiring dielectric layer 110. The lower shielding line 105 may be formed to be spaced apart from the conductive line 101 in a vertical direction (e.g., a third direction D3).

[0074] According to some embodiments, the lower wiring 102 may be formed in the wiring dielectric layer 110. The wiring dielectric layer 110 may expose the top surface of the lower wiring 102. The top surface of the lower wiring 102 may be coplanar with the top surface of the wiring dielectric layer 110. According to some embodiments, as discussed with reference to Figure 5A and Figure 5B , the lower wiring 102 may be formed to contact the lower shield line 105. According to some embodiments, as discussed with reference to Figure 6A and Figure 6B , the lower wiring 102 may be formed to be vertically (e.g., in the third direction D3) spaced apart from the lower shield line 105. A contact portion (not shown) may be formed in the wiring dielectric layer 110. The lower wiring 102 may be connected to the conductive line 101 through the contact portion (not shown).

[0075] According to some embodiments, as discussed with reference to Figure 4A and Figure 4B , the formation of the lower wiring 102 may be omitted. In this case, the wiring dielectric layer 110 may expose the top surface of the lower shield line 105, and the top surface of the lower shield line 105 may be coplanar with the top surface of the wiring dielectric layer 110.

[0076] The first lower dielectric layer 120 and the second lower dielectric layer 130 may be sequentially formed on the wiring dielectric layer 110. A plurality of lower electrode contact portions 140 may be formed in the first lower dielectric layer 120 and the second lower dielectric layer 130. According to some embodiments, the lower electrode contact portions 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 and may be connected to a corresponding one of the lower wirings 102. According to some embodiments, the lower electrode contact portions 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 and may be connected to a corresponding one of the lower shield lines 105.

[0077] Forming the lower electrode contact portions 140 may include, for example: forming lower contact holes (not shown) that penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130; forming a lower contact layer (not shown) that fills the lower contact holes; and planarizing the lower contact layer until the top surface of the second lower dielectric layer 130 is exposed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0078] Referring to Figure 9 , the bottom electrode layer BEL and the magnetic tunnel junction layer MTJL may be sequentially formed on the second lower dielectric layer 130. According to some embodiments, the magnetic tunnel junction layer MTJL may include a seed layer 150L, a first magnetic layer ML1, a tunnel barrier layer TBL, a second magnetic layer ML2, and a capping layer 160L sequentially stacked on the bottom electrode layer BEL. The bottom electrode layer BEL and the magnetic tunnel junction layer MTJL may be formed by, for example, sputtering, chemical vapor deposition, or atomic layer deposition.

[0079] A conductive mask pattern 175 may be formed on the magnetic tunnel junction layer MTJL. The conductive mask pattern 175 may define an area on which a magnetic tunnel junction pattern will be formed, as described below. The conductive mask pattern 175 may include at least one of a metal (e.g., Ta, W, Ru, or Ir) or a conductive metal nitride (e.g., TiN).

[0080] Referring Figure 10 , the conductive mask pattern 175 may be used as an etch mask to sequentially etch the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL. Thus, a magnetic tunnel junction pattern MTJ and a bottom electrode BE may be formed on the second lower dielectric layer 130. The bottom electrode BE may be connected to a corresponding lower electrode contact portion 140, and the magnetic tunnel junction pattern MTJ may be formed on the bottom electrode BE.

[0081] Etching the magnetic tunnel junction layer MTJL may include: sequentially etching the capping layer 160L, the second magnetic layer ML2, the tunnel barrier layer TBL, the first magnetic layer ML1, and the seed layer 150L using the conductive mask pattern 175 as an etch mask. Thus, the magnetic tunnel junction pattern MTJ may include a seed pattern 150, a first magnetic pattern MP1, a tunnel barrier pattern TBP, a second magnetic pattern MP2, and a capping pattern 160 sequentially stacked on the bottom electrode BE.

[0082] For example, an ion beam etching process using an ion beam may be employed as the etching process for etching the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL. The ion beam may include inert ions. The ion beam etching process may cause the top surface of the second lower dielectric layer 130 on opposite sides of the magnetic tunnel junction pattern MTJ to be recessed. Thus, the second lower dielectric layer 130 may have a recessed top surface 130RU on opposite sides of the magnetic tunnel junction pattern MTJ. For example, the second lower dielectric layer 130 may have a recessed top surface 130RU between a plurality of magnetic tunnel junction patterns MTJ spaced apart from each other in a first direction D1 and a second direction D2.

[0083] After the ion beam etching process, residues of each conductive mask pattern 175 may remain on the magnetic tunnel junction pattern MTJ. The residues of each conductive mask pattern 175 may be used as the top electrode TE. In the following description, the residues of each conductive mask pattern 175 may be referred to as the top electrode TE. The top electrode TE, the magnetic tunnel junction pattern MTJ, and the bottom electrode BE may constitute a data storage pattern DS.

[0084] Referring Figure 11, an initial capping dielectric layer 165L can be formed to conformally cover the top and side surfaces of each data storage pattern DS. The initial capping dielectric layer 165L can extend onto the recessed top surface 130RU of the second lower dielectric layer 130. The initial capping dielectric layer 165L can conformally cover the recessed top surface 130RU of the second lower dielectric layer 130. Forming the initial capping dielectric layer 165L can include: using a layer formation technique with excellent step coverage, such as atomic layer deposition (ALD).

[0085] Referring to Figure 12 , a cell dielectric layer 170 can be formed on the initial capping dielectric layer 165L. The cell dielectric layer 170 can be formed on the initial capping dielectric layer 165L to cover the data storage pattern DS and fill the space between the data storage patterns DS. The cell dielectric layer 170 can be formed by using, for example, a high density plasma chemical vapor deposition (HDPCVD) process.

[0086] Referring to Figure 13 , the upper portions of each of the cell dielectric layer 170 and the initial capping dielectric layer 165L can be partially etched to form trenches TR. The upper portion of the initial capping dielectric layer 165L can be partially etched to form a capping dielectric layer 165. The trenches TR can extend along a second direction D2 and can be spaced apart from each other in a first direction D1. Each trench TR can have a linear shape extending along the second direction D2 and can expose corresponding data storage patterns DS spaced apart from each other in the second direction D2. Each trench TR can expose the top electrode TE of the corresponding data storage pattern DS.

[0087] Referring to Figure 14 , an upper wiring 200 can be formed in the trenches TR. Forming the upper wiring 200 can include, for example: forming a conductive layer to fill the trenches TR; and planarizing the conductive layer until the top surface of the cell dielectric layer 170 is exposed. The planarization process can make the top surface of the cell dielectric layer 170 coplanar with the top surface of the upper wiring 200.

[0088] According to some embodiments, as referred to Figure 4A and Figure 4B discussed, forming the upper wiring 200 can be omitted. In this case, an upper shielding line 215 can be formed in the trenches TR.

[0089] According to some embodiments, referring to Figure 5A and Figure 5B , the upper shielding line 215 can be formed on the upper wiring 200. Each upper shielding line 215 can have a bottom surface contacting the top surface of a corresponding one of the upper wirings 200. When observed in a plan view, each upper shielding line 215 can be vertically overlapped with a corresponding one of the upper wirings 200.

[0090] According to some embodiments, referring back to Figure 6A and Figure 6B , an upper dielectric layer 210 may be formed on the cell dielectric layer 170. The upper dielectric layer 210 may cover the upper wiring 200. An upper shielding line 215 may be formed in the upper dielectric layer 210. The upper shielding line 215 may span a portion of the upper dielectric layer 210 and be spaced apart from the upper wiring 200 in a vertical direction (e.g., the third direction D3). Each upper shielding line 215 may be vertically overlapped with a corresponding one of the upper wirings 200. The length of the upper shielding line 215 in the second direction D2 may be less than the length of the upper wiring 200 in the second direction D2.

[0091] Figure 15A and Figure 15B show cross-sectional views taken along lines A-A' and B-B' of Figure 2 , showing a method of manufacturing a magnetic storage device of Figure 3A and Figure 3B . For simplicity of description, repeated explanations will be omitted.

[0092] Referring back to Figure 15A and Figure 15B , a substrate 100 may be provided. A select element (see SE of Figure 1 ) may be formed on the substrate 100. A conductive line 101 may be formed on the substrate 100. The conductive line 101 may be electrically connected to one end (e.g., a source / drain terminal) of the select element.

[0093] A wiring dielectric layer 110 may be formed on the substrate 100. The wiring dielectric layer 110 may cover the conductive line 101. Different from the illustration, the wiring dielectric layer 110 may include multiple layers.

[0094] A lower shielding line 105 may be formed in the wiring dielectric layer 110. The lower shielding line 105 may be formed to be spaced apart from the conductive line 101 in a vertical direction (e.g., the third direction D3). The wiring dielectric layer 110 may expose the top surface of the lower shielding line 105. The top surface of the lower shielding line 105 may be coplanar with the top surface of the wiring dielectric layer 110. The lower shielding line 105 may extend along the first direction D1 and may be spaced apart from each other in the second direction D2.

[0095] Referring back to Figure 3A and Figure 3B , a data storage pattern DS, a capping dielectric layer 165, a cell dielectric layer 170, and an upper shielding line 215 may be formed. Forming the data storage pattern DS, the capping dielectric layer 165, and the cell dielectric layer 170 may be substantially the same as those discussed referring to Figures 9 to 14 . However, the formation of the upper wiring 200 may be omitted, and the upper shielding line 215 may be formed in the trench TR.

[0096] According to the inventive concept, shielding lines extending in a first direction and a second direction may exist at the top and bottom of a data storage pattern. The shielding lines may reduce the magnetic flux of the horizontal component of an external magnetic field in a magnetic storage device using perpendicular magnetization. Accordingly, the reliability of the magnetic storage device may be improved.

[0097] Although the present invention has been described in connection with some embodiments of the inventive concept shown in the drawings, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and basic features of the inventive concept. Accordingly, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A magnetic storage device comprising: substrate; a conductive line on the substrate; a wiring dielectric layer covering the conductive wires; a lower shielding line, in the wiring dielectric layer, the lower shielding line extending along a first direction; a data storage pattern comprising a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the lower shield line; as well as an upper shielding line, on the data storage pattern, the upper shielding line extending in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, Wherein, the lower shielding wire and the upper shielding wire include magnetic materials.

2. The magnetic memory device according to claim 1, wherein The lower shield wire and the upper shield wire include at least one of cobalt (Co), iron (Fe), or nickel (Ni).

3. The magnetic memory device according to claim 1, wherein The bottom surface of the lower electrode contacts the top surface of the lower shielding line, and A top surface of the top electrode contacts a bottom surface of the upper shield line.

4. The magnetic memory device according to claim 1, wherein The magnetic tunnel junction pattern includes a seed pattern, a first magnetic pattern, a tunnel barrier pattern, a second magnetic pattern, and a capping pattern sequentially stacked on the bottom electrode.

5. The magnetic memory device according to claim 1 , further comprising: a lower dielectric layer between the data storage pattern and the wiring dielectric layer; as well as A lower electrode contact portion is in the lower dielectric layer and is electrically connected to the data storage pattern, the lower electrode contact portion penetrating the lower dielectric layer. The magnetic memory device according to claim 5 , wherein: The top surface of the upper electrode contacts the bottom surface of the upper shield line, and The lower electrode contact is electrically connected to the lower shield line.

7. The magnetic memory device according to claim 6, wherein The lower dielectric layer has a recessed top surface that is recessed toward the substrate in a region of the lower dielectric layer that does not vertically overlap the data storage pattern.

8. The magnetic memory device according to claim 7, further comprising: A capping dielectric layer surrounds side surfaces of the data storing pattern, and the capping dielectric layer extends onto the recessed top surface of the lower dielectric layer.

9. The magnetic memory device according to claim 5, further comprising: a lower wiring, between the lower electrode contact portion and the lower shielding line, the lower wiring extending along the first direction; as well as an upper wiring line, between the upper shielding line and the data storage pattern, the upper wiring line extending along the second direction, wherein the lower electrode contact portion is electrically connected to the lower wiring, and Wherein, the data storage pattern is electrically connected to the upper wiring.

10. The magnetic memory device according to claim 9, wherein The lower wiring is in contact with the lower shielding line, and The upper wiring is in contact with the upper shielding line.

11. The magnetic memory device according to claim 9, further comprising: an upper dielectric layer, between the upper wiring and the upper shielding line, The lower wiring and the lower shielding line are vertically spaced apart from each other across a portion of the wiring dielectric layer.

12. A magnetic memory device comprising: substrate; a conductive line on the substrate; a wiring dielectric layer covering the conductive wires; lower shield lines extending in a first direction in the wiring dielectric layer, and each of the lower shield lines being spaced apart from each other in a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate; data storage patterns disposed on the lower shield line, wherein each of the data storage patterns is spaced apart from each other in the first direction and the second direction; as well as upper shielding lines extending along the second direction on the data storage pattern, and each of the upper shielding lines being spaced apart from each other in the first direction, Each of the lower shielding wires and each of the upper shielding wires includes a magnetic material.

13. The magnetic memory device according to claim 12, wherein The magnetic material is at least one of cobalt (Co), iron (Fe) or nickel (Ni).

14. The magnetic memory device according to claim 12, wherein A bottom surface of each of the data storage patterns contacts a top surface of a corresponding one of the lower shield lines, and A top surface of each of the data storage patterns contacts a bottom surface of a corresponding one of the upper shield lines.

15. The magnetic memory device according to claim 12, further comprising: a lower dielectric layer between the data storage pattern and the wiring dielectric layer; as well as Lower electrode contacts are in the lower dielectric layer, and each of the lower electrode contacts is electrically connected to a corresponding one of the data storage patterns, the lower electrode contacts penetrating the lower dielectric layer.

16. The magnetic memory device according to claim 15, wherein The lower dielectric layer has a recessed top surface that is recessed toward the substrate between at least two of the data storage patterns.

17. The magnetic memory device according to claim 16, further comprising: lower wirings, wherein each of the lower wirings is between a corresponding one of the lower electrode contact portions and a corresponding one of the lower shield lines, the lower wirings extending along the first direction, and each of the lower wirings is spaced apart from each other in the second direction; and upper wirings, wherein each of the upper wirings is between a corresponding one of the upper shield lines and a corresponding one of the data storage patterns, the upper wirings extend along the second direction, and each of the upper wirings is spaced apart from each other in the first direction.

18. The magnetic memory device according to claim 17, wherein Each of the lower wirings is in contact with a corresponding one of the lower shielding lines, and Each of the upper wirings is in contact with a corresponding one of the upper shield lines.

19. The magnetic memory device according to claim 17, further comprising: an upper dielectric layer, between the upper wiring and the upper shielding line, The lower wiring and the lower shielding line are vertically spaced apart from each other across a portion of the wiring dielectric layer.

20. A magnetic memory device comprising: substrate; a conductive line on the substrate; a wiring dielectric layer covering the conductive wires; lower shield lines extending in a first direction in the wiring dielectric layer, and each of the lower shield lines being spaced apart from each other in a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate; data storage patterns on the lower shield line, each of the data storage patterns being spaced apart from one another in the first direction and the second direction, each of the data storage patterns including a bottom electrode, a first magnetic pattern, a tunnel barrier pattern, a second magnetic pattern, and a top electrode stacked sequentially; as well as upper shielding lines extending along the second direction on the data storage pattern, and each of the upper shielding lines being spaced apart from each other in the first direction, wherein a bottom surface of each of the bottom electrodes contacts a top surface of a corresponding one of the lower shield lines, and A top surface of each of the top electrodes contacts a bottom surface of a corresponding upper shield line among the upper shield lines.

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