Heterogeneous integrated sensing, storage and calculation integrated structure and preparation method thereof

Abstract

The invention belongs to the related technical field of chip structure design, and discloses a heterogeneous integrated sensing-storage-calculation integrated structure and a preparation method thereof.The preparation method comprises the steps that an isolation region is formed before a PN junction is constructed, then an active region of the PN junction is marked through the isolation region, a transverse photodiode is manufactured through etching and injection processes, and an isolation wall is reserved; alignment of subsequent overlay metal electrodes is facilitated; simultaneously preparing a phase change film resistor and a phase change memory; a wafer containing a rear-end logic circuit is interconnected through wafer bonding; and then back silicon is turned and thinned, a layer of nano metal particles and a passivation layer are deposited, the range of a photosensitive wave band is expanded by using the nano metal particles, and the surface state density of an interface is reduced by using the passivation layer, so that dark current is reduced. According to the invention, on one hand, the phase change memory is introduced to reduce the power consumption and delay of sensor data stream processing, and on the other hand, the process and the wafer structure are optimally designed, so that the structural performance is improved, and the process difficulty is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field related to chip structure design, and more specifically, relates to a heterogeneously integrated sensing, storage and computing structure and a preparation method thereof. Background Art

[0002] With the continuous development of artificial intelligence, autonomous driving, and intelligent manufacturing, the resolution and frame rate of high-performance photoelectric sensors continue to increase, resulting in a sharp increase in the amount of data generated. This data explosion poses a huge challenge to data transmission, storage, and processing capabilities, and more efficient solutions are urgently needed to cope with increasingly complex needs.

[0003] To improve the overall performance of photoelectric sensor chips, a common solution is to integrate photoelectric sensors with ADCs, or photoelectric sensors with DRAM, ADCs, and control circuits through 3D stacking technology, with data stored in DRAM or SRAM. This is essentially still a sensor-storage-computing separation architecture. Chips typically require ADCs to convert analog signals sensed by sensors into digital signals for storage, and then convert the digital signals back into analog signals when calculations are required. However, as high-power modules, ADCs often account for over 50% of the power consumption of high-speed sensors. Furthermore, data processing is subject to latency.

[0004] Integrated sensing, storage, and computing is a new architecture for developing image sensor chips, offering advantages for achieving higher performance. However, the development of such chips requires innovative integration solutions, particularly innovations in the structure and fabrication methods for heterogeneous device integration. Summary of the Invention

[0005] In response to the above-mentioned defects or improvement needs of the prior art, the present invention provides a heterogeneously integrated sensing, storage and computing structure and a preparation method thereof, the purpose of which is to reduce the power consumption and delay of data stream processing of general photoelectric sensor chips.

[0006] To achieve the above objectives, according to a first aspect of the present invention, a method for preparing a heterogeneously integrated sensing, storage, and computing structure is provided, comprising: Etching an isolation trench on a substrate, depositing a first passivation layer on the sidewalls of the isolation trench and the upper surface of the substrate, and then depositing polysilicon until the height of the polysilicon in the isolation trench exceeds the upper surface of the first passivation layer, grinding the polysilicon flat, and forming an isolation region in the isolation trench; Using the isolation region as an overlay mark, the substrate is exposed between adjacent isolation regions and adjacent first and second trenches are formed, with an isolation wall between the first and second trenches. A first conductive type material is injected into the substrate through the first trench, and a second conductive type material is injected into the substrate through the second trench. One of the two materials forms a P-type region and the other forms an N-type region. Annealing is performed to cause ion diffusion between the P-type region and the N-type region to form a PN junction. Using the isolation region and the isolation wall as overlay marks, forming a P-region first electrode and an N-region first electrode on the P-type region and the N-type region respectively; Depositing a dielectric layer on the side where the first electrode is formed, and simultaneously forming a phase change material group, wherein the phase change material group includes three parallel phase change material structures, one end of each phase change material structure penetrates the dielectric layer until it is electrically connected to the first electrode in the N region, and the other end is provided with a first bonding electrode; forming a second bonding electrode that penetrates the dielectric layer and is electrically connected to the first electrode in the P region; and obtaining a first wafer assembly; Bonding the front surface of the first wafer assembly having the bonding electrodes to the second wafer assembly so that the bonding electrodes in the first wafer assembly are connected to the control circuit in the second wafer assembly; Thinning the back side of the first wafer assembly until the P-type region and the N-type region are exposed, and then sequentially forming a nano-metal particle quantum dot layer and a second passivation layer; A voltage is applied to one of the phase change material structures in the phase change material group through a control circuit to cause hard breakdown to form resistance, and the other two phase change material structures serve as phase change memories.

[0007] Optionally, a dielectric layer is deposited on the side where the first electrode is formed, and a phase change material group is simultaneously formed, wherein the phase change material group includes three parallel phase change material structures, one end of each phase change material structure penetrates the dielectric layer until it is electrically connected to the first electrode in the N region, and a bonding electrode is provided on the other end. Forming the bonding electrode that penetrates the dielectric layer and is electrically connected to the first electrode in the P region includes: Depositing a first dielectric layer on the side where the first electrode is to be formed and smoothing the upper surface; A through-hole group exposing the first electrode of the N region is opened on the first dielectric layer and filled with phase change material to form a phase change material group, wherein each N-type region corresponds to a through-hole group, and each through-hole group has three through-holes; forming a second electrode penetrating the first dielectric layer and connected to the first electrode of the P region; A second dielectric layer is deposited on the side where the second electrode is formed, forming a P-region third electrode penetrating the second dielectric layer and interconnected with the second electrode, and an N-region third electrode electrically connected to the phase change material structure as bonding electrodes.

[0008] Optionally, before forming the P region first electrode and the N region first electrode, a layer of metal silicide is first deposited in both the P-type region and the N-type region, and then the P region first electrode and the N region first electrode are deposited.

[0009] Optionally, after the phase change material is filled into the through hole, TiN material is further filled into the through hole.

[0010] Optionally, the phase change material structure includes at least one of Ge2Sb2Te5, Si-Sb-Te, NbTe4, Hf-Ge-Se, GeTe, and Sb2Te3.

[0011] Optionally, the nano-metal particle quantum dot layer is formed by an atomic layer deposition process or a spin coating process.

[0012] Optionally, the through hole group includes a first through hole, a second through hole and a third through hole, the first through hole has a first diameter, the second through hole and the third through hole have a second diameter, and the second diameter is larger than the first diameter.

[0013] According to a second aspect of the present invention, a heterogeneously integrated sensing, storage and computing structure is provided, comprising a first wafer assembly and a second wafer assembly bonded to each other; The first wafer assembly comprises: substrate; a plurality of parallel isolation trenches extending through the substrate; a first passivation layer formed on the sidewalls of the isolation trench and the front surface of the substrate; Polysilicon is filled in the isolation trench and covers the first passivation layer on the front side of the substrate; the structure in the isolation trench forms an isolation region; a PN junction formed between adjacent isolation regions, comprising a P-type region and an N-type region distributed in parallel, wherein the lower surfaces of the P-type region and the N-type region are both exposed to the back surface of the substrate, and the upper surfaces of the P-type region and the N-type region do not exceed the isolation region; A first electrode in the P region, penetrating the polysilicon until it is electrically connected to the upper surface of the P-type region; An N-type first electrode penetrates the polysilicon until it is electrically connected to the upper surface of the N-type region; an isolation wall is present between the P-region first electrode and the N-type first electrode; a dielectric layer covering a surface of the substrate having the first electrode; a phase change material group, comprising three parallel phase change material structures, one end of each phase change material structure penetrating the dielectric layer until electrically connected to the first electrode of the N region, and a first bonding electrode disposed on the other end; one of the phase change material structures is hard-punctured to form a resistor, and the other two phase change material structures form a phase change memory; a second bonding electrode, penetrating the dielectric layer until interconnected with the first electrode in the P region; a nano-metal particle quantum dot layer formed on the back side of the substrate; a second passivation layer formed on the nano-metal particle quantum dot layer; The second wafer assembly includes a control circuit, and the front side of the first wafer assembly having the bonding electrode is bonded to the second wafer assembly to achieve connection between the bonding electrode in the first wafer assembly and the control circuit in the second wafer assembly.

[0014] Optionally, the phase change material structure includes at least one of Ge2Sb2Te5, Si-Sb-Te, NbTe4, Hf-Ge-Se, GeTe, and Sb2Te3.

[0015] Optionally, TiN material is further provided between the other end of the phase change material structure and the first bonding electrode.

[0016] In general, compared with the prior art, the above technical solutions conceived by the present invention mainly have the following beneficial effects.

[0017] 1. The heterogeneously integrated sensing, storage, and computing structure and its preparation method mentioned in the present invention form a PN junction, a resistor, and a phase-change memory. The PN junction acts as a light-emitting diode, and one end of the resistor and phase-change memory is connected to the negative end of the light-emitting diode. The positive end of the light-emitting diode, the other end of the resistor and the phase-change memory are all controllable ends. In this structure, by introducing the phase-change memory, different resistance values can be written to the phase-change memory as needed. After the light information is converted into an electrical signal by the light-emitting diode, different current outputs are obtained through two phase-change memories, and differential calculations can then be performed, thereby realizing sensing, storage, and computing operations. Moreover, the phase-change memory can store data in a non-volatile manner, and analog signals can be directly calculated and stored by the phase-change memory without the need for an analog-to-digital converter (ADC), reducing energy consumption and delays generated during data exchange. This forms a three-dimensional heterogeneous integrated architecture for sensing, storage, and computing, realizing the integration of sensing, storage, and computing, and reducing the time and energy overhead of data processing.

[0018] 2. The heterogeneously integrated sensing, storage and computing structure and its preparation method mentioned in the present invention have an isolation region formed therein. On the one hand, the isolation region can isolate the PN junction, thereby forming a deep photodiode and effectively reducing the probability of surface recombination. On the other hand, the isolation region can also be used as an overlay mark in the subsequent photolithography process to facilitate the alignment of the subsequent photolithography process.

[0019] 3. In the heterogeneously integrated sensing, storage and computing structure and its preparation method mentioned in the present invention, the heights of the P-type region and the N-type region are lower than the isolation wall. Therefore, the portion of the isolation wall that is not in contact with the active area still exists after the active area is activated. The retained isolation wall facilitates alignment during subsequent electrode overlay.

[0020] 4. The heterogeneously integrated sensing, storage and computing structure and its preparation method mentioned in the present invention, by forming nano-metal particles on the surface of the PN junction, is conducive to improving the response of the PN junction to external light, thereby improving the sensitivity of the photodiode, and the combination of the second passivation layer and the first passivation layer can reduce the dark current at the boundary surface of the PN junction.

[0021] 5. Compared with traditional thin-film resistors, the heterogeneously integrated sensing, storage, and computing structure and its preparation method mentioned in the present invention can reduce the resistor area overhead by hard-breaking the phase-change material structure to form a fixed-value resistor. In addition, during the preparation process, the phase-change material structure is formed simultaneously, and the fixed-value resistor and phase-change memory are subsequently obtained by applying voltage, making the device preparation process more streamlined. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a circuit diagram of the integrated sensing, storage and computing structure provided by the present invention in detection mode.

[0023] Figure 2 This is a circuit diagram of the sensing, storage and computing integrated structure provided by the present invention in write mode.

[0024] Figure 3 This is a circuit diagram of the sensing, storage and computing integrated structure provided by the present invention in the reading mode.

[0025] Figure 4 It is a flow chart of the steps of the preparation method in one embodiment of the present invention.

[0026] Figures 5 to 13 It is a schematic structural diagram after relevant preparation steps in one embodiment of the present invention.

[0027] Figure 14 Schematic diagram of a passivation layer reducing dark current at the PN junction boundary in one embodiment of the present invention.

[0028] Figure 15 It is a structural diagram of a heterogeneously integrated sensing, storage and computing structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0030] like Figures 1 to 3The figure shows a circuit structure diagram of the heterogeneously integrated sensing, storage and computing structure provided by the present invention, which includes a photodiode PD, a phase change memory R+, a phase change memory R- and a fixed resistor R0 formed by a phase change material.

[0031] Taking image processing as an example, image pixels correspond to light intensity information. Under lighting conditions, the photodiode PD generates photocurrent.

[0032] In the detection mode, the terminals of the fixed resistor R0 and the photodiode PD are in a control state, while the terminals of the two phase change memories are suspended. At this time, the photocurrent can be detected.

[0033] In write mode, the terminals of the fixed resistor R0, phase change memory R+, and phase change memory R- are in control state, and the terminal of the photodiode PD is left floating. When the resistance value needs to be written to the phase change memory R+, the terminal of the phase change memory R+ is grounded and the terminal of the phase change memory R- is left floating, and the fixed resistor R0 is connected to the corresponding voltage V cc , by applying voltage to the phase change memory R+ to write the corresponding resistance value; when it is necessary to write the resistance value to the phase change memory R-, the terminal of the phase change memory R- is grounded and the terminal of the phase change memory R+ is left floating, and the fixed value resistor R0 is connected to the corresponding voltage V cc , by applying voltage to the phase change memory R- to write the corresponding resistance value.

[0034] In read mode, the photodiode PD is grounded, and the fixed resistor R0 is left floating. The photodiode PD generates a photo-generated voltage under illumination, which rapidly reads the currents of the phase-change memory R+ and phase-change memory R-. When reading the current of the phase-change memory, one terminal is grounded, and the other terminal is left floating. By using a peripheral circuit to subtract the current of the phase-change memory R- from the output current of the phase-change memory R+, the differential calculation of the photo-generated electrical signal can be performed, thereby achieving the calculation of weights with both positive and negative signs.

[0035] The present invention provides a method for preparing a heterogeneous integrated sensing, storage and computing structure. Figure 4 The figure shows a flow chart of the steps of a method for preparing a heterogeneously integrated sensing, storage and computing structure in one embodiment of the present invention, and the steps are described in detail below.

[0036] S1. Etch an isolation trench on the substrate, deposit a first passivation layer on the sidewalls of the isolation trench and the upper surface of the substrate, and then deposit polysilicon until the height of the polysilicon in the isolation trench exceeds the upper surface of the first passivation layer. Grind the polysilicon flat, and the structure in the isolation trench forms an isolation region.

[0037] Specifically, a P-type silicon substrate can be selected.

[0038] like Figure 5As shown, a first photolithographic pattern is formed on the substrate to expose the area to be etched, and a 1500nm deep groove is etched as an isolation groove by a dry etching process. Then, 50nm aluminum oxide and 50nm zirconium oxide are deposited in sequence as the first passivation layer by an atomic layer deposition (ALD) process. Subsequently, a low-pressure chemical vapor deposition (LPCVD) process is used to fill polysilicon, and then a chemical grinding and polishing (CMP) process is used to flatten the polysilicon surface. Specifically, the polysilicon on the upper surface of the substrate can retain a thickness of 300nm.

[0039] On the one hand, the isolation region can isolate the PN junction, thereby forming a deep photodiode and effectively reducing the probability of surface recombination. On the other hand, the isolation region can also be used as an overlay mark for subsequent photolithography processes, facilitating the alignment of subsequent photolithography processes.

[0040] S2. Using the isolation area as an overlay mark, the substrate is exposed between adjacent isolation areas and adjacent first trenches and second trenches are opened. An isolation wall is present between the first trench and the second trench. A first conductive type material is injected into the substrate through the first trench, and a second conductive type material is injected into the substrate through the second trench. One of the two materials forms a P-type region and the other forms an N-type region. Annealing causes ions in the P-type region and the N-type region to diffuse to form a PN junction.

[0041] Specifically, such as Figure 6As shown, a PN junction is formed between adjacent isolation regions. Thus, a second photolithographic pattern can be formed on the polysilicon top surface, using the isolation regions as overlay marks, exposing the area between the isolation regions where the first trench is to be etched. The polysilicon, first passivation layer, and substrate are then dry-etched to a predetermined depth to form a first trench. P-type ion material is then implanted into the first trench via ion implantation to form a P-type conductive active region. Subsequently, a second photolithographic pattern is formed on the polysilicon top surface, using the isolation regions as overlay marks, exposing the area between the isolation regions where the second trench is to be etched. The first trench and the second trench are spaced apart by a predetermined distance. The polysilicon, first passivation layer, and substrate are then dry-etched to a predetermined depth to form a second trench. An isolation wall is formed between the first and second trenches. N-type ion material is then implanted into the second trench via ion implantation to form an N-type conductive active region. It should be noted that the N-type ion material can also be implanted first, followed by the P-type ion material. The present invention does not limit the order of implantation. At this point, the P-type and N-type regions are separated by an isolation wall formed by a stack of substrate, first passivation layer, and polysilicon. A high-temperature annealing process can then be used to diffuse ions between the P-type and N-type regions, forming a PN junction and activating the active region of the photodiode (PD). In the present invention, since the P-type and N-type regions are lower than the isolation wall, the portion of the isolation wall that is not in contact with the active region remains after activation. This retained isolation wall facilitates alignment during subsequent electrode overlay.

[0042] At this point, it is understood that to ensure the isolation effect of the isolation region, the depths of the P-type region and the N-type region do not exceed the depth of the isolation region and can be shallower than the isolation region. For example, the depth of the isolation trench can be 1500nm, and the depths of the first trench and the second trench can be 800nm. Specifically, the distance between the P-type region and the N-type region is 3μm. The high-temperature annealing can be specifically performed at 900°C for 1 hour.

[0043] S3. Using the isolation region and the isolation wall as overlay marks, a P-region first electrode and an N-region first electrode are formed on the P-type region and the N-type region respectively.

[0044] like Figure 7 As shown, the isolation region and the isolation wall are used as overlay marks to form a fifth photolithography pattern to expose the top of each P-type region and N-type region, and then a first electrode is formed on each active region through a deposition process.

[0045] In one embodiment, a layer of metal silicide can be deposited on each active region before the first electrode is deposited. Specifically, a fourth photolithography pattern is formed using the isolation region and isolation wall as overlay marks to expose the P-type and N-type regions. Metal silicide is then formed on each active region through a deposition process. Metal silicide can lower the Schottky barrier and reduce contact resistance.

[0046] Specifically, the thickness of the metal silicide is 600 nm and can be selected from TiSi2, CoSi2, NiSi, and PtSi. Specifically, the first electrode is a 150 nm W electrode.

[0047] S4. Deposit a dielectric layer on the side where the first electrode is formed, and simultaneously form a phase change material group, wherein the phase change material group includes three parallel phase change material structures, one end of each phase change material structure penetrates the dielectric layer until it is electrically connected to the first electrode of the N region, and a first bonding electrode is provided on the other end; form a second bonding electrode that penetrates the dielectric layer and is electrically connected to the first electrode of the P region, and obtain a first wafer assembly.

[0048] In one embodiment, the process may include the following sub-steps.

[0049] S41 , depositing a first dielectric layer on the side where the first electrode is formed and smoothing the upper surface.

[0050] like Figure 8 As shown, a first dielectric layer is deposited by LPCVD process and then polished. The first dielectric layer can be 150nm SiO2.

[0051] S42 , opening a through hole group exposing the first electrode of the N region on the first dielectric layer and filling the through hole group with a phase change material structure to form a phase change material group. Each N-type region corresponds to a through hole group, and each through hole group has three through holes.

[0052] like Figure 9 As shown, a sixth photolithographic pattern is formed on the first dielectric layer to expose the area to be etched, and through holes are etched by reactive ion etching (RIE) to expose the first electrodes electrically connected to the N-type region, and each first electrode electrically connected to the N-type region corresponds to three through holes, and a phase change material structure is filled into the through holes.

[0053] In one embodiment, the through hole may be filled with a phase change material first and then filled with a TiN material to improve the interface contact.

[0054] Specifically, the phase change material structure is selected from at least one of Ge2Sb2Te5, Si-Sb-Te, NbTe4, Hf-Ge-Se, GeTe, and Sb2Te3.

[0055] S43 , forming a second electrode penetrating the first dielectric layer and connected to the first electrode of the P region.

[0056] like Figure 10 , forming a seventh photolithographic pattern, etching the first dielectric layer with a thickness of 150nm by reactive ion etching (RIE) to expose the first electrode electrically connected to the P-type region, and depositing 150nm of metal W to obtain a second electrode interconnected with the first electrode in the P-type region.

[0057] S44, depositing a second dielectric layer toward the side where the second electrode is formed, forming a P-region third electrode penetrating the second dielectric layer and interconnected with the second electrode, and an N-region third electrode electrically connected to the phase change material structure as bonding electrodes.

[0058] like Figure 11 As shown, 150nm of SiO2 is deposited as the second dielectric layer using an LPCVD deposition process. An eighth photolithographic pattern is formed on the second dielectric layer. Reactive ion etching (RIE) is then used to etch the second dielectric layer, exposing the second electrode and the phase-change material structure (or the electrical connection structure on the phase-change material structure). A 150nm layer of metal W is deposited as the third electrode using a CVD deposition process. The third electrode serves as a metal bonding wire, and then CMP polishing is performed.

[0059] S5. Bond the front side of the first wafer assembly having the bonding electrode to the second wafer assembly, so that the bonding electrode in the first wafer assembly is connected to the control circuit in the second wafer assembly.

[0060] like Figure 12 As shown, the first wafer assembly is flipped over and its surface activated using a plasma treatment (such as oxygen plasma) to remove surface organic matter and increase surface energy, promoting bonding. It is then aligned with the metal traces on the second wafer assembly, which contains the peripheral logic circuitry. The two wafers are heated to an appropriate temperature (typically 300°C to 400°C) and mechanical pressure is applied, completing the bonding process through thermal diffusion or metal bonding. The bonded wafers are then annealed to eliminate internal stress and improve bond strength. The annealing temperature is 350°C and maintained for 2 hours. During this process, the oxygen and silicon at the interface undergo a dehydration condensation reaction to form stable silicon-oxygen-silicon (Si-O-Si) covalent bonds.

[0061] S6. Thinning the back side of the first wafer assembly until the P-type region and the N-type region are exposed, and then sequentially forming a nano-metal particle quantum dot layer and a second passivation layer.

[0062] like Figure 13 As shown, the back side with the PN junction is thinned to 800 nm by CMP, and then a nano-metal particle quantum dot layer and a second passivation layer are prepared.

[0063] Specifically, the ALD process can be used to deposit 2nm nano-metal particles that have not yet formed into a film, and then the ALD process can be used to sequentially deposit 50nm aluminum oxide and 30nm zirconium oxide as the second passivation layer.

[0064] In this step, by forming nano-metal particles on the surface of the PN junction, it is beneficial to improve the response of the PN junction to external light, thereby improving the sensitivity of the photodiode. Figure 14As shown, the second passivation layer is combined with the first passivation layer to reduce the dark current at the boundary surface of the PN junction.

[0065] S7. Applying a voltage to one of the phase change material structures in the phase change material group through the control circuit causes it to undergo hard breakdown to form a resistor, and the other two phase change material structures serve as phase change memories.

[0066] In the present invention, compared with traditional thin film resistors, the resistor area overhead can be reduced by hard breakdown of the phase change material structure to form a fixed resistor. Moreover, in the preparation process, a through-hole group is formed and the phase change material structure is filled in simultaneously. Subsequently, the fixed resistor and the phase change memory are obtained respectively by applying voltage, and the device preparation process is more streamlined.

[0067] In one embodiment, the through-hole group includes a first through-hole, a second through-hole, and a third through-hole, wherein the first through-hole has a first diameter, and the second through-hole and the third through-hole have a second diameter, wherein the second diameter is larger than the first diameter. For example, the first diameter is 5 μm, and the second diameter is 20 μm. The smaller the aperture of the first through-hole, the more conducive it is to perform voltage hard breakdown to form a constant resistance. The smaller the through-hole diameter, the more concentrated the voltage drop. Through-hole groups with different through-hole diameters can be designed to achieve soft breakdown to form a phase change memory and hard breakdown to form a constant resistance under the same magnitude of control voltage.

[0068] In the above embodiments, SiO2 is used as an example for the dielectric layer. However, other low-k dielectric materials (low-k dielectrics) such as SiOC, SiCOH, and combinations thereof may also be used. The preparation process may be chemical vapor deposition (CVD) or thermal oxidation. The dielectric layer thickness ranges from 100nm to 800nm. This thickness can be set based on the actual device usage conditions. Each dielectric layer can be a single-layer or multi-layer structure.

[0069] In the above embodiments, the electrode is made of tungsten (W), but in practice, it can also be made of at least one of copper (Cu), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), zinc (Zn), vanadium (V), palladium (Pd), hafnium (Hf), yttrium (Y), manganese (Mn), tantalum (Ta), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum nitride (TiAlN), aluminum nitride (AlNx), ruthenium (Ru), ruthenium oxide (RuO), or indium tin oxide (ITO). The preparation process can be physical vapor deposition (PVD), magnetron sputtering, ion beam sputtering, electron beam evaporation, thermal evaporation, atomic layer deposition (ALD), or chemical vapor deposition (CVD), and the thickness can be 20-120 nm.

[0070] In the above embodiments, the passivation layer is made of aluminum oxide and zirconium oxide, and can also be made of MgF2, Si3N4, Al2O 3、 One or more of Ta2O5, ZrO2.

[0071] The present invention also provides a heterogeneous integrated sensing, storage and computing structure, such as Figure 15 As shown, it includes a first wafer assembly and a second wafer assembly bonded to each other.

[0072] The first wafer assembly includes: substrate; a plurality of parallel isolation trenches extending through the substrate; a first passivation layer formed on the sidewalls of the isolation trench and the front surface of the substrate; Polysilicon is filled in the isolation trench and covers the first passivation layer on the front side of the substrate; the structure in the isolation trench forms an isolation region; A PN junction is formed between adjacent isolation regions and includes a P-type region and an N-type region distributed in parallel, wherein the lower surfaces of the P-type region and the N-type region are exposed to the back side of the substrate, and the upper surfaces of the P-type region and the N-type region do not exceed the isolation region; A first electrode in the P region, penetrating the polysilicon until it is electrically connected to the upper surface of the P-type region; An N-type first electrode penetrates the polysilicon until it is electrically connected to the upper surface of the N-type region; an isolation wall is present between the P-region first electrode and the N-type first electrode; a dielectric layer covering a surface of the substrate having the first electrode; A phase-change material group, comprising three parallel phase-change material structures, one end of each phase-change material structure penetrating the dielectric layer until electrically connected to the first electrode of the N region, and a first bonding electrode disposed on the other end. One of the phase-change material structures is hard-punctured to form a resistor, and the other two phase-change material structures form a phase-change memory; a second bonding electrode, penetrating the dielectric layer until interconnected with the first electrode in the P region; a nano-metal particle quantum dot layer formed on the back side of the substrate; a second passivation layer formed on the nano-metal particle quantum dot layer; The second wafer assembly includes a control circuit, and the front side of the first wafer assembly having the bonding electrode is bonded to the second wafer assembly to achieve connection between the bonding electrode in the first wafer assembly and the control circuit in the second wafer assembly.

[0073] In one embodiment, TiN material is further disposed between the other end of the phase-change material structure and the first bonding electrode.

[0074] In one embodiment, a metal silicide is further provided between the P-type region and the first electrode of the P region, and a metal silicide is also provided between the N-type region and the first electrode of the N region.

[0075] Specifically, regarding the material selection of each layer structure, please refer to the above introduction and will not be repeated here.

[0076] In general, the present invention not only introduces phase change memory to reduce power consumption and delay in sensor data stream processing, but also designs the process and wafer structure to improve structural performance and reduce process difficulty. On the one hand, the present invention forms an isolation region before forming a PN junction, then marks the active region of the PN junction through the isolation region, and manufactures a lateral photodiode through etching and filling processes; on the other hand, the PN junction does not fill the groove, leaving an isolation wall to facilitate the subsequent alignment of the metal electrode; moreover, in the present invention, the fixed resistance function is realized by hard breakdown of the phase change material structure, and the specific resistance after breakdown can be controlled by changing the cross-sectional area of the phase change material structure, so that the phase change thin film resistor and the phase change memory can be prepared simultaneously by etching the groove process and the filling process; then the wafer (Carrier Wafer) is used to complete the rear end logic circuit wiring wafer; the back side silicon is flipped and thinned to the edge position of the PN junction, and a layer of nano-metal particles is deposited, and the nano-metal particles are used to excite LSPR in the visible light-near infrared band to generate a strong local electric field, so that the near-infrared light absorption efficiency of the silicon-based PN junction is improved, and the photosensitive band range is improved, and then a passivation layer is deposited, and the interface surface state density is reduced by field effect passivation to reduce the dark current.

[0077] The technical features of the above embodiments can be combined in any manner. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. It should be noted that the phrases "in one embodiment", "for example", "and another example", etc. of the present invention are intended to illustrate the present invention and are not intended to limit the present invention.

[0078] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. A method for preparing a heterogeneously integrated sensing, storage and computing structure, characterized in that: include: Etching an isolation trench on a substrate, depositing a first passivation layer on the sidewalls of the isolation trench and the upper surface of the substrate, and then depositing polysilicon until the height of the polysilicon in the isolation trench exceeds the upper surface of the first passivation layer, grinding the polysilicon flat, and forming an isolation region in the isolation trench; Using the isolation region as an overlay mark, the substrate is exposed between adjacent isolation regions and adjacent first and second trenches are formed, with an isolation wall between the first and second trenches. A first conductive type material is injected into the substrate through the first trench, and a second conductive type material is injected into the substrate through the second trench. One of the two materials forms a P-type region and the other forms an N-type region. Annealing is performed to cause ion diffusion between the P-type region and the N-type region to form a PN junction. Using the isolation region and the isolation wall as overlay marks, forming a P-region first electrode and an N-region first electrode on the P-type region and the N-type region respectively; Depositing a dielectric layer on the side where the first electrode is formed, and simultaneously forming a phase change material group, wherein the phase change material group includes three parallel phase change material structures, one end of each phase change material structure penetrates the dielectric layer until it is electrically connected to the first electrode in the N region, and the other end is provided with a first bonding electrode; forming a second bonding electrode that penetrates the dielectric layer and is electrically connected to the first electrode in the P region; and obtaining a first wafer assembly; Bonding the front surface of the first wafer assembly having the bonding electrodes to the second wafer assembly so that the bonding electrodes in the first wafer assembly are connected to the control circuit in the second wafer assembly; Thinning the back side of the first wafer assembly until the P-type region and the N-type region are exposed, and then sequentially forming a nano-metal particle quantum dot layer and a second passivation layer; A voltage is applied to one of the phase change material structures in the phase change material group through a control circuit to cause hard breakdown to form resistance, and the other two phase change material structures serve as phase change memories.

2. The method for preparing a heterogeneously integrated sensing, storage and computing structure according to claim 1, wherein: Depositing a dielectric layer on the side where the first electrode is formed, and simultaneously forming a phase change material group, wherein the phase change material group includes three parallel phase change material structures, one end of each phase change material structure penetrates the dielectric layer until it is electrically connected to the first electrode of the N region, and a bonding electrode is provided on the other end; Forming a bonding electrode that penetrates the dielectric layer and is electrically connected to the first electrode of the P region, comprising: Depositing a first dielectric layer on the side where the first electrode is to be formed and smoothing the upper surface; A through-hole group exposing the first electrode of the N region is opened on the first dielectric layer and filled with phase change material to form a phase change material group, wherein each N-type region corresponds to a through-hole group, and each through-hole group has three through-holes; forming a second electrode penetrating the first dielectric layer and connected to the first electrode of the P region; A second dielectric layer is deposited on the side where the second electrode is formed, forming a P-region third electrode penetrating the second dielectric layer and interconnected with the second electrode, and an N-region third electrode electrically connected to the phase change material structure as bonding electrodes.

3. The method for preparing a heterogeneously integrated sensing, storage and computing structure according to claim 2, wherein: Before forming the P region first electrode and the N region first electrode, a layer of metal silicide is first deposited on both the P-type region and the N-type region, and then the P region first electrode and the N region first electrode are deposited.

4. The method for preparing a heterogeneously integrated sensing, storage and computing structure according to claim 2, wherein: After the phase change material is filled into the through hole, TiN material is further filled into the through hole.

5. The method for preparing a heterogeneously integrated sensing, storage and computing structure according to claim 1, wherein: The phase change material structure includes at least one of Ge2Sb2Te5, Si-Sb-Te, NbTe4, Hf-Ge-Se, GeTe, and Sb2Te3.

6. The method for preparing a heterogeneously integrated sensing, storage and computing structure according to claim 1, wherein: The nano-metal particle quantum dot layer is formed by an atomic layer deposition process or a spin coating process.

7. The method for preparing a heterogeneously integrated sensing, storage and computing structure according to claim 2, wherein: The through hole group includes a first through hole, a second through hole and a third through hole, the first through hole has a first diameter, the second through hole and the third through hole have a second diameter, and the second diameter is larger than the first diameter.

8. A heterogeneous integrated sensing, storage and computing structure, characterized by: comprising a first wafer assembly and a second wafer assembly bonded to each other; The first wafer assembly comprises: substrate; a plurality of parallel isolation trenches extending through the substrate; a first passivation layer formed on the sidewalls of the isolation trench and the front surface of the substrate; Polysilicon is filled in the isolation trench and covers the first passivation layer on the front side of the substrate; the structure in the isolation trench forms an isolation region; a PN junction formed between adjacent isolation regions, comprising a P-type region and an N-type region distributed in parallel, wherein the lower surfaces of the P-type region and the N-type region are both exposed to the back surface of the substrate, and the upper surfaces of the P-type region and the N-type region do not exceed the isolation region; a first electrode in the P region, penetrating the polysilicon until electrically connected to the upper surface of the P-type region; An N-type first electrode penetrates the polysilicon until it is electrically connected to the upper surface of the N-type region; an isolation wall is present between the P-region first electrode and the N-type first electrode; a dielectric layer covering a surface of the substrate having the first electrode; a phase change material group, comprising three parallel phase change material structures, one end of each phase change material structure penetrating the dielectric layer until electrically connected to the first electrode of the N region, and a first bonding electrode disposed on the other end; one of the phase change material structures is hard-punctured to form a resistor, and the other two phase change material structures form a phase change memory; a second bonding electrode, penetrating the dielectric layer until interconnected with the first electrode in the P region; a nano-metal particle quantum dot layer formed on the back side of the substrate; a second passivation layer formed on the nano-metal particle quantum dot layer; The second wafer assembly includes a control circuit, and the front side of the first wafer assembly having the bonding electrode is bonded to the second wafer assembly to achieve connection between the bonding electrode in the first wafer assembly and the control circuit in the second wafer assembly.

9. The heterogeneously integrated sensing, storage and computing structure according to claim 8, characterized in that: The phase change material structure includes at least one of Ge2Sb2Te5, Si-Sb-Te, NbTe4, Hf-Ge-Se, GeTe, and Sb2Te3.

10. The heterogeneous integrated sensing, storage and computing structure according to claim 8, characterized in that: TiN material is further provided between the other end of the phase change material structure and the first bonding electrode.

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