Micro LED device of strip-shaped LED light source and manufacturing method

Abstract

The application relates to the technical field of MicroLED display and illumination, and discloses a MicroLED device of a strip-shaped LED light source and a manufacturing method, wherein the device comprises a chip array, a first substrate, a transparent conductive layer, a metal electrode, a planar layer, a wiring layer, an encapsulation layer and a driving circuit; the chip array is composed of multiple chips; the first substrate is selected from sapphire, silicon or gallium arsenide; the chip array is fixed to the surface of the first substrate; the transparent conductive layer is deposited on the surface of the chip array and used for forming a current transmission path; the metal electrode is arranged in an electrode area of the chip array and electrically connected with the transparent conductive layer. Through a split manufacturing process, the light bar and the control part are respectively manufactured and high-precision assembled, material utilization is improved, and the manufacturing process is optimized. Through a step-by-step encapsulation process, the MicroLED Chip is first manufactured, and then encapsulated into a light bar, so that the manufacturing precision requirement is reduced, and the production yield is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of MicroLED display and lighting, in particular to a MicroLED device of a strip-shaped LED light source and a manufacturing method. BACKGROUND

[0002] MicroLED technology has attracted widespread attention in the fields of display and lighting due to its high brightness, low power consumption and long service life. However, during the manufacturing and assembly of MicroLED, there are still many technical challenges, which directly affect the performance, production cost and manufacturing yield of the product.

[0003] In the traditional MicroLED manufacturing process, the light bar is usually manufactured in an integrated manner, that is, the fabrication of MicroLED chips, the integration of driving circuits and the light bar level packaging are completed on the same substrate. This method is relatively direct in process integration, but it is greatly limited in material utilization and manufacturing flexibility. Since the MicroLED chip and the driving part have different process requirements, unified manufacturing will cause material waste, and at the same time, high-precision processing on a large-size substrate is prone to cause accumulation of local errors, reducing the yield of the final product.

[0004] During the MicroLED packaging process, if the chip manufacturing is directly performed on the light bar substrate, it is necessary to ensure that the optical performance, electrical characteristics and physical structure of all chips are completely consistent, otherwise it will affect the display uniformity. However, due to the size of the substrate, the uniformity of etching, photolithography and deposition processes is difficult to control, especially in large-scale production, small deviations can easily lead to a decrease in light consistency of the light bar. The single manufacturing process also increases the process complexity, and defects in each process will directly affect the overall yield.

[0005] In terms of thermal management, the existing MicroLED structure usually uses silicon-based, glass-based substrates or traditional PCBs as the bearing material, which has certain limitations in thermal conductivity. In high-power applications, heat is difficult to dissipate, causing the temperature of the chip to rise, affecting the service life and luminous efficiency of the device. At the same time, due to the difference in thermal expansion coefficient, thermal stress is easily generated between the substrate material and the MicroLED chip, further affecting the reliability. SUMMARY

[0006] In view of the deficiencies of the prior art, the present application provides a MicroLED device of a strip-shaped LED light source and a manufacturing method, which solves the problems of material waste, high wiring resistance, uneven current distribution and insufficient heat dissipation caused by traditional integrated manufacturing.

[0007] To achieve the above object, the application is implemented by the following technical solutions: a MicroLED device of a strip-shaped LED light source, comprising a MicroLED chip array composed of a plurality of MicroLED chips;

[0008] a second substrate, the MicroLED chip array being fixed on the surface of the second substrate;

[0009] a transparent conductive layer deposited on the surface of the MicroLED chip array for forming a current transmission path;

[0010] a metal electrode arranged in the electrode area of the MicroLED chip array and electrically connected with the transparent conductive layer;

[0011] a planar layer covering the gaps of the MicroLED chip array to provide surface flatness, the planar layer being selected from polyimide or benzocyclobutene and formed by spin coating and baking solidification;

[0012] a wiring layer arranged on the planar layer for realizing the electrical connection between the MicroLED chip and the external circuit;

[0013] an encapsulation layer covering the surface of the wiring layer and the MicroLED chip array to provide environmental protection, the encapsulation layer being solidified by ultraviolet curing or thermal curing;

[0014] a driving circuit for providing an electrical signal to control the light-emitting state of the MicroLED chip array and being electrically connected with the wiring layer.

[0015] Preferably, the light-emitting area of the MicroLED chip array is arranged perpendicularly to the scanning direction of the strip-shaped light source.

[0016] Preferably, the MicroLED chip array adopts a common anode connection mode to improve the current uniformity.

[0017] Preferably, the light-emitting uniformity of the light source is realized by adjusting the distance between the MicroLED chips and the driving current.

[0018] A manufacturing method of a MicroLED chip, comprising the following steps:

[0019] S1.ISO: forming a MicroLED epitaxial structure on a sapphire, silicon-based or gallium arsenide-based substrate, and performing insulating layer etching to define a single MicroLED chip area;

[0020] S2.MESA: mesa etching the MicroLED chip structure by dry etching or laser etching to form an independent light-emitting unit 102;

[0021] S3. Ohmic contact ITO layer: depositing an indium tin oxide transparent conductive layer on the light-emitting layer of the MicroLED chip and performing annealing treatment to form an ohmic contact, improving current injection efficiency;

[0022] S4. PV opening: forming a via hole on the transparent conductive layer using a photolithography process to expose the p-type electrode contact area;

[0023] S5. Metal electrode deposition: depositing a metal electrode on the PV opening area and the n-type electrode area, the material of the metal electrode being selected from aluminum, gold or silver, and being formed by evaporation or sputtering deposition.

[0024] A method for assembling a MicroLED chip into a Unit, comprising the following steps:

[0025] Sa. Mass transfer: transferring the MicroLED chip from the first substrate to the second substrate by laser peeling or mechanical handling, and bonding by permanent bonding glue;

[0026] Sb. Flat layer formation: filling the gap of the MicroLED chip array with a flat layer selected from polyimide or benzocyclobutene, and forming by spin coating and baking curing;

[0027] Sc. Wiring layer formation: depositing a metal wiring layer on the flat layer to realize electrical connection of the MicroLED chip and the driving circuit;

[0028] Sd. Substrate circuit connection: connecting the wiring layer and the driving circuit by metal wires to complete the electrical connection of the MicroLED unit;

[0029] Se. Encapsulation: encapsulating the MicroLED chip with silicone or epoxy resin material.

[0030] Preferably, the mass transfer adopts laser peeling technology to transfer the MicroLED chip, and the transfer precision is controlled within ±2μm.

[0031] Preferably, the material of the wiring layer is selected from copper, aluminum or gold, and is formed by sputtering or electroplating process.

[0032] Preferably, the second substrate circuit connection adopts reflow soldering process or eutectic bonding process to ensure low resistance connection of the wiring layer and the driving circuit.

[0033] Preferably, the encapsulation layer is cured by ultraviolet curing or thermal curing to improve the environmental resistance of the encapsulation layer.

[0034] The present invention provides a MicroLED device and a manufacturing method for a strip-shaped LED light source. It has the following beneficial effects:

[0035] 1. This invention utilizes a split-type manufacturing solution for high-precision MicroLED light strips, manufacturing the MicroLED light strips and control unit separately and then performing high-precision assembly, thereby improving overall manufacturing efficiency. Compared to existing integrated manufacturing processes, this solution optimizes material utilization, reduces material waste during the manufacturing process, and increases process flexibility, enabling more efficient matching of MicroLED light strips and drive control units of varying specifications, making it suitable for large-scale production.

[0036] 2. This invention utilizes a step-by-step process to manufacture MicroLED light strips, first using high-precision manufactured MicroLED chips, which are then integrated into the MicroLED light strip through a packaging process. Compared to the traditional process of manufacturing MicroLEDs directly on the light strip substrate, this solution reduces the manufacturing precision requirements, resulting in a higher yield rate in each manufacturing step, while also reducing the overall defect rate caused by the large substrate size and improving product consistency.

[0037] 3. This invention utilizes an optimized MicroLED unit structure and precision assembly using independent packaging, ensuring high-density arrangement of MicroLED light strips during assembly while maintaining electrical isolation between units. Compared to integrated manufacturing methods, this avoids electrical interference between units, improves the independence of drive signals, and optimizes the display uniformity and response speed of the light strip.

[0038] 4. This invention utilizes a modular unit wiring structure. Within the MicroLED light strip, a separate electrode structure allows for independent optimization of chip-level signal transmission and light strip-level control circuitry. Compared to traditional direct wiring solutions, this reduces signal attenuation caused by long-distance transmission and optimizes current distribution, enabling the light strip to maintain high brightness uniformity and low power consumption even in large-area applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the MicroLED chip array structure in the present invention;

[0040] Figure 2 Schematic diagram of the steps of the method for manufacturing a MicroLED chip in the present invention;

[0041] Figure 3 Schematic diagram of the steps of assembling MicroLED chips into Units in the present invention;

[0042] Figure 4The connection diagram of the driving circuit in the application.

[0043] 1, MicroLED chip; 101, first substrate; 102, light emitting unit; 103, transparent conductive layer; 104, metal electrode; 105, PV opening; 2, second substrate; 3, permanent bonding glue; 4, planar layer; 5, wiring layer; 6, driving circuit. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the description of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0045] Embodiment:

[0046] Please refer to the drawings in the description of the application Figure 1 The embodiment of the application provides a MicroLED device of a strip-shaped LED light source, which comprises,

[0047] a MicroLED chip 1 array, the MicroLED chip 1 array is composed of a plurality of MicroLED chips 1;

[0048] The manufacturing of the MicroLED chip 1 is one of the key technologies of the application. First, we grow a MicroLED epitaxial layer on a suitable first substrate 101. Common substrates include sapphire, silicon-based or gallium arsenide-based substrates. By selecting appropriate materials and processes, we ensure that the MicroLED structure can be successfully formed on the epitaxial layer. Next, through the ISO (insulation layer etching) step, we etch independent MicroLED chip 1 regions on the surface of the epitaxial layer. This process ensures that each MicroLED chip 1 can be processed individually in subsequent processes. Then, MESA (mesa etching) is performed. This step is to separate the MicroLED chip 1 from the epitaxial layer by dry etching or laser etching to form individual discrete light emitting units 102.

[0049] On the surface of the MicroLED chip 1, an ohmic contact ITO layer needs to be applied. This is a transparent conductive layer that effectively ensures uniform current injection into the light-emitting area. At this time, we further improve the current injection efficiency through annealing treatment. Next, we will use photolithography to form PV openings 105 on the ITO layer, which exposes the p-type electrode contact area. Then, metal electrodes are deposited using evaporation or sputtering methods, which provide the basis for subsequent electrical connections. The electrode material is generally selected from aluminum, gold or silver, which has good electrical conductivity and ensures the electrical properties of the MicroLED chip 1.

[0050] The first substrate 101 is selected from sapphire, silicon-based or gallium arsenide-based substrate, and the array of MicroLED chips 1 is fixed on the surface of the first substrate 101.

[0051] Sapphire substrate: Because sapphire has excellent thermal stability and high-quality optical properties, it is widely used in MicroLED applications.

[0052] Silicon-based substrate: Silicon material is low in cost, suitable for mass production, and can be effectively integrated with traditional silicon circuits.

[0053] Gallium arsenide substrate: Suitable for high brightness requirements, the excellent optoelectronic properties of gallium arsenide can ensure the efficient light emission of MicroLED.

[0054] The array of MicroLED chips 1 is fixed on the surface of the first substrate 101, which not only provides mechanical support, but also ensures that the chip does not overheat during operation through good thermal conductivity.

[0055] Transparent conductive layer 103, deposited on the surface of the array of MicroLED chips 1, used to form a current transmission path.

[0056] The transparent conductive layer 103 is mainly used for current transmission and is an indispensable component of MicroLED devices. The transparent conductive layer 103 generally uses indium tin oxide or other transparent conductive materials, which not only have good electrical conductivity, but also have high light transmittance and do not affect the light-emitting efficiency of the light source.

[0057] The transparent conductive layer 103 is deposited on the surface of the array of MicroLED chips 1 and ensures that the current can be uniformly distributed to the light-emitting area of each MicroLED chip 1, thereby improving the overall brightness of the light source. The thickness and uniformity of the transparent conductive layer 103 are crucial to the performance of the chip, so the deposition process must be strictly controlled.

[0058] Metal electrode, disposed in the electrode area of the array of MicroLED chips 1, electrically connected with the transparent conductive layer 103;

[0059] The metal electrode is located in the electrode area of the array of MicroLED chips 1 and is electrically connected with the transparent conductive layer 103. The main function of the metal electrode is to guide the current to the light-emitting layer of the MicroLED chip 1, thereby exciting it to emit light.

[0060] The metal electrode material is generally selected from metals with strong electrical conductivity and good thermal stability, such as aluminum, gold or silver. The electrode is usually deposited by evaporation or sputtering process to deposit a thin layer of metal on the transparent conductive layer 103, ensuring smooth current transmission and minimizing resistance.

[0061] Flat layer 4, covering the gaps between the array of MicroLED chips 1, to provide surface flatness, the flat layer 4 is selected from polyimide or benzocyclobutene and formed by spin coating and baking;

[0062] The main function of the flat layer 4 is to fill the gaps between the array of MicroLED chips 1 and improve the flatness of the device surface, avoiding uneven light sources caused by differences between chips. In order to achieve better surface flatness, the flat layer 4 needs to be selected from materials with low viscosity, usually polyimide or benzocyclobutene.

[0063] The application of this material is uniformly coated by spin coating process, and then cured by baking. This process ensures the uniform thickness of the planarization layer, while improving the filling rate of the chip gap, making the surface more flat.

[0064] Wiring layer, disposed on the flat layer 4, for realizing the electrical connection between the MicroLED chip 1 and the external circuit;

[0065] The wiring layer is used to connect the MicroLED chip 1 and the external circuit, which is a key electrical connection part in the MicroLED device. The wiring layer is usually made of conductive materials such as copper, aluminum or gold, which have good electrical conductivity and can effectively conduct current.

[0066] The formation of the wiring layer is generally completed by sputtering or electroplating process to ensure the stability of the wiring layer and the reliability of current transmission. The design of the wiring layer needs to consider the working environment of the device, so special attention should be paid to the density, thickness and laying method of the wiring to avoid current loss or short circuit.

[0067] Encapsulation layer, covering the surface of the wiring layer and the array of MicroLED chips 1, to provide environmental protection, the encapsulation layer is cured by ultraviolet light curing or thermal curing;

[0068] The role of the encapsulation layer is to protect the MicroLED device from the external environment, such as moisture, dust, gas, etc. The encapsulation layer can also improve the durability and stability of the device, ensuring its performance does not decline over time.

[0069] The encapsulation material can be selected from silicone, epoxy resin or other environmentally friendly and high-temperature resistant materials. The encapsulation layer is generally cured by ultraviolet light or thermal curing, which can ensure that the encapsulation material completely covers and firmly fixes the array of MicroLED chips 1.

[0070] The design of the encapsulation layer should also consider the optical performance to avoid the negative impact of the color or optical properties of the material on the light source.

[0071] The driving circuit 6 is used to provide electrical signals to control the light-emitting state of the array of MicroLED chips 1 and is electrically connected to the wiring layer.

[0072] The driving circuit 6 is another important component in the present application, which is responsible for providing electrical signals to control the light-emitting state of the array of MicroLED chips 1. The driving circuit 6 adjusts the brightness of each MicroLED chip 1 according to the input signal, and achieves precise control of brightness through pulse modulation or direct current driving.

[0073] The driving circuit 6 is electrically connected to the wiring layer and can accurately adjust the working state of the chip according to the external control signal. The design of the circuit needs to consider factors such as current stability, driving voltage range and power consumption. Reasonable circuit design can ensure the efficiency and stability of the MicroLED light source in various applications.

[0074] Please refer to the accompanying Figure 2 The present application also provides a manufacturing method of a MicroLED chip, comprising the following steps:

[0075] S1. ISO (insulation layer etching): Forming a MicroLED epitaxial structure on a sapphire, silicon or gallium arsenide substrate and performing insulation layer etching to define the area of a single MicroLED chip 1;

[0076] In the manufacturing process of the MicroLED chip 1, the ISO step is one of the key preliminary processes. It performs insulation layer etching on the first substrate 101 to provide necessary structural support for subsequent processes and ensure the independence of each MicroLED chip 1. Insulation layer etching not only defines the area of the chip, but also provides a stable and efficient working platform for subsequent electrode deposition. The success or failure of this step directly affects the performance and electrical characteristics of the entire array of MicroLED chips 1. Therefore, precise etching process is the basis for ensuring the efficient operation of the MicroLED device.

[0077] In this embodiment, the ISO process is mainly completed through the combination of photolithography and dry etching. In this process, the first substrate 101 is first cleaned to remove surface impurities and contaminants, ensuring the accuracy and effectiveness of the etching process. Next, a layer of photoresist is coated on the surface of the first substrate 101 to form a pattern in a specific area, defining the area of each MicroLED chip 1. The exposure, development, and etching processes of the photoresist are carefully controlled to ensure that the etched area meets the design requirements and that each chip area can form an accurate structure.

[0078] Specifically, in the ISO step, first select a suitable first substrate 101 material, such as sapphire, silicon-based or gallium arsenide-based substrate. The selection of these materials not only considers their mechanical strength and thermal stability, but also ensures that they can withstand the high temperature and chemical action in the subsequent process. By epitaxial growth method, the MicroLED epitaxial structure is grown on the first substrate 101. Subsequently, a layer of insulating layer is deposited on the surface of the epitaxial structure. Common insulating materials include aluminum nitride, aluminum oxide, etc., which have excellent insulating properties and high stability.

[0079] In the photolithography process, the photoresist is exposed to a predetermined pattern using ultraviolet light exposure or electron beam exposure, etc. Then, through the development process, the unexposed part is removed, leaving the pattern to be etched. At this time, the remaining photoresist acts as a mask to protect the area of the first substrate 101 that needs to be maintained from the etching liquid. Next, dry etching (such as reactive ion etching RIE) or wet etching technology is used to etch the insulating layer, thereby exposing the chip area.

[0080] In this embodiment, the reason for using dry etching is that it can provide higher etching precision, especially suitable for the manufacture of micron-level chips. Dry etching forms a plasma by introducing gas (such as hydrogen fluoride gas, argon, fluorine gas, etc.) to etch the surface of the first substrate 101, thereby removing the unnecessary insulating layer. The etching process is affected by multiple parameters such as gas flow, pressure, power, etc., so in actual operation, these parameters need to be accurately controlled to ensure the uniformity of etching depth and etching rate.

[0081] In some embodiments, the etching depth is controlled within a few microns to ensure the independence of each MicroLED chip 1 area. Specifically, the selection of etching depth is usually adjusted according to the size, thickness requirements of the MicroLED chip 1 and the need for subsequent electrode deposition. During the etching process, it is necessary to ensure that the etching rate is uniform to avoid local over-etching or non-etching. As an option, a double-layer photoresist film is used during the etching process to increase the control precision of etching.

[0082] In this embodiment, the thickness of the insulating layer is generally controlled between 50-200 nm. Too thin thickness may result in insufficient electrical isolation, leading to mutual interference between chips; while too thick thickness may affect the deposition quality of electrodes in subsequent processes. After etching, the photoresist residue is removed by cleaning to ensure the surface of the first substrate 101 is clean, providing a stable working platform for subsequent processes.

[0083] In this scheme, the key of ISO step lies in precise etching control, which ensures the fine division of chip regions of MicroLED chip 1 array and lays a solid foundation for subsequent electrode deposition and other processes. Through the application of dry etching technology, high-precision etching effect can be achieved, ensuring that the size and shape of each chip region meet the design requirements and providing guarantee for the performance of the entire chip array.

[0084] Formula part: The etching depth control in ISO step can be calculated by the following formula:

[0085]

[0086] Where: is the etching depth (unit: μm); is the power used in etching process (unit: W); is the etching time (unit: seconds); is the gas flow (unit: sccm); is the area of etching region (unit: cm 2 ).

[0087] This formula provides the relationship between etching depth and etching process parameters, which can help process personnel adjust etching conditions according to actual needs during operation, ensuring the precision and stability of etching process.

[0088] The etching depth control needs to be precise to avoid over-etching or incomplete etching.

[0089] Dry etching can improve precision and is suitable for high-density and high-precision MicroLED chip 1 array.

[0090] The gas flow, pressure, power and other parameters in etching process need to be strictly controlled to ensure uniformity and stability.

[0091] In summary, ISO step is an indispensable step in the entire MicroLED chip 1 manufacturing process. By reasonably selecting photoresist, photolithography process and etching method, combined with precise control of process parameters, this step can ensure high efficiency, precision and reliability of MicroLED chip 1 array, laying a solid foundation for subsequent process steps.

[0092] S2. Mesa (mesa etching): mesa etching is performed on the structure of the Micro LED chip 1 by dry etching or laser etching to form independent light emitting units 102.

[0093] After the completion of the ISO, the area of the Micro LED chip 1 has been clearly divided, and the first substrate 101 surface forms an insulating isolation structure, providing a foundation for subsequent processes. In order to make each Micro LED chip 1 have an independent light emitting unit 102 structure, further MESA process is needed. The main purpose of this step is to form an independent mesa structure of the light emitting unit 102 in the area of each Micro LED chip 1, while ensuring the integrity of the p-n junction, reducing parasitic effects and improving current injection efficiency.

[0094] The quality of MESA etching directly affects the optical and electrical properties of the Micro LED chip 1 and the deposition effect of the subsequent metal electrode, so accurate control of the process parameters is particularly important. Generally, this step uses dry etching or laser etching to etch a mesa of a certain depth in the Micro LED epitaxial structure, ensuring the independence between chips and forming a structure suitable for subsequent processes.

[0095] In this embodiment, the MESA process first applies a layer of photoresist on the surface of the first substrate 101. The thickness of the photoresist is generally selected to be 1.5-3 μm to ensure the masking effect of the subsequent etching process. The thickness of the photoresist needs to be selected in combination with the etching depth and the need for sidewall protection. Too thin may cause the mask layer to be damaged during etching, while too thick may affect the verticality of etching.

[0096] After applying the photoresist, photolithography exposure and development are performed to form a mask pattern for MESA etching, so that the area to be etched is exposed. The design of the mask pattern needs to strictly match the layout of the chip array to ensure that the mesa area of each Micro LED chip 1 meets the size requirements, while avoiding uneven etching or structural defects caused by improper mask design.

[0097] Specifically, in the etching process, reactive ion etching or deep reactive ion etching methods are usually used. This process uses high-energy plasma to physically and chemically interact with the epitaxial layer, selectively removing materials to form independent Micro LED chip 1 mesas.

[0098] In some embodiments, the depth of the etching depends on the thickness of the epitaxial layer of the Micro LED chip 1, which is usually in the range of 1-5 pm, and the etching is performed below the p-type layer to ensure the integrity of the mesa structure while optimizing the current injection. Alternatively, different depths of the mesa structure etching can be achieved by adjusting the type of plasma and the flow rate of the etching gas. For example, common etching gas combinations include chlorine, argon, and trifluoromethane, etc., which can control the etching rate and sidewall angle so that the MESA structure meets the expected design.

[0099] The verticality of the etching can also be improved by reducing the radio frequency power, thereby reducing the non-uniform etching of the sidewall, and after the etching is completed, an oxygen plasma treatment is used to remove the photoresist residue to ensure the cleanliness of the mesa area.

[0100] In some embodiments, the MESA structure after etching needs to be modified by wet etching, using chemical solutions such as phosphoric acid, hydrofluoric acid, etc., to smooth the sidewall after etching to reduce surface roughness and improve the uniformity of subsequent electrode deposition. Alternatively, a plasma-assisted etching process can be used for sidewall passivation to reduce leakage current and improve the reliability of the Micro LED chip 1.

[0101] Specifically, after the etching is completed, the removal of the etching residue is required. During the etching process, some etching by-products such as chlorides or polymers may be deposited on the mesa sidewall and surface, which will affect the subsequent electrode contact performance of the Micro LED chip 1. Therefore, a method of deionized water cleaning combined with plasma treatment can effectively remove these residues to ensure that the cleanliness of the mesa structure meets the process requirements.

[0102] Generally, the MESA structure after cleaning needs to be subjected to oxidation layer growth or passivation treatment. In one possible implementation, a low-temperature oxidation method can be used to grow an oxidation layer on the MESA sidewall in the temperature range of 200-400°C to reduce surface defects and improve the adhesion of the subsequent metal electrode. The thickness of the oxidation layer is generally controlled in the range of 5-20 nm, and too thick may affect the electrode contact, while too thin may not provide sufficient passivation protection.

[0103] Alternatively, a layer of silicon nitride or silicon dioxide passivation layer can be further deposited after the growth of the oxidation layer to further optimize the interface characteristics of the MESA structure.

[0104] In this scheme, the mesa structure after MESA etching needs to meet the following design standards:

[0105] Etching depth: 1-5 pm, depending on the layer thickness of the MicroLED epitaxial structure. Sidewall angle: 80-90° to ensure the stability of the mesa structure. Surface roughness: less than 2 nm RMS to reduce electrode contact resistance. Residue removal rate: >99% to ensure the yield of subsequent processes.

[0106] In summary, the implementation of the MESA (mesa etching) process not only involves the control of etching depth, sidewall angle, and surface quality, but also needs to consider the cleaning treatment after etching, oxide layer growth, and interface passivation to optimize the optical, electrical, and structural properties of the MicroLED chip 1. By precisely controlling the etching process parameters, the mesa structure of each MicroLED chip 1 can be ensured to meet the design requirements, laying a good foundation for subsequent electrode deposition and device packaging.

[0107] S3. Ohmic contact ITO layer: Depositing an indium tin oxide (ITO) transparent conductive layer 103 on the light-emitting layer of the MicroLED chip 1 and performing annealing treatment to form ohmic contact, improving current injection efficiency;

[0108] After completing the MESA, the light-emitting unit 102 of the MicroLED chip 1 has formed an independent structure, and the profile of its p-n junction has been precisely etched, providing a physical basis for subsequent electrode contact. However, the exposed p-type region still needs to be further optimized to reduce contact resistance and improve current injection efficiency. Therefore, the deposition of the ohmic contact ITO layer becomes one of the key steps. The main purpose of this step is to deposit an indium tin oxide transparent conductive layer 103 on the p-type electrode region of the MicroLED chip 1, and to improve the ohmic contact characteristics through the annealing process to achieve efficient carrier transport.

[0109] Generally, the ITO layer not only needs to have good conductivity, but also must have high light transmittance to reduce the influence of light absorption on the light-emitting efficiency of the MicroLED device. Therefore, the preparation process of the ITO layer needs to balance between conductivity, optical properties, and interface contact characteristics. As an option, sputtering or electron beam evaporation can be used for the deposition of ITO thin film to obtain a high-quality transparent conductive layer 103.

[0110] In this embodiment, the ITO layer deposition adopts a radio frequency magnetron sputtering process to ensure the uniformity and high density of the ITO thin film. First, before deposition, the surface of the MicroLED chip 1 needs to be cleaned by plasma to remove residual oxides and organic contaminants, in order to improve the bonding quality of the ITO and the p-type GaN contact area. The cleaning process generally uses argon plasma or oxygen plasma etching to ensure that the surface cleanliness meets the deposition process requirements.

[0111] Specifically, the deposition thickness of the ITO film is generally controlled in the range of 50-200 nm, and the selection of the specific thickness needs to consider the following factors:

[0112] Too thin thickness may result in too high film resistance, affecting the uniformity of current distribution;

[0113] Too thick thickness may reduce the light transmittance of ITO, thereby affecting the light output efficiency of the MicroLED chip 1.

[0114] In one possible implementation, the working gas for ITO sputtering uses a mixed gas of argon and oxygen to control the composition and electrical properties of the ITO film. Argon is mainly used for sputtering, while oxygen can affect the oxygen content of the ITO film, thereby adjusting its electrical and optical properties. Generally, the flow ratio of oxygen is controlled in the range of 2%-10% to avoid the increase of film resistance caused by excessive oxygen content.

[0115] In this embodiment, the specific parameters of the ITO sputtering process can be calculated by the following formula:

[0116]

[0117] Wherein: is the surface resistance of the ITO film (unit: Ω / □); is the resistivity of the ITO material (unit: Ω·cm); is the thickness of the ITO layer (unit: nm).

[0118] Generally, the surface resistance of the ITO film is required to be in the range of 30-200 Ω / □ to ensure good current spreading performance. Too high surface resistance may result in uneven current density, while too low surface resistance may cause current concentration effect, affecting the reliability of the MicroLED chip 1.

[0119] After the deposition of the ITO layer, annealing treatment is needed to improve the ohmic properties of the ITO and p-type GaN contact interface. The annealing treatment is usually performed in the range of 250°C in a nitrogen or oxygen environment to reduce the contact resistance and improve the current injection efficiency. In one possible implementation, the annealing time is controlled in 10 minutes, and the higher the temperature, the shorter the annealing time, to avoid damage to the crystalline structure of the ITO film.

[0120] In some embodiments, laser-assisted annealing can be used to locally increase the temperature of the ITO and p-type GaN contact area, while reducing the impact of heat diffusion on the entire device. As an alternative, rapid thermal annealing process can also be used to improve the electrical conductivity of the ITO film and optimize its optical transmittance.

[0121] In actual process, the optical transmittance of ITO film is an important indicator. Generally, the transmittance needs to be greater than 85% (in the wavelength range of 400-700 nm) to ensure that most of the LED light can be transmitted out instead of being absorbed by the ITO layer. The transmittance can be calculated by the following formula:

[0122]

[0123] Wherein: is the optical transmittance of ITO layer (unit: %); is the surface resistance of ITO film (unit: Ω / □); is the photoconductivity of ITO film (unit: S / cm).

[0124] In one possible implementation, the optical and electrical properties of ITO film can be optimized by adjusting the doping concentration (such as doping with tin Sn). For example, the doping concentration is generally controlled in the range of 5%-15% to ensure good electrical conductivity and high transmittance.

[0125] Generally, after the deposition of ITO layer is completed, thickness uniformity test needs to be performed, usually using ellipsometer or four-probe test to evaluate the thickness distribution and electrical properties of ITO film. The uniformity error is generally required to be less than ±5% to ensure the consistency of the photoelectric properties of MicroLED array.

[0126] In summary, the deposition of ohmic contact ITO layer not only involves the preparation, thickness control and surface resistance adjustment of ITO film, but also includes annealing optimization and optical transmittance optimization. In this embodiment, by optimizing the sputtering parameters, annealing process and doping concentration, the contact resistance of MicroLED chip 1 can be significantly reduced, the carrier injection efficiency can be improved, and the light transmittance can be ensured to reach a high level, thereby improving the overall luminous efficiency and device stability.

[0127] S4. PV opening 105: forming a via on the transparent conductive layer 103 using photolithography process to expose the p-type electrode contact area;

[0128] After the deposition of ohmic contact ITO layer is completed, a uniform transparent conductive layer 103 has been formed on the surface of MicroLED chip 1 to provide a good carrier transport path. However, in order to ensure that the electrode can directly contact the p-type GaN layer and establish a stable electrical connection, it is necessary to form an opening on the ITO layer, i.e. PV opening 105 process. This step etches a via on the ITO layer through photolithography process to expose the p-type electrode contact area, so that the subsequent metal electrode can directly contact the p-GaN layer, thereby reducing the contact resistance and improving the carrier injection efficiency.

[0129] Generally, the quality of the PV opening 105 process directly affects the adhesion and contact characteristics of the subsequent metal electrode, so the size, position accuracy and etching depth of the opening need to be strictly controlled. As an option, wet etching or dry etching can be used to achieve selective removal of the ITO layer. Specifically, wet etching is suitable for uniform opening of a large area, while dry etching is more suitable for high-precision and small-size micro-hole structures.

[0130] In this embodiment, the PV opening 105 process uses a photolithography process combined with wet etching to ensure high selectivity of the ITO layer etching while avoiding damage to the p-GaN layer. First, a layer of positive photoresist is applied to the surface of the MicroLED chip 1 with the deposited ITO layer, and the thickness of the photoresist is generally controlled at 1-3 μm to ensure good masking ability and provide sufficient etch resistance during etching. The selection of the photoresist needs to consider its etch resistance and bonding ability with the ITO layer. Common types of photoresist include ultraviolet photoresist or deep ultraviolet photoresist to match different exposure wavelength requirements.

[0131] After the photoresist is applied, ultraviolet light exposure is performed to transfer the pattern of the PV opening 105 to the photoresist layer through a mask plate. The control of exposure energy is crucial, and generally the exposure dose is between 100-300 mJ / cm 2 After exposure, development is performed using a development solution (such as TMAH, Tetra-Methyl Ammonium Hydroxide) to remove the photoresist in the exposed area and form a mask structure for the PV opening 105.

[0132] As an option, oxygen plasma treatment can be used after development to remove residual photoresist and organic contaminants to improve the reliability of the subsequent etching process. This treatment process is usually carried out in a low-pressure environment of 50-200 mTorr, with a plasma power of 50-300 W and a time of 30-90 seconds to ensure that the residual amount of photoresist is minimized.

[0133] In this embodiment, wet etching is used for etching the ITO layer, and the etching liquid is a mixture of hydrochloric acid and deionized water with a volume ratio of 1:10-1:20 to control the etching rate and selectivity. The etching temperature is usually controlled at 25-50°C, and the etching time is adjusted according to the thickness of the ITO layer and the etching rate. Generally, the etching rate is 10-50 nm / s.

[0134] The etching rate can be calculated by the following formula:

[0135]

[0136] where: Etching rate of ITO (unit: nm / s); Volume of hydrochloric acid in etching solution (unit: mL); Concentration of hydrochloric acid (unit: mol / L); Etching time (unit: seconds); Area of etching region (unit: cm 2 ).

[0137] In one possible implementation, the etching rate can be optimized by adjusting the ratio of hydrochloric acid and deionized water to avoid the problem of poor contact caused by etching too deep or too shallow. As an option, a buffered HF solution can be used instead of hydrochloric acid to obtain higher etching uniformity and reduce damage to the p-GaN layer.

[0138] In some embodiments, if the size of the MicroLED chip 1 is small and higher etching precision is required, dry etching can be used. This method uses plasma etching technology to achieve high anisotropic etching in a low-temperature environment. The RIE etching gas is generally a mixture of chlorine and oxygen to optimize the etching rate and sidewall angle. The etching cavity pressure is generally controlled at 5-50 mTorr, the radio frequency power is set to 100-500 W, and the etching time is adjusted according to the thickness of the ITO layer.

[0139] After the PV opening 105 etching is completed, photoresist removal and cleaning treatment are required. Generally, the photoresist is removed using acetone or a stripping liquid, and the stripping time is generally 5-15 minutes, and the stripping temperature is controlled at 60-80°C. Subsequently, deionized water is used for cleaning to remove possible etching byproducts and ensure the cleanliness of the opening area.

[0140] To further optimize the contact interface, in some embodiments, plasma treatment can be used to perform Ar / O2 plasma bombardment in the PV opening 105 area to enhance the adhesion of the metal electrode and reduce the contact resistance. This treatment is usually performed at low power (50-200 W) for 30-90 seconds to avoid damage to the p-GaN layer.

[0141] Generally, the size of the PV opening 105 needs to meet the design requirements to ensure that the metal electrode can be well covered. The diameter of the opening is generally controlled at 1-10 pm, and the specific size is optimized according to the chip design. Too small opening may result in the electrode unable to effectively contact the p-GaN layer, while too large opening may affect the uniformity of current distribution, thereby reducing the overall performance of the MicroLED.

[0142] In summary, the PV opening 105 step involves multiple critical links such as photolithography, etching, and cleaning. In this embodiment, by optimizing the photolithography mask design, etching process parameters, and cleaning method, the size of the PV opening 105 can be ensured to be accurate and the sidewall clean, and a good contact interface is provided for the subsequent deposition of metal electrodes, thereby improving the electrical performance and luminous efficiency of the MicroLED chip 1.

[0143] S5. Metal electrode deposition: depositing metal electrodes in the PV opening 105 area and the n-type electrode area, the material of the metal electrode being selected from aluminum, gold, or silver, and formed by evaporation or sputtering deposition.

[0144] After completing the PV opening 105 step, the p-type electrode contact area of the MicroLED chip 1 has been exposed, providing a path for the subsequent deposition of electrode material. In order to ensure that the MicroLED chip 1 has good current injection capability, metal electrodes need to be deposited in the p-type electrode area and the n-type electrode area. The main purpose of this step is to form a stable ohmic contact to reduce the electrode contact resistance, while providing a reliable current transmission path, thereby optimizing the overall performance of the MicroLED.

[0145] Generally, the selection of metal electrodes needs to consider factors such as electrical conductivity, work function matching, thermal stability, and adhesion. As an option, the metal electrode material typically includes aluminum, gold, or silver, which all have low resistivity and can form good ohmic contacts with the p-GaN or n-GaN layers of the MicroLED. In addition, in some embodiments, in order to improve the adhesion of the electrode to the semiconductor surface, titanium, chromium, or nickel may be introduced as an adhesion layer under the main electrode metal layer to enhance the stability of the electrode.

[0146] In this embodiment, the deposition of metal electrodes uses electron beam evaporation or magnetron sputtering process to ensure that the metal layer has high density and uniformity. Before electrode deposition, the MicroLED chip 1 needs to be plasma cleaned first to remove surface organic contaminants and oxides, improving the adhesion of the metal electrode. This cleaning process typically uses argon plasma at a radio frequency power of 50-300 W and a chamber pressure of 50-200 mTorr, with a cleaning time of 30-90 s.

[0147] Specifically, the deposition thickness of the metal electrode is generally controlled to be 50-300 nm to ensure sufficient conductivity while avoiding mechanical stress problems caused by excessive thickness. As an option, the p-type electrode typically uses a Ni / Au double-layer structure, with the Ni layer as an adhesion layer and the Au layer as the main conductive layer. This structure can form a stable low-contact-resistance ohmic contact at an annealing temperature of 400-600°C.

[0148] The sheet resistance of the metal electrode can be calculated by the following formula:

[0149]

[0150] Wherein: Rsheet is the surface resistance of the metal film (unit: Ω / □); ρ is the resistivity of the metal electrode material (unit: Ω·cm); t is the thickness of the metal electrode (unit: nm).

[0151] In one possible implementation, the material of the n-type electrode can be selected as a Ti / Al double-layer structure, in which the Ti layer is used to improve the adhesion with the n-GaN layer, and the Al layer serves as the main conductive layer to reduce the contact resistance. Generally, the deposition thickness of the electrode of this structure is slightly thicker than that of the p-type electrode, to ensure better conductivity.

[0152] In some embodiments, a conformal metal deposition technique can be used to ensure the uniformity of the electrode layer covering the area of the PV opening 105. As an option, the metal evaporation can be performed at different angles by means of inclined angle deposition, to optimize the electrode coverage effect, especially on small-size MicroLED chips 1. This method can improve the uniformity of the metal layer.

[0153] In this embodiment, the deposition process of the metal electrode involves the following key parameters: deposition rate: generally controlled at 0.1-2 nm / s to ensure film uniformity; deposition pressure: generally in the range of 1-10 mTorr to optimize sputtering uniformity; first substrate 101 temperature: adjustable between room temperature and 300°C to control the film structure and stress.

[0154] After the deposition of the metal electrode, annealing treatment is needed to improve the contact properties of the metal with the p-GaN or n-GaN. The annealing is usually performed in a nitrogen or argon environment at 300°C, with a time control of 300 seconds to optimize the carrier injection capability of the metal-semiconductor interface.

[0155] The contact resistance optimized by annealing can be calculated by the following formula:

[0156]

[0157] Wherein: Rc is the contact resistance of the metal-semiconductor (unit: Ω·cm 2 ); V is the applied voltage (unit: V); I is the current flowing through the electrode (unit: A); A is the contact area (unit: cm 2 ); The electrode spacing is in cm.

[0158] Generally, the contact resistance of the p-type electrode needs to be controlled at 10 -3 -5 Ω·cm 2 to ensure sufficient current injection efficiency, and the contact resistance of the n-type electrode needs to be less than 10 -6 Ω·cm 2 to reduce current loss.

[0159] In one possible implementation, a passivation layer can be deposited after the metal electrode to improve the oxidation resistance of the electrode. Alternatively, a silicon nitride or silicon dioxide layer can be deposited on the surface of the metal electrode to enhance the long-term stability of the metal electrode and reduce the influence of environmental factors on the contact resistance.

[0160] In some embodiments, in order to optimize the optical performance of the Micro LED chip 1, a reflective layer can be designed on the metal electrode, for example, using an Ag / Ni or Ag / Au multilayer structure to improve the light reflectivity and thus improve the light extraction efficiency of the chip.

[0161] In summary, metal electrode deposition involves multiple key links such as selection of electrode material, optimization of deposition process, control of annealing treatment, and surface passivation. In the present embodiment, by reasonably selecting the metal layer structure, optimizing the film resistance, and controlling the contact resistance, the current injection efficiency and long-term stability of the Micro LED chip 1 can be significantly improved, providing a good electrical interface for subsequent chip packaging and driving circuit 6 connection.

[0162] Please refer to the accompanying Figure 3 - the accompanying drawings, Figure 4 The present application also provides a method for assembling a Micro LED chip into a Unit, comprising the following steps,

[0163] Sa. Mass transfer: using laser peeling or mechanical handling, the Micro LED chip 1 is transferred from the first substrate 101 to the second substrate 2, and is bonded by permanent bonding glue 3, with a transfer precision controlled within ±2μm;

[0164] After the manufacture of the Micro LED chip 1 is completed, the individual chips are still distributed on the original first substrate 101. In order to realize large-scale packaging of light source arrays, it is necessary to transfer these independent Micro LED chips 1 to the second substrate 2, ensure accurate arrangement, and have good electrical connection conditions, and be bonded by permanent bonding glue 3. Therefore, mass transfer is an indispensable key step in the assembly process of the Micro LED chip 1, and its quality directly affects the yield, light emission uniformity and stability of the final device.

[0165] ​Generally, the core goal of mass transfer is high precision, high yield and high speed, while avoiding damage or position deviation caused by external force. As an option, laser stripping or mechanical handling can be used to accurately transfer the MicroLED chip 1 from the first substrate 101 to the second substrate 2, and bond through the permanent bonding glue 3, and ensure that it maintains good optical and electrical performance in the subsequent packaging process.

[0166] In this embodiment, mass transfer uses laser stripping technology to improve the precision and reliability of the transfer process. First, after the MicroLED chip 1 is manufactured, the back of the first substrate 101 needs to be pre-treated with laser. This step uses ultraviolet laser or excimer laser to reduce the adhesion between the MicroLED epitaxial layer and the first substrate 101, thereby facilitating subsequent stripping operations.

[0167] Specifically, during the laser stripping process, an excimer laser with a wavelength of 248nm or 308nm is used, with an energy density of 200-500mJ / cm 2 The energy of the laser needs to be accurately controlled. Too high may cause damage to the MicroLED chip 1, and too low may not completely strip the chip.

[0168] The stripped MicroLED chip 1 is transferred to the intermediate carrier through the elastic medium (such as PDMS, polydimethylsiloxane). In this way, the surface tension of the PDMS material can provide sufficient adsorption force to keep the chip in a specific position, and will not cause mechanical stress to the chip surface during the release process.

[0169] In one possible implementation, in order to reduce transfer errors, alignment marks can be prepared in advance on the second substrate 2 to assist the visual recognition system in accurate alignment. These marks can be prepared by metal deposition or photolithography etching, and their size is generally controlled at 2-5μm to ensure sufficient alignment accuracy.

[0170] In some embodiments, if higher transfer accuracy is required, electrostatically assisted transfer can be used to adjust the adsorption force of the PDMS carrier using an electrostatic field, so that the accuracy of the chip transfer is controlled within ±2μm. As an option, microstructures can also be applied to the PDMS carrier to increase the contact area and optimize the adsorption performance.

[0171] In this embodiment, after mass transfer, the MicroLED chip 1 needs to be reflowed and solidified on the second substrate 2 to further enhance adhesion and optimize electrode contact characteristics. This process is usually carried out in an environment of 150°C, with a time control of 30 minutes to ensure the bonding quality between the chip and the second substrate 2.

[0172] To evaluate the stability of mass transfer, the transfer yield can be calculated. Generally, the transfer yield needs to be maintained above 95% to ensure the production efficiency and cost control of the final device. In one possible implementation, infrared detection or optical microscopic detection can be used to detect the transferred chips to confirm whether there are cracks, displacement or poor adhesion.

[0173] In some embodiments, if the size of the MicroLED chip 1 is small (e.g., less than 10 μm), microbubble adsorption transfer can be used. The surface tension of the liquid microbubble is used to enable precise adsorption and release of the chip in a liquid environment. As an option, ultrasonic vibration assisted technology can be combined to reduce the mechanical stress of the chip during the transfer process and improve the overall transfer precision.

[0174] After completing the mass transfer, drying treatment is needed to remove the solvent or adhesion medium that may be left over during the transfer process. Generally, this process uses low-temperature baking (100°C) or vacuum drying (-100 Torr) for 10-60 minutes to ensure that the chip surface is free of residual materials that affect subsequent processes.

[0175] Sb. Flat layer 4 formation: filling the gap of the array of MicroLED chips 1 with a flat layer 4 selected from polyimide or benzocyclobutene, and forming by spin coating and baking solidification;

[0176] After completing the deposition of the metal electrodes of the MicroLED chips 1 and the mass transfer, the topography of the chip surface can have some unevenness, especially in the electrode area and the chip edge, which can form a step structure. This surface unevenness can affect subsequent processes such as photolithography, packaging and electrical interconnection, so a flat layer 4 needs to be formed on the chip surface. This layer not only fills the concave-convex areas of the surface to improve the flatness of the overall surface, but also can serve as an insulating layer or a passivation layer to reduce the impact of the environment on the chip and optimize the optical properties.

[0177] Generally, the selection of the flat layer 4 needs to consider factors such as refractive index, dielectric constant, thermal stability and mechanical strength. As an option, silicon dioxide, silicon nitride or organic polymer materials can be used to meet different packaging and application requirements.

[0178] In this embodiment, the flat layer 4 is deposited using a chemical vapor deposition or spin coating process to ensure the uniformity and controllability of the thickness of the medium layer. In a specific implementation, the surface of the MicroLED chip 1 is first pretreated and cleaned to remove possible organic contaminants and particulate matter to improve the adhesion of the medium layer. Hydrofluoric acid etching or oxygen plasma treatment is usually used during the cleaning process to remove the surface oxide layer and improve the interface cleanliness.

[0179] If SiO2 is used as the planarization layer 4, its deposition thickness is generally controlled at 300-1000 nm to provide sufficient coverage while avoiding stress accumulation caused by excessive thickness. To optimize the planarization effect, a multi-step deposition and etching process can be used, i.e., after depositing a layer of dielectric, the high parts are removed using plasma etching or chemical mechanical polishing to make the final surface more uniform.

[0180] If polyimide is selected as the planarization layer 4, a spin coating process can be used, i.e., first coating the liquid PI material on the surface of the Micro LED chip 1, and then curing at 200°C to form a uniform insulating layer. The thickness of the polyimide film is controlled at 500-2000 nm to provide better planarization effect while having certain mechanical strength and thermal stability.

[0181] In this embodiment, to improve the optical properties of the planarization layer 4, the refractive index can be further adjusted based on SiO2 or Si3N4 to reduce interface light reflection loss. Specifically, aluminum oxide or titanium oxide can be introduced into the dielectric layer to adjust its refractive index to 1.6-2.2, thereby optimizing the light extraction efficiency of the Micro LED chip 1.

[0182] To evaluate the planarization effect, the surface uniformity can be calculated using the following formula:

[0183]

[0184] Wherein:

[0185] is the surface uniformity (unit: %); and are the highest point and the lowest point of the dielectric layer surface (unit: nm); is the average thickness (unit: nm).

[0186] In general, the surface uniformity needs to be controlled within 5% to ensure the stability of subsequent packaging and optical performance. To further improve the reliability of the dielectric layer, a moisture-resistant passivation layer can be deposited on the surface of the planarization layer, such as aluminum nitride or silicon nitride, to reduce the impact of environmental humidity on the stability of the chip.

[0187] In this embodiment, after forming the planarization layer 4, heat treatment is needed to optimize the film density and reduce internal stress. The heat treatment is usually carried out in a nitrogen or argon environment at 300°C for 60 minutes to ensure the stability and electrical insulation of the dielectric layer.

[0188] In summary, the formation of the planarization layer 4 involves multiple key steps, such as material selection, deposition process, uniformity optimization, and heat treatment. In this embodiment, by optimizing the deposition parameters of the SiO2, Si3N4, or PI layer, adjusting the refractive index and surface uniformity, and combining the passivation layer and heat treatment process, the flatness and stability of the Micro LED chip 1 can be effectively improved, providing a reliable foundation for subsequent packaging and optical optimization.

[0189] Sc. Wiring layer formation: depositing a metal wiring layer on the planarization layer 4 to achieve electrical connection between the Micro LED chip 1 and the driving circuit 6; after completing the metal electrode deposition, mass transfer, and planarization layer 4 formation, in order to ensure that the Micro LED array has stable current driving capability, a PV wiring layer needs to be further formed on the chip surface. This wiring layer not only serves to connect the anode and cathode of the Micro LED, but also serves to achieve electrical connection with the external driving circuit 6 and optimize current distribution to improve overall light emission uniformity and device stability.

[0190] Generally, the design of the PV wiring layer needs to consider factors such as resistance, parasitic capacitance, thermal stability, and signal integrity. As an option, the PV wiring layer can adopt a multi-metal layer structure, such as aluminum, copper, or silver, to reduce resistance, while titanium, chromium, or nickel can be used as an adhesion layer to enhance the mechanical stability of the wiring.

[0191] In this embodiment, the formation of the PV wiring layer adopts a process combining photolithography and metal sputtering to ensure high precision and low impedance of the wiring. First, spin-coat photoresist on the surface of the planarization layer 4, the spin-coating process is usually controlled at 1500-5000 rpm.

[0192] During exposure, ultraviolet or deep ultraviolet light sources are used, and the exposure dose is generally controlled at 100-500 mJ / cm 2 to ensure complete development of the pattern. After development, the wiring area is subjected to plasma etching or wet etching to remove the metal in the uncovered area to form the final wiring pattern.

[0193] Specifically, the metal thickness of the PV wiring layer is generally controlled at 200-1000 nm to provide sufficient conductivity while avoiding mechanical stress accumulation due to excessive thickness.

[0194] In one possible implementation, in order to reduce the parasitic resistance of the wiring, a protective layer such as silicon nitride or silicon dioxide can be further deposited on the metal layer to prevent oxidation and environmental corrosion. As an option, the thickness of the protective layer is generally controlled at 50-300 nm to ensure sufficient durability while avoiding excessive thickness affecting the capacitance characteristics of the wiring.

[0195] In some embodiments, if the PV wiring layer needs to carry a large current, a double-layer metal structure such as Ti / Al, Ti / Cu or Cr / Au can be used, in which the bottom layer of metal is used to improve adhesion, and the top layer of metal is used to reduce resistance.

[0196] In this embodiment, in order to optimize the signal integrity of the PV wiring layer, a low-impedance loop can be designed in the wiring structure to reduce RC delay and signal attenuation.

[0197] In some embodiments, in order to reduce cross-interference, a ground shield layer can be introduced in the wiring spacing, such as using a Ti / Au or Ti / Cu structure, to reduce signal crosstalk and parasitic coupling effects. As an option, the spacing of the ground shield layer is generally controlled to be 5-20 μm to ensure the electromagnetic compatibility of the wiring.

[0198] In this embodiment, after the PV wiring layer is formed, high-temperature annealing is needed to optimize the crystalline quality of the metal layer and reduce interface defects. The annealing temperature is usually in the range of 250°C, and the duration is 60 minutes, to improve the electrical stability and mechanical strength of the wiring.

[0199] In summary, the formation of the PV wiring layer involves multiple key links such as photolithography process, metal deposition, etching process, passivation protection and signal optimization. In this embodiment, by reasonably selecting the metal layer structure, optimizing the wiring resistance, adjusting the characteristic impedance and introducing the ground shield, the current distribution uniformity and signal integrity of the MicroLED chip 1 can be effectively improved, providing a stable electrical connection scheme for the subsequent packaging and driving circuit 6.

[0200] Sd. Substrate circuit connection: connecting the wiring layer and the driving circuit 6 by wire bonding or flip-chip bonding to complete the electrical connection of the MicroLED unit;

[0201] After the formation of the PV wiring layer, the MicroLED chip 1 and the external driving circuit 6 still need to establish a stable electrical connection to ensure that the device can work normally. Therefore, the substrate circuit connection needs to be completed on the second substrate 2, which not only involves the interconnection of the MicroLED array and the driving chip, but also needs to optimize the signal integrity, current distribution and thermal management to improve the overall performance and reliability of the device.

[0202] In general, the design of the substrate circuit needs to consider factors such as electrical conductivity, thermal expansion matching, connection strength and parasitic parameter control. As an option, the substrate can be made of glass, silicon or high-thermal-conductivity PCB (such as metal-core PCB, MCPCB) to meet different application requirements. At the same time, in order to reduce the contact resistance, the wiring of the substrate circuit is usually made of copper, silver or aluminum, and is treated with surface gold plating or palladium plating to improve the corrosion resistance and soldering reliability of the electrode.

[0203] In this embodiment, the connection between the electrodes of the MicroLED chip 1 and the substrate circuitry utilizes a flip-chip bonding process to reduce parasitic inductance and optimize current distribution. First, solder balls are formed on the electrode pads of the PV wiring layer. The solder balls are typically 10 to 50 μm in diameter and made of indium, tin-silver, or gold-tin alloy to ensure soldering quality and mechanical strength.

[0204] In one possible implementation, to improve solder ball wettability, the substrate electrodes can be coated with flux before soldering to remove oxides and enhance soldering stability. Flux typically consists of rosin and an activator, with a coating thickness of 1 to 5 μm to ensure uniform coverage without affecting soldering accuracy.

[0205] In some embodiments, eutectic soldering can be used to reduce soldering thermal stress. During the soldering process, the solder and the substrate electrode material form a eutectic alloy, reducing interfacial stress and improving soldering strength. Alternatively, AuSn eutectic soldering temperatures are typically controlled between 280°C and 320°C, with a soldering time of 10 to 60 seconds to optimize soldering quality.

[0206] In this embodiment, to reduce signal loss and cross-interference, a shielding layer, such as titanium / gold or copper, can be introduced on the substrate circuit to provide better electromagnetic compatibility. The thickness of the shielding layer is generally controlled to be 50 to 300 nm, and its characteristic impedance can be calculated using the following formula:

[0207] In some embodiments, if the size of the MicroLED chip 1 is small (e.g., less than 10 μm), nano-soldering technology can be used to ensure the stability of high-density wiring. As an alternative, gold nanowires or silver nanowires can be used, and their contact resistance is generally controlled within 10 -3 ~10 -5 Ω·cm 2 , to optimize signal transmission performance.

[0208] In this embodiment, after the substrate circuit is connected, reflow soldering is required to ensure sufficient melting and solidification of the solder joints. The reflow soldering temperature profile typically includes preheating (150°C), main soldering (300°C), and cooling (100-150°C). The entire process lasts 30-180 seconds to ensure uniform soldering and mechanical strength.

[0209] In general, the contact resistance needs to be controlled within 10 -3 Ω·cm 2 In one possible implementation, X-ray inspection or scanning acoustic microscopy can be used to analyze the welding quality to confirm whether there are voids, cracks or lack of fusion defects in the weld.

[0210] In some embodiments, to optimize the thermal management of the second substrate 2 circuit, a heat dissipation layer can be added at the bottom of the second substrate 2, for example, a metal heat dissipation sheet (Al, Cu) or a heat conductive graphite sheet, to enhance the heat dissipation capacity. Alternatively, the thickness of the heat conductive layer is generally controlled at 50-500 pm.

[0211] In the present embodiment, after the circuit connection of the second substrate 2 is completed, a high-temperature aging test is needed to evaluate the long-term reliability of the soldering and interconnection structure. The aging test is usually carried out in an environment of 85°C / 85% RH, and the test time is 48-168 hours, to ensure the stability of the second substrate 2 circuit in long-term use.

[0212] In summary, the circuit connection of the second substrate 2 involves multiple key links such as solder ball formation, flip-chip soldering, flux coating, reflow soldering, and reliability testing. In the present embodiment, by optimizing the soldering process, adjusting the wiring impedance, and introducing a heat dissipation structure, the electrical connection stability and long-term reliability of the MicroLED chip 1 can be significantly improved, providing an efficient and stable electrical interconnection scheme for subsequent packaging and system integration.

[0213] Se. Packaging: The MicroLED chip 1 is packaged with silicone or epoxy resin material, and is cured by ultraviolet light curing or thermal curing.

[0214] Although embodiments of the present application have been shown and described, it is to be understood that various modifications, substitutions, replacements and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A MicroLED device with a strip-shaped LED light source, characterized in that: include, A MicroLED chip (1) array, wherein the MicroLED chip (1) array is composed of a plurality of MicroLED chips (1); A second substrate (2), the MicroLED chip array being fixed on the surface of the second substrate (2); A transparent conductive layer (103) is deposited on the surface of the MicroLED chip (1) array to form a current transmission path; A metal electrode (104) is provided in an electrode region of the MicroLED chip (1) array and is electrically connected to the transparent conductive layer (103); A flat layer (4) covering the gaps of the MicroLED chip (1) array to provide surface flatness, wherein the flat layer (4) is selected from polyimide or benzocyclobutene and is formed by spin coating and baking; A wiring layer (5), provided on the flat layer (4), for achieving electrical connection between the MicroLED chip and an external circuit; An encapsulation layer covering the wiring layer (5) and the surface of the MicroLED chip (1) array to provide environmental protection, wherein the encapsulation layer is cured by ultraviolet light curing or thermal curing; A driving circuit (6), used for providing an electrical signal to control the light-emitting state of the MicroLED chip (1) array, and electrically connected to the wiring layer; The light-emitting area of ​​the MicroLED chip (1) array is arranged perpendicular to the scanning direction of the strip light source.

2. The MicroLED device of a strip-shaped LED light source according to claim 1, characterized in that: The MicroLED chip (1) array adopts a common anode connection method to improve current uniformity.

3. The MicroLED device of a strip LED light source according to claim 1, characterized in that: The luminous uniformity of the light source is achieved by adjusting the spacing between the MicroLED chips (1) and the driving current.

4. A method for manufacturing a MicroLED chip, characterized in that: A MicroLED device applied to a strip LED light source according to any one of claims 1 to 3 comprises the following steps: S1.ISO: Forming a MicroLED epitaxial structure on a sapphire, silicon-based or gallium arsenide substrate and performing insulating layer etching to define the area of ​​a single MicroLED chip (1); S2.MESA: performing mesa etching on the MicroLED chip (1) structure by dry etching or laser etching to form an independent light-emitting unit 102; S3. Ohmic contact ITO layer: depositing an indium tin oxide transparent conductive layer (103) on the light-emitting layer of the MicroLED chip (1), and performing annealing treatment to form an ohmic contact to improve current injection efficiency; S4. PV opening (105): forming a through hole on the transparent conductive layer (103) using a photolithography process to expose the p-type electrode contact area; S5. Metal electrode deposition: depositing metal electrodes in the PV opening (105) region and the n-type electrode region, wherein the material of the metal electrodes is selected from aluminum, gold or silver and is formed by evaporation or sputtering deposition.

5. A method for assembling MicroLED chips into units, characterized in that: The method for manufacturing a MicroLED chip according to claim 4 comprises the following steps: Sa. Mass transfer: using laser lift-off or mechanical handling to transfer the MicroLED chip (1) from the first substrate (101) to the second substrate (2), and bonding them with a permanent bonding adhesive (3); Sb. Formation of a flat layer (4): filling a flat layer (4) in the gaps of the MicroLED chip (1) array, wherein the flat layer (4) is selected from polyimide or benzocyclobutene and is formed by spin coating and baking; Sc. Wiring layer formation: depositing a metal wiring layer on the flat layer (4) to achieve electrical connection between the MicroLED chip (1) and the driving circuit (6); Sd. Substrate circuit connection: Connect the wiring layer to the driving circuit (6) through metal wires to complete the electrical connection of the MicroLED unit; Se. Encapsulation: Encapsulate the MicroLED chip (1) using silicone or epoxy resin material.

6. The method for assembling MicroLED chips into a unit according to claim 5, characterized in that: The mass transfer uses laser lift-off technology to transfer the MicroLED chip (1), and the transfer accuracy is controlled within ±2μm.

7. The method for assembling MicroLED chips into a unit according to claim 5, wherein: The wiring layer is made of a material selected from copper, aluminum or gold and is formed by sputtering or electroplating.

8. The method for assembling MicroLED chips into a unit according to claim 5, wherein: The circuit connection of the second substrate (2) adopts a reflow process or a eutectic bonding process to ensure a low resistance connection between the wiring layer and the driving circuit (6); The driving circuit (6) is manufactured on the second substrate (2). The driving circuit (6) is a part of the wiring. The driving circuit (6) leads out the pad and is connected to the outside world.

9. The method for assembling MicroLED chips into a unit according to claim 5, wherein: The encapsulation layer is cured by ultraviolet light curing or thermal curing to improve the environmental resistance of the encapsulation layer.

Images