Deposition mask and deposition apparatus including the same

Abstract

A deposition mask and a deposition apparatus including the deposition mask are provided. The deposition mask includes: a substrate including a cell region and a mask frame region other than the cell region; and a mask film disposed in each of the cell regions. A cross-sectional structure of the mask film includes a plurality of layers in which inorganic layers and metal layers are alternately stacked with each other.

Description

Technical Field

[0001] Embodiments relate to a deposition mask and a deposition apparatus including the deposition mask. Background Art

[0002] Wearable devices that focus at a distance close to the user's eyes have been developed in the form of glasses or helmets. For example, the wearable device may be a head-mounted display (HMD) device or AR glasses. The wearable device provides the user with augmented reality (hereinafter referred to as "AR") images or virtual reality (hereinafter referred to as "VR") images.

[0003] Wearable devices such as HMD devices or AR glasses require a display specification of at least 2000 PPI (pixels per inch) so that users can use it for a long time without feeling dizzy. To this end, organic light-emitting diode on silicon (OLEDoS) technology is emerging as a high-resolution small organic light-emitting display device. Organic light-emitting diode on silicon (OLEDoS) is a technology for providing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided.

[0004] To manufacture high-resolution display panels with a resolution of 2000 PPI, high-resolution deposition masks are required. To this end, silicon masks that can form masks with the precision of semiconductor processes are being researched and developed.

[0005] The silicon mask may be a mask that deposits an inorganic layer pattern on a silicon substrate and allows the inorganic layer pattern to be used as a mask film. Such a silicon mask may have a problem in that damage occurs when cleaning the mask due to the thin mask film.

[0006] A silicon mask can form a coating film on a silicon substrate and form a mask film by patterning the coating film. Although such a silicon mask has high mechanical strength and is easy to clean, the mask film made of the coating film has a high coefficient of thermal expansion (CTE), so there is a high possibility of misalignment with the backplane substrate as the substrate to be deposited, and there is a possibility of deposition defects caused by deviations in the coating film thickness during the process.

[0007] It should be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts, or realizations that were not known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0008] Embodiments provide a deposition mask that has high mechanical strength and is easy to clean and is capable of improving alignment accuracy by reducing a coefficient of thermal expansion (CTE), and a deposition apparatus including the same.

[0009] According to an embodiment, a deposition mask may include a substrate including a plurality of unit regions and a mask frame region other than the plurality of unit regions; and a mask film disposed in each of the plurality of unit regions. The cross-sectional structure of the mask film may include a multilayer structure in which a plurality of inorganic layers and a plurality of metal layers are alternately stacked.

[0010] The cross-sectional structure of the mask film may include a first metal layer, a first inorganic layer disposed on the first metal layer, a second metal layer disposed on the first inorganic layer, a second inorganic layer disposed on the second metal layer, a third metal layer disposed on the second inorganic layer, and a third inorganic layer disposed on the third metal layer.

[0011] When viewed from a cross section in which the mask film is cut, the first metal layer may be disposed on a lowermost layer of the mask film, and the third inorganic layer may be disposed on an uppermost layer of the mask film.

[0012] The first inorganic layer may include silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of.

[0013] The second inorganic layer may include silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of.

[0014] The third inorganic layer may include silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of.

[0015] The materials of the first inorganic layer, the second inorganic layer, and the third inorganic layer may be the same.

[0016] Materials of the first inorganic layer, the second inorganic layer, and the third inorganic layer may be different from each other.

[0017] The first metal layer may include at least one material of copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar.

[0018] The second metal layer may include at least one material of copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar.

[0019] The third metal layer may include at least one material of copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar.

[0020] The materials of the first metal layer, the second metal layer, and the third metal layer may be the same.

[0021] Materials of the first metal layer, the second metal layer, and the third metal layer may be different from each other.

[0022] According to an embodiment, a deposition mask may include: a substrate including a plurality of unit regions and a mask frame region other than the plurality of unit regions; and a mask film disposed in each of the plurality of unit regions. The mask film may include a mixed layer in which at least one inorganic layer and at least one metal layer are mixed.

[0023] The mixed layer may include a mixed material containing silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), at least one inorganic material among amorphous silicon (a-Si) and aluminum oxide and at least one metal material among copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti) and Invar alloy.

[0024] The substrate may be a silicon substrate.

[0025] According to an embodiment, a deposition apparatus may include: a chamber; a deposition source disposed in the chamber; a mask disposed in the chamber between a first substrate and the deposition source; and a mask support disposed between the deposition source and the mask to support at least a portion of the mask. The mask may include: a second substrate including a plurality of unit regions and a mask frame region other than the plurality of unit regions; and a mask film disposed in each of the plurality of unit regions. The cross-sectional structure of the mask film may include a multilayer structure in which a plurality of inorganic layers and a plurality of metal layers are alternately stacked.

[0026] The cross-sectional structure of the mask film may include a first metal layer, a first inorganic layer disposed on the first metal layer, a second metal layer disposed on the first inorganic layer, a second inorganic layer disposed on the second metal layer, a third metal layer disposed on the second inorganic layer, and a third inorganic layer disposed on the third metal layer.

[0027] When viewed from a cross section in which the mask film is cut, the first metal layer may be disposed on a lowermost layer of the mask film, and the third inorganic layer may be disposed on an uppermost layer of the mask film.

[0028] The first inorganic layer, the second inorganic layer and the third inorganic layer may include silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x The first metal layer, the second metal layer, and the third metal layer may include at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar alloy.

[0029] According to embodiments, a deposition mask and a deposition apparatus including the same may have high mechanical strength and be easy to clean, and improve accuracy of alignment by reducing a coefficient of thermal expansion (CTE).

[0030] According to embodiments, the deposition mask and the deposition apparatus may also reduce deposition defects caused by thickness deviation of the mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the present disclosure, illustrate embodiments, in which:

[0032] Figure 1 is an exploded perspective view showing a display device according to one embodiment;

[0033] Figure 2 is a block diagram showing a display device according to one embodiment;

[0034] Figure 3 is a schematic diagram of an equivalent circuit of a first sub-pixel according to one embodiment;

[0035] Figure 4 is a plan view showing an example of a display panel according to one embodiment;

[0036] Figure 5 and Figure 6 It shows Figure 4 A plan view of an embodiment of a display area;

[0037] Figure 7 It is along Figure 5 A schematic cross-sectional view showing an example of a display panel taken along line I1-I1';

[0038] Figure 8is a schematic perspective view showing a head-mounted display according to one embodiment;

[0039] Figure 9 It shows Figure 8 An exploded perspective view of an example of a head-mounted display;

[0040] Figure 10 is a schematic perspective view showing a head-mounted display according to one embodiment;

[0041] Figure 11 is a schematic perspective view of a mask according to one embodiment;

[0042] Figure 12 is a schematic plan view of a mask according to one embodiment;

[0043] Figure 13 is a configuration diagram of a deposition apparatus according to one embodiment;

[0044] Figure 14 and Figure 15 is a diagram showing a stacked structure of a mask film according to one embodiment;

[0045] Figures 16 to 20 is a process cross-sectional view illustrating a method for manufacturing a mask according to one embodiment; and

[0046] Figures 21 to 25 is a diagram illustrating a method of forming a mask film as a mixed layer according to one embodiment. DETAILED DESCRIPTION

[0047] The embodiments will be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals represent the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0048] For the purpose of describing the embodiments of the present disclosure, some components not related to the description may not be provided.

[0049] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0050] Furthermore, the phrase “in a plan view” means when the subject portion is viewed from above, and the phrase “in a schematic sectional view” means when a schematic cross section taken by vertically cutting the subject portion is viewed from the side.

[0051] The term "overlap" or "overlapping" means that a first object can be above or below a second object, or to one side of the second object, and vice versa. Additionally, the term "overlap" may include layering, stacking, facing, extending over, covering, or partially covering, or any other suitable term that will be appreciated and understood by one of ordinary skill in the art.

[0052] The expression "non-overlapping" may include meanings such as "separate from," "separated from," or "offset from," as well as any other suitable equivalents that will be appreciated and understood by one of ordinary skill in the art.

[0053] The term facing or facing can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object, although still facing each other, can be understood as indirectly opposite to each other.

[0054] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. are used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It should be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the device shown in the figures is flipped, a device that is "below" or "below" another device can be placed "above" the other device. Thus, the illustrative term "below" can include both a lower orientation and an upper orientation. The device can also be oriented in other directions, and thus the spatially relative terms can be interpreted differently depending on the orientation.

[0055] When an element is referred to as being “connected” or “coupled” to another element, it may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements disposed therebetween.

[0056] It will be further understood that when the terms “comprises,” “comprising,” “have,” “having,” “includes,” and / or “including” are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0057] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or to facilitate description and illustration. For example, when discussing a "first element" in the specification, it can be referred to as a "second element" or a "third element" without departing from the teachings of this document, and the "second element" and "third element" can be referred to in a similar manner.

[0058] As used herein, the terms "about" or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art in view of the measurement in question and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within about ±30%, ±20%, ±10%, ±5% of the stated value.

[0059] In this specification, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purposes of its meaning and description. For example, "A and / or B" may be understood to mean A, B, or A and B. The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or." In this specification, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for the purposes of its meaning and description. For example, "at least one of A and B" may be understood to mean A, B, or A and B.

[0060] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0061] Figure 1 is an exploded perspective view showing a display device according to one embodiment. Figure 2 is a block diagram illustrating a display device according to one embodiment.

[0062] Reference Figure 1 and Figure 2, the display device 10 according to one embodiment is a device that displays a moving image or a still image. Within the scope of the present disclosure, the display device 10 according to one embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 according to one embodiment can be used as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. For example, within the scope of the present disclosure, the display device 10 according to one embodiment can be applied to smart watches, watch phones, head-mounted displays (HMDs) for realizing virtual reality and augmented reality, etc.

[0063] A display device 10 according to one embodiment may include a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0064] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or rounded with an optional curvature. The planar shape of the display panel 100 is not limited to a quadrilateral and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but embodiments are not limited thereto.

[0065] like Figure 2 As shown, the display panel 100 may include a display area DAA displaying an image and a non-display area NDA not displaying an image.

[0066] The display area DAA may include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0067] A plurality of pixels PX may be arranged or disposed in a matrix in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and be disposed in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and be disposed in the first direction DR1.

[0068] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0069] The plurality of pixels PX include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. 1 and FIG. 2 can be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. 2 ). Figure 7 For example, a plurality of pixel transistors of the data driver 700 may be formed of a complementary metal oxide semiconductor (CMOS).

[0070] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to any one of a plurality of write scan lines GWL, any one of a plurality of control scan lines GCL, any one of a plurality of bias scan lines GBL, any one of a plurality of first emission control lines EL1, any one of a plurality of second emission control lines EL2, and any one of a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light-emitting element according to the data voltage.

[0071] The non-display area NDA may include a scan driver 610 , an emission driver 620 , and a data driver 700 .

[0072] The scan driver 610 may include a plurality of scan transistors, and the emission driver 620 may include a plurality of light emitting transistors. Figure 7 ) are formed on a plurality of scanning transistors and a plurality of light emitting transistors. For example, the plurality of scanning transistors and the plurality of light emitting transistors can be formed by CMOS. Figure 2 6 shows that the scan driver 610 is provided on the left side of the display area DAA and the emission driver 620 is provided on the right side of the display area DAA, but the present embodiment is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be provided on both the left and right sides of the display area DAA.

[0073] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400 and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS and sequentially output the bias scan signal to the bias scan line GBL.

[0074] The emission driver 620 may include a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a first emission control signal based on the emission timing control signal ECS and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 622 may generate a second emission control signal based on the emission timing control signal ECS and sequentially output the second emission control signal to the second emission control line EL2.

[0075] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, the plurality of data transistors may be formed of CMOS.

[0076] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into analog data voltages according to the data timing control signal DCS and outputs the analog data voltages to the data lines DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltages may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0077] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is a thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface or surfaces of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer having high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al), or graphite.

[0078] The circuit board 300 may be electrically connected to the first pad portion PDA1 of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film (see FIG. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board having a flexible material or a flexible film. Figure 1 100, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be the first pad portion PDA1 of the circuit board 300 connected to the display panel 100 by using a conductive adhesive member (see FIG. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ) is connected to the opposite end of the other end.

[0079] The timing control circuit 400 can receive digital video data DATA and timing signals input from the outside. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0080] The power supply circuit 500 can generate a plurality of panel driving voltages according to the power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD and a third driving voltage VINT and provide them to the display panel 100. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0081] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface or surfaces of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be provided to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be provided to the display panel 100 through the circuit board 300.

[0082] As an example, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be provided in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on a semiconductor substrate SSUB (see FIG. 1 ) by a semiconductor process. Figure 7 ) is formed on. For example, a plurality of timing transistors and a plurality of power transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be provided between the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0083] Figure 3 is a schematic diagram of an equivalent circuit of a first sub-pixel according to one embodiment.

[0084] Reference Figure 3 The first subpixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, the first subpixel SP1 can be connected to a first drive voltage line VSL, a second drive voltage line VDL, and a third drive voltage line VIL. A first drive voltage VSS corresponding to a low potential voltage is applied to the first drive voltage line VSL, a second drive voltage VDD corresponding to a high potential voltage is applied to the second drive voltage line VDL, and a third drive voltage VINT corresponding to an initialization voltage is applied to the third drive voltage line VIL. For example, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0085] The first subpixel SP1 may include a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor CP1 , and a second capacitor CP2 .

[0086] The light-emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE may be proportional to the driving current Ids. The light-emitting element LE may be arranged between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer arranged between the first electrode and the second electrode, but the embodiment is not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0087] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter referred to as a "driving current Ids") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 may include a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0088] The second transistor T2 may be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Thus, a data voltage of the data line DL may be applied to one electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0089] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, since the gate electrode and source electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0090] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the driving current Ids of the first transistor T1 can be provided to the light emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0091] The fifth transistor T5 may be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Thus, the third drive voltage VINT of the third drive voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0092] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Thus, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0093] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0094] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0095] The first node N1 is a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0096] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but embodiments are not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. For example, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, while each of the remaining transistors may be an N-type MOSFET.

[0097] Despite Figure 3 FIG. 4 shows that the first sub-pixel SP1 may include six transistors T1 to T6 and two capacitors CP1 and CP2 , but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to FIG. Figure 3 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3 The number of transistors and the number of capacitors are shown.

[0098] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be substantially combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is the same as that of the first sub-pixel SP1. Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 may be omitted in the specification.

[0099] Figure 4 is a plan view illustrating an example of a display panel according to one embodiment.

[0100] Reference Figure 4 The display area DAA of the display panel 100 according to one embodiment may include a plurality of pixels PX arranged or disposed in a matrix form. The non-display area NDA of the display panel 100 according to one embodiment may include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0101] The scan driver 610 may be provided on a first side of the display area DAA, and the emission driver 620 may be provided on a second side of the display area DAA. For example, the scan driver 610 may be provided on one side or one side of the display area DAA in the first direction DR1, and the emission driver 620 may be provided on the other side of the display area DAA in the first direction DR1. For example, the scan driver 610 may be provided on the left side of the display area DAA, and the emission driver 620 may be provided on the right side of the display area DAA. However, embodiments are not limited thereto, and the scan driver 610 and the emission driver 620 may be provided on both the first side and the second side of the display area DAA.

[0102] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through a conductive adhesive member. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side or sides of the display area DAA in the second direction DR2.

[0103] The first pad portion PDA1 may be disposed outside the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 may be disposed closer to an edge of the display panel 100 than the data driver 700.

[0104] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for inspecting whether the display panel 100 is operating normally. The plurality of second pads PD2 may be connected to a jig or probe pins during an inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0105] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of the plurality of first pads PD1. The first distribution circuit 710 can be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side or sides of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0106] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0107] Figure 5 and Figure 6 It shows Figure 4 A plan view of an embodiment of a display area.

[0108] Reference Figure 5 and Figure 6 Each of the pixels PX may include a first emission area EA1, a second emission area EA2, and a third emission area EA3, the first emission area EA1 being the emission area of the first sub-pixel SP1, the second emission area EA2 being the emission area of the second sub-pixel SP2, and the third emission area EA3 being the emission area of the third sub-pixel SP3.

[0109] Each of the first, second, and third emission areas EA1, EA2, and EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in a plan view.

[0110] The maximum length of the first emission area EA1 in the first direction DR1 may be less than the maximum length of the second emission area EA2 and the maximum length of the third emission area EA3 in the first direction DR1. The maximum length of the second emission area EA2 and the maximum length of the third emission area EA3 in the first direction DR1 may be substantially the same.

[0111] The maximum length of the first emission area EA1 in the second direction DR2 may be greater than the maximum length of the second emission area EA2 in the second direction DR2 and the maximum length of the third emission area EA3 in the second direction DR2. The maximum length of the second emission area EA2 in the second direction DR2 may be less than the maximum length of the third emission area EA3 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 may be greater than the maximum length of the third emission area EA3 in the second direction DR2.

[0112] In a plan view, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a structure such as Figure 5 and Figure 6The six straight lines shown in FIG form a hexagonal shape, but the embodiment is not limited thereto. In a plan view, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than the hexagonal shape, a circular shape, an elliptical shape, or an irregular shape.

[0113] like Figure 5 As shown, in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The second emission area EA2 and the third emission area EA3 may be adjacent to each other in the second direction DR2. The area of the first emission area EA1, the area of the second emission area EA2, and the area of the third emission area EA3 may be different.

[0114] For example, Figure 6 As shown, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2, and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0115] The first emission area EA1 may emit a first light, the second emission area EA2 may emit a second light, and the third emission area EA3 may emit a third light. Here, the first light may be light of a blue wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0116] exist Figure 5 and Figure 6 In the embodiment, each of the plurality of pixels PX may include three emission areas EA1, EA2, and EA3, but the embodiment is not limited thereto. For example, each of the plurality of pixels PX may include four emission areas.

[0117] The plane of the emission area of the plurality of pixels PX is not limited to Figure 5 and Figure 6For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged or disposed in the first direction DR1, or in a diamond shape in which the emission regions are arranged or disposed. Structure or Figure 6 The emitting regions shown in FIG. 1 have a hexagonal shape in a plan view and are arranged or disposed side by side in a hexagonal structure.

[0118] Figure 7 It is along Figure 5 Schematic cross-sectional view showing an example of a display panel taken along line I1-I1'.

[0119] Reference Figure 7 The display panel 100 may include a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizer POL.

[0120] The semiconductor backplane SBP may include a semiconductor substrate SSUB having a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0121] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the aforementioned first-type impurities. For example, if the first-type impurities are P-type impurities, the second-type impurities may be N-type impurities. For example, if the first-type impurities are N-type impurities, the second-type impurities may be P-type impurities.

[0122] Each of the plurality of well regions WA may include a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0123] The lower insulating layer BINS may be disposed between the gate electrode GE and the well area WA. The side insulating layer SINS may be disposed on the side surface of the gate electrode GE. The side insulating layer SINS may be disposed on the lower insulating layer BINS.

[0124] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side or on the side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0125] Each of the plurality of well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA may be increased. Therefore, the length of the channel region CH of each pixel transistor PTR may be increased, thereby preventing punch-through and hot carrier phenomena that may be caused by a short channel.

[0126] The first semiconductor insulating layer SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be made of a silicon carbon nitride (SiCN) or silicon oxide (SiO x ) is formed in an inorganic layer, but the embodiment is not limited thereto.

[0127] The second semiconductor insulating layer SINS2 may be provided on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be formed of a silicon oxide (SiO x ) is formed in an inorganic layer, but the embodiment is not limited thereto.

[0128] A plurality of contact terminals CTE may be provided on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, source area SA, and drain area DA of each of the pixel transistors PTR via a hole passing through the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these.

[0129] The third semiconductor insulating layer SINS3 may be provided on the side surface of each of the plurality of contact terminals CTE. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of a silicon oxide (SiO x ) is formed in an inorganic layer, but the embodiment is not limited thereto.

[0130] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate (e.g., a polyimide substrate). In this case, the thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can bend or flex.

[0131] The light emitting element back plate EBP may include a plurality of conductive layers ML1 to ML8, a plurality of via portions VA1 to VA9, and a plurality of insulating layers INS1 to INS9. The light emitting element back plate EBP may include a plurality of insulating layers INS1 to INS9 disposed above, below, or between the first to eighth conductive layers ML1 to ML8.

[0132] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing Figure 4 The circuit of the first subpixel SP1 is shown. For example, the first to sixth transistors T1 to T6 are formed on the semiconductor backplane SBP, and the first to sixth transistors T1 to T6 are connected to the first capacitor CP1 and the second capacitor CP2 via the first to eighth conductive layers ML1 to ML8. The drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE are also connected via the first to eighth conductive layers ML1 to ML8.

[0133] The first insulating layer INS1 may be disposed on the semiconductor backplane SBP. Each first through-hole portion VA1 may penetrate the first insulating layer INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each first conductive layer ML1 may be disposed on the first insulating layer INS1 and may be connected to the first through-hole portion VA1.

[0134] The second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each second through-hole portion VA2 may penetrate the second insulating layer INS2 and be connected to the exposed first conductive layer ML1. Each second conductive layer ML2 may be disposed on the second insulating layer INS2 and may be connected to the second through-hole portion VA2.

[0135] The third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each third through-hole portion VA3 may penetrate the third insulating layer INS3 and be connected to the exposed second conductive layer ML2. Each third conductive layer ML3 may be disposed on the third insulating layer INS3 and may be connected to the third through-hole portion VA3.

[0136] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each fourth through-hole portion VA4 may penetrate the fourth insulating layer INS4 and be connected to the exposed third conductive layer ML3. Each fourth conductive layer ML4 may be disposed on the fourth insulating layer INS4 and may be connected to the fourth through-hole portion VA4.

[0137] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each fifth through-hole portion VA5 may penetrate the fifth insulating layer INS5 and be connected to the exposed fourth conductive layer ML4. Each fifth conductive layer ML5 may be disposed on the fifth insulating layer INS5 and may be connected to the fifth through-hole portion VA5.

[0138] The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each sixth through-hole portion VA6 may penetrate the sixth insulating layer INS6 and be connected to the exposed fifth conductive layer ML5. Each sixth conductive layer ML6 may be disposed on the sixth insulating layer INS6 and may be connected to the sixth through-hole portion VA6.

[0139] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each seventh through-hole portion VA7 may penetrate the seventh insulating layer INS7 and be connected to the exposed sixth conductive layer ML6. Each seventh conductive layer ML7 may be disposed on the seventh insulating layer INS7 and may be connected to the seventh through-hole portion VA7.

[0140] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each eighth through-hole portion VA8 may penetrate the eighth insulating layer INS8 and be connected to the exposed seventh conductive layer ML7. Each eighth conductive layer ML8 may be disposed on the eighth insulating layer INS8 and may be connected to the eighth through-hole portion VA8.

[0141] The first to eighth conductive layers ML1 to ML8 and the first to eighth via portions VA1 to VA8 may be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth via portions VA1 to VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any one of them. The first to eighth insulating layers INS1 to INS8 may be made of substantially the same material. The first to eighth insulating layers INS1 to INS8 may be made of a silicon oxide (SiO x ) is formed in an inorganic layer, but the embodiment is not limited thereto.

[0142] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be respectively greater than the thickness of the first through-hole portion VA1, the second through-hole portion VA2, the third through-hole portion VA3, the fourth through-hole portion VA4, the fifth through-hole portion VA5 and the sixth through-hole portion VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5 and the thickness of the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be about The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be about 100 nm. And the thickness of each of the first through hole portion VA1, the second through hole portion VA2, the third through hole portion VA3, the fourth through hole portion VA4, the fifth through hole portion VA5 and the sixth through hole portion VA6 may be approximately

[0143] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh through-hole portion VA7 and the thickness of the eighth through-hole portion VA8, respectively. The thickness of each of the seventh through-hole portion VA7 and the eighth through-hole portion VA8 may be greater than the thickness of the first through-hole portion VA1, the thickness of the second through-hole portion VA2, the thickness of the third through-hole portion VA3, the thickness of the fourth through-hole portion VA4, the thickness of the fifth through-hole portion VA5, and the thickness of the sixth through-hole portion VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately The thickness of each of the seventh through hole portion VA7 and the eighth through hole portion VA8 may be about

[0144] The ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 may be formed of a silicon oxide (SiO x ) is formed in an inorganic layer, but the embodiment is not limited thereto.

[0145] Each of the ninth through-hole portions VA9 may penetrate the ninth insulating layer INS9 and be connected to the exposed eighth conductive layer ML8. The ninth through-hole portion VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any one of them. The thickness of the ninth through-hole portion VA9 may be approximately

[0146] The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include light emitting elements LE, each of which includes a reflective electrode layer RL, a tenth insulating layer INS10 and an eleventh insulating layer INS11, a tenth through-hole portion VA10, a first electrode AND, a light emitting stack IL, a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0147] The reflective electrode layer RL may be disposed on the ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. Figure 7 As shown, the reflective electrode layer RL may include first to fourth reflective electrodes RL1 , RL2 , RL3 , and RL4 .

[0148] Each first reflective electrode RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth through-hole portion VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0149] Each second reflective electrode RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the second reflective electrode RL2 may include aluminum (Al).

[0150] Each third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0151] Each fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0152] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately And the thickness of the second reflective electrode RL2 may be about

[0153] The tenth insulating layer INS10 may be provided on the ninth insulating layer INS9. The tenth insulating layer INS10 may be provided between the reflective electrode layers RL adjacent to each other in the horizontal direction. Alternatively, the tenth insulating layer INS10 may be provided on the reflective electrode layer RL in the third sub-pixel SP3. The tenth insulating layer INS10 may be made of a silicon oxide (SiO x ) is formed in an inorganic layer, but the embodiment is not limited thereto.

[0154] The eleventh insulating layer INS11 may be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 may be made of a silicon oxide (SiO x ), but the embodiment is not limited thereto. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL, of light emitted from the light emitting element LE, passes.

[0155] In order to match the resonance distance of light emitted from the light-emitting element LE in at least one of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may not be disposed under or below the first electrode AND of the first subpixel SP1. The first electrode AND of the first subpixel SP1 may be disposed directly on the reflective electrode layer RL. The eleventh insulating layer INS11 may be disposed under or below the first electrode AND of the second subpixel SP2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed under or below the first electrode AND of the third subpixel SP3.

[0156] In summary, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, Figure 7 1 and 2. It is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, but the present specification is not limited thereto.

[0157] Although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in the embodiment, a twelfth insulating layer disposed under or below the first electrode AND of the first sub-pixel SP1 may be added. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer may be disposed under or below the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer may be disposed under or below the first electrode AND of the third sub-pixel SP3.

[0158] Each tenth through-hole portion VA10 may penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second sub-pixel SP2 and the third sub-pixel SP3 and may be connected to the exposed reflective electrode layer RL. The tenth through-hole portion VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of them. The thickness of the tenth through-hole portion VA10 in the second sub-pixel SP2 may be less than the thickness of the tenth through-hole portion VA10 in the third sub-pixel SP3.

[0159] The first electrode AND of each light-emitting element LE can be disposed on the eleventh insulating layer INS11 and connected to the tenth through-hole portion VA10. The first electrode AND of each light-emitting element LE can be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth through-hole portion VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth through-hole portions VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound including any of these. For example, the first electrode AND of each light-emitting element LE can be titanium nitride (TiN).

[0160] The pixel defining layer PDL may be disposed on a portion of the first electrode AND of each light emitting element LE. The pixel defining layer PDL may cover an edge of the first electrode AND of each light emitting element LE. The pixel defining layer PDL may be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0161] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting laminate IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting laminate IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting laminate IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0162] The pixel defining layer PDL may include first to third pixel defining layers PDL1, PDL2, and PDL3. The first pixel defining layer PDL1 may be disposed on the edge of the first electrode AND of each light emitting element LE, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of a silicon oxide (SiO x ), but the embodiment is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have an area of about 100 nm. thickness.

[0163] When the first, second, and third pixel defining layers (PDL1, PDL2, and PDL3) are formed as a single pixel defining layer, the height of the single pixel defining layer increases, potentially causing the first encapsulating inorganic layer (TFE1) to be cut due to step coverage. Step coverage refers to the ratio of the amount of film applied on a sloped portion to the amount applied on a flat portion. The lower the step coverage, the greater the likelihood that the film will be cut on the sloped portion.

[0164] Therefore, to prevent the first encapsulating inorganic layer TFE1 from being cut due to step coverage, the first, second, and third pixel defining layers (PDL1, PDL2, and PDL3) can have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining layer (PDL1) can be greater than the widths of the second and third pixel defining layers (PDL2 and PDL3), and the width of the second pixel defining layer (PDL2) can be greater than the width of the third pixel defining layer (PDL3). The width of the first pixel defining layer (PDL1) refers to the horizontal length of the first pixel defining layer (PDL1) as defined in the first and second directions (DR1, DR2).

[0165] Each of the plurality of trenches TRC may penetrate the first, second, and third pixel defining layers PDL1, PDL2, and PDL3. In addition, each of the plurality of trenches TRC may penetrate the eleventh insulating layer INS11. The tenth insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0166] At least one trench TRC may be provided between adjacent sub-pixels SP1, SP2, and SP3. Figure 7 It is shown that two trenches TRC are provided between adjacent sub-pixels SP1 , SP2 , and SP3 , but the present embodiment is not limited thereto.

[0167] The light emitting stack IL may include a plurality of intermediate layers. Figure 7 The light emitting stack IL is shown to have a three-series structure including a first stack IL1, a second stack IL2, and a third stack IL3, but the embodiment is not limited thereto. For example, the light emitting stack IL may have a two-series structure including two intermediate layers.

[0168] In the three-series structure, the light emitting stack IL may have a series structure including a plurality of stacks IL1, IL2, and IL3 that emit different lights. For example, the light emitting stack IL may include a first stack IL1 that emits a first light, a second stack IL2 that emits a third light, and a third stack IL3 that emits a second light. The first stack IL1, the second stack IL2, and the third stack IL3 may be sequentially stacked.

[0169] The first stack IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting the first light, and a first electron transport layer are sequentially stacked. The second stack IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting the third light, and a second electron transport layer are sequentially stacked. The third stack IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting the second light, and a third electron transport layer are sequentially stacked.

[0170] A first charge generation layer for providing charges to the second stack IL2 and electrons to the first stack IL1 may be provided between the first stack IL1 and the second stack IL2. The first charge generation layer may include an N-type charge generation layer for providing electrons to the first stack IL1 and a P-type charge generation layer for providing holes to the second stack IL2. The N-type charge generation layer may include a dopant of a metal material.

[0171] A second charge generation layer for supplying charges to the third stack IL3 and electrons to the second stack IL2 may be provided between the second and third stacks IL2 and IL3. The second charge generation layer may include an N-type charge generation layer supplying electrons to the second stack IL2 and a P-type charge generation layer supplying holes to the third stack IL3.

[0172] The first stack IL1 can be arranged on the first electrode AND and the pixel defining layer PDL, and can be arranged on the bottom surface of each groove TRC. Due to the groove TRC, the first stack IL1 can be cut off between adjacent sub-pixels SP1, SP2 and SP3. The second stack IL2 can be arranged on the first stack IL1. Due to the groove TRC, the second stack IL2 can be cut off between adjacent sub-pixels SP1, SP2 and SP3. A cavity ESS or empty space can be provided between the first stack IL1 and the second stack IL2. The third stack IL3 can be arranged on the second stack IL2. The third stack IL3 is not cut off by the groove TRC and can be arranged to cover the second stack IL2 in each groove TRC. For example, in a three-series structure, each of the multiple grooves TRC can be a structure for cutting off the first stack IL1 to the second stack IL2, the first charge generation layer and the second charge generation layer of the display element layer EML between the adjacent sub-pixels SP1, SP2 and SP3. In the two-tandem structure, each trench TRC may be a structure for cutting off the charge generation layer provided between the lower intermediate layer and the upper intermediate layer, and the lower intermediate layer.

[0173] To stably cut off the first stack IL1 and the second stack IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To cut off the first to third stacks IL1, IL2, and IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure may be provided in place of the grooves TRC. For example, instead of the grooves TRC, an inverted tapered partition wall may be provided on the pixel defining layer PDL.

[0174] The number of stacked layers IL1, IL2 and IL3 emitting different light is not limited to Figure 7The number shown. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for providing electrons to one intermediate layer and charges to the other intermediate layer may be provided between the two intermediate layers.

[0175] Figure 7 It is shown that the first to third stacks IL1, IL2 and IL3 are all arranged in the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the embodiment is not limited thereto. For example, the first stack IL1 can be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, the second stack IL2 can be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third stack IL3 can be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. In this case, the first to third color filters CF1, CF2 and CF3 of the optical layer OPL can be omitted.

[0176] The second electrode CAT may be disposed on the third stack IL3. The second electrode CAT may be disposed on the third stack IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the microcavity effect may improve the luminous efficiency in each of the first to third sub-pixels SP1, SP2, and SP3.

[0177] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0178] The first encapsulation inorganic layer TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be formed to include a material selected from silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ) of a material may be alternately stacked on each other. The first encapsulation inorganic layer TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0179] The second encapsulating inorganic layer TFE2 may be disposed on the first encapsulating inorganic layer TFE1. The second encapsulating inorganic layer TFE2 may be made of titanium oxide (TiO x ) or aluminum oxide (AlO x ) is formed, but the embodiment is not limited thereto. The second encapsulation inorganic layer TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic layer TFE2 may be less than the thickness of the first encapsulation inorganic layer TFE1.

[0180] The organic layer APL may be a layer for increasing interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL may be an organic layer including a material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0181] The optical layer OPL may include a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filler layer FIL. The plurality of color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the organic layer APL.

[0182] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit the first light, for example, light in a blue wavelength band. The blue wavelength band may be in the range of about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit the first light among the light emitted from the first emission area EA1.

[0183] The second color filter CF2 may overlap with the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit the second light, for example, light in a green wavelength band. The green wavelength band may be in the range of about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit the second light in the light emitted from the second emission area EA2.

[0184] The third color filter CF3 may overlap the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit a third light, such as light in a red wavelength band. The red wavelength band may be in a range of approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 may transmit the third light in the light emitted from the third emission area EA3.

[0185] A plurality of lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light directed to the front of the display device 10. Each of the plurality of lenses LNS may have a convex cross-sectional shape in an upward direction.

[0186] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a selectable refractive index such that light propagates in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer containing a material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0187] The cover layer CVL can be disposed on the filling layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. If the cover layer CVL is a glass substrate, it can be attached to the filling layer FIL. In this case, the filling layer FIL can be used to bond the cover layer CVL. If the cover layer CVL is a glass substrate, it can serve as a packaging substrate. If the cover layer CVL is a polymer resin, it can be directly applied to the filling layer FIL.

[0188] The polarizer POL may be provided on one or more surfaces of the cover layer CVL. The polarizer POL may be a structure for preventing visibility reduction caused by reflection of external light. The polarizer POL may include a linear polarizer and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter wave plate), but embodiments are not limited thereto. However, if the first to third color filters CF1, CF2, and CF3 sufficiently overcome the visibility reduction caused by reflection of external light, the polarizer POL may be omitted.

[0189] Figure 8 is a schematic perspective view showing a head-mounted display according to one embodiment. Figure 9 It shows Figure 8 An exploded perspective view of an example of a head-mounted display.

[0190] Reference Figure 8 and Figure 9 According to one embodiment, a head mounted display 1000 may include a first display device 10_1, a second display device 10_2, a display device housing 1100, a display device housing 1200, a first eyepiece 1210, a second eyepiece 1220, a head mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600, and Figure 8 and Figure 9Directions X, Y, Z are shown.

[0191] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 and Figure 2 The display devices 10 described are the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 may be omitted.

[0192] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0193] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0194] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. Figure 8 and Figure 9 As shown in FIG, the display device housing 1100 has a horizontal length in the X-axis direction, a vertical length in the Y-axis direction, and a thickness in the Z-axis direction. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via the connector.

[0195] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. For example, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0196] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The display device housing 1200 is provided to cover one open surface of the display device housing 1100. The display device housing 1200 may include a first eyepiece 1210 and a second eyepiece 1220, where the user's left eye is provided, and where the user's right eye is provided. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately provided, but the embodiment is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0197] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0198] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the display device housing 1200 are respectively kept set on the left eye and the right eye of the user. Figure 10 As shown, the head-mounted display 1000 may be provided with a glasses frame instead of the head-mounted band 1300 .

[0199] The head-mounted display 1000 may also include a battery for power supply, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0200] Figure 10 is a schematic perspective view showing a head-mounted display according to one embodiment.

[0201] Reference Figure 10According to one embodiment, the head-mounted display 1000_1 may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one embodiment may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the display device housing 1200_1.

[0202] The display device housing 1200_1 may house the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the user's right eye through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user may view an augmented reality image, which is a combination of a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020, through the right eye.

[0203] Figure 10 The display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, but embodiments are not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the user's left eye. As an example, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 with both the left eye and the right eye.

[0204] Figure 11 is a schematic perspective view of a mask according to one embodiment. Figure 12 is a schematic plan view of a mask according to one embodiment. Figure 11 1 is a schematic perspective view showing a state where one unit mask UM is separated from a plurality of unit masks UM. Figure 11 and Figure 12 The mask MK of the embodiment shown can be used to deposit a reference Figure 7 For example, the light emitting stack IL may be configured to emit light of different colors in the sub-pixels SP1 to SP3.

[0205] Reference Figure 11 and Figure 12 , the mask MK according to the present embodiment may be a shadow mask in which the mask film MM is provided on the silicon substrate 1700. The mask MK according to the embodiment may be referred to as a "silicon mask."

[0206] According to an embodiment, the mask MK may include a silicon substrate 1700, and the mask film MM may be provided on the silicon substrate 1700. The mask films MM may be respectively provided in the cell regions 1710 arranged or provided in a matrix form, and each cell region 1710 may be surrounded by a mask rib region 1721. The mask rib region 1721 may support the mask film MM.

[0207] The mask film MM may be a portion of the unit mask UM provided in each cell region 1710 .

[0208] The silicon substrate 1700 may include a plurality of cell regions 1710 and a mask frame region 1720 excluding the cell regions 1710. The mask frame region 1720 may include a mask rib region 1721 surrounding each cell region 1710 and an outer frame region 1722 disposed at the outermost periphery of the silicon substrate 1700. The mask frame MF may be disposed in the mask frame region 1720. The mask frame MF may include a mask rib 7211 (see FIG. 1 ) surrounding the cell regions 1710. Figure 13 ).

[0209] The mask rib region 1721 may be a region that separates the unit regions 1710. For example, the unit regions 1710 may be arranged or disposed in a matrix form, and the mask ribs 7211 (see FIG. 17A ) disposed in the mask rib region 1721 may be arranged or disposed in a matrix form. Figure 13 ) may surround the outside of the mask film MM provided in each cell region 1710 .

[0210] A cell opening COP and a cell mask UM masking at least a portion of the cell opening COP may be provided in each cell region 1710 of the silicon substrate 1700 .

[0211] A plurality of cell openings COP may penetrate the mask frame MF along a thickness direction (eg, third direction DR3 ) of the mask MK. The cell openings COP may be formed by partially etching the silicon substrate 1700 from the back side.

[0212] Each of the unit masks UM may include a mask film MM, and the mask film MM may include a mask opening.

[0213] The mask opening of each mask film MM may be referred to as a “hole” or a “mask hole.” The mask opening may penetrate the unit mask UM along a thickness direction (eg, third direction DR3 ) of the mask MK.

[0214] One unit mask UM may be used in the deposition process of one display panel 100. In the present disclosure, the term "unit mask UM" may be replaced with a term such as "mask unit UM."

[0215] Figure 13is a configuration diagram of a deposition apparatus according to one embodiment.

[0216] Reference Figure 13 According to one embodiment, a deposition apparatus may include a chamber 1810, a deposition source DS disposed within the chamber 1810, a mask MK disposed between a first substrate 1820 and the deposition source DS within the chamber 1810, and a mask supporter 1840 disposed between the deposition source DS and the mask MK to support at least a portion of the mask MK.

[0217] According to one embodiment, the mask MK may include a silicon substrate 1700 (or a second substrate 1700) and a mask film MM, wherein the silicon substrate 1700 includes a plurality of unit regions 1710 and a mask frame region 1720 other than the plurality of unit regions 1710, the mask film MM is arranged at each unit region 1710, and the cross-sectional structure of the mask film MM may be configured as a multilayer in which a plurality of inorganic layers and a plurality of metal layers may be alternately stacked on each other, or may be configured as a mixed layer in which at least one inorganic material and at least one metal are mixed.

[0218] Figure 13 The first substrate 1820 shown may be a reference Figures 1 to 10 Therefore, the description of the first substrate 1820 will be referred to. Figures 1 to 10 The description of the display panel 100 is replaced.

[0219] Figure 13 The second substrate 1700 shown may be a reference Figures 11 to 12 Therefore, the silicon substrate 1700 will be described with reference to Figures 11 to 12 The description of the silicon substrate 1700 replaces the description of the second substrate 1700.

[0220] The mask support 1840 can be used to support the mask MK and fix the mask MK at the bottom of the mask MK. For example, the mask support 1840 can include an electrostatic chuck. According to one embodiment, the mask support 1840 includes a first support area 1841 that supports the mask rib area 1721 and a second support area 1842 that supports the outer frame area 1722. However, the mask support 1840 may not support the mask rib area 1721, and for example, the first support area 1841 may be omitted.

[0221] Figure 13 1830 shown in FIG. 1 is a fixing member that fixes the first substrate 1820 and may be configured as an electrostatic chuck, for example.

[0222] In the deposition apparatus according to one embodiment, the mask film MM of the mask MK is configured as a multilayer in which a plurality of inorganic layers and a plurality of metal layers are alternately stacked on each other, or as a mixed layer in which at least one inorganic material and at least one metal are mixed. Figures 14 and 15 Such a stacked structure of the mask film MM is described in detail.

[0223] Figure 14 is a diagram showing a stacked structure of a mask film according to one embodiment. For example, Figure 14 The illustrated mask film MM is configured as a multilayer in which a plurality of inorganic layers and a plurality of metal layers may be alternately stacked on one another.

[0224] According to one embodiment, the cross-sectional structure of the mask film MM may include a first metal layer 1811, a first inorganic layer 1821 arranged on the first metal layer 1811, a second metal layer 1812 arranged on the first inorganic layer 1821, a second inorganic layer 1822 arranged on the second metal layer 1812, a third metal layer 1813 arranged on the second inorganic layer 1822, and a third inorganic layer 1823 arranged on the third metal layer 1813.

[0225] In the illustrated example, the first to third inorganic layers 1821 , 1822 , and 1823 are described as a plurality of inorganic layers, but the number of layers including the inorganic layers is not limited thereto.

[0226] In the illustrated example, the first to third metal layers 1811 , 1812 , and 1813 are described as a plurality of metal layers, but the number of layers including the metal layers is not limited thereto.

[0227] Although not shown, according to one embodiment, the cross-sectional structure of the mask film MM may include multiple layers including two inorganic layers and three metal layers. In this case, the inorganic layers and the metal layers may be alternately stacked on each other.

[0228] Although not shown, according to one embodiment, the cross-sectional structure of the mask film MM may include a plurality of layers including three inorganic layers and two metal layers. In this case, the inorganic layers and the metal layers may be alternately stacked on each other.

[0229] Although not shown, according to one embodiment, the cross-sectional structure of the mask film MM may include multiple layers including two inorganic layers and two metal layers. In this case, the inorganic layers and the metal layers may be alternately stacked on each other.

[0230] Although not shown, according to one embodiment, the cross-sectional structure of the mask film MM may include multiple layers including one or more inorganic layers and one or more metal layers. For example, the mask film MM may include one inorganic layer and one metal layer. For example, the mask film MM may include one inorganic layer and two metal layers. For example, the mask film MM may include two inorganic layers and one metal layer. According to one embodiment, when viewed from a cross-section of the mask film MM, the first metal layer 1811 is disposed on the lowermost layer of the mask film MM, and the third inorganic layer 1823 is disposed on the uppermost layer.

[0231] According to one embodiment, the first inorganic layer 1821 may include a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of .

[0232] According to one embodiment, the second inorganic layer 1822 may include a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of .

[0233] According to one embodiment, the third inorganic layer 1823 may include a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of.

[0234] According to one embodiment, the materials of the first to third inorganic layers 1821 , 1822 , and 1823 may be the same.

[0235] According to one embodiment, the materials of the first to third inorganic layers 1821, 1822, and 1823 may be different. For example, at least two layers selected from the first to third inorganic layers 1821, 1822, and 1823 may include inorganic layers of different materials.

[0236] According to one embodiment, the first metal layer 1811 may include at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar.

[0237] According to one embodiment, the second metal layer 1812 may include at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar.

[0238] According to one embodiment, the third metal layer 1813 may include at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar.

[0239] According to one embodiment, the materials of the first to third metal layers 1811 , 1812 , and 1813 may be the same.

[0240] According to one embodiment, the materials of the first to third metal layers 1811, 1812, and 1813 may be different. For example, at least two layers selected from the first to third metal layers 1811, 1812, and 1813 may include metal layers of different materials.

[0241] Figure 15 19 is a diagram illustrating a stacked structure of a mask film according to an embodiment. For example, the mask film MM is configured as a mixed layer 1910 in which at least one inorganic material and at least one metal material are mixed.

[0242] According to one embodiment, the mixed layer 1910 may include a mixed material in which silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) and at least one metal material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti) and Invar alloy.

[0243] According to one embodiment, when forming the mixed layer 1910 , processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and sputtering may be used.

[0244] Figures 16 to 20 1 is a cross-sectional view showing a process of manufacturing a mask according to an embodiment of the present invention. Figures 16 to 20 may be shown for making including Figure 14An example of a method of masking MK using a mask film MM is shown.

[0245] The following will refer to Figures 16 to 20 Description for manufacturing including Figure 14 The mask film MM is shown in the mask MK method.

[0246] Reference Figure 16 , a silicon substrate 1700 can be prepared. Figure 12 As depicted, silicon substrate 1700 may include a plurality of cell regions 1710 and a mask frame region 1720 excluding the cell regions 1710 . Mask frame region 1720 may include a mask rib region 1721 surrounding each cell region 1710 and an outer frame region 1722 disposed at the outermost periphery of silicon substrate 1700 .

[0247] Reference Figure 17 , the alignment key 2001 can be formed in a portion of the mask frame region 1720 of the silicon substrate 1700. For example, the alignment key 2001 can be formed by depositing an inorganic layer or a metal layer on the silicon substrate 1700 and patterning the deposited inorganic layer or metal layer. In the present disclosure, the material of the alignment key 2001 is not limited.

[0248] Reference Figure 18 , a plurality of layers for the mask film MM may be sequentially stacked on the silicon substrate 1700 on which the alignment key 2001 is formed. For example, the mask film MM is configured as a multilayer in which a plurality of inorganic layers and a plurality of metal layers may be alternately stacked on each other. Although the first metal layer 1811, the first inorganic layer 1821 provided on the first metal layer 1811, the second metal layer 1812 provided on the first inorganic layer 1821, and the second inorganic layer 1822 provided on the second metal layer 1812 are shown as Figure 18 , but the present disclosure is not limited thereto.

[0249] Reference Figure 19 The multiple layers stacked on the silicon substrate 1700 (e.g., a first metal layer 1811, a first inorganic layer 1821 disposed on the first metal layer 1811, a second metal layer 1812 disposed on the first inorganic layer 1821, and a second inorganic layer 1822 disposed on the second metal layer 1812) are patterned to form a mask film MM. During the process, the mask film MM may form an opening in each cell region 1710 that exposes the bottom surface of the silicon substrate 1700.

[0250] Reference Figure 20 , a cell opening COP is formed by etching the rear surface of the silicon substrate 1700 corresponding to the cell region 1710. The cell opening COP may expose the rear surface of the mask film MM in the cell region 1710.

[0251] Figures 21 to 25 is a diagram illustrating a method of forming a mask film as a mixed layer according to one embodiment. Figures 21 to 25 Each of which may be shown for making include Figure 15 An example of a method of depositing a mask MK with a mask film MM is shown in FIG. For example, deposition may be performed with reference to Figures 21 to 25 Each of the described hybrid layer methods does not perform Figure 18 The multi-layer deposition process shown in FIG.

[0252] In the following, reference will be made to Figures 21 to 25 describe Figure 15 The mask film is shown.

[0253] Reference Figure 21 The mixed layer configuring the mask film MM according to one embodiment can be formed by moving the silicon substrate 1700 to a chamber equipped with the first deposition material 2111, the second deposition material 2112, and the third deposition material 2113 and evaporating the first deposition material 2111, the second deposition material 2112, and the third deposition material 2113. For example, the mixed layer can be a three-type layer in which three types of materials are mixed by simultaneously depositing the first deposition material 2111, the second deposition material 2112, and the third deposition material 2113. At this time, when evaporating each of the first deposition material 2111, the second deposition material 2112, and the third deposition material 2113, the ratio of the materials included in the mixed layer can be adjusted by adjusting the power used to evaporate each material.

[0254] Reference Figure 22 The mixed layer configuring the mask film MM according to one embodiment can be formed by moving the silicon substrate 1700 to a chamber equipped with the first deposition material 2111, the second deposition material 2112, and the third deposition material 2113 and generating plasma 2210 in the first deposition material 2111, the second deposition material 2112, and the third deposition material 2113. At this time, the ratio of the materials included in the mixed layer can be adjusted by adjusting the power of the plasma 2210 for each material.

[0255] Reference Figure 23 The mixed layer configuring the mask film MM according to one embodiment can be formed by moving the silicon substrate 1700 to a chamber equipped with a first deposition material 2111, a second deposition material 2112, and a third deposition material 2113 injected with three different gases and generating a gas reaction using plasma 2210 or heat 2220. At this time, the ratio of the materials included in the mixed layer can be adjusted by adjusting the ratio of the gas of each material in the chamber.

[0256] Reference Figure 24The mixed layer configuring the mask film MM according to one embodiment may include a first mixed layer 2311 in which a first deposition material (A) 2111 and a second deposition material (B) 2112 are mixed, and a second mixed layer 2312 in which the first deposition material 2111 and a third deposition material (C) 2113 are mixed and deposited on the first mixed layer 2311. First, to form the first mixed layer 2311, the silicon substrate 1700 may be moved to a chamber into which two different gases including the first deposition material 2111 and the second deposition material 2112 are injected, and a gas reaction may be generated using heat 2220 or plasma 2210. Subsequently, to form the second mixed layer 2312 on the first mixed layer 2311, the silicon substrate 1700 may be moved to a chamber into which two different gases including the first deposition material 2111 and the third deposition material 2113 are injected, and a gas reaction may be generated using heat 2220 or plasma 2210.

[0257] exist Figure 25 In the embodiment of Figure 24 In a different embodiment, when three different gases including a first deposition material (A) 2111, a second deposition material (B) 2112, and a third deposition material (C) 2113 are applied, after injecting a first gas of the first deposition material 2111 and a second gas of the second deposition material 2112 as source gases, a third gas of the third deposition material 2113 as a reaction gas can be injected to form a mixed layer 2411. At this time, the ratio of the materials included in the mixed layer 2411 can be adjusted by adjusting the ratio of the first gas and the second gas in the chamber. According to an embodiment, the deposition mask and the deposition apparatus including the deposition mask can have high mechanical strength and be easy to clean, and the accuracy of alignment can be improved by reducing the coefficient of thermal expansion (CTE).

[0258] According to embodiments, the deposition mask and the deposition apparatus may also reduce deposition defects caused by thickness deviation of the mask.

[0259] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0260] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles and scope of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. Deposition mask, including: a substrate comprising a plurality of unit regions and a mask frame region excluding the plurality of unit regions; as well as a mask film provided in each of the plurality of unit regions, Herein, the cross-sectional structure of the mask film includes a multilayer in which a plurality of inorganic layers and a plurality of metal layers are alternately stacked on each other.

2. The deposition mask according to claim 1, wherein The cross-sectional structure of the mask film includes: a first metal layer; a first inorganic layer, disposed on the first metal layer; a second metal layer, disposed on the first inorganic layer; a second inorganic layer, disposed on the second metal layer; a third metal layer disposed on the second inorganic layer; and The third inorganic layer is disposed on the third metal layer.

3. The deposition mask according to claim 2, wherein: When viewed from a cross section in which the mask film is cut, the first metal layer is provided on a lowermost layer of the mask film, and the third inorganic layer is provided on an uppermost layer of the mask film.

4. The deposition mask according to claim 2, wherein: The first inorganic layer includes at least one of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon, and aluminum oxide.

5. The deposition mask according to claim 4, wherein The second inorganic layer includes at least one of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon, and aluminum oxide.

6. The deposition mask according to claim 5, wherein The third inorganic layer includes at least one of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon, and aluminum oxide.

7. The deposition mask according to claim 6, wherein: The materials of the first inorganic layer, the second inorganic layer, and the third inorganic layer are the same.

8. The deposition mask according to claim 6, wherein Materials of the first inorganic layer, the second inorganic layer, and the third inorganic layer are different from each other.

9. The deposition mask according to claim 2, wherein: The first metal layer includes at least one material selected from the group consisting of copper, nickel, aluminum, tungsten, molybdenum, titanium, and Invar alloy.

10. The deposition mask according to claim 9, wherein The second metal layer includes at least one material selected from the group consisting of copper, nickel, aluminum, tungsten, molybdenum, titanium, and Invar alloy.

11. The deposition mask according to claim 10, wherein The third metal layer includes at least one material selected from the group consisting of copper, nickel, aluminum, tungsten, molybdenum, titanium, and Invar alloy.

12. The deposition mask according to claim 11, wherein The materials of the first metal layer, the second metal layer and the third metal layer are the same.

13. The deposition mask according to claim 11, wherein Materials of the first metal layer, the second metal layer, and the third metal layer are different from each other.

14. Deposition mask, comprising: a substrate comprising a plurality of unit regions and a mask frame region excluding the plurality of unit regions; as well as a mask film provided in each of the plurality of unit regions, The mask film includes a mixed layer in which at least one inorganic material and at least one metal material are mixed.

15. The deposition mask according to claim 14, wherein The mixed layer includes a mixed material in which at least one inorganic material of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon and aluminum oxide and at least one metal material of copper, nickel, aluminum, tungsten, molybdenum, titanium and Invar alloy are mixed.

16. The deposition mask according to claim 15, wherein The substrate is a silicon substrate.

17. A deposition apparatus comprising: room; a deposition source disposed in the chamber; a mask disposed in the chamber between a first substrate and the deposition source; as well as a mask support member disposed between the deposition source and the mask to support at least a portion of the mask, wherein The mask comprises: a second substrate including a plurality of unit regions and a mask frame region excluding the plurality of unit regions; and a mask film provided in each of the plurality of unit regions, and The cross-sectional structure of the mask film includes a multilayer in which a plurality of inorganic layers and a plurality of metal layers are alternately stacked on each other.

18. The deposition apparatus according to claim 17, wherein: The cross-sectional structure of the mask film includes: a first metal layer; a first inorganic layer, disposed on the first metal layer; a second metal layer, disposed on the first inorganic layer; a second inorganic layer, disposed on the second metal layer; a third metal layer disposed on the second inorganic layer; and The third inorganic layer is disposed on the third metal layer.

19. The deposition apparatus according to claim 18, wherein: When viewed from a cross section in which the mask film is cut, the first metal layer is provided on a lowermost layer of the mask film, and the third inorganic layer is provided on an uppermost layer of the mask film.

20. The deposition apparatus according to claim 19, wherein The first inorganic layer, the second inorganic layer, and the third inorganic layer include at least one of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon, and aluminum oxide, and The first metal layer, the second metal layer, and the third metal layer include at least one material selected from the group consisting of copper, nickel, aluminum, tungsten, molybdenum, titanium, and Invar alloy.

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