Damping circuit for linear voltage stabilizing circuit, working method of damping circuit and linear voltage stabilizer circuit

Abstract

The invention relates to a damping circuit for a linear voltage stabilizing circuit, a working method of the damping circuit and a linear voltage stabilizer circuit, the damping circuit comprises a response module, the response module comprises an input end and an output end, the input end of the response module is used for amplifying the uprush voltage of the output voltage end of the linear voltage stabilizing circuit and outputting the amplified uprush voltage to the output end of the linear voltage stabilizing circuit; the output end of the response module is used for outputting the amplified uprush voltage; the control module comprises an input end and an output end, the input end of the control module is used for adjusting a control voltage according to the amplified uprush voltage, the control voltage is used for reducing the output voltage of the linear voltage stabilizing circuit, and the output end of the control module is used for outputting the control voltage and the output voltage. The overshoot voltage of the output voltage end of the linear voltage stabilizing circuit is amplified through the response module and the control module, and the output voltage and the control voltage are adjusted according to the amplified overshoot voltage, so that the control voltage is rapidly increased under the adjustment of the amplified overshoot voltage, and then rapid reduction of the output voltage is achieved.

Description

Technical Field

[0001] The present invention relates to the field of linear voltage stabilizers, and in particular to a damping circuit for a linear voltage stabilizer circuit, a working method thereof, and a linear voltage stabilizer circuit. Background Art

[0002] A linear regulator is a device that provides a stable output voltage when the power supply voltage or load current varies. Because the load varies, linear regulators often experience load switching. When the load switches from heavy to light, the linear regulator output overshoots. This overshoot is particularly pronounced when the loop gain is low, reducing the linear regulator's load regulation.

[0003] At present, when an overshoot occurs at the output end of a linear regulator, the output voltage rises accordingly. After loop feedback, the output voltage of the error amplifier also increases, that is, the control voltage increases, the threshold voltage of the output power tube decreases, and the output voltage drops to the original output voltage value. In the above scheme, the output voltage value is reduced through loop feedback, which will affect the response speed. In addition, the greater the load switching change rate, the higher the overshoot voltage, the longer the duration, and the slower the recovery time. The excessively high output voltage may cause power supply overvoltage shock to the subsequent circuit, and even cause momentary operating abnormalities, thereby reducing the load's operating performance and reliability. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a damping circuit for a linear voltage stabilization circuit and a working method thereof, as well as a linear voltage stabilizer circuit, so as to improve the working performance and reliability of a load.

[0005] To solve the above technical problems, an embodiment of the present invention provides a damping circuit for a linear voltage regulator circuit, comprising: a response module, comprising an input end and an output end, wherein the input end of the response module is used to amplify the overshoot voltage at the output voltage end of the linear voltage regulator circuit, and the output end of the response module is used to output the amplified overshoot voltage; a control module, comprising an input end and an output end, wherein the input end of the control module is used to adjust a control voltage according to the amplified overshoot voltage, wherein the control voltage is used to reduce the output voltage of the linear voltage regulator circuit, and the output end of the control module is used to output the control voltage and the output voltage.

[0006] Optionally, the response module includes: a bias current module, the input end of the bias current module is connected to an external bias circuit; a current mirror module, the input end of the current mirror module is connected to the input end of the bias current module, and the output end of the current mirror module is used to output the amplified overshoot voltage.

[0007] Optionally, the control module includes: an inverter, the input end of the inverter is connected to the output end of the response module; a control voltage unit, the input end of the control voltage unit is connected to the output end of the inverter, and the output end of the control voltage unit is used to output the control voltage; an output voltage unit, the input end of the output voltage unit is connected to the output end of the response module, and the output end of the output voltage unit is used to output the output voltage.

[0008] Optionally, the current mirror module includes a first current mirror, a second current mirror, a third current mirror, a first voltage node and a second voltage node, the first current mirror and the second current mirror are connected in parallel, the first current mirror and the third current mirror are connected in series, the first voltage node is located between the first current mirror and the third current mirror, the second current mirror and the third current mirror are connected in series, and the second voltage node is located between the second current mirror and the third current mirror.

[0009] Optionally, the bias current module includes a first NMOS transistor, a gate of the first NMOS transistor is connected to an external bias circuit, and a source of the first NMOS transistor is grounded.

[0010] Optionally, the first current mirror includes a first PMOS tube and a second PMOS tube, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the source of the first PMOS tube is connected to the output voltage terminal, the drain of the first PMOS tube is connected to the drain of the first NMOS tube and the gate of the first PMOS tube, and the source of the second PMOS tube is connected to the first reference voltage terminal; the second current mirror includes a first PMOS tube and a third PMOS tube, the gate of the third PMOS tube is connected to the gate of the first PMOS tube, and the source of the third PMOS tube is connected to the output voltage terminal; the third current mirror includes a second NMOS tube and a third NMOS tube, The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the first voltage node is located between the drain of the second NMOS transistor and the drain of the second PMOS transistor, the source of the second NMOS transistor is grounded, the gate of the second NMOS transistor is connected to the gate of the third NMOS transistor and the drain of the second NMOS transistor, the source of the third NMOS transistor is grounded, the second voltage node is located between the drain of the third NMOS transistor and the drain of the third PMOS transistor, the third NMOS transistor and the third PMOS transistor further constitute a single-stage amplifier, and the third NMOS transistor and the third PMOS transistor are used to amplify the overshoot voltage at the output voltage end of the linear voltage regulator circuit.

[0011] Optionally, the inverter includes a fourth PMOS tube and a fourth NMOS tube, the gate of the fourth PMOS tube and the gate of the fourth NMOS tube are both connected to the output end of the response module, the source of the fourth PMOS tube is connected to the power supply voltage end, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded.

[0012] Optionally, the control voltage unit includes a fifth PMOS tube, the source of the fifth PMOS tube is connected to the power supply voltage end, the gate of the fifth PMOS tube is connected to the drain of the fourth PMOS tube, and the drain of the fifth PMOS tube is used to output the control voltage; the output voltage unit includes a fifth NMOS tube, the gate of the fifth NMOS tube is connected to the output end of the response module, the source of the fifth NMOS tube is grounded, and the drain of the fifth NMOS tube is used to output the output voltage.

[0013] Correspondingly, the technical solution of the present invention also provides a working method of a damping circuit, including: amplifying the overshoot voltage at the output voltage end of the linear voltage regulator circuit and outputting the amplified overshoot voltage; adjusting the control voltage according to the amplified overshoot voltage, the control voltage being used to reduce the output voltage of the linear voltage regulator circuit, and outputting the control voltage and the output voltage.

[0014] Correspondingly, the technical solution of the present invention also provides a linear voltage regulator circuit, including: a linear voltage regulator module and the above-mentioned damping circuit for the linear voltage regulator circuit; the linear voltage regulator module is used to perform error amplification processing on the input voltage and the reference voltage, obtain the control voltage, adjust the output voltage according to the control voltage, and output the output voltage to the load through the output voltage terminal.

[0015] Optionally, the linear regulator module includes: an error amplifier, the inverting input terminal of the error amplifier is connected to the second reference voltage terminal, and the output terminal of the error amplifier is connected to the damping circuit; a switching tube, one of the source or drain of the switching tube is connected to the power supply voltage terminal, and the other source or drain of the switching tube is connected to the output voltage terminal; a first resistor and a second resistor, the first end of the first resistor is connected to the output voltage terminal, the second end of the first resistor is connected to the first end of the second resistor and the non-inverting input terminal of the error amplifier, and the second end of the second resistor is grounded; a voltage stabilizing module, the first end of the voltage stabilizing module is connected to the output voltage terminal, and the second end of the voltage stabilizing module is grounded.

[0016] Optionally, the voltage stabilizing module includes a load capacitor, a first end of the load capacitor is connected to the output voltage end, and a second end of the load capacitor is grounded; and a load resistor, a first end of the load resistor is connected to the output voltage end, and a second end of the load resistor is grounded.

[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0018] The damping circuit for a linear voltage stabilization circuit in the technical solution of the present invention amplifies the overshoot voltage at the output voltage end of the linear voltage stabilization circuit through a response module and a control module, and adjusts the output voltage and the control voltage according to the amplified overshoot voltage, so that under the regulation of the amplified overshoot voltage, the control voltage is quickly raised, thereby achieving a rapid reduction in the output voltage, reducing the peak value, duration and recovery time of the overshoot voltage, and thus improving the working performance and reliability of the load.

[0019] Furthermore, the technical solution of the present invention inverts the overshoot voltage signal through an inverter, so that the change trend of the control voltage output by the control voltage unit is opposite to the change trend of the output voltage output by the output voltage unit, that is, as the control voltage rises rapidly, the falling speed of the output voltage also increases, thereby enabling the overshoot voltage on the output voltage end of the linear voltage regulator circuit to quickly drop to the original value of the output voltage, thereby improving the working performance and reliability of the load.

[0020] Furthermore, in the technical solution of the present invention, the overshoot voltage is amplified and output through the current mirror module, so that the subsequent control voltage rises faster under the regulation of the amplified overshoot voltage, thereby increasing the falling speed of the output voltage to improve the working performance and reliability of the load.

[0021] The working method of the damping circuit in the technical solution of the present invention amplifies the overshoot voltage at the output voltage end of the linear voltage regulator circuit, and adjusts the output voltage and the control voltage according to the amplified overshoot voltage, so that under the regulation of the amplified overshoot voltage, the control voltage is quickly pulled up, thereby achieving a rapid reduction in the output voltage, reducing the peak value, duration and recovery time of the overshoot voltage, and thus improving the working performance and reliability of the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the structure of the damping circuit in one embodiment of the present invention. Figure 1 ;

[0023] Figure 2 This is a schematic diagram of the structure of the damping circuit in one embodiment of the present invention. Figure 2 ;

[0024] Figure 3 1 is a schematic structural diagram of a linear voltage regulator circuit according to an embodiment of the present invention;

[0025] Figure 4 FIG. 1 is a schematic diagram of operating performance parameters of a linear voltage regulator circuit in one embodiment of the present invention. DETAILED DESCRIPTION

[0026] As mentioned in the background art, the performance of current linear regulators still needs to be improved.

[0027] At present, when an overshoot occurs at the output end of a linear regulator, the output voltage rises accordingly. After loop feedback, the output voltage of the error amplifier also increases, that is, the control voltage increases, the threshold voltage of the output power tube decreases, and the output voltage drops to the original output voltage value. In the above scheme, the output voltage value is reduced through loop feedback, which will affect the response speed. In addition, the greater the load switching change rate, the higher the overshoot voltage, the longer the duration, and the slower the recovery time. The excessively high output voltage may cause power supply overvoltage shock to the subsequent circuit, and even cause momentary operating abnormalities, thereby reducing the load's operating performance and reliability.

[0028] In order to solve the above problems, the present invention provides a damping circuit for a linear voltage stabilization circuit, a working method thereof, and a linear voltage regulator circuit. The overshoot voltage at the output voltage end of the linear voltage stabilization circuit is amplified by a response module and a control module, and the output voltage and the control voltage are adjusted according to the amplified overshoot voltage. Under the regulation of the amplified overshoot voltage, the control voltage is rapidly raised, thereby achieving a rapid reduction in the output voltage, reducing the peak value, duration and recovery time of the overshoot voltage, and thereby improving the working performance and reliability of the load.

[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the structure of the damping circuit in one embodiment of the present invention. Figure 1 .

[0031] Please refer to Figure 1 The damping circuit 1 is used for a linear voltage stabilization circuit, and includes: a response module 101, including an input end and an output end, the input end of the response module 101 is used to amplify the overshoot voltage at the output voltage VOUT of the linear voltage stabilization circuit, and the output end of the response module 101 is used to output the amplified overshoot voltage; a control module 102, including an input end and an output end, the input end of the control module 102 is used to adjust the control voltage VG according to the amplified overshoot voltage, and the control voltage VG is used to reduce the output voltage VOUT of the linear voltage stabilization circuit, and the output end of the control module 102 is used to output the control voltage VG and the output voltage VOUT.

[0032] In the above scheme, the overshoot voltage at the output voltage VOUT end of the linear voltage regulator circuit is amplified by the response module 101 and the control module 102, and the output voltage VOUT and the control voltage VG are adjusted according to the amplified overshoot voltage, so that under the regulation of the amplified overshoot voltage, the control voltage VG is quickly pulled up, thereby achieving a rapid reduction in the output voltage VOUT, reducing the peak value, duration and recovery time of the overshoot voltage, and thereby improving the working performance and reliability of the load.

[0033] Figure 2 This is a schematic diagram of the structure of the damping circuit in one embodiment of the present invention. Figure 2 .

[0034] Please refer to Figure 2 The response module 101 includes: a bias current module, the input end of the bias current module is connected to the external bias circuit; a current mirror module, the input end of the current mirror module is connected to the input end of the bias current module, and the output end of the current mirror module is used to output the amplified overshoot voltage.

[0035] The current mirror module includes a first current mirror, a second current mirror, a third current mirror, a first voltage node A and a second voltage node B. The first current mirror and the second current mirror are connected in parallel, the first current mirror and the third current mirror are connected in series, the first voltage node A is located between the first current mirror and the third current mirror, the second current mirror and the third current mirror are connected in series, and the second voltage node B is located between the second current mirror and the third current mirror.

[0036] In this embodiment, the first current mirror and the second current mirror are P-type current mirrors.

[0037] In this embodiment, the third current mirror is an N-type current mirror.

[0038] The bias current module includes a first NMOS transistor NM1 , a gate of the first NMOS transistor NM1 is connected to an external bias circuit, and a source of the first NMOS transistor NM1 is grounded AVSS.

[0039] Specifically, the first NMOS transistor NM1 is configured to obtain a first bias voltage Vbias according to an external bias circuit.

[0040] The first current mirror includes a first PMOS transistor PM1 and a second PMOS transistor PM2, the gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2, the source of the first PMOS transistor PM1 is connected to the output voltage terminal, the drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1 and the gate of the first PMOS transistor PM1, and the source of the second PMOS transistor PM2 is connected to the first reference voltage terminal VREF1; the second current mirror includes a first PMOS transistor PM1 and a third PMOS transistor PM3, the gate of the third PMOS transistor PM3 is connected to the gate of the first PMOS transistor PM1, and the source of the third PMOS transistor PM3 is connected to the output voltage terminal; the third current mirror includes a second NMOS transistor NM2 and a third NMOS transistor NM3, the second The drain of the NMOS transistor NM2 is connected to the drain of the second PMOS transistor PM2, the first voltage node A is located between the drain of the second NMOS transistor NM2 and the drain of the second PMOS transistor PM2, the source of the second NMOS transistor NM2 is grounded to AVSS, the gate of the second NMOS transistor NM2 is connected to the gate of the third NMOS transistor NM3 and the drain of the second NMOS transistor NM2, the source of the third NMOS transistor NM3 is grounded to AVSS, the second voltage node B is located between the drain of the third NMOS transistor NM3 and the drain of the third PMOS transistor PM3, the third NMOS transistor NM3 and the third PMOS transistor PM3 further constitute a single-stage amplifier, and the third NMOS transistor NM3 and the third PMOS transistor PM3 are used to amplify the overshoot voltage at the output voltage end of the linear voltage regulator circuit.

[0041] The gate voltages of the second PMOS transistor PM2 and the third PMOS transistor PM3 vary with the gate voltage of the first PMOS transistor PM1 , and the gate voltage of the third NMOS transistor NM3 varies with the gate voltage of the second NMOS transistor NM2 .

[0042] The first PMOS transistor PM1 and the second NMOS transistor NM2 are connected in a diode manner.

[0043] In this embodiment, the ratio of the first PMOS transistor PM1 , the second PMOS transistor PM2 , and the third PMOS transistor PM3 is 1:6:2.

[0044] The gate voltage V G-PM1 (i.e., the gate voltages of PM2 and PM3) are determined by the bias current Ibias and the size of the first PMOS transistor PM1. The bias current Ibias is determined by the size of the first NMOS transistor NM1.

[0045] Cox PM1 It is the unit capacitance of the gate oxide layer of the first PMOS tube PM1, up PM1 is the electrical mobility of the first PMOS transistor PM1, W / L is the width-to-length ratio of the first PMOS transistor PM1, Vt PM1 is the absolute value of the threshold voltage of the first PMOS transistor PM1.

[0046] In this embodiment, the source of the second PMOS transistor PM2 is connected to the first reference voltage terminal VREF1 to obtain a stable power supply voltage, reduce noise interference introduced by the power supply, and improve the working performance of the damping circuit 1.

[0047] The second PMOS transistor PM2 and the second NMOS transistor NM2 further form a bias branch to provide a second bias voltage VA for the third NMOS transistor NM3 of the subsequent stage. The magnitude of the second bias voltage VA is determined by the size ratio of the second PMOS transistor PM2 to the first PMOS transistor PM1 and the size of the second NMOS transistor NM2. The second bias voltage VA is the bias voltage at the first voltage node A, that is,

[0048] Among them, Cox NM2 is the unit capacitance of the gate oxide layer of the second NMOS tube NM2, un NM2 is the electrical mobility of the second NMOS transistor NM2, W / L is the width-to-length ratio of the second NMOS tube NM2, Vt NM2 is the absolute value of the threshold voltage of the second NMOS tube NM2, I bias is the bias current generated by the first NMOS transistor NM1, and N is the size ratio between the first PMOS transistor PM1 and the second PMOS transistor PM2.

[0049] In this embodiment, N is 1.

[0050] In this embodiment, the sizes of the first PMOS transistor PM1 , the second PMOS transistor PM2 , the third PMOS transistor PM3 , the first NMOS transistor NM1 , and the second NMOS transistor NM2 are characterized by the channel width-to-length ratios of the MOS transistors.

[0051] The control module 102 includes: an inverter, the input end of the inverter is connected to the output end of the response module 101; a control voltage unit, the input end of the control voltage unit is connected to the output end of the inverter, and the output end of the control voltage unit is used to output the control voltage VG; an output voltage unit, the input end of the output voltage unit is connected to the output end of the response module 101, and the output end of the output voltage unit is used to output the output voltage VOUT.

[0052] The inverter includes a fourth PMOS transistor PM4 and a fourth NMOS transistor NM4. The gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4 are both connected to the output end of the response module 101. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage terminal AVDD, the drain of the fourth PMOS transistor PM4 is connected to the drain of the fourth NMOS transistor NM4, and the source of the fourth NMOS transistor NM4 is grounded to AVSS.

[0053] The control voltage unit includes a fifth PMOS transistor PM5, a source of which is connected to the power supply voltage terminal AVDD, a gate of which is connected to the drain of the fourth PMOS transistor PM4, and a drain of which is used to output the control voltage VG; the output voltage unit includes a fifth NMOS transistor NM5, a gate of which is connected to the output terminal of the response module 101, a source of which is grounded AVSS, and a drain of which is used to output the output voltage VOUT.

[0054] The following combination Figure 2 The working process of the damping circuit 1 is described as follows:

[0055] When the linear voltage regulator circuit outputs a constant heavy load current, the output voltage VOUT and the control voltage VG are both maintained at constant values, that is, the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5 must both be in the off state to avoid affecting the output voltage VOUT and the control voltage VG. That is, at this time, the input voltage of the inverter should be at least lower than the threshold voltage of the fourth NMOS transistor NM4 and the fifth NMOS transistor.

[0056] The input voltage of the inverter is determined by the output voltage VOUT of the single-stage amplifier. By adjusting the ratio of the third PMOS transistor PM3 to the first PMOS transistor PM1, and the ratio of the third NMOS transistor NM3 to the second NMOS transistor NM2, the output voltages at the drains of the third PMOS transistor PM3 and the third NMOS transistor NM3 meet the above requirements (i.e., at least less than the threshold voltages of the fourth NMOS transistor NM4 and the fifth NMOS transistor). Furthermore, in order to achieve a greater gain for the single-stage amplifier, the output impedance of the third NMOS transistor NM3 needs to be greater. Therefore, the gate length of the third NMOS transistor NM3 is selected to be larger than that of the second NMOS transistor NM2.

[0057] The intrinsic gain of the third NMOS transistor NM3 is described as follows: Since a larger amplification factor is required for the change of the output voltage VOUT, the channel length of the third NMOS transistor NM3 needs to be increased, because the channel length modulation coefficient λ is more affected by the channel length than the transconductance g NM3 Bigger.

[0058] When the output load current of the linear voltage regulator circuit suddenly changes from heavy load to light load, an overshoot peak value (i.e., overshoot voltage ΔVOUT) appears at the output voltage end. The overshoot voltage ΔVOUT is converted into a gate voltage change ΔV of the first PMOS transistor PM1 through the first PMOS transistor PM1. G-PM1 , that is, the gate voltages of the second PMOS transistor PM2 and the third PMOS transistor PM3 are both increased by A△V G-PM1 , where A is a constant. Because the gate voltage of the second PMOS transistor PM2 is momentarily raised, the voltage at the first voltage node A momentarily decreases. This means that the gate voltages of the second and third NMOS transistors NM2 and NM3 decrease momentarily, and the voltage at the second voltage node B subsequently increases momentarily. Before the current enters the single-stage amplifier, the gate voltage of the third NMOS transistor NM3 changes slightly, approximately tens of millivolts. Under the amplification effect of the single-stage amplifier, this change is amplified and output to the second voltage node B. The voltage change at the second voltage node B can reach several hundred millivolts, thereby amplifying the overshoot voltage ΔVOUT.

[0059] Specifically, when the voltage at the second voltage node B exceeds the threshold voltages of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5, the fifth NMOS transistor NM5 turns on, rapidly pulling down the output voltage VOUT. Simultaneously, the inverter flips, causing the gate voltage of the fifth PMOS transistor PM5 to transition from high to low. This means the fifth PMOS transistor PM5 turns on, rapidly increasing the control voltage VG. As the control voltage VG increases, the output voltage VOUT decreases more rapidly and returns to its original value.

[0060] When the output voltage VOUT returns to its original value, the voltage of the first voltage node A changes from low to high, the voltage of the second voltage node B changes from high to low, the fifth NMOS transistor NM5 is turned off, and the inverter is flipped again, and the fifth PMOS transistor PM5 is turned off, so that the circuit enters a steady state.

[0061] In the above scheme, the inverter inverts the overshoot voltage signal so that the change trend of the control voltage VG output by the control voltage unit is opposite to the change trend of the output voltage VOUT output by the output voltage unit. That is, as the control voltage VG rises rapidly, the falling speed of the output voltage VOUT also increases, thereby enabling the overshoot voltage on the output voltage end of the linear voltage regulator circuit to drop quickly to the original value of the output voltage VOUT, thereby improving the working performance and reliability of the load.

[0062] In addition, the overshoot voltage is amplified and outputted through the current mirror module, so that the subsequent control voltage VG rises faster under the regulation of the amplified overshoot voltage, thereby increasing the falling speed of the output voltage VOUT, thereby improving the working performance and reliability of the load.

[0063] Correspondingly, the technical solution of the present invention also provides a working method of the damping circuit 1 as described above, comprising: amplifying the overshoot voltage at the output voltage end of the linear voltage regulator circuit and outputting the amplified overshoot voltage; adjusting the control voltage VG according to the amplified overshoot voltage, wherein the control voltage VG is used to reduce the output voltage VOUT of the linear voltage regulator circuit, and outputting the control voltage VG and the output voltage VOUT.

[0064] In the above scheme, the overshoot voltage at the output voltage end of the linear voltage regulator circuit is amplified, and the output voltage VOUT and the control voltage VG are adjusted according to the amplified overshoot voltage, so that under the regulation of the amplified overshoot voltage, the control voltage VG is quickly pulled up, thereby achieving a rapid reduction in the output voltage VOUT, reducing the peak value, duration and recovery time of the overshoot voltage, and thus improving the working performance and reliability of the load.

[0065] Figure 3 FIG. 1 is a schematic structural diagram of a linear voltage regulator circuit in one embodiment of the present invention.

[0066] Accordingly, please Figure 2 Based on reference Figure 3 The technical solution of the present invention also provides a linear voltage regulator circuit, including: a linear voltage regulator module 2 and the above-mentioned damping circuit 1; the linear voltage regulator module 2 is used to perform error amplification processing on the input voltage and the reference voltage, obtain a control voltage VG, adjust the output voltage VOUT according to the control voltage VG, and output the output voltage VOUT to the load through the output voltage terminal.

[0067] In this embodiment, the linear regulator module 2 includes: an error amplifier ERR AMP, wherein the inverting input terminal of the error amplifier ERR AMP is connected to the second reference voltage terminal VREF2, and the output terminal of the error amplifier ERR AMP is connected to the damping circuit 1; a switch tube M1, wherein one of the source or drain of the switch tube M1 is connected to the power supply voltage terminal AVDD, and the other source or drain of the switch tube M1 is connected to the output voltage terminal; a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is connected to the output voltage terminal, a second end of the first resistor R1 is connected to a first end of the second resistor R2 and the non-inverting input terminal of the error amplifier ERR AMP, and a second end of the second resistor R2 is grounded to AVSS; and a voltage stabilizing module, wherein a first end of the voltage stabilizing module is connected to the output voltage terminal, and a second end of the voltage stabilizing module is grounded to AVSS.

[0068] In this embodiment, the voltage stabilizing module includes a load capacitor Cload, a first end of the load capacitor Cload is connected to the output voltage end, and a second end of the load capacitor Cload is grounded AVSS; a load resistor Rload, a first end of the load resistor Rload is connected to the output voltage end, and a second end of the load resistor Rload is grounded AVSS.

[0069] Figure 4 FIG. 1 is a schematic diagram of operating performance parameters of a linear voltage regulator circuit in one embodiment of the present invention.

[0070] Figure 4 The following is a simulation comparison of the working performance of the linear regulator circuit with and without damping circuit 1, where the X-axis is the recovery time and the Y-axis is the output voltage. It should be noted that under this simulation condition, the steady-state output voltage VOUT of the linear regulator circuit is 1.58V, and the output current load is switched from 6mA to 0.1mA to simulate the situation where the output load current suddenly changes from heavy load to light load.

[0071] Depend on Figure 4 It can be seen from the first change trend 3 and the second change trend 4 that the first change trend 3 is the working performance of the linear voltage regulator circuit without using the damping circuit, and the second change trend 4 is the working performance of the linear voltage regulator circuit with using the damping circuit. When the damping circuit 1 is not used, the output voltage VOUT instantly surges to about 1.77V, and the recovery time is relatively long (about 3 microseconds); however, when the damping circuit 1 is used, the output voltage VOUT instantly surges to 1.7V, which is 70mV lower than the peak value when the damping circuit 1 is not used, thereby reducing the recovery time. Specifically, based on the voltage dropping to 95% of the peak voltage as the benchmark, that is, when the output voltage VOUT without using the damping circuit 1 and after using the damping circuit 1 drops to 1.65V, the fall time of the output voltage VOUT after using the damping circuit 1 is shortened by nearly 1 microsecond, that is, the recovery time of the output voltage VOUT after using the damping circuit 1 is shortened by nearly 1 microsecond, and the overall recovery speed is increased by about 50%.

[0072] In the above scheme, the overshoot voltage at the output voltage end of the linear voltage regulator circuit is amplified by the damping circuit 1, and the output voltage and the control voltage are adjusted according to the amplified overshoot voltage, so that under the regulation of the amplified overshoot voltage, the control voltage is quickly pulled up, thereby achieving a rapid reduction in the output voltage, reducing the peak value, duration and recovery time of the overshoot voltage, and thus improving the working performance and reliability of the load.

[0073] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A damping circuit for a linear voltage stabilization circuit, characterized in that: include: A response module, comprising an input end and an output end, wherein the input end of the response module is used to amplify the overshoot voltage of the output voltage end of the linear voltage regulator circuit, and the output end of the response module is used to output the amplified overshoot voltage; The control module includes an input end and an output end. The input end of the control module is used to adjust the control voltage according to the amplified overshoot voltage, and the control voltage is used to reduce the output voltage of the linear voltage regulator circuit. The output end of the control module is used to output the control voltage and the output voltage.

2. The damping circuit according to claim 1, wherein: The response module includes: a bias current module, the input end of the bias current module is connected to the external bias circuit; a current mirror module, the input end of the current mirror module is connected to the input end of the bias current module, and the output end of the current mirror module is used to output the amplified overshoot voltage.

3. The damping circuit according to claim 1, wherein: The control module includes: an inverter, the input end of the inverter is connected to the output end of the response module; a control voltage unit, the input end of the control voltage unit is connected to the output end of the inverter, and the output end of the control voltage unit is used to output the control voltage; an output voltage unit, the input end of the output voltage unit is connected to the output end of the response module, and the output end of the output voltage unit is used to output the output voltage.

4. The damping circuit according to claim 2, wherein: The current mirror module includes a first current mirror, a second current mirror, a third current mirror, a first voltage node and a second voltage node, the first current mirror and the second current mirror are connected in parallel, the first current mirror and the third current mirror are connected in series, the first voltage node is located between the first current mirror and the third current mirror, the second current mirror and the third current mirror are connected in series, and the second voltage node is located between the second current mirror and the third current mirror.

5. The damping circuit according to claim 2, wherein: The bias current module includes a first NMOS transistor, a gate of the first NMOS transistor is connected to an external bias circuit, and a source of the first NMOS transistor is grounded.

6. The damping circuit according to claim 4, wherein: The first current mirror includes a first PMOS transistor and a second PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the source of the first PMOS transistor is connected to the output voltage terminal, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the first PMOS transistor, and the source of the second PMOS transistor is connected to the first reference voltage terminal; the second current mirror includes a first PMOS transistor and a third PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the first PMOS transistor, and the source of the third PMOS transistor is connected to the output voltage terminal; the third current mirror includes a second NMOS transistor and a third NMOS transistor, The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the first voltage node is located between the drain of the second NMOS transistor and the drain of the second PMOS transistor, the source of the second NMOS transistor is grounded, the gate of the second NMOS transistor is connected to the gate of the third NMOS transistor and the drain of the second NMOS transistor, the source of the third NMOS transistor is grounded, the second voltage node is located between the drain of the third NMOS transistor and the drain of the third PMOS transistor, the third NMOS transistor and the third PMOS transistor further constitute a single-stage amplifier, and the third NMOS transistor and the third PMOS transistor are used to amplify the overshoot voltage at the output voltage end of the linear voltage regulator circuit.

7. The damping circuit according to claim 3, wherein: The inverter includes a fourth PMOS transistor and a fourth NMOS transistor, wherein the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are both connected to the output end of the response module, the source of the fourth PMOS transistor is connected to the power supply voltage end, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded.

8. The damping circuit according to claim 7, wherein: The control voltage unit includes a fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the power supply voltage terminal, the gate of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the fifth PMOS transistor is used to output the control voltage; the output voltage unit includes a fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the output terminal of the response module, the source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is used to output the output voltage.

9. A method for operating a damping circuit according to any one of claims 1 to 8, characterized in that: include: After amplifying the overshoot voltage at the output voltage end of the linear voltage stabilization circuit, the amplified overshoot voltage is output; The control voltage is adjusted according to the amplified overshoot voltage, and the control voltage is used to reduce the output voltage of the linear voltage stabilization circuit, and the control voltage and the output voltage are output.

10. A linear voltage regulator circuit, characterized in that: include: A linear voltage regulator module and a damping circuit for a linear voltage regulator circuit according to any one of claims 1 to 8; The linear regulator module is used to perform error amplification processing on the input voltage and the reference voltage, obtain the control voltage, adjust the output voltage according to the control voltage, and output the output voltage to the load through the output voltage terminal.

11. The linear regulator circuit according to claim 10, wherein: The linear regulator module includes: an error amplifier, the inverting input terminal of the error amplifier is connected to the second reference voltage terminal, and the output terminal of the error amplifier is connected to the damping circuit; a switching tube, one of the source or drain of the switching tube is connected to the power supply voltage terminal, and the other source or drain of the switching tube is connected to the output voltage terminal; a first resistor and a second resistor, the first end of the first resistor is connected to the output voltage terminal, the second end of the first resistor is connected to the first end of the second resistor and the non-inverting input terminal of the error amplifier, and the second end of the second resistor is grounded; a voltage stabilizing module, the first end of the voltage stabilizing module is connected to the output voltage terminal, and the second end of the voltage stabilizing module is grounded.

12. The linear regulator circuit according to claim 11, wherein: The voltage stabilizing module includes a load capacitor, a first end of the load capacitor is connected to the output voltage end, and a second end of the load capacitor is grounded; and a load resistor, a first end of the load resistor is connected to the output voltage end, and a second end of the load resistor is grounded.

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