Current mirror circuit

Abstract

The present invention discloses a current mirror circuit. The current mirror circuit includes a voltage replication module, an isolation module, and a voltage recovery module. The voltage replication module is configured to generate a differential signal based on the voltage between the first electrode and the gate of a first switching tube. The isolation module is configured to isolate and output the differential signal to the voltage recovery module. The voltage recovery module is configured to generate a recovery voltage relative to a second power supply provided by a second power supply terminal based on the differential signal. The difference between the recovery voltage and the voltage between the first electrode and the gate of the first switching tube is less than or equal to a preset voltage value. This ensures that the difference between the voltage between the first electrode and the gate of the second switching tube and the voltage between the first electrode and the gate of the first switching tube is less than or equal to the preset voltage value. This enables current mirroring to be implemented in the isolation circuit, resolves the common source limitation of the input and output terminals of the current mirror circuit, and expands the application scenarios of the current mirror circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of circuit technology, and in particular to a current mirror circuit. Background Art

[0002] Current mirrors can achieve proportional changes in input and output currents, ensuring stable current transmission in a circuit. However, the transistors between the input and output of current mirrors currently have a common-source structure, which limits their use in isolation circuits. Summary of the Invention

[0003] The present invention provides a current mirror circuit to solve the common source limitation of the input and output ends of the current mirror circuit, thereby increasing the application scenarios of the current mirror circuit.

[0004] In a first aspect, an embodiment of the present invention provides a current mirror circuit, comprising:

[0005] a first switching tube, wherein a first electrode of the first switching tube is connected to a first power supply terminal, and a second electrode of the first switching tube and a gate of the first switching tube are used to input a reference current;

[0006] a voltage replication module, the voltage replication module being connected to the gate and the first electrode of the first switching tube, and configured to generate a differential signal according to a voltage between the first electrode and the gate of the first switching tube;

[0007] An isolation module, a voltage recovery module, and a second switching tube, wherein the input end of the isolation module is connected to the output end of the voltage replication module, the output end of the isolation module is connected to the input end and the control end of the voltage recovery module, the power supply end of the voltage recovery module and the first electrode of the second switching tube are connected to the second power supply end, the output end of the voltage recovery module is connected to the gate of the second switching tube, and the second electrode of the second switching tube serves as the output end of the current mirror circuit; the isolation module is configured to isolate and output the differential signal to the voltage recovery module, the voltage recovery module is configured to form a recovery voltage relative to the second power supply provided by the second power supply end based on the differential signal, the difference between the recovery voltage and the voltage between the first electrode and the gate of the first switching tube being less than or equal to a preset voltage value; the second switching tube is configured to output a target current based on the voltage between the first electrode and the gate, and the ratio of the target current to the reference current is the ratio of the width-to-length ratio of the second switching tube to the width-to-length ratio of the first switching tube.

[0008] Optionally, the voltage replication module includes a clock unit, an inverting buffer unit and a non-inverting buffer unit;

[0009] The power supply end of the clock unit is connected to the first power supply end, the input end of the clock unit is connected to the gate of the first switching tube, and the output end of the clock unit is connected to the input end of the inverting buffer unit and the input end of the in-phase buffer unit. The output end of the inverting buffer unit is the first single-ended differential signal output end of the voltage replication module, and the output end of the in-phase buffer unit is the second single-ended differential signal output end of the voltage replication module. The clock unit is used to form a clock signal according to the voltage between the first pole and the gate of the first switching tube. The inverting buffer unit is used to invert the clock signal and output a first differential signal. The in-phase buffer unit is used to synchronize the clock signal and output a second differential signal.

[0010] Optionally, the isolation module includes a first capacitor and a second capacitor, wherein a first electrode of the first capacitor is connected to the first single-ended differential signal output terminal, a second electrode of the first capacitor is connected to the first control terminal and the first input terminal of the voltage recovery module, a first electrode of the second capacitor is connected to the second single-ended differential signal output terminal, and a second electrode of the second capacitor is connected to the second control terminal and the second input terminal of the voltage recovery module;

[0011] Alternatively, the isolation module includes a transformer, a primary first end of the transformer is connected to the first single-ended differential signal output end, a primary second end of the transformer is connected to the second single-ended differential signal output end, a secondary first end of the transformer is connected to the first control end and the first input end of the voltage recovery module, and a secondary second end of the transformer is connected to the second control end and the second input end of the voltage recovery module;

[0012] The voltage recovery module is configured to generate the recovery voltage according to the second differential signal when the first differential signal is valid, and to generate the recovery voltage according to the first differential signal when the second differential signal is valid.

[0013] Optionally, the voltage recovery module includes a rectifier unit, the control end of the first bridge arm of the rectifier unit and the input end of the second bridge arm of the rectifier unit are connected to the first output end of the isolation module, the control end of the second bridge arm and the input end of the first bridge arm are connected to the second output end of the isolation module, the first end of the first bridge arm and the first end of the second bridge arm are connected to the second power supply end, and the second end of the first bridge arm and the second end of the second bridge arm are connected to the gate of the second switching tube; the first bridge arm is used to provide a current path for the second differential signal when the first differential signal is valid, and the second bridge arm is used to provide a current path for the first differential signal when the second differential signal is valid.

[0014] Optionally, the first bridge arm includes a first transistor and a second transistor, and the second bridge arm includes a third transistor and a fourth transistor;

[0015] The gate of the first transistor, the gate of the second transistor, the second electrode of the third transistor, and the second electrode of the fourth transistor are connected to the first output end of the isolation module, the second electrode of the first transistor, the second electrode of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are connected to the second output end of the isolation module, the first electrode of the first transistor and the first electrode of the third transistor are connected to the second power supply end, and the first electrode of the second transistor and the first electrode of the fourth transistor are connected to the gate of the second switching tube; wherein, the channel type of the first transistor is opposite to the channel type of the second transistor, the channel type of the first transistor is the same as the channel type of the third transistor, and the channel type of the third transistor is opposite to the channel type of the fourth transistor.

[0016] Optionally, the clock unit includes an oscillator and a voltage conversion subunit, wherein the input end of the oscillator is connected to the gate of the first switching tube, the power end of the oscillator is connected to the first power end, the input end of the voltage conversion subunit is connected to the output end of the oscillator, and the output end of the voltage conversion subunit is connected to the input end of the in-phase buffer unit and the input end of the inverting buffer unit. The oscillator is used to form an initial clock signal based on the voltage between the first electrode and the gate of the first switching tube, and the voltage conversion subunit is used to perform voltage conversion on the initial clock signal to form the clock signal, and the ratio of the voltage of the clock signal to the voltage of the initial clock signal is a first ratio;

[0017] The voltage recovery module also includes a voltage divider unit; the first end of the voltage divider unit is connected to the second end of the first bridge arm and the second end of the second bridge arm, the second end of the voltage divider unit is connected to the second power supply end, and the output end of the voltage divider unit is connected to the gate of the second switching tube. The voltage divider unit is used to divide the rectified signal output by the rectifier unit to form the recovery voltage; when the isolation module includes the first capacitor and the second capacitor, the voltage divider ratio of the voltage divider unit is the reciprocal of the first ratio; when the isolation module includes the transformer, the product of the voltage divider ratio of the voltage divider unit and the reciprocal of the transformer transformation ratio is equal to the reciprocal of the first ratio.

[0018] Optionally, the voltage conversion subunit includes a charge pump, the input end of the charge pump is connected to the output end of the clock unit, the power supply end of the charge pump is connected to the gate of the first switching tube, the output end of the charge pump is connected to the input end of the in-phase cache unit and the input end of the inverting cache unit, and the charge pump is used to boost the initial clock signal to form the clock signal.

[0019] Optionally, the voltage divider unit includes a first resistor and a second resistor, the first end of the first resistor is connected to the second end of the first bridge arm and the second end of the second bridge arm, the second end of the first resistor and the first end of the second resistor are connected to the gate of the second switching tube, and the second end of the second resistor is connected to the second power supply end.

[0020] Optionally, the voltage of the first power source provided by the first power source terminal relative to 0 potential is different from the voltage of the second power source provided by the second power source terminal relative to 0 potential.

[0021] Optionally, the first switching tube and the second switching tube are N-type transistors, the first power supply terminal is a first floating terminal, and the second power supply terminal is a second floating terminal;

[0022] Alternatively, the first switching tube and the second switching tube are P-type transistors, the first power supply end is used to provide a first power supply, the voltage of the first power supply is greater than 0, and the second power supply end is used to provide a second power supply, the voltage of the second power supply is greater than 0.

[0023] The technical solution of an embodiment of the present invention uses a voltage replication module to generate a differential signal based on the voltage between the first electrode and gate of a first switching transistor. The differential signal is then isolated and transmitted to a voltage recovery module through an isolation module. Simultaneously, the power supply terminal of the voltage recovery module is connected to a second power supply terminal, so that the voltage at the input terminal of the voltage recovery module is maintained at the voltage of the differential signal relative to the voltage of the second power supply provided by the second power supply terminal. This allows the recovered voltage output by the voltage recovery module to be relative to the voltage of the second power supply. When the difference between the recovered voltage and the voltage between the first electrode and gate of the first switching transistor is less than or equal to a preset voltage value, the difference between the voltage between the first electrode and gate of the second switching transistor and the voltage between the first electrode and gate of the first switching transistor is less than or equal to the preset voltage value. This allows the first and second switching transistors to act as a "common source" in the isolation circuit, so that the ratio of the target current output by the second electrode of the second switching transistor to the reference current input by the second electrode of the first switching transistor is the ratio of the width-to-length ratio of the second switching transistor to the width-to-length ratio of the first switching transistor. This achieves current mirroring in the isolation circuit, resolves the common source limitation of the input and output terminals of the current mirror circuit, and expands the application scenarios of the current mirror circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic structural diagram of a current mirror circuit provided by an embodiment of the present invention;

[0025] Figure 2 A schematic structural diagram of another current mirror circuit provided by an embodiment of the present invention;

[0026] Figure 3 A schematic structural diagram of another current mirror circuit provided by an embodiment of the present invention;

[0027] Figure 4 A schematic structural diagram of another current mirror circuit provided by an embodiment of the present invention;

[0028] Figure 5 A schematic structural diagram of another current mirror circuit provided by an embodiment of the present invention;

[0029] Figure 6 A schematic structural diagram of another current mirror circuit provided by an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of the structure of another current mirror circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0032] Figure 1 Schematic diagram of the structure of a current mirror circuit provided by an embodiment of the present invention. Figure 1 As shown, the current mirror circuit includes:

[0033] A first switch tube T1, wherein a first electrode S1 of the first switch tube T1 is connected to a first power supply terminal V1, and a second electrode D1 of the first switch tube T1 and a gate G1 of the first switch tube T1 are used to input a reference current I1;

[0034] A voltage replication module 110 is connected to the gate G1 and the first electrode S1 of the first switch tube T1. The voltage replication module 110 is configured to generate a differential signal based on the voltage between the first electrode S1 and the gate G1 of the first switch tube T1.

[0035] The isolation module 120, the voltage recovery module 130 and the second switch tube T2, the input end of the isolation module 120 is connected to the output end of the voltage replication module 110, the output end of the isolation module 120 is connected to the control end and the input end of the voltage recovery module 130, the power supply end of the voltage recovery module 130 and the first electrode S2 of the second switch tube T2 are connected to the second power supply end V2, the output end of the voltage recovery module 130 is connected to the gate G2 of the second switch tube T2, and the second electrode D2 of the second switch tube T2 serves as the output end OUT of the current mirror circuit; the isolation module 120, the voltage recovery module 130 and the second electrode D2 of the second switch tube T2 are connected to the control end and the input end of the voltage recovery module 130, the power supply end and the first electrode S2 of the second switch tube T2 are connected to the second power supply end V2, the output end of the voltage recovery module 130 is connected to the gate G2 of the second switch tube T2, and the second electrode D2 of the second switch tube T2 serves as the output end OUT of the current mirror circuit; Module 120 is used to isolate and output the differential signal to the voltage recovery module 130. The voltage recovery module 130 is used to form a recovery voltage relative to the second power supply provided by the second power supply terminal V2 based on the differential signal. The difference between the recovery voltage and the voltage between the first electrode S1 and the gate G1 of the first switch tube T1 is less than or equal to a preset voltage value. The second switch tube T2 is used to output a target current based on the voltage between the first electrode S2 and the gate G2. The ratio of the target current to the reference current is the ratio of the width-to-length ratio of the second switch tube T2 to the width-to-length ratio of the first switch tube T1.

[0036] Specifically, when the first switching transistor T1 and the second switching transistor T2 are transistors, the first electrode S1 of the first switching transistor T1 and the first electrode S2 of the second switching transistor T2 can be source electrodes, and the second electrode D1 of the first switching transistor T1 and the second electrode D2 of the second switching transistor T2 can be drain electrodes. When the reference currents input to the current mirror circuit are different, the gate-source voltage difference of the first switching transistor T1 is different, that is, the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1 is different. The voltage replication module 110 can generate a differential signal based on the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1. The voltage value of the single-ended differential signal of the differential signal can have a positive correlation with the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1, thereby adjusting the voltage value of the single-ended differential signal of the differential signal based on the reference current. The isolation module 120 can have two isolation circuits, each of which isolates and transmits the two single-ended differential signals of the differential signal. This allows the voltage recovery module 130 to isolate and receive the differential signal, and maintain the voltage at the input of the voltage recovery module 130 at the voltage value of the differential signal. Simultaneously, the power supply terminal of the voltage recovery module 130 is connected to the second power supply terminal V2, so that the voltage at the input of the voltage recovery module 130 is converted to the voltage of the second power supply provided relative to the second power supply terminal V2. Simultaneously, the output of the voltage recovery module 130 is connected to the gate G2 of the second switch transistor T2, and the first electrode S2 of the second switch transistor T2 is connected to the second power supply terminal V2. When the voltage recovery module 130 outputs a recovered voltage based on the differential signal, the recovered voltage can be a voltage relative to the second power supply. When the difference between the recovery voltage and the voltage between the first electrode S1 and the gate G1 of the first switch transistor T1 is less than or equal to a preset voltage value, the difference between the voltage between the first electrode S2 and the gate G2 of the second switch transistor T2 and the voltage between the first electrode S1 and the gate G1 of the first switch transistor T1 is less than or equal to the preset voltage value. This allows the first and second switches T1 and T2 to function as a "common source" in the isolation circuit, such that the ratio of the target current output by the second electrode D2 of the second switch transistor T2 to the reference current input by the second electrode D1 of the first switch transistor T1 is equal to the ratio of the width-to-length ratio of the second switch transistor T2 to the width-to-length ratio of the first switch transistor T1. This enables current mirroring in the isolation circuit, resolves the common source limitation of the input and output terminals of the current mirror circuit, and expands the application scenarios of the current mirror circuit. The preset voltage value can be set based on the accuracy of the target current output by the current mirror circuit. The higher the accuracy of the target current, the smaller the preset voltage value. Under ideal conditions, the preset voltage value can be set to 0, so that the voltage between the first electrode S2 and the gate G2 of the second switch tube T2 is equal to the voltage between the first electrode S1 and the gate G1 of the first switch tube T1, thereby avoiding the influence of the difference between the two voltages on the ratio of the target current to the reference current, thereby ensuring the accuracy of the target current.

[0037] The technical solution of this embodiment uses a voltage replication module to generate a differential signal based on the voltage between the first electrode and gate of the first switching transistor. The differential signal is then isolated and transmitted to a voltage recovery module through an isolation module. Simultaneously, the power supply terminal of the voltage recovery module is connected to the second power supply terminal, so that the voltage at the input terminal of the voltage recovery module is maintained at the voltage of the differential signal relative to the voltage of the second power supply provided by the second power supply terminal. This allows the recovered voltage output by the voltage recovery module to be relative to the voltage of the second power supply. When the difference between the recovered voltage and the voltage between the first electrode and gate of the first switching transistor is less than or equal to a preset voltage value, the difference between the voltage between the first electrode and gate of the second switching transistor and the voltage between the first electrode and gate of the first switching transistor is less than or equal to the preset voltage value. This allows the first and second switching transistors to act as a "common source" in the isolation circuit, so that the ratio of the target current output by the second electrode of the second switching transistor to the reference current input by the second electrode of the first switching transistor is the ratio of the width-to-length ratio of the second switching transistor to the width-to-length ratio of the first switching transistor. This enables current mirroring in the isolation circuit, addresses the common source limitation of the input and output terminals of the current mirror circuit, and expands the application scenarios of the current mirror circuit.

[0038] Figure 2 FIG1 is a structural diagram of another current mirror circuit provided by an embodiment of the present invention. Figure 2 As shown, the voltage replication module 110 includes a clock unit 111, an inverting buffer unit 112, and a non-inverting buffer unit 113; the power supply terminal of the clock unit 111 is connected to the first power supply terminal V1, the input terminal of the clock unit 111 is connected to the gate G1 of the first switch tube T1, and the output terminal of the clock unit 111 is connected to the input terminal of the inverting buffer unit 112 and the input terminal of the non-inverting buffer unit 113. The output terminal of the inverting buffer unit 112 is the first single-ended differential signal output terminal OUT1 of the voltage replication module 110, and the output terminal of the non-inverting buffer unit 113 is the second single-ended differential signal output terminal OUT2 of the voltage replication module 110. The clock unit 111 is used to generate a clock signal according to the voltage between the first electrode S1 and the gate G1 of the first switch tube T1. The inverting buffer unit 112 is used to invert the clock signal and output a first differential signal. The non-inverting buffer unit 113 is used to synchronize the clock signal and output a second differential signal.

[0039] Specifically, the clock unit 111 may include an oscillator (OSC). The power supply terminal of the clock unit 111 is connected to the first power supply terminal V1, which is equivalent to the power supply terminal of the clock unit 111 being connected to the first electrode S1 of the first switching transistor T1. The input terminal of the clock unit 111 is connected to the gate G1 of the first switching transistor T1, so that the voltage between the input terminal and the power supply terminal of the clock unit 111 is equal to the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1. This allows the clock unit 111 to generate a clock signal based on the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1. The voltage value of the clock signal is positively correlated with the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1. For example, by adjusting the internal structure of the clock unit 111, the voltage value of the clock signal can be equal to the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1. That is, the absolute value of the high-level voltage of the clock signal, the absolute value of the low-level voltage of the clock signal, and the absolute value of the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1 are equal.

[0040] The inverting buffer unit 112 may include an inverter, and the in-phase buffer unit 113 may include a non-inverting device. After the clock signal passes through the inverting buffer unit 112 and the non-in-phase buffer unit 113, the inverting buffer unit 112 can output the inverted clock signal as the first differential signal, while the non-in-phase buffer unit 113 can output the non-in-phase clock signal as the second differential signal. This ensures that the first differential signal and the second differential signal are a set of differential signals with equal amplitudes and opposite phases. At the same time, the voltage value of the differential signal can be positively correlated with the voltage between the first electrode S1 and the gate G1 of the first switch tube T1, thereby adjusting the voltage value of the differential signal based on the reference current. When the voltage recovery module 130 forms a recovery voltage based on the differential signal, the recovery voltage can be adjusted based on the reference current. Furthermore, the voltage between the first electrode S2 and the gate G2 of the second switch tube T2 can be adjusted based on the reference current, thus achieving current mirroring in the isolation circuit.

[0041] Continue to refer Figure 2 The isolation module 120 includes a first capacitor C1 and a second capacitor C2. The first electrode of the first capacitor C1 is connected to the first single-ended differential signal output terminal OUT1, the second electrode of the first capacitor C1 is connected to the first control terminal and the first input terminal of the voltage recovery module 130, the first electrode of the second capacitor C2 is connected to the second single-ended differential signal output terminal OUT2, and the second electrode of the second capacitor C2 is connected to the second control terminal and the second input terminal of the voltage recovery module 130; the voltage recovery module 130 is used to form a recovery voltage according to the second differential signal when the first differential signal is valid, and to form a recovery voltage according to the first differential signal when the second differential signal is valid.

[0042] Specifically, the first capacitor C1 and the second capacitor C2 function to block direct current (DC) and resist alternating current (AC). When the inverting buffer unit 112 outputs the first differential signal, the first capacitor C1 electrically isolates the inverting buffer unit 112 from the voltage recovery module 130, while allowing the AC first differential signal to be output to the first control terminal and first input terminal of the voltage recovery module 130. When the in-phase buffer unit 113 outputs the in-phase clock signal, the second capacitor C2 electrically isolates the in-phase buffer unit 113 from the voltage recovery module 130, while allowing the AC second differential signal to be output to the second control terminal and second input terminal of the voltage recovery module 130. This allows the voltage recovery module 130 to form a current loop between the second input terminal and the output terminal of the voltage recovery module 130 when the first differential signal is valid, thereby enabling the voltage recovery module 130 to generate a recovered voltage based on the second differential signal. Alternatively, when the second differential signal is valid, a current loop can be formed between the first input terminal and the output terminal of the voltage recovery module 130, thereby enabling the voltage recovery module 130 to generate a recovered voltage based on the first differential signal. Furthermore, the first differential signal and the second differential signal have opposite phases, allowing the voltage recovery module 130 to continuously generate a recovery voltage based on the first differential signal or the second differential signal, thereby rectifying the differential signal. This ensures that the difference between the recovery voltage and the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1 is less than a preset voltage value, thereby enabling current mirroring to be implemented on the second switching transistor T2.

[0043] Figure 3 FIG1 is a structural diagram of another current mirror circuit provided by an embodiment of the present invention. Figure 3 As shown, the isolation module 120 includes a transformer 121, the first end of the primary side of the transformer 121 is connected to the first single-ended differential signal output end OUT1, the second end of the primary side of the transformer 121 is connected to the second single-ended differential signal output end OUT2, the first end of the secondary side of the transformer 121 is connected to the first control end and the first input end of the voltage recovery module 130, and the second end of the secondary side of the transformer is connected to the second control end and the second input end of the voltage recovery module 130.

[0044] Specifically, Figure 3 and Figure 2The difference is that the isolation module 120 uses a transformer 121 to achieve electrical isolation. The differential signal can also be electrically isolated and then output to the electrical recovery module 130, which will not be further described here. Furthermore, when the voltage difference between the single-ended differential signal of the differential signal output by the voltage replication module 110 and the voltage between the first electrode S1 and the gate G1 of the first switch transistor T1 is within a preset voltage range, the transformation ratio of the transformer 121 can be 1:1, so that the voltage difference between the single-ended differential signal of the differential signal output by the isolation module 120 and the voltage between the first electrode S1 and the gate G1 of the first switch transistor T1 is within the preset voltage range. In this case, the voltage recovery module 130 can directly output the differential signal as the recovery voltage, ensuring that the voltage difference between the first electrode S1 and the gate G1 of the first switch transistor T1 and the voltage between the first electrode S2 and the gate G2 of the second switch transistor T2 is within the preset voltage range. This allows for mirroring of the reference current when the voltages of the first power supply provided by the first power supply terminal V1 and the second power supply provided by the second power supply terminal V2 are unequal.

[0045] For example, Figure 4 FIG1 is a structural diagram of another current mirror circuit provided by an embodiment of the present invention. Figure 4 As shown, the voltage recovery module 130 includes a rectifier unit 131, the control end of the first bridge arm H1 of the rectifier unit 131 and the input end of the second bridge arm H2 of the rectifier unit 131 are connected to the first output end of the isolation module 120, the control end of the second bridge arm H2 and the input end of the first bridge arm H1 are connected to the second output end of the isolation module 120, the first end of the first bridge arm H1 and the first end of the second bridge arm H2 are connected to the second power supply end V2, and the second end of the first bridge arm H1 and the second end of the second bridge arm H2 are connected to the gate G2 of the second switch tube T2; the first bridge arm H1 is used to provide a current path for the second differential signal when the first differential signal is valid, and the second bridge arm H2 is used to provide a current path for the first differential signal when the second differential signal is valid.

[0046] Specifically, when the isolation module 120 includes a first capacitor C1 and a second capacitor C2, the second terminal of the first capacitor C1 serves as the first output terminal of the isolation module 120, and the second terminal of the second capacitor C2 serves as the second output terminal of the isolation module 120. When the isolation module 120 includes a transformer 121, the first terminal of the secondary side of the transformer 121 serves as the first output terminal of the isolation module 120, and the second terminal of the secondary side of the transformer 121 serves as the second output terminal of the isolation module 120. The rectifier unit 131 may be a full-bridge rectifier unit. The first differential signal is transmitted to the input terminal of the second bridge arm H2 through the isolation module 120, and the second differential signal is transmitted to the input terminal of the first bridge arm H1 through the isolation module 120. Simultaneously, the first terminal of the first bridge arm H1 and the first terminal of the second bridge arm H2 are connected to the second power supply terminal V2. When the first differential signal is valid and the second differential signal is invalid, the input terminal of the first bridge arm H1 is connected to the second terminal, and the first terminal of the second bridge arm H2 is connected to the input terminal, and the voltage of the second differential signal is converted to a voltage relative to the second power supply terminal V2. At the same time, the second differential signal can be transmitted through the input end of the first bridge arm H1 to the second end, namely, to the gate G2 of the second switch transistor T2. This causes the voltage between the gate G2 of the second switch transistor T2 and the first electrode S2 to be the voltage of the second differential signal. This voltage, combined with the voltage between the gate G1 of the first switch transistor T1 and the first electrode S1, is less than a preset voltage value, thereby enabling mirroring of the reference current. When the second differential signal is valid and the first differential signal is invalid, the input end of the second bridge arm H2 is connected to the second end, and the first end of the first bridge arm H1 is connected to the input end. The voltage of the first differential signal is converted to a voltage relative to the second power supply terminal V2. At the same time, the first differential signal can be transmitted through the input end of the second bridge arm H2 to the second end, namely, to the gate G2 of the second switch transistor T2. This causes the voltage between the gate G2 of the second switch transistor T2 and the first electrode S2 to be the voltage of the first differential signal. This voltage, combined with the voltage between the gate G1 of the first switch transistor T1 and the first electrode S1, is less than a preset voltage value, thereby enabling mirroring of the reference current.

[0047] Continue to refer Figure 4The first bridge arm H1 includes a first transistor M1 and a second transistor M2, and the second bridge arm H2 includes a third transistor M3 and a fourth transistor M4; the gate of the first transistor M1, the gate of the second transistor M2, the second electrode of the third transistor M3, and the second electrode of the fourth transistor M4 are connected to the first output terminal of the isolation module 120, the second electrode of the first transistor M1, the second electrode of the second transistor M2, the gate of the third transistor M3, and the gate of the fourth transistor M4 are connected to the second output terminal of the isolation module 120, the first electrode of the first transistor M1 and the first electrode of the third transistor M3 are connected to the second power supply terminal V2, and the first electrode of the second transistor M2 and the first electrode of the fourth transistor M4 are connected to the gate G2 of the second switch transistor T2; wherein, the channel type of the first transistor M1 is opposite to the channel type of the second transistor M2, the channel type of the first transistor M1 is the same as the channel type of the third transistor M3, and the channel type of the third transistor M3 is opposite to the channel type of the fourth transistor M4.

[0048] Specifically, Figure 4The figure exemplarily shows that the first transistor M1 and the third transistor M3 are P-type transistors, and the second transistor M2 and the fourth transistor M4 are N-type transistors. The gates of the first transistor M1 and the second transistor M2 serve as the control terminals of the first bridge arm H1, the second electrodes of the first transistor M1 and the second transistor M2 serve as the input terminals of the first bridge arm H1, the first electrode of the first transistor M1 serves as the first terminal of the first bridge arm H1, and the first electrode of the second transistor M2 serves as the second terminal of the first bridge arm H1. The gates of the third transistor M3 and the fourth transistor M4 serve as the control terminals of the second bridge arm H2, the second electrodes of the third transistor M3 and the fourth transistor M4 serve as the input terminals of the second bridge arm H2, the first electrode of the third transistor M3 serves as the first terminal of the second bridge arm H1, and the first electrode of the fourth transistor M4 serves as the second terminal of the second bridge arm H1. At this time, the active level of the first differential signal and the second differential signal is a high level, and the inactive level is a low level. When the first differential signal is at a high level and the second differential signal is at a low level, the second transistor M2 and the third transistor M3 are turned on, and the second differential signal is transmitted to the second electrode of the second transistor M2, causing the voltage at the second electrode of the second transistor M2 relative to the voltage at the second power supply terminal V2 to equal the voltage of the second differential signal. The second transistor M2 outputs the second differential signal to the gate G2 of the second switch transistor T2, and forms a loop with the second electrode of the third transistor M3 through the second switch transistor T2 and the third transistor M3. This causes the voltage at the gate G2 of the second switch transistor T2 relative to the voltage at the second power supply terminal V2 to equal the voltage of the second differential signal. As a result, the voltage between the gate G2 of the second switch transistor T2 and the first electrode S2 equals the voltage of the second differential signal, and the difference between the voltage between the gate G2 of the second switch transistor T2 and the first electrode S2 is less than or equal to a preset voltage value, thereby achieving mirroring of the reference current. When the first differential signal is at a low level and the second differential signal is at a high level, the first transistor M1 and the fourth transistor M4 are turned on, and the first differential signal is transmitted to the second electrode of the fourth transistor M4, causing the voltage at the second electrode of the fourth transistor M4 relative to the voltage of the second power supply terminal V2 to equal the voltage of the first differential signal. The fourth transistor M4 outputs the first differential signal to the gate G2 of the second switch transistor T2, forming a loop with the second electrode of the first transistor M1 through the second switch transistor T2 and the first transistor M1. This causes the voltage at the gate G2 of the second switch transistor T2 relative to the voltage of the second power supply terminal V2 to equal the voltage of the first differential signal. As a result, the voltage between the gate G2 of the second switch transistor T2 and the first electrode S2 equals the voltage of the first differential signal, and the difference between the voltage between the gate G2 of the second switch transistor T2 and the first electrode S2 is less than or equal to a preset voltage value, thereby mirroring the reference current.

[0049] It should be noted that in some embodiments, the first transistor M1 may also be an N-type transistor, in which case the second transistor M2 is a P-type transistor, the third transistor M3 is an N-type transistor, and the fourth transistor M4 is a P-type transistor. Simultaneously, the active level of the first differential signal and the second differential signal is a low level, and the inactive level is a high level. The specific operating process is similar to the above-described operating process and will not be further described here.

[0050] Figure 5 FIG1 is a structural diagram of another current mirror circuit provided by an embodiment of the present invention. Figure 5 As shown, the clock unit 111 includes an oscillator 1111 and a voltage conversion subunit 1112. The input end of the oscillator 1111 is connected to the gate G1 of the first switch tube T1, the power end of the oscillator 1111 is connected to the first power end V1, the input end of the voltage conversion subunit 1112 is connected to the output end of the oscillator 1111, and the output end of the voltage conversion subunit 1112 is connected to the input end of the in-phase buffer unit 113 and the input end of the inverting buffer unit 112. The oscillator 111 is used to form an initial clock signal according to the voltage between the first pole S1 and the gate G1 of the first switch tube T1, and the voltage conversion subunit 1112 is used to perform voltage conversion on the initial clock signal to form a clock signal. The voltage of the clock signal is equal to the voltage of the initial clock signal. The voltage ratio is a first ratio; the voltage recovery module 130 also includes a voltage divider unit 132; the first end of the voltage divider unit 132 is connected to the second end of the first bridge arm H1 and the second end of the second bridge arm H2, the second end of the voltage divider unit 132 is connected to the second power supply end V2, and the output end of the voltage divider unit 132 is connected to the gate G2 of the second switch tube T2. The voltage divider unit 132 is used to divide the rectified signal output by the rectifier unit 131 to form a recovery voltage; when the isolation module 120 includes a first capacitor C1 and a second capacitor C2, the voltage divider ratio of the voltage divider unit 132 is the reciprocal of the first ratio; when the isolation module 120 includes a transformer 121, the product of the voltage divider ratio of the voltage divider unit 132 and the reciprocal of the transformation ratio of the transformer 121 is equal to the reciprocal of the first ratio.

[0051] Specifically, the voltage value of the initial clock signal can be equal to the difference between the voltages between the first electrode S1 and the gate G1 of the first switching transistor T1. After the oscillator 1111 generates the initial clock signal based on the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1, the voltage conversion subunit 1112 can change the voltage of the initial clock signal so that the ratio of the voltage value of the clock signal to the voltage value of the initial clock signal is a first ratio. Exemplarily, the voltage conversion subunit 1112 can include a charge pump, the input of the charge pump being connected to the output of the clock unit, the power supply of the charge pump being connected to the gate of the first switching transistor, and the output of the charge pump being connected to the input of the in-phase buffer unit and the input of the inverting buffer unit. The charge pump is used to boost the initial clock signal to form the clock signal, thereby improving the transmission efficiency of the clock signal. At this time, the ratio of the voltage value of the clock signal to the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1 is the first ratio.

[0052] When the isolation module 120 includes a first capacitor C1 and a second capacitor C2, the isolation module 120 has no effect on the voltage of the clock signal. The voltage value of the differential signal received by the voltage recovery module 130 is the same as the voltage value of the clock signal. In this case, the voltage recovery module 130 can be configured to include a rectifier unit 131 and a voltage divider unit 132. The voltage value of the rectifier unit 131 outputs the rectified signal after rectifying the differential signal, and the voltage value of the rectified signal is the same as the voltage value of the clock signal. The voltage divider unit 132 divides the rectified signal so that the ratio of the recovered voltage output by the voltage divider unit 132 to the voltage value of the rectified signal is the voltage divider ratio. At the same time, the voltage value of the rectified signal is the same as the voltage value of the clock signal, that is, the ratio of the voltage value of the rectified signal to the voltage between the first pole S1 and the gate G1 of the first switch tube T1 is the first ratio. The voltage division ratio of the voltage divider unit 132 is the inverse of the first ratio. This theoretically ensures that the recovery voltage is equal to the voltage between the first electrode S1 and the gate G1 of the first switch transistor T1, ensuring that the difference between the recovery voltage and the voltage between the first electrode S1 and the gate G1 of the first switch transistor T1 is less than or equal to a preset voltage value. This allows the second switch transistor T2 to mirror the reference current based on the voltage between the first electrode S2 and the gate G2, outputting a target current. For example, when the voltage conversion subunit 1112 boosts the initial clock signal so that the voltage value of the clock signal is twice the voltage value of the initial clock signal, the voltage division ratio of the voltage divider unit 132 can be 1 / 2.

[0053] Figure 6 FIG1 is a structural diagram of another current mirror circuit provided by an embodiment of the present invention. Figure 6As shown, when the isolation module 120 includes a transformer 121, the isolation module 120 can perform voltage conversion on the clock signal, with the ratio of the voltage value of the clock signal after conversion to the voltage value of the clock signal before conversion being equal to the transformation ratio of the transformer 121. In this case, the ratio of the voltage value of the differential signal received by the voltage recovery module 130 to the voltage value of the clock signal is equal to the transformation ratio of the transformer 121. In this case, the product of the voltage divider ratio of the voltage divider unit 132 and the inverse of the transformation ratio of the transformer 121 can be set equal to the inverse of the first ratio, so that the product of the voltage conversion of the signal by the voltage conversion subunit 1112, the transformer 121, and the voltage divider unit 132 is equal to 1. This ensures that the recovered voltage is theoretically equal to the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1, ensuring that the difference between the recovered voltage and the voltage between the first electrode S1 and the gate G1 of the first switching transistor T1 is less than or equal to a preset voltage value. Similarly, the second switching transistor T2 can mirror the reference current based on the voltage between the first electrode S2 and the gate G2 to output the target current. Exemplarily, when the voltage conversion subunit 1112 boosts the initial clock signal so that the voltage value of the clock signal is twice the voltage value of the initial clock signal, and the transformation ratio of the transformer 121 is 3, the voltage division ratio of the voltage division unit 132 may be 1 / 6.

[0054] Continue to refer Figure 5 and Figure 6 The voltage dividing unit 132 includes a first resistor R1 and a second resistor R2, the first end of the first resistor R1 is connected to the second end of the first bridge arm H1 and the second end of the second bridge arm H2, the second end of the first resistor R1 and the first end of the second resistor R2 are connected to the gate G2 of the second switch tube T2, and the second end of the second resistor R2 is connected to the second power supply terminal V2.

[0055] Specifically, the first resistor R1 and the second resistor R2 are connected in series between the second ends of the first bridge arm H1 and the second bridge arm H2 and the second power supply terminal V2, so that the first resistor R1 and the second resistor R2 can divide the rectified signal output by the rectifier unit 131 to form a recovery voltage. The recovery voltage is then output to the gate G2 of the second switch tube T2.

[0056] Based on the above technical solutions, the voltage of the first power supply provided by the first power supply terminal relative to 0 potential is not equal to the voltage of the second power supply provided by the second power supply terminal relative to 0 potential, that is, the potentials of the first power supply terminal and the second power supply terminal are not equal.

[0057] Continue to refer Figures 1 to 6The first switch tube T1 and the second switch tube T2 are N-type transistors, the first power supply terminal V1 is the first floating ground terminal GND1, and the second power supply terminal V2 is the second floating ground terminal GND2. In this case, the first floating ground terminal GND1 can provide a reference ground potential for the circuit of the isolation module 120 located on the first switch tube T1 side. The second floating ground terminal GND2 can provide a reference ground potential for the circuit of the isolation module 120 located on the second switch tube T2 side. When the second electrode D1 of the first switch tube T1 provides a reference current I1, the voltage difference between the gate G1 of the first switch tube T1 and the first electrode S1 can be greater than 0, and the first switch tube T1 is in the on state. When the voltage recovery module 130 provides a recovery voltage to the gate of the second switch tube T2, the voltage difference between the gate G2 of the second switch tube T2 and the first electrode S2 can also be greater than 0, and the second switch tube T2 is in the on state.

[0058] Figure 7 FIG1 is a structural diagram of another current mirror circuit provided by an embodiment of the present invention. Figure 7 As shown, the first switching transistor T1 and the second switching transistor T2 are P-type transistors. The first power supply terminal V1 is used to provide a first power supply, the voltage of which is greater than 0. The second power supply terminal V2 is used to provide a second power supply, the voltage of which is greater than 0. The voltage of the first power supply provided by the first power supply terminal V1 relative to the reference ground potential of the circuit on the first switching transistor T1 side of the isolation module 120 is greater than 0, allowing the first power supply to power the circuit on the first switching transistor T1 side of the isolation module 120. This reduces the voltage difference between the gate G1 and the first electrode S1 of the first switching transistor T1 to less than 0, thereby controlling the first switching transistor T1 to conduct. The voltage of the second power supply provided by the second power supply terminal V2 relative to the reference ground potential of the circuit on the second switching transistor T2 side of the isolation module 120 is greater than 0, allowing the second power supply to power the circuit on the second switching transistor T2 side of the isolation module 120. When the voltage recovery module 130 provides a recovery voltage for the gate of the second switch tube T2, the voltage difference between the gate G2 of the second switch tube T2 and the first electrode S2 can also be made less than 0, and the second switch tube T2 is in the on state, ensuring the normal operation of the current mirror circuit.

[0059] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A current mirror circuit, characterized in that: include: a first switching tube, wherein a first electrode of the first switching tube is connected to a first power supply terminal, and a second electrode of the first switching tube and a gate of the first switching tube are used to input a reference current; a voltage replication module, the voltage replication module being connected to the gate and the first electrode of the first switching tube, and configured to generate a differential signal according to a voltage between the first electrode and the gate of the first switching tube; An isolation module, a voltage recovery module, and a second switching tube, wherein the input end of the isolation module is connected to the output end of the voltage replication module, the output end of the isolation module is connected to the input end and the control end of the voltage recovery module, the power supply end of the voltage recovery module and the first electrode of the second switching tube are connected to the second power supply end, the output end of the voltage recovery module is connected to the gate of the second switching tube, and the second electrode of the second switching tube serves as the output end of the current mirror circuit; the isolation module is configured to isolate and output the differential signal to the voltage recovery module, and the voltage recovery module is configured to form a recovery voltage relative to the second power supply provided by the second power supply end based on the differential signal, and the difference between the recovery voltage and the voltage between the first electrode and the gate of the first switching tube is less than or equal to a preset voltage value; The second switch tube is used to output a target current according to the voltage between the first electrode and the gate, and the ratio of the target current to the reference current is the ratio of the width-to-length ratio of the second switch tube to the width-to-length ratio of the first switch tube.

2. The current mirror circuit according to claim 1, wherein: The voltage replication module includes a clock unit, an inverting buffer unit and a non-inverting buffer unit; The power supply end of the clock unit is connected to the first power supply end, the input end of the clock unit is connected to the gate of the first switching tube, and the output end of the clock unit is connected to the input end of the inverting buffer unit and the input end of the in-phase buffer unit. The output end of the inverting buffer unit is the first single-ended differential signal output end of the voltage replication module, and the output end of the in-phase buffer unit is the second single-ended differential signal output end of the voltage replication module. The clock unit is used to form a clock signal according to the voltage between the first pole and the gate of the first switching tube. The inverting buffer unit is used to invert the clock signal and output a first differential signal. The in-phase buffer unit is used to synchronize the clock signal and output a second differential signal.

3. The current mirror circuit according to claim 2, wherein: The isolation module includes a first capacitor and a second capacitor, wherein a first electrode of the first capacitor is connected to the first single-ended differential signal output terminal, a second electrode of the first capacitor is connected to the first control terminal and the first input terminal of the voltage recovery module, a first electrode of the second capacitor is connected to the second single-ended differential signal output terminal, and a second electrode of the second capacitor is connected to the second control terminal and the second input terminal of the voltage recovery module; Alternatively, the isolation module includes a transformer, a primary first end of the transformer is connected to the first single-ended differential signal output end, a primary second end of the transformer is connected to the second single-ended differential signal output end, a secondary first end of the transformer is connected to the first control end and the first input end of the voltage recovery module, and a secondary second end of the transformer is connected to the second control end and the second input end of the voltage recovery module; The voltage recovery module is configured to generate the recovery voltage according to the second differential signal when the first differential signal is valid, and to generate the recovery voltage according to the first differential signal when the second differential signal is valid.

4. The current mirror circuit according to claim 3, wherein: The voltage recovery module includes a rectifier unit, the control end of the first bridge arm of the rectifier unit and the input end of the second bridge arm of the rectifier unit are connected to the first output end of the isolation module, the control end of the second bridge arm and the input end of the first bridge arm are connected to the second output end of the isolation module, the first end of the first bridge arm and the first end of the second bridge arm are connected to the second power supply end, and the second end of the first bridge arm and the second end of the second bridge arm are connected to the gate of the second switching tube; the first bridge arm is used to provide a current path for the second differential signal when the first differential signal is valid, and the second bridge arm is used to provide a current path for the first differential signal when the second differential signal is valid.

5. The current mirror circuit according to claim 4, wherein: The first bridge arm includes a first transistor and a second transistor, and the second bridge arm includes a third transistor and a fourth transistor; The gate of the first transistor, the gate of the second transistor, the second electrode of the third transistor, and the second electrode of the fourth transistor are connected to the first output end of the isolation module, the second electrode of the first transistor, the second electrode of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are connected to the second output end of the isolation module, the first electrode of the first transistor and the first electrode of the third transistor are connected to the second power supply end, and the first electrode of the second transistor and the first electrode of the fourth transistor are connected to the gate of the second switching tube; wherein, the channel type of the first transistor is opposite to the channel type of the second transistor, the channel type of the first transistor is the same as the channel type of the third transistor, and the channel type of the third transistor is opposite to the channel type of the fourth transistor.

6. The current mirror circuit according to claim 4, wherein: The clock unit includes an oscillator and a voltage conversion subunit, wherein the input end of the oscillator is connected to the gate of the first switching tube, the power end of the oscillator is connected to the first power end, the input end of the voltage conversion subunit is connected to the output end of the oscillator, and the output end of the voltage conversion subunit is connected to the input end of the in-phase buffer unit and the input end of the inverting buffer unit. The oscillator is used to form an initial clock signal according to the voltage between the first electrode and the gate of the first switching tube, and the voltage conversion subunit is used to perform voltage conversion on the initial clock signal to form the clock signal, and the ratio of the voltage of the clock signal to the voltage of the initial clock signal is a first ratio; The voltage recovery module also includes a voltage divider unit; the first end of the voltage divider unit is connected to the second end of the first bridge arm and the second end of the second bridge arm, the second end of the voltage divider unit is connected to the second power supply end, and the output end of the voltage divider unit is connected to the gate of the second switching tube. The voltage divider unit is used to divide the rectified signal output by the rectifier unit to form the recovery voltage; when the isolation module includes the first capacitor and the second capacitor, the voltage divider ratio of the voltage divider unit is the reciprocal of the first ratio; when the isolation module includes the transformer, the product of the voltage divider ratio of the voltage divider unit and the reciprocal of the transformer transformation ratio is equal to the reciprocal of the first ratio.

7. The current mirror circuit according to claim 6, wherein: The voltage conversion subunit includes a charge pump, the input end of the charge pump is connected to the output end of the clock unit, the power supply end of the charge pump is connected to the gate of the first switching tube, the output end of the charge pump is connected to the input end of the in-phase buffer unit and the input end of the inverting buffer unit, and the charge pump is used to boost the initial clock signal to form the clock signal.

8. The current mirror circuit according to claim 6, wherein: The voltage divider unit includes a first resistor and a second resistor, the first end of the first resistor is connected to the second end of the first bridge arm and the second end of the second bridge arm, the second end of the first resistor and the first end of the second resistor are connected to the gate of the second switching tube, and the second end of the second resistor is connected to the second power supply end.

9. The current mirror circuit according to claim 1, wherein: The voltage of the first power source provided by the first power source terminal relative to the 0 potential is different from the voltage of the second power source provided by the second power source terminal relative to the 0 potential.

10. The current mirror circuit according to claim 1, wherein: The first switch tube and the second switch tube are N-type transistors, the first power supply terminal is a first floating terminal, and the second power supply terminal is a second floating terminal; Alternatively, the first switching tube and the second switching tube are P-type transistors, the first power supply end is used to provide a first power supply, the voltage of the first power supply is greater than 0, and the second power supply end is used to provide a second power supply, the voltage of the second power supply is greater than 0.

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